Datasheet S29GL064A, S29GL032A, S29GL016A Datasheet (SPANSION)

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S29GL-A MirrorBit™ Flash Family

S29GL064A, S29GL032A, and S29GL016A 64 Megabit, 32 Megabit, and 16 Megabit

3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology

Data Sheet

Notice to Readers: The Advance Information status indicates that this document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.

ADVANCE

INFORMATION

Publication Number S29GL-A_00 Revision A Amendment 3 Issue Date April 22, 2005

Page 2

Advance Information

Notice On Data Sheet Designations

Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, in cluding development, qualification, initial production, and full produc tion. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.

Advance Informatio n

The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to produc tion. Information p resented in a document with this designation is likely to change, and in some cases , development on the prod uct may discontinue. Spansion LLC therefore places the following conditions upon Advance Informa tion content:

“This document contains information on one or more products under development at Spansion LLC. The information is inten ded to help you evaluate this produ ct. Do not de sign in this pro duct withou t contacting the factor y. Spansion LLC reserves the right to chan ge or discontinue wo rk on this proposed product wi t h o u t notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a P reliminar y documen t shoul d be e xpected wh ile keepin g these as pects of production under consideration. Spansion places the following conditions upon Preliminary content:

“This document states the c urrent techni cal spe cific ations rega rding t he Sp ansio n produc t(s ) descr ibe d herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in techni c a l spec if ications.”

Combination

Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with DC Characteristics table and A C Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in product ion for a period of time suc h that no changes or only nomi nal changes are expected, th e Preliminary des ignation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range . C h an g es may also include those needed to clarify a description or to correct a typographical error or incor rect specification. Spansion LLC applies the following conditions to documents in this category:

“This document states the c urrent techni cal spe cific ations rega rding t he Sp ansio n produc t(s ) descr ibe d herein. Spansion LLC deem s the pro du cts to have been in suffi cient prod uc tion volume such tha t subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to th e val id combinations of fered may occur.”

Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.

ii S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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S29GL-A MirrorBit™ Flash Family

S29GL064A, S29GL032A, and S29GL016A 64 Megabit, 32 Megabit, and 16 Megabit

3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology

Data Sheet

Distinctive Characteristics

Architectural Advantages

 Single power supply operation

— 3 volt read, erase, and program operations

 Manufactured on 200 nm MirrorBit process

technology

 Secure d Silicon Sector region

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence

— May be programmed and locked at the factory or by

the customer

 Flexible sector architecture

— 64Mb (uniform sector models): 128 32 Kword (64 KB)

sectors

— 64Mb (boot sector models): 127 32 Kword (64 KB)

sectors + 8 4Kword (8KB) boot sectors

— 32Mb (uniform sector models): 64 32Kword (64KB)

sectors

— 32Mb (boot sector models): 63 32Kword (64KB)

sectors + 8 4Kword (8KB) boot sectors

— 16MB (boot sector models): 31 31Kword (64KB)

sectors + 8 4Kword (8KB) boot sectors

 Compa tibility with JEDEC standards

— Provides pinout and softw are compatibility for single-

power supply flash, and superior inadvertent write protection

 100,000 erase cycles typical per sector  20-year data retention typical

Performance Characteristics

 High performance

— 90 ns access time — 4-word/8-byte page read buffer — 25 ns page read times — 16-word/32-byte write buffer which reduces overall

programming time for multiple-word updates

ADVANCE

INFORMATION

 Low power consumption (typical values at 3.0 V, 5

MHz)

— 18 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current

 Package options

— 48-pin TSOP — 56-pin TSOP — 64-ba ll Fortified BGA — 48-ball fine-pitch BGA

Software & Hardware Features

 Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed — Data# polling & toggle bits provide status — CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices — Unlock Bypass Program command reduces overall

multiple-word programming time

 Hardware features

— Sector Group Protection: hardware-level method of

preventing write operations within a sector group — Temporary Sector Unprotect : VID-level method of

charging code in lock ed sectors — WP#/ACC input accelerates programming time

(when high voltage is ap plied) for gr eater throughput

during system production. Protects first or last sector

regardless of sector protection settings on uniform

sector models — Hardware r eset input (RES ET#) resets device — Ready/Busy# output (RY/BY#) detects pro gram or

erase cycle completion

Publication Number S29GL-A_00 Revision A Amendment 3 Issue Date April 22, 2005

This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or disco ntinue work on this proposed product without notice.

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General Description

The S29GL-A family of devices are 3.0 V single power Flash memory manufactured using 200 nm MirrorBit technology. The S29GL064A is a 64-Mb device organized as 4,194,304 words or 8,388,608 bytes. T he S29GL032A is a 32-Mb device organized as 2,097,152 words or 4,194,304 bytes. The S29Gl016A is a 16 Mb device organized as 1,048,576 words or 2,097,152 bytes. Depending on the model number, the devices have an 8-bit wide data bus only, 16-bit wide data bus only, or a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The d evices can be programmed either in the host system or in standard EPROM programmers.

Access times as fast as 90 ns are available. Note that each access time has a specific operating voltage range (V and the and Ordering Informat ion–S29GL064A. Package offerings include 48-pin TSOP, 56-pin TSOP, 48-ball fine-pitch BGA and 64-ball Fortified BGA, depending on model number . Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V (ACC) feature provides shorter programming times through increased current on the WP#/ACC input. This feature is intended t o facilitate factory throughput during system production, but may also be used in the field if desired.

The device is entirely command set compatible with the JEDEC single-power- supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.

The sector erase architecture allows me mory sec tor s to be e ra sed and rep rogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Ordering Information–S29GL016A, Ordering Information–S29GL032A ,

Advance Information

) as specified in the Product Selector Guide

input, a high-volta ge accelerated program

Device programming and erasure are initiated through command sequences. Once a program or erase operation begins, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four.

Hardware data protection measures include a low VCC detector that automat- ically inhib its write operations du ring power transitions. The hardware sector protection feature disables both program and erase operations in any combina tion of sectors of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend/Er ase Resume feature a llows the host system t o pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program R esume feature enables the host system to pause a program operation in a giv e n sector to read any other sector and then complete the program operation.

The hardware RESET# pin terminates any operation in progress and resets the device, after whic h it i s then read y for a new ope rat ion. The RESET# pin ma y be tied to the system reset circuitry. A system reset would thus also reset the de

2 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

vice, enabling the host system to read boot-up firmware from the Flash memory device.

The device reduces power consumption in the standby mode when it detect s specific voltage levels on CE# and RESET#, or when addresses are stable for a specified period of time.

The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP#/ACC pin or WP# pin, depending on model number. The protected sector is still protected even during accelerated programming.

The Secured Silicon Sector provides a 12 8-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur.

Spansion MirrorBit flash technology combines years of Flash me mory manufacturing experi ence to produce the high est levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simulta neously via hot-hole assisted erase. The data is programmed using hot electron injection.

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 3

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Advance Information

Table of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6

S29GL064A, S29GL032A, S29GL016A .............................................................6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 8

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Logic Symbol–S29GL064A (Models R1, R2, R8, R9) ................................... 11

Logic Symbol–S29GL064A (Model R5) .......................................................... 12

Logic Symbol–S29GL064A (Model R6, R7) .................................................. 12

Logic Symbol–S29GL032A (Models R1, R2) ..................................................13

Logic Symbol–S29GL032A (Models R3, R4) ..................................................13

Logic Symbol–S29GL016A (Models R1, R2) ...................................................13

Ordering Information–S29GL016A . . . . . . . . . . . 14

S29GL016A Standard Products ........................................................................ 14

Table 1. S2 9 G L 0 1 6 A O rd er i ng O ptions ... ... ... ... ...... ... .. ... ... ... ... . 14

Ordering Information–S29GL032A . . . . . . . . . . . 15

S29GL032A Standard Products .........................................................................15

Table 2. S2 9 G L 0 3 2 A O rd er i ng O ptions ... ... ... ... ...... ... .. ... ... ... ... . 15

Ordering Information–S29GL064A . . . . . . . . . . . 16

S29GL064A Standard Products ....................................................................... 16

Table 3. S2 9 G L 0 6 4 A V alid Combinations ...... ... ... ... ... .. ... ... ... ... . 17

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 18

Table 4. D ev ic e Bus Opera ti o ns ..................... ... ... ... .. ... ... ... ... . 18

Word/Byte Configuration ..................................................................................19

Requirements for Reading Array Data .......................................................... 19

Writing Commands/Command Sequences .................................................. 19

Standby Mode .......................................................................................................20

Automatic Sleep Mode ....................................................................................... 21

RESET#: Hardware Reset Pin .......................................................................... 21

Output Disable Mode ......................................................................................... 21

Table 5. S29GL016A (Model R1) Top Boot Sector Addresses ...... 22

Table 6. S29GL016A (Model R2) Bottom Boot Sector

Address es . ...... ...... ...... ..... ...... ...... ...... ...... ...... ........ ...... ...... . 22

Table 7. S29GL03 2 A (M o d e ls R 1, R2) Sec t or Ad d re s s es ............ 23

Table 8. S29GL032A (Model R3) Top Boot Sector Addresses ...... 24

Table 9. S29GL032A (Model R4) Bottom Boot Sector Addresses . 24 Table 10 . S 2 9 GL 064A (M o d els R1, R2, R 8 , R 9 ) S ector Add r es se s 25 Table 11. S29GL064A (Model R3) Top Boot Sector

Address es . ...... ...... ...... ..... ...... ...... ...... ...... ...... ........ ...... ...... . 26

Table 12. S29GL0 64A (M o del R 4) Bottom Boot Sector Addresses 27

Table 13 . S 2 9 G L064A (M o d el R5 ) Se c tor A d d re s se s ................. 28

Table 14 . S 2 9 G L 0 64 A ( M o d el s R 6 , R 7 ) S e ct o r Addresse s .......... 29

Autoselect Mode .................................................................................................30

Table 15 . A u to s el ec t C o d es , (H igh Voltag e M et h o d ) .. .. ... ... ... .... 31

Sector Group Protection and Unprotection ................................................31

Table 16. S29GL016A (Model R1) Sector Group Protection/

Unprote c ti o n A d d resses ................. ... ... ... ... ... ...... ... .. ... ... ... ... . 32

Table 17. S29GL016A (Model R2) Sector Group Protection/

Unprote c ti o n A d d resses ................. ... ... ... ... ... ...... ... .. ... ... ... ... . 32

Table 18. S29GL032A (Models R1, R2) Sector Group Protection/

Unprote c ti o n A d d resses ................. ... ... ... ... ... ...... ... .. ... ... ... ... . 32

Table 19. S29GL032A (Models R3) Sector Group Protection/

Unprote c ti o n A d d re s s Table ........... ... ... ... ... ... ... ... ... .. ... ...... ... . 32

Table 20. S29GL032A (Models R4) Sector Group Protection/

Unprote c ti o n A d d re s s Table ........... ... ... ... ... ... ... ... ... .. ... ...... ... . 33

Table 21 . S 2 9 G L064A (M o d el s R 1 , R 2 , R 8 , R 9) Sector G ro u p

Protectio n /U n p r o te c tio n Addres se s ..... ... ... ... ... ... ... ... ..... ... ... ... . 33

Table 22. S29GL064A (Model R3) Top Boot Sector Protection/

Unprote c ti o n A d d resses ................. ... ... ... ... ... ...... ... .. ... ... ... ... . 33

Table 23. S29GL064A (Model R4) Bottom Boot Sector Protection/

Unprote c ti o n A d d resses ................. ... ... ... ... ... ...... ... .. ... ... ... ... . 34

Table 24. S29GL064A (Model R5) Sector Group Protection/

Unprote c ti o n A d d resses ................... ... ... ... ... ... ... ... .. ... ... ... ... ..34

Table 25. S29GL064A (Models R6, R7) Sector Group Protection/

Unprote c ti o n A d d resses ................... ... ... ... ... ... ... ... .. ... ... ... ... ..34

Temporary Sector Group Unprotect ............................................................35

Figure 1 . Te mporary S ec t or Gr o u p U n pr o te c t Operatio n............ 35

Figure 2. In-System Sector Group Protect/Unprotect Algorithms 36

Secured Silicon Sector Flash Memory Region ............................................ 37

Write Protect (WP#) ........................................................................................38

Hardware Data Protection ...............................................................................38

Common Flash Memory Interface (CFI) . . . . . . 40

Table 26 . C F I Q uery Ident ifi ca ti o n S t r in g ............. ... .. ...... ... ... ..40

Command Definitions . . . . . . . . . . . . . . . . . . . . . 44

Reading Array Data ............................................................................................44

Reset Command ..................................................................................................44

Autoselect Command Sequence .....................................................................45

Enter/Exit Secured Silicon Sector Command Sequence .......................... 45

Figure 3 . W r it e B u ff er P r og r a m m i n g Operatio n . ... ... ... .. ...... ... ... . 49

Figure 4 . P ro g ra m Operatio n................... ... ... ... ... ... .. ... ... ... .... 50

Program Suspend/Program Resume Command Sequence .....................50

Figure 5 . P ro g ra m Suspen d /P ro g ram Res u me......................... . 51

Chip Erase Command Sequence ..................................................................... 51

Sector Erase Command Sequence . . . . . . . . . . . 53

Figure 6 . E ra se Operatio n............................. ... ... ... .. ... ... ... ... . 54

Erase Suspend/Erase Resume Commands ...................................................54

Command Definitions .........................................................................................56

Table 30. Comm and Defi nitions (x16 M o de, B YTE# = VIH) ........ 56

Table 31. Comm an d D efini tions (x8 Mode, BYTE# = V

) ..........57

Write Operation Status .................................................................................... 58

DQ7: Data# Polling .............................................................................................58

Figure 7 . D a ta # Polling Algorith m........................... .. ... ... ... ... . 59

RY/BY#: Ready/Busy# ........................................................................................59

DQ6: Toggle Bit I ................................................................................................60

Figure 8 . To ggle Bit A lg o ri thm.. ... ... ...... ... ... ... ... ... ... .. ... ... ... ... . 61

DQ2: Toggle Bit II ............................................................................................... 62

Reading Toggle Bits DQ6/DQ2 .......................................................................62

DQ5: Exceeded Timing Limits .........................................................................62

DQ3: Sector Erase Timer .................................................................................63

DQ1: Write-to-Buffer Abort ............................................................................ 63

Table 32 . Write Op er at ion Status ........................ ... .. ... ... ... ... ..63

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 64

Figure 9 . M a x im u m Nega tiv e O vershoot W a v e fo r m ........ ... ... .... 64

Figure 1 0. M aximum P o s itiv e O v er s h o o t Wavefo rm.................. 6 4

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 65

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 66

CMOS Compatible ..............................................................................................66

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 1 1. Test Set up.................... ... ... ... ... ... ... ...... .. ... ... ... ... . 67

Table 33 . T e s t S p e c ific at io n s ........................... ... ... .. ... ... ...... ..67

Figure 1 2 . I np u t Waveforms and M easurement Le v el s.............. 67

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 34 . R e a d - O nl y O peration s-S29GL0 6 4A Only ...... ... ... ... ... ..68

Table 35 . R e a d - O nl y O peration s-S29GL0 3 2A Only ...... ... ... ... ... ..68

Table 36 . R e a d - O nl y O peration -S 2 9 G L 0 16 A Only ................... ..69

Figure 1 3. R e a d Operati o n T imings ............. ... ... ... ... .. ... ... ... ... . 69

Figure 1 4. Page Re a d Ti mings .............. ... ... ... ... ... ... .. ...... ... ... . 70

Table 37 . Hardwa re Reset ( R E SET#) ...................... .. ...... ... ... ..70

Figure 1 5. R e s e t Timings........................... ... ...... ... .. ... ... ... ... . 71

Table 38 . E ra se a n d Pr o gr a m Operatio ns -S 2 9 GL064A ...............72

Table 39 . E ra se a n d Pr o gr a m Operatio ns -S 2 9 GL032A Only ........73

Table 40 . E ra se a n d Pr o gr a m Operatio ns -S 2 9 GL016A Only ........74

4 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

Figure 1 6. Program Opera t io n T imings...... ... ... ... ... ... .. ... ... ... ... . 75

Figure 1 7. Acceler at e d Pr o gr a m Timing D ia g ra m .. ... ... .. ... ... ... ... . 75

Figure 1 8. C hip/Sec to r E r as e O p e ra ti on T imings....................... 76

Figure 19. Data# Polling Timings

(During Embedde d A lg o rit h ms) ....... ... ... ... ... ... ... ... ... .. ... ... ... ... . 76

Figure 20. Toggle Bit Timings (During Embedded Algorithms)..... 77

Figure 2 1. DQ2 vs. D Q 6... .. ... ... ... ... ... ... ... ... ... ... ...... .. ... ... ... ... . 7 7

Table 41 . Tempor a ry S e ct o r U nprotect .................... .. ...... ... ... . 77

Figure 22. Temporary Sector Group Unprotect Timing Diagram .. 78 Figure 23. Sector Group Protect and Unprotect Timing Diagram.. 78 Table 42. Alternate CE# Controlled Erase and Program

Operations-S29GL064A ........................................................ 79

Table 43. Alternate CE# Controlled Erase and Program

Operations-S29GL032A ........................................................ 80

Table 44. Alternate CE# Controlled Erase and Program

Operations-S29GL016A ........................................................ 81

Figure 24. Alternate CE# Controlled Write (Erase/Program )

Operat ion Timing s...................... ... ... ... ... ... ... ... ... ... .. ... ... ...... . 8 2

Erase And Programming Performance . . . . . . . 83

Table 45 . T S O P Pin and BGA Pack a ge C a pacitanc e ..... ... ... ... ... ..83

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 84

TS048—48-Pin Standard Thin Small Outline Package (TSOP) .............84

TS056—56-Pin Standard Thin Small Outline Package (TSOP) ..............85

LAA064—64-Ball Fortified Ball Grid Array (BGA) ...................................86

VBN048—48-Ball Fine-pitch Ball Grid Array (BGA)

10x 6 mm Package ...............................................................................................87

VBK048—Ball Fine-pitch Ball Grid Array (BGA)

8.15x 6.15 mm Package ........................................................................................88

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 89

Revision A (October 13, 2004) ........................................................................89

Revision A1 (December 17, 2004)s .................................................................89

Revision A2 (January 28, 2005) .......................................................................89

Revision A3 (April 20, 2005) ............................................................................89

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 5

Page 8

Product Selector Guide

S29GL064A, S29GL032A, S29GL016A

Advance Information

Part Number

Speed Option Max. Access Time (ns) 90 100 110 90 100 110 90 100 Max. CE# Access Time (ns) 90 100 110 90 100 110 90 100 Max. Page Access Time (ns) 25 30 30 25 30 30 25 30 Max. OE# Access Ti me (ns) 25 30 30 25 30 30 25 30

S29GL064A S29GL032A S29GL016A

90 10 11 90 10 11 90 10

6 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 9

Block Diagram

Advance Information

RESET#

WE#

WP#/ACC

BYTE#

CE#

OE#

RY/BY#

State

Control

Command

VCC Detector

PGM Voltage

Generator

Timer

Sector Switches

Erase Voltage

Generator

STB

Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

DQ15–DQ0 (A-1)

Input/Output

Buffers

STB

Y-Gating

Cell Matrix

Data

Latch

Max

Note:

**A **A **A

**–A0

MAX

GL032A = A20.

MAX

GL016A = A19.

MAX

Address Latch

GL064A = A21.

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 7

Page 10

Connection Diagrams

Advance Information

A15 A14 A13 A12 A11 A10

A19 A20

WE#

RESET#

A21

WP#/ACC

RY/BY#

A18 A17

A9 A8

1,2

A7 A6 A5 A4 A3 A2 A1

1 3

1 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48-Pin Standard TSOP

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A16

BYTE# V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V

CC DQ11 DQ3 DQ10

DQ2 DQ9 DQ1 DQ8 DQ0 OE#

SS CE# A0

Notes:

1. Pin 9 is A21, Pin 13 is ACC, Pin 14 is WP#, Pin 15 is A19, and Pin 47 is VIO on S29GL064A (models R6, R7).

2. Pin 13 is NC on S29GL032A, and S29GL016A.

3. Pin 10 is NC on S29GL016A.

NC A15 A14

A13

A12 A11 A10

A8 A19 A20

WE#

RESET#

A21

WP#/ACC

RY/BY#

A18 A17

NC NC

1 2 3 4 5 6 7 8

9 10 11

56-Pin Standard TSOP

12 13 14

15 16 17 18 19 20 21 22 23 24 25 26 27 28

A16

BYTE#

V DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

35 34

OE#

V CE#

Notes:

1. Pin 15 is NC on S29GL032A.

8 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

64-ball Fortified BGA

Top View, Balls Facing Down

A8 C8

A7 C7 D7 E7 F7 G7 H7

A6 C6 D6 E6 F6 G6 H6

A5 C5 D5 E5 F5 G5 H5

A4 C4 D4 E4 F4 G4 H4

A3 C3 D3 E3 F3 G3 H3

A2 C2 D2 E2 F2 G2 H2

A1 C1 D1 E1 F1 G1 H1

B8 D8 E8 F8 G8 H8

NCNCNC

RESET#WE#

A18WP#/ACCRY/BY#

A16A15A14A12A13

NCNCNCNCNC

NCV

DQ15/A-1VSSBYTE#

DQ13 DQ6DQ14DQ7A11A10A8A9

CC DQ4DQ12DQ5A19A21

DQ11 DQ3DQ10DQ2A20

DQ9 DQ1DQ8DQ0A5A6A17A7

OE#

SSCE#A0A1A2A4A3

Notes:

1. Ball D8 and Ball F1 are NC on S29GL064A (models R3, R4).

2. Ball F7 is NC on S29GL064A (model R5).

3. Ball C5 is NC on S29GL032A and S29GL016A.

4. Ball D4 is NC on S29GL016A.

Special Package Handling Instructions

Special handling is required for Flash Memory products in moulded packages (TSOP and BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 9

Page 12

Advance Information

48-ball Fine-pitch BGA

Top View, Balls Facing Down

A6 B6 C6 D6 E6 F6 G6 H6

A16A15A14A12A13

A5 B5 C5 D5 E5 F5 G5 H5

A4 B4 C4 D4 E4 F4 G4 H4

RESET#WE#

A3 B3 C3 D3 E3 F3 G3 H3

A2 B2 C2 D2 E2 F2 G2 H2

A18WP#/ACCRY/BY#

DQ15/A-1VSSBYTE#

DQ13 DQ6DQ14DQ7A11A10A8A9

CC DQ4DQ12DQ5A19A21

DQ11 DQ3DQ10DQ2A20

DQ9 DQ1DQ8DQ0A5A6A17A7

A1 B1 C1 D1 E1 F1 G1 H1

Notes:

1. Ball F6 is VIO on S29GL064A (model R5).

2. Ball C4 is NC on S29GL032A and S29GL016A.

3. Ball D3 is NC on S29GL016A.

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods o f time.

OE#

SSCE#A0A1A2A4A3

10 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 13

Pin Descriptions

A21–A0 = 22 Address inputs A20–A0 = 21 Address inputs A19–A0 = 20 Address inputs DQ7–DQ0 = 8 Data inputs/outputs DQ14–DQ0 = 15 Data inputs/outputs DQ15/A-1 = DQ15 (Data input/output, word mode), A-1 (LSB

CE# = Chip Enab le input OE# = Output Enable input WE# = Write Enable input WP#/ACC = Hardware Write Pro tect input/Programming

ACC = Acceleration input WP# = Hardware Write Protect inp ut RESET# = Hardware Reset Pin inpu t RY/BY# = Ready/Busy output BYTE# = Selects 8-bit or 16-bit mode VCC = 3.0 volt-only singl e p ower supply

NC = Pin Not Connected Internal ly V

Advance Information

Address input, byte mode)

Acceleration input

(see Product Selector Guide for speed options and voltage supply

=Device Ground

= Output Buffer Power

tolerances)

Logic Symbols

Logic Symbol–S29GL064A (Models R1, R2, R8, R9)

A21–A0

CE# OE# WE#

WP#/ACC RESET# BYTE#

16 or 8

DQ15–DQ0

(A-1)

RY/BY#

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 11

Page 14

Advance Information

Logic Symbol–S29GL064A (Models R3, R4)

A21–A0

CE# OE# WE#

WP#/ACC RESET#

DQ15–DQ0

(A-1)

16 or 8

BYTE#

RY/BY#

Logic Symbol–S29GL064A (Model R5)

A21–A0

CE# OE#

WE# ACC

RESET#

DQ15–DQ0

RY/BY#

Logic Symbol–S29GL064A (Models R6, R7)

A21–A0

CE#

DQ15–DQ0

OE# WE# WP# ACC

RESET#

RESET# V

12 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 15

Advance Information

Logic Symbol–S29GL032A (Models R1, R2)

A20–A0

CE# OE# WE#

WP#/ACC RESET#

BYTE#

DQ15–DQ0

(A-1)

RY/BY#

Logic Symbol–S29GL032A (Models R3, R4)

A20–A0

CE#

DQ15–DQ0

(A-1)

16 or 8

OE# WE#

WP#/ACC RESET#

RY/BY#

BYTE#

Logic Symbol–S29GL016A (Models R1, R2)

A19–A0

CE# OE# WE#

WP#/ACC RESET#

BYTE#

DQ15–DQ0

(A-1)

RY/BY#

16 or 8

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 13

Page 16

Advance Information

Ordering Information–S29GL016A

S29GL016A Standard Products

Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:

S29GL016A 10 T A I R1 0

PACKING TYPE

0= Tray 2= 7-inch Tape and Reel 3 = 13-inch Tape and Reel

Additional Ordering Options

R1 = x8/x16, VCC=3.0-3.6V , T op boot sector device, top two address sectors

R2 = x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two

TEMPERATURE RANGE

I = Industrial (–40°C to +85°C) E = Engineering Samples (ava ilab le pr ior to Produc tio n Release only)

PACKAGE MATERIAL SET

A= Standard F= Pb-Free

PACKAGE TYPE

T = Thin Small Outline Package (TSOP) Standard Pinout B = Fine-pitch Ball-Grid Array Package F = Fortified Ball-Grid Array Package

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

S29GL016A

3.0 Volt-only, 16 Megabit Page-Mode Flash Memory Manufactured on 200 nm MirrorBit™ Process Technology.

protected when WP#/ACC=V

address sectors protected when WP#/ACC=V

Table 1. S29GL016A Ordering Options

S29GL016A Valid Combinations

Number

S29GL016A 90, 10

Speed

Option

Package, Material,

& Temperature Range

TAI,TFI

BAI,BFI

FAI,FFI

Model

Number

R1, R2

Packing

Type

0,2,3

(Note 1)

TS048 (Note 2) TSOP VBK048 (Note 3) Fine-Pitch BGA LAA064 (Note 3) Fortified BGA

Note:

1. Type 0 is standard. Specify others as required: TSOP’s can be packed in Types 0 and 3; BGA’s can be packed in Types 0, 2, or 3.

2. TSOP package marking omits packing type designator from orde ring part number.

3. BGA package marking omit s leading S29 and packing type designator from orde ring part number.

Valid Combinations

Valid C ombinatio ns li st c onfi gurations planned to be supp ort ed i n v olume for t his device. Consult your loc al sales offi ce to confirm av ailabili ty of specific valid com binations and to check on newly released combinations.

Package Description

(Notes)Device

14 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 17

Advance Information

Ordering Information–S29GL032A

S29GL032A Standard Products

Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:

S29GL032A 90 T A I R1 0

PACKING TYPE

0= Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel

MODEL NUMBER

R1 = x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address sector

R2 = x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector

R3 = x8/x16, VCC=3.0-3.6V , T op boot sector device, top two address sectors

R4 = x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two

TEMPERATURE RANGE

I = Industrial (–40°C to +85°C) E = Engineering Samples (available prior to Production Release only)

protected when WP#/ACC=V

address sectors protected when WP#/ACC=V

DEVICE NUMBER/DESCRIPTION

S29GL032A 32 Megabit Page-Mode Flash Memory Manufactured using 200 nm MirrorBit™ Process Technology, 3.0 Volt-only Read, Program, and Erase

Device

Number

S29GL032A 90, 10, 11

Speed

Option

PACKAGE MATERIAL SET

A= Standard F= Pb-Free

PACKAGE TYP E

T = Thin Small Outline Pac kage (TS OP) Stan da rd Pinout B = Fine-pitch Ball-Grid Array Package F = Fortified Ball-Grid Array Package

SPEED OPTION

See Product Selector Guide and Valid Combinations

Ta b le 2. S29GL032A Ordering Options

S29GL032A Valid Combinations

Package, Material,

& Temperature Range

TAI,TFI FAI,FFI LAA064 (Note 3) Fortif ied BGA TAI,TFI

BAI,BFI VBN048 (Note 3) Fine-Pitch BGA

FAI,FFI LAA064 (Note 3) Fortif ied BGA

Model

Number

R1, R2

R3 ,R4

Packing

Type

0,2,3

(Note 1)

Package Description

(Notes)

TS056 (Note 2) TSOP

TS048 (Note 2) TSOP

Notes:

1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Type s 0, 2, or 3.

2. TSOP package marking omits packing type designator from the ordering part number.

3. BGA package marking omits lead ing “S29” and packi ng type designator from the ordering part n um ber.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid com

binations and to check on newly released combinations.

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 15

Page 18

Advance Information

Ordering Information–S29GL064A

S29GL064A Standard Products

Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:

S29GL064A 90 T A I R1 2

PACKING TYPE

0 = Tray 2 = 7” Tape and Reel 3 = 13” Tape and Reel

MODEL NUMBER

R1 = x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address

R2 = x8/x16, VCC=3.0-3. 6V, Uniform sec tor device , lowest address se ctor

R3 = x8/x16, VCC=3.0-3.6V, Top boot sector device, top two address

R4 = x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two

R5 = x16, VCC=3.0-3.6V, Uniform sector device R6 = x16, V

R7 = x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector

R8 = x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address

R9 = x8/x16, V

TEMPERATURE RANGE

I = Industrial (–40°C to +85°C) E = Engineering Samples (available prior to Production Release only)

PACKAGE MATERIAL SET

A= Standard F= Pb-Free

sector pro t e c ted when WP #/ACC=V

protected when WP#/ ACC=V

sectors p rotected wh en WP#/ACC=V

address sectors protected when WP#/ACC=V

=3.0-3.6V, Uniform sector device, highest addr ess sector

protected when WP#=V

sector pro t e c ted when WP #=V

protected when WP#=V

=3.0-3. 6V, Uniform sec tor device , lowest address se ctor

TSO48 only

IL,

TSO48 only

IL,

PACKAGE TYP E

T = Thin Small Outline Package ( TSO P) Stan dar d Pinout B = Fine-pitch Ball-Grid Array P a ckag e F = Fortified Ball-Grid Array Package

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

S29GL064A, 64 Megabit Page-Mode Flash Memory Manufactured using 200 nm MirrorBit Process Technology, 3.0 Volt- only R e ad , Progr am, and Er as e

16 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 19

Advance Information

Ta b le 3. S29GL064A Valid Combinations

S29GL064A Valid Com binations

Device Number Speed Option

S29GL064A 90, 10, 11

Package, Material & Temperature Range

TAI, TFI

BAI, BFI R3, R4, R5

FAI, FFI R1, R2, R3, R4, R5

Model Number Packing Type

R3, R4, R6, R7, R8, R9

R1, R2

0, 2, 3

(Note 1)

Notes:

1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.

2. TSOP package marking omits packing type designator from orde ring part number.

3. BGA package marking omit s leading S29 and packing type designator from orde ring part number.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid com binations and to check on newly released combinations.

Package Description

TS048 (Note 2) TSOP

TS056 (Note 2) TSOP VBN048 (Note 3) Fine-pitch BGA LAA064 (Note 3) Fortified BGA

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 17

Page 20

Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command regis ter itself does not occupy any addressable m emory location. The register is a latch used to store the commands, along with the address and data informati on needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. require, and the resulting output. The following subsections describe each of these operations in further detail.

Table 4 lists the device bus operations, the inputs and control levels they

Advance Information

Ta b le 4. Device Bus Operations

DQ8–DQ15

Addresses

Operation CE# OE# WE# RESET# WP# ACC

(

Note 1)

Read L L H H X X A Write (Prog ram/Er ase) L H L H (Note 3) X A Accelerated Program L H L H (Note 3) V

Standby

VCC ±

0.3 V

X X

VCC ±

0.3 V

X H X High-Z High-Z High-Z

DQ0–

DQ7

OUT

BYTE#

= V

OUT

(Note 4) (Note 4) (Note 4) (Note 4)

BYTE#

= V

DQ8–DQ14

= High-Z,

DQ15 = A-1

Output Disable L H H H X X X High-Z High-Z High-Z Reset X X X L X X X High-Z High-Z High-Z

Sector Group Protect (Note 2)

L H L V

H X

Sector Group Unprotect

L H L V

H X

(Note 2) Temporary Sector

Group Unprotect

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, D

Notes:

1. Addresses are Amax:A0 in word mode; Amax:A-1 in byte mode. Sector addresses are Amax:A15 in both modes.

2. The sector protect and sector un pr otect fun cti ons may als o be implement ed vi a pr og rammin g equi pment . See the “Sector Group Protection and Unprotection” section.

3. If WP# = VIL, the first or last sector remains prote cted (for unif orm sector devic es), and the two o uter boot sect ors are protected (for boot sector devices). If WP# = VIH, the first or last sector, or the two ou ter boot sectors are protected or unprotected as determined by the method described in Sector Group Protection and Unprotection

X X X V

OUT

= Data Out

H X A

SA, A6 =L, A3=L, A2=L, A1=H, A0=L

SA, A6=H, A3=L, A2=L, A1=H, A0=L

(Note 4) X X

(Note 4) (Note 4) High-Z

on page 31. All sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory

protected depending on version ordered.)

4. DIN or D

as required by co mmand se quenc e, data po lli ng, or se ctor pr otect algori thm (s ee Fi gure 7, on p age 57).

OUT

18 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 21

Advance Information

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic 1, the devic e is in word con figuration, DQ0–DQ15 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/ O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V control and gates array data to the output pins. WE# should remain at V

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the mem ory content occurs during the power transition. No command is nece ssary in this mode to obtain array data. Standard microprocessor read c ycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

. CE# is the power control and selects the device. OE# is the output

See R eading Array Data on page 43 for more information. Refer to the AC R eadOnly Operations table for timing specifications and the timing diagram. Refer to the DC Characteristics table for the active current specificat ion on reading arr ay data.

Page Mode Read

The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a pa ge. The page size of the devi ce is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2. Address bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is an asynchronous operat ion; the microprocessor sup plies the specific word location.

The random or initial page access is equal to t read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t for a subsequent access, the access time is t are obtained by keeping the read-page addresses constant and changing the intra-read page addresses.

. When CE# is deasserted and reasserted

PACC

ACC

or tCE. Fas t page mo de acces ses

ACC

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re quired to program a word, instead of four. The Wo rd P rog ram C om man d

Sequence on pa ge 44 contains details on programming data to the device using

both standard and Unlock Bypass command sequences.

, and OE# to VIH.

or tCE and subsequent page

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 19

Page 22

Advance Information

An erase operation can erase one sector, multiple sectors, or the entire device.

Tables

Refer to the DC Characteristics table for the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.

7 – 25 indicate the address space that each sector occupies.

Write Buffer

page 20 for more information.

Accelerated Program Operation

The device offers accelerated program operations through the ACC funct ion. This is one of two functions provided by the WP#/ACC or ACC pin, depending on model number. This function is primarily intended to allow faster manufacturing throughput at the factory.

If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the p in to reduce the time required for program operations. The system would use a two-cycle program command se quence as required by the Unlock Bypass mode. Removing VHH from the WP#/ ACC or ACC pin, depending on model number, returns the device to norm al op eration. Note that the WP#/ACC or ACC pin must not be at VHH for operati ons

other than accelerated programming, or device dam age may result. WP# con tains an internal pullup; when unconnected, WP# is at VIH.

Autoselect Functions

If the system writes the autoselect com mand sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to

toselect Command Sequence on page 44 for more information.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V

.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device

is in the standby mode, but the standby current is greater. The device requires standard access time (t standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

Refer to the DC Characteris tics on page 64 for the standby current specificat ion.

Autoselect Mode on page 30 and Au-

± 0.3 V. (Note that this is a more restricted voltage range than

) for read access when the device is in either of these

20 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 23

Advance Information

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t

ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-

30 trol signals. Standard address access timings provide new da t a w hen ad d res s es are changed. While in sleep mode, output data is latched and always available to the system. Refer to the sleep mode current specification.

DC Characteristics on page 64 for the automatic

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal sta te ma chine to reading ar r ay data . The op eration that was interrupt ed should be reinitiate d once the device is re ady to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESE T# p ulse . Whe n R E SET# is held

±0.3 V, the device draws CMOS standby current (I

at V

but not withi n VSS±0.3 V, the standby current is greater.

at V

The RESET# pin may be tied to the system reset circuitry . A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm ware from the Flash memo ry.

). If RESET# is held

CC5

ACC

, the

Refer to the AC Characteristics tables for RES E T# parameters an d to Figure 15,

on page 69 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 21

Page 24

Advance Information

Ta b le 5. S29GL016A (Model R1) Top Boot Sector Addresses

Sector

Sector A19–A12

SA0 000000xxx 64/32 000000h–00FFFFh 00000h–07FFFh SA20 010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh SA1 000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh SA2 000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA3 000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA4 000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA5 000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA6 000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA7 000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA8 001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh

SA9 001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA10 001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA11 001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA12 001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh SA13 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh SA14 001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh SA15 001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh SA16 010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh SA17 010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh SA18 010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh SA19 010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Sector A19–A12

SA21 010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh SA22 010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh SA23 010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh SA24 011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh SA25 011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh SA26 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh SA27 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh SA28 011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh SA29 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh SA30 011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh SA31 111111000 8/4 1F0000h–1F1FFFh 0F8000h–0F8FFFh SA32 111111001 8/4 1F2000h–1F3FFFh 0F9000h–0F9FFFh SA33 111111010 8/4 1F4000h–1F5FFFh 0FA000h–0FAFFFh SA34 111111011 8/4 1F6000h–1F7FFFh 0FB000h–0FBFFFh SA35 111111100 8/4 1F8000h–1F9FFFh 0FC000h–0FCFFFh SA36 111111101 8/4 1FA000h–1FBFFFh 0FD000h–0FDFFFh SA37 111111110 8/4 1FC000h–1FDFFFh 0FE000h–0FEFFFh SA38 111111111 8/4 1FE000h–1FFFFFh 0FF000h–0FFFFFh

Sector

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Ta bl e 6 . S29GL016A (Model R2) Bottom Boot Sector Addresses

Sector

Sector A19–A12

SA0 000000000 8/4 000000h–001FFFh 00000h–00FFFh SA19 001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh

SA1 000000001 8/4 002000h–003FFFh 01000h–01FFFh SA20 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh

SA2 000000010 8/4 004000h–005FFFh 02000h–02FFFh

SA3 000000011 8/4 006000h–007FFFh 03000h–03FFFh

SA4 000000100 8/4 008000h–009FFFh 04000h–04FFFh

SA5 000000101 8/4 00A000h–00BFFFh 05000h–05FFFh

SA6 000000110 8/4 00C000h–00DFFFh 06000h–06FFFh

SA7 000000111 8/4 00E000h–00FFFFFh 07000h–07FFFh

SA8 000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh

SA9 000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA10 000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA11 000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA12 000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA13 000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA14 000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA15 001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA16 001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA17 001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA18 001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Sector A19–A12

SA21 001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh SA22 001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh SA23 010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh SA24 010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh SA25 010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh SA26 010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh SA27 010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh SA28 010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh SA29 010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh SA30 010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh SA31 011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh SA32 011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh SA33 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh SA34 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh SA35 011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh SA36 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh SA37 011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh SA38 011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh

Sector

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

22 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 25

Advance Information

Ta b le 7. S29GL032A (Models R1, R2) Sector Addresses

Sector

Sector A20-A15

SA0 000000 64/32 000000–00FFFF 000000–007FFF SA32 100000 64/32 200000–20FFFF 100000–107FFF SA1 000001 64/32 010000–01FFFF 008000–00FFFF SA33 100001 64/32 210000–21FFFF 108000–10FFFF SA2 000010 64/32 020000–02FFFF 010000–017FFF SA34 100010 64/32 220000–22FFFF 110000–117FFF SA3 000011 64/32 030000–03FFFF 018000–01FFFF SA35 100011 64/32 230000–23FFFF 118000–11FFFF SA4 000100 64/32 040000–04FFFF 020000–027FFF SA36 100100 64/32 240000–24FFFF 120000–127FFF SA5 000101 64/32 050000–05FFFF 028000–02FFFF SA37 100101 64/32 250000–25FFFF 128000–12FFFF SA6 000110 64/32 060000–06FFFF 030000–037FFF SA38 100110 64/32 260000–26FFFF 130000–137FFF SA7 000111 64/32 070000–07FFFF 038000–03FFFF SA39 100111 64/32 270000–27FFFF 138000–13FFFF SA8 001000 64/32 080000–08FFFF 040000–047FFF SA40 101000 64/32 280000–28FFFF 140000–147FFF

SA9 001001 64/32 090000–09FFFF 048000–04FFFF SA41 101001 64/32 290000–29FFFF 148000–14FFFF SA10 001010 64/32 0A0000–0AFFFF 050000–057FFF SA42 101010 64/32 2A0000–2AFFFF 150000–157FFF SA11 001011 64/32 0B0000–0BFFFF 058000–05FFFF SA43 101011 64/32 2B0000–2BFFFF 158000–15FFFF SA12 001100 64/32 0C0000–0CFFFF 060000–067FFF SA44 101100 64/32 2C0000–2CFFFF 160000–167FFF SA13 001101 64/32 0D0000–0DFFFF 068000–06FFFF SA45 101101 64/32 2D0000–2DFFFF 168000–16FFFF SA14 001110 64/32 0E0000–0EFFFF 070000–077FFF SA46 101110 64/32 2E0000–2EFFFF 170000–177FFF SA15 001111 64/32 0F0000–0FFFFF 078000–07FFFF SA47 101111 64/32 2F0000–2FFFFF 178000–17FFFF SA16 010000 64/32 100000–10FFFF 080000–087FFF SA48 110000 64/32 300000–30FFFF 180000–187FFF SA17 010001 64/32 110000–11FFFF 088000–08FFFF SA49 110001 64/32 310000–31FFFF 188000–18FFFF SA18 010010 64/32 120000–12FFFF 090000–097FFF SA50 110010 64/32 320000–32FFFF 190000–197FFF SA19 010011 64/32 130000–13FFFF 098000–09FFFF SA51 110011 64/32 330000–33FFFF 198000–19FFFF SA20 010100 64/32 140000–14FFFF 0A0000–0A7FFF SA52 110100 64/32 340000–34FFFF 1A0000–1A7FFF SA21 010101 64/32 150000–15FFFF 0A8000–0AFFFF SA53 110101 64/32 350000–35FFFF 1A8000–1AFFFF SA22 010110 64/32 160000–16FFFF 0B0000–0B7FFF SA54 110110 64/32 360000–36FFFF 1B0000–1B7FFF SA23 010111 64/32 170000–17FFFF 0B8000–0BFFFF SA55 110111 64/32 370000–37FFFF 1B8000–1BFFFF SA24 011000 64/32 180000–18FFFF 0C 0000–0C7FFF SA56 111000 64/32 380000–38FFFF 1C0000–1C7FFF SA25 011001 64/32 1 SA26 011010 64/32 1A0000–1AFFFF 0D0000–0D7FFF SA58 111010 64/32 3A0000–3AFFFF 1D0000–1D7FFF SA27 011011 64/32 1B0000–1BFFFF 0D8000–0DFFFF SA59 111011 64/32 3B0000–3BFFFF 1D8000–1DFFFF SA28 011100 64/32 1C0000–1CFFFF 0E0000–0E7FFF SA60 111100 64/32 3C0000–3CFFFF 1E0000–1E7FFF SA29 011101 64/32 1D0000–1DFFFF 0E8000–0EFFFF SA61 111101 64/32 3D0000–3DFFFF 1E8000–1EFFFF SA30 011110 64/32 1E0000–1EFFFF 0F0000–0F7FFF SA62 111110 64/32 3E0000–3EFFFF 1F0000–1F7FFF SA31 011111 64/32 1F0000–1FFFFF 0F8000–0FFFFF SA63 111111 64/32 3F0000–3FFFFF 1F8000–1FFFFF

Size

(KB/

Kwords)

8-bit

Address

Range

90000–19FFFF 0C8000–0CFFFF SA57 111001 64/32 390000–39FFFF 1C8000–1CFFFF

16-bit

Address

Range

Sector A20-A15

Sector

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 23

Page 26

Advance Information

Ta b le 8. S29GL032A (Model R3) Top Boot Sector Addresses

Sector

Sector A20–A12

SA0 000000xxx 64/32 000000h–00FFFFh 00000h–07FFFh SA36 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh SA1 000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh SA37 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh SA2 000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA38 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh SA3 000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA39 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh SA4 000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA40 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh SA5 000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA41 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh SA6 000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA42 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh SA7 000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA43 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh SA8 001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA44 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh

SA9 001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA45 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh SA10 001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA46 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh SA11 001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA47 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh SA12 001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh SA48 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh SA13 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh SA49 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh SA14 001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh SA50 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh SA15 001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh SA51 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh SA16 010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh SA52 100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh SA17 010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh SA53 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh SA18 010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh SA54 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh SA19 010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh SA55 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh SA20 010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh SA56 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh SA21 010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh SA57 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh SA22 010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh SA58 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh SA23 010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh SA59 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh SA24 011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh SA60 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh SA25 011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh SA61 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh SA26 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh SA62 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh SA27 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh SA63 111111000 8/4 3F 0000h–3F1FFFh 1F8000h–1F8FFFh SA28 011100xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh SA64 111111001 8/4 3F2000h–3F3FFFh 1F9000h–1F9FFFh SA29 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh SA65 111111010 8/4 3F4000h–3F5FFFh 1FA000h–1FAFFFh SA30 011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh SA66 111111011 8/4 3F6000h–3F7FFFh 1FB000h–1FBFFFh SA31 011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh SA67 111111100 8/4 3F 8000h–3F9FFFh 1FC000h–1FCFFFh SA32 100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh SA68 111111101 8/4 3FA000h–3FBFFFh 1FD000h–1FDFFFh SA33 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh SA69 111111110 8/4 3FC000h–3FDFFFh 1FE000h–1FEFFFh SA34 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh S A70 111111111 8/4 3FE000h–3FFFFFh 1FF000h–1FFFFFh SA35 101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Sector A20–A12

Sector

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Ta b le 9. S29GL032A (Model R4) Bottom Boot Sector Addresses (Sheet 1 of 2)

Sector

Sector A20–A12

SA0 000000000 8/4 000000h–001FFFh 00000h–00FFFh SA19 001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh

SA1 000000001 8/4 002000h–003FFFh 01000h–01FFFh SA20 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh

SA2 000000010 8/4 004000h–005FFFh 02000h–02FFFh SA21 001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh

SA3 000000011 8/4 006000h–007FFFh 03000h–03FFFh SA22 001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh

SA4 000000100 8/4 008000h–009FFFh 04000h–04FFFh SA23 010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh

SA5 000000101 8/4 00A000h–00BFFFh 05000h–05FFFh SA24 010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh

SA6 000000110 8/4 00C000h–00DFFFh 06000h–06FFFh SA25 010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh

SA7 000000111 8/4 00E000h–00FFFFFh 07000h–07FFFh SA26 010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh

SA8 000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh SA27 010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh

SA9 000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA28 010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh SA10 000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA29 010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh SA11 000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA30 010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh SA12 000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA31 011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh SA13 000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA32 011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh SA14 000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA33 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh SA15 001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA34 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh SA16 001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA35 011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh SA17 001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA36 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh SA18 001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA37 011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Sector A20–A12

Sector

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

24 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 27

Advance Information

Table 9. S29GL032A (Model R4) Bottom Boot Sector Addresses (Sheet 2 of 2)

Sector

Sector A20–A12

SA38 011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh SA55 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh SA39 100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh SA56 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh SA40 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh SA57 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh SA41 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh SA58 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh SA42 101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh SA59 100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh SA43 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh SA60 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh SA44 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh SA61 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh SA45 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh SA62 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh SA46 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh SA63 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh SA47 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh SA64 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh SA48 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh SA65 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh SA49 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh SA66 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh SA50 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh SA67 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh SA51 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh SA68 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh SA52 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh SA69 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh SA53 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh SA70 111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh SA54 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Sector A20–A12

Sector

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Ta b le 10 . S29GL064A (Models R1, R2, R8, R9) Sector Addresses (Sheet 1 of 2)

Sector

Sector A21–A15

SA0 0000000 64/32 000000–00FFFF 000000–007FFF SA37 0100101 64/32 250000–25FFFF 128000–12FFFF SA1 0000001 64/32 010000–01FFFF 008000–00FFFF SA38 0100110 64/32 260000–26FFFF 130000–137FFF SA2 0000010 64/32 020000–02FFFF 010000–017FFF SA39 0100111 64/32 270000–27FFFF 138000–13FFFF SA3 0000011 64/32 030000–03FFFF 018000–01FFFF SA40 0101000 64/32 280000–28FFFF 140000–147FFF SA4 0000100 64/32 040000–04FFFF 020000–027FFF SA41 0101001 64/32 290000–29FFFF 148000–14FFFF SA5 0000101 64/32 050000–05FFFF 028000–02FFFF SA42 0101010 64/32 2A0000–2AFFFF 150000–157FFF SA6 0000110 64/32 060000–06FFFF 030000–037FFF SA43 0101011 64/32 2B0000–2BFFFF 158000–15FFFF SA7 0000111 64/32 070000–07FFFF 038000–03FFFF SA44 0101100 64/32 2C0000–2CFFFF 160000–167FFF SA8 0001000 64/32 080000–08FFFF 040000–047FFF SA45 0101101 64/32 2D 0000–2DFFFF 168000–16FFFF

SA9 0001001 64/32 090000–09FFFF 048000–04FFFF SA46 0101110 64/32 2E0000–2EFFFF 170000–177FFF SA10 0001010 64/32 0A0000–0AFFFF 050000–057FFF SA47 0101111 64/32 2F0000–2FFFFF 178000–17FFFF SA11 0001011 64/32 0B0000–0BFFFF 058000–05FFFF SA48 0110000 64/32 300000–30FFFF 180000–187FFF SA12 0001100 64/32 0C0000–0CFFFF 060000–067FFF SA49 0110001 64/32 310000–31FFFF 188000–18FFFF SA13 0001101 64/32 0D0000–0DFFFF 068000–06FFFF SA50 0110010 64/32 320000–32FFFF 190000–197FFF SA14 0001110 64/32 0E0000–0EFFFF 070000–077FFF SA51 0110011 64/32 330000–33FFFF 198000–19FFFF SA15 0001111 64/32 0F0000–0FFFFF 078000–07FFFF SA52 0110100 64/32 340000–34FFFF 1A0000–1A7FFF SA16 0010000 64/32 100000–10FFFF 080000–087FFF SA53 0110101 64/32 350000–35FFFF 1A8000–1AFFFF SA17 0010001 64/32 110000–11FFFF 088000–08FFFF SA54 0110110 64/32 360000–36FFFF 1B0000–1B7FFF SA18 0010010 64/32 120000–12FFFF 090000–097FFF SA55 0110111 64/32 370000–37FFFF 1B8000–1BFFFF SA19 0010011 64/32 130000–13FFFF 098000–09FFFF SA56 0111000 64/32 380000–38FFFF 1C0000–1C7FFF SA20 0010100 64/32 140000–14FFFF 0A0000–0A7FFF SA57 0111001 64/32 390000–39FFFF 1C8000–1CFFFF SA21 0010101 64/32 150000–15FFFF 0A8000–0AFFFF SA58 0111010 64/32 3A0000–3AFFFF 1D 0000–1D7FFF SA22 0010110 64/32 160000–16FFFF 0B0000–0B7FFF SA59 0111011 64/32 3B0000–3BFFFF 1D8000–1DFFFF SA23 0010111 64/32 170000–17FFFF 0B8000–0BFFFF SA60 0111100 64/32 3C0000–3CFFFF 1E0000–1E7FFF SA24 0011000 64/32 180000–18FFFF 0C0000–0C7FFF SA61 0111101 64/32 3D0000–3DFFFF 1E8000–1EFFFF SA25 0011001 64/32 190000–19FFFF 0C8000–0CFFFF SA62 0111110 64/32 3E0000–3EFFFF 1F0000–1F7FFF SA26 0011010 64/32 1A0000–1AFFFF 0D0000–0D7FFF SA63 0111111 64/32 3F0000–3FFFFF 1F8000–1FFFFF SA27 0011011 64/32 1B0000–1BFFFF 0D8000–0DFFFF SA64 1000000 64/32 400000–40FFFF 200000–207FFF SA28 0011100 64/32 1C0000–1CFFFF 0E0000–0E7FFF SA65 1000001 64/32 410000–41FFFF 208000–20FFFF SA29 0011101 64/32 1D0000–1DFFFF 0E8000–0EFFFF SA66 1000010 64/32 420000–42FFFF 210000–217FFF SA30 0011110 64/32 1E0000–1EFFFF 0F0000–0F7FFF SA67 1000011 64/32 430000–43FFFF 218000–21FFFF SA31 0011111 64/32 1F0000–1FFFFF 0F8000–0FFFFF SA68 1000100 64/32 440000–44FFFF 220000–227FFF SA32 0100000 64/32 200000–20FFFF 100000–107FFF SA69 1000101 64/32 450000–45FFFF 228000–22FFFF SA33 0100001 64/32 210000–21FFFF 108000–10FFFF SA70 1000110 64/32 460000–46FFFF 230000–237FFF SA34 0100010 64/32 220000–22FFFF 110000–117FFF SA71 1000111 64/32 470000–47FFFF 238000–23FFFF SA35 0100011 64/32 230000–23FFFF 118000–11FFFF SA72 1001000 64/32 480000–48FFFF 240000–247FFF SA36 0100100 64/32 240000–24FFFF 120000–127FFF SA73 1001001 64/32 490000–49FFFF 248000–24FFFF

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Sector A21–A15

Sector

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 25

Page 28

Advance Information

Table 10. S29GL064A (Models R1, R2, R8, R9) Sector Addresses (Sheet 2 of 2)

Sector

Sector A21–A15

SA74 1001010 64/32 4A0000–4AFFFF 250000–257FFF SA101 1100101 64/32 650000–65FFFF 328000–32FFFF SA75 1001011 64/32 4B0000–4BFFFF 258000–25FFFF SA102 1100110 64/32 660000–66FFFF 330000–337FFF SA76 1001100 64/32 4C0000–4CFFFF 260000–267FFF SA103 1100111 64/32 670000–67FFFF 338000–33FFFF SA77 1001101 64/32 4D0000–4DFFFF 268000–26FFFF SA104 1101000 64/32 680000–68FFFF 340000–347FFF SA78 1001110 64/32 4E0000–4EFFFF 270000–277FFF SA105 1101001 64/32 690000–69FFFF 348000–34FFFF SA79 1001111 64/32 4F0000–4FFFFF 278000–27FFFF SA106 1101010 64/32 6A 0000–6AFFFF 350000–357FFF SA80 1010000 64/32 500000–50FFFF 280000–287FFF SA107 1101011 64/32 6B0000–6BFFFF 358000–35FFFF SA81 1010001 64/32 510000–51FFFF 288000–28FFFF SA108 1101100 64/32 6C0000–6CFFFF 360000–367FFF SA82 1010010 64/32 520000–52FFFF 290000–297FFF SA109 1101101 64/32 6D0000–6DFFFF 368000–36FFFF SA83 1010011 64/32 530000–53FFFF 298000–29FFFF SA110 1101110 64/32 6E0000–6EFFFF 370000–377FFF SA84 1010100 64/32 540000–54FFFF 2A0000–2A7FFF SA111 1101111 64/32 6F0000–6FFFFF 378000–37FFFF SA85 1010101 64/32 550000–55FFFF 2A8000–2AFFFF SA112 1110000 64/32 700000–70FFFF 380000–387FFF SA86 1010110 64/32 560000–56FFFF 2B0000–2B7FFF SA113 1110001 64/32 710000–71FFFF 388000–38FFFF SA87 1010111 64/32 570000–57FFFF 2B8000–2BFFFF SA114 1110010 64/32 720000–72FFFF 390000–397FFF SA88 1011000 64/32 580000–58FFFF 2C0000–2C7FFF SA115 1110011 64/32 730000–73FFFF 398000–39FFFF SA89 1011001 64/32 590000–59FFFF 2C8000–2CFFFF SA116 1110100 64/32 740000–74FFFF 3A0000–3A7FFF SA90 1011010 64/32 5A0000–5AFFFF 2D0000–2D7FFF SA117 1110101 64/32 750000–75FFFF 3A8000–3AFFFF SA91 1011011 64/32 5B0000–5BFFFF 2D8000–2DFFFF SA118 1110110 64/32 760000–76FFFF 3B0000–3B7FFF SA92 1011100 64/32 5C0000–5CFFFF 2E0000–2E7FFF SA119 1110111 64/32 770000–77FFFF 3B8000–3BFFFF SA93 1011101 64/32 5D0000–5DFFFF 2E8000–2EFFFF SA120 1111000 64/32 780000–78FFFF 3C0000–3C7FFF SA94 1011110 64/32 5E0000–5EFFFF 2F0000–2F7FFF SA121 1111001 64/32 790000–79FFFF 3C8000–3CFFFF SA95 1011111 64/32 5F0000–5FFFFF 2F8000–2FFFFF SA122 1111010 64/32 7A0000–7AFFFF 3D0000–3D7FFF SA96 1100000 64/32 600000–60FFFF 300000–307FFF SA123 1111011 64/32 7B0000–7BFFFF 3D8000–3DFFFF SA97 1100001 64/32 610000–61FFFF 308000–30FFFF SA124 1111100 64/32 7C0000–7CFFFF 3E0000–3E7FFF SA98 1100010 64/32 620000–62FFFF 310000–317FFF SA125 1111101 64/32 7D0000–7DFFFF 3E8000–3EFFFF SA99 1100011 64/32 630000–63FFFF 318000–31FFFF SA126 1111110 64/32 7E0000–7EFFFF 3F0000–3F7FFF

SA100 1100100 64/32 640000–64FFFF 320000–327FFF SA127 1111111 64/32 7F0000–7FFFFF 3F8000–3FFFFF

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Sector A21–A15

Sector

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Ta b le 11 . S29GL064A (Model R3) Top Boot Sector Addresses (Sheet 1 of 2)

Sector

Sector A21–A15

SA0 0000000xxx 64/32 000000h–00FFFFh 00000h–07FFFh SA34 0100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh SA1 0000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh SA35 0101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh SA2 0000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA36 0100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh SA3 0000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA37 0100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh SA4 0000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA38 0100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh SA5 0000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA39 0100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh SA6 0000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA40 0101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh SA7 0000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA41 0101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh SA8 0001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA42 0101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh SA9 0001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA43 0101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh

SA10 0001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA44 0101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh SA11 0001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA45 0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh SA12 0001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh SA46 0101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh SA13 0001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh SA47 0101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh SA14 0001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh SA48 0110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh SA15 0001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh SA49 0110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh SA16 0010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh SA50 0110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh SA17 0010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh SA51 0110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh SA18 0010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh SA52 0100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh SA19 0010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh SA53 0110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh SA20 0010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh SA54 0110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh SA21 0010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh SA55 0110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh SA22 0010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh SA56 0111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh SA23 0010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh SA57 0111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh SA24 0011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh SA58 0111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh SA25 0011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh SA59 0111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh SA26 0011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh SA60 0111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh SA27 0011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh SA61 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh SA28 0011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh SA62 0111110xxx 64/32 3E0000h–3EFFFFh 1F 0000h–1F7FFFh SA29 0011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh SA63 0111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh SA30 0011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh SA64 1000000xxx 64/32 400000h–40FFFFh 200000h–207FFFh SA31 0011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh SA65 1000001xxx 64/32 410000h–41FFFFh 208000h–20FFFFh SA32 0100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh SA66 1000010xxx 64/32 420000h–42FFFFh 210000h–217FFFh SA33 0100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh SA67 1000011xxx 64/32 430000h–43FFFFh 218000h–21FFFFh

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Sector A21–A15

Sector

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

26 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 29

Advance Information

Table 11. S29GL064A (Model R3) Top Boot Sector Addresses (Sheet 2 of 2)

Sector

Sector A21–A15

SA68 1000100xxx 64/32 440000h–44FFFFh 220000h–227FFFh SA102 1100110xxx 64/32 660000h–66FFFFh 330000h–337FFFh SA69 1000101xxx 64/32 450000h–45FFFFh 228000h–22FFFFh SA103 1100111xxx 64/32 670000h–67FFFFh 338000h–33FFFFh SA70 1000110xxx 64/32 460000h–46FFFFh 230000h–237FFFh SA104 1101000xxx 64/32 680000h–68FFFFh 340000h–347FFFh SA71 1000111xxx 64/32 470000h–47FFFFh 238000h–23FFFFh SA105 1101001xxx 64/32 690000h–69FFFFh 348000h–34FFFFh SA72 1001000xxx 64/32 480000h–48FFFFh 240000h–247FFFh SA106 1101010xxx 64/32 6A0000h–6AFFFFh 350000h–357FFFh SA73 1001001xxx 64/32 490000h–49FFFFh 248000h–24FFFFh SA107 1101011xxx 64/32 6B0000h–6BFFFFh 358000h–35FFFFh SA74 1001010xxx 64/32 4A0000h–4AFFFFh 250000h–257FFFh SA108 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh SA75 1001011xxx 64/32 4B0000h–4BFFFFh 258000h–25FFFFh SA109 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh SA76 1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh SA110 1101110xxx 64/32 6E0000h–6EFFFFh 370000h–377FFFh SA77 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh SA111 1101111xxx 64/32 6F0000h–6FFFFFh 378000h–37FFFFh SA78 1001110xxx 64/32 4E0000h–4EFFFFh 270000h–277FFFh SA112 1110000xxx 64/32 700000h–70FFFFh 380000h–387FFFh SA79 1001111xxx 64/32 4F0000h–4FFFFFh 278000h–27FFFFh SA113 1110001xxx 64/32 710000h–71FFFFh 388000h–38FFFFh SA80 1010000xxx 64/32 500000h–50FFFFh 280000h–28FFFFh SA114 1110010xxx 64/32 720000h–72FFFFh 390000h–397FFFh SA81 1010001xxx 64/32 510000h–51FFFFh 288000h–28FFFFh SA115 1110011xxx 64/32 730000h–73FFFFh 398000h–39FFFFh SA82 1010010xxx 64/32 520000h–52FFFFh 290000h–297FFFh SA116 1110100xxx 64/32 740000h–74FFFFh 3A0000h–3A7FFFh SA83 1010011xxx 64/32 530000h–53FFFFh 298000h–29FFFFh SA117 1110101xxx 64/32 750000h–75FFFFh 3A8000h–3AFFFFh SA84 1010100xxx 64/32 540000h–54FFFFh 2A0000h–2A7FFFh SA118 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh SA85 1010101xxx 64/32 550000h–55FFFFh 2A8000h–2AFFFFh SA119 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh SA86 1010110xxx 64/32 560000h–56FFFFh 2B0000h–2B7FFFh SA120 1111000xxx 64/32 780000h–78FFFFh 3C 0000h–3C7FFFh SA87 1010111xxx 64/32 570000h–57FFFFh 2B8000h–2BFFFFh SA121 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh SA88 1011000xxx 64/32 580000h–58FFFFh 2C0000h–2C7FFFh SA122 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh SA89 1011001xxx 64/32 590000h–59FFFFh 2C8000h–2CFFFFh SA123 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh SA90 1011010xxx 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh SA124 1111100xxx 64/32 7C 0000h–7CFFFFh 3E0000h–3E7FFFh SA91 1011011xxx 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh SA125 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh SA92 1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh SA126 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh SA93 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh SA127 1111111000 8/4 7F0000h–7F1FFFh 3F8000h–3F8FFFh SA94 1011110xxx 64/32 5E0000h–5EFFFFh 2F0000h–2FFFFFh SA128 1111111001 8/4 7F2000h–7F3FFFh 3F9000h–3F9FFFh SA95 1011111xxx 64/32 5F0000h–5FFFFFh 2F8000h–2FFFFFh SA129 1111111010 8/4 7F4000h–7F5FFFh 3FA000h–3FAFFFh SA96 1100000xxx 64/32 600000h–60FFFFh 300000h–307FFFh SA130 1111111011 8/4 7F6000h–7F7FFFh 3FB000h–3FBFFFh SA97 1100001xxx 64/32 610000h–61FFFFh 308000h–30FFFFh SA131 1111111100 8/4 7F8000h–7F9FFFh 3FC000h–3FCFFFh SA98 1100010xxx 64/32 620000h–62FFFFh 310000h–317FFFh SA132 1111111101 8/4 7FA000h–7FBFFFh 3FD000h–3FDFFFh

SA99 1100011xxx 64/32 630000h–63FFFFh 318000h–31FFFFh SA133 1111111110 8/4 7FC000h–7FDFFFh 3FE000h–3FEFFFh SA100 1100100xxx 64/32 640000h–64FFFFh 320000h–327FFFh SA134 1111111111 8/4 7FE000h–7FFFFFh 3FF000h–3FFFFFh SA101 1100101xxx 64/32 650000h–65FFFFh 328000h–32FFFFh

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Sector A21–A15

Sector

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Ta b le 12 . S29GL064A (Model R4) Bottom Boot Sector Addresses (Sheet 1 of 2)

Sector

A21–A15

Sector

SA0 0000000000 8/4 000000h–001FFFh 00000h–00FFFh SA27 0010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh SA1 0000000001 8/4 002000h–003FFFh 01000h–01FFFh SA28 0010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh SA2 0000000010 8/4 004000h–005FFFh 02000h–02FFFh SA29 0010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh SA3 0000000011 8/4 006000h–007FFFh 03000h–03FFFh SA30 0010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh SA4 0000000100 8/4 008000h–009FFFh 04000h–04FFFh SA31 0011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh SA5 0000000101 8/4 00A000h–00BFFFh 05000h–05FFFh SA32 0011001xxx 64/32 190000h–19FFFFh C 8000h–CFFFFh SA6 0000000110 8/4 00C000h–00DFFFh 06000h–06FFFh SA33 0011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh SA7 0000000111 8/4 00E000h–00FFFFFh 07000h–07FFFh SA34 0011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh SA8 0000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh SA35 0011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh

SA9 0000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA36 0011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh SA10 0000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA37 0011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh SA11 0000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA38 0011111xxx 64/32 1F0000h–1FFFFFh F 8000h–FFFFFh SA12 0000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA39 0100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh SA13 0000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA40 0100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh SA14 0000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA41 0100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh SA15 0001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA42 0101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh SA16 0001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA43 0100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh SA17 0001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA44 0100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh SA18 0001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA45 0100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh SA19 0001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh SA46 0100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh SA20 0001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh SA47 0101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh SA21 0001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh SA48 0101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh SA22 0001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh SA49 0101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh SA23 0010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh SA50 0101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh SA24 0010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh SA51 0101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh SA25 0010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh SA52 0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh SA26 0010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh SA53 0101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh SA54 0101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh SA95 1011000xxx 64/32 580000h–58FFFFh 2C0000h–2C7FFFh

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

A21–A15

Sector

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 27

Page 30

Advance Information

Table 12. S29GL064A (Model R4) Bottom Boot Sector Addresses (Sheet 2 of 2)

Sector

A21–A15

Sector

SA55 0110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh SA96 1011001xxx 64/32 590000h–59FFFFh 2C 8000h–2CFFFFh SA56 0110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh SA97 1011010xxx 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh SA57 0110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh SA98 1011011xxx 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh SA58 0110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh SA99 1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh SA59 0100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh SA100 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh SA60 0110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh SA101 1011110xxx 64/32 5E0000h–5EFFFFh 2F0000h–2FFFFFh SA61 0110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh SA102 1011111xxx 64/32 5F0000h–5FFFFFh 2F8000h–2FFFFFh SA62 0110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh SA103 1100000xxx 64/32 600000h–60FFFFh 300000h–307FFFh SA63 0111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh SA104 1100001xxx 64/32 610000h–61FFFFh 308000h–30FFFFh SA64 0111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh SA105 1100010xxx 64/32 620000h–62FFFFh 310000h–317FFFh SA65 0111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh SA106 1100011xxx 64/32 630000h–63FFFFh 318000h–31FFFFh SA66 0111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh SA107 1100100xxx 64/32 640000h–64FFFFh 320000h–327FFFh SA67 0111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh SA108 1100101xxx 64/32 650000h–65FFFFh 328000h–32FFFFh SA68 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh SA109 1100110xxx 64/32 660000h–66FFFFh 330000h–337FFFh SA69 0111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh SA110 1100111xxx 64/32 670000h–67FFFFh 338000h–33FFFFh SA70 0111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh SA111 1101000xxx 64/32 680000h–68FFFFh 340000h–347FFFh SA71 1000000xxx 64/32 400000h–40FFFFh 200000h–207FFFh SA112 1101001xxx 64/32 690000h–69FFFFh 348000h–34FFFFh SA72 1000001xxx 64/32 410000h–41FFFFh 208000h–20FFFFh SA113 1101010xxx 64/32 6A0000h–6AFFFFh 350000h–357FFFh SA73 1000010xxx 64/32 420000h–42FFFFh 210000h–217FFFh SA114 1101011xxx 64/32 6B0000h–6BFFFFh 358000h–35FFFFh SA74 1000011xxx 64/32 430000h–43FFFFh 218000h–21FFFFh SA115 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh SA75 1000100xxx 64/32 440000h–44FFFFh 220000h–227FFFh SA116 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh SA76 1000101xxx 64/32 450000h–45FFFFh 228000h–22FFFFh SA117 1101110xxx 64/32 6E0000h–6EFFFFh 370000h–377FFFh SA77 1000110xxx 64/32 460000h–46FFFFh 230000h–237FFFh SA118 1101111xxx 64/32 6F0000h–6FFFFFh 378000h–37FFFFh SA78 1000111xxx 64/32 470000h–47FFFFh 238000h–23FFFFh SA119 1110000xxx 64/32 700000h–70FFFFh 380000h–387FFFh SA79 1001000xxx 64/32 480000h–48FFFFh 240000h–247FFFh SA120 1110001xxx 64/32 710000h–71FFFFh 388000h–38FFFFh SA80 1001001xxx 64/32 490000h–49FFFFh 248000h–24FFFFh SA121 1110010xxx 64/32 720000h–72FFFFh 390000h–397FFFh SA81 1001010xxx 64/32 4A0000h–4AFFFFh 250000h–257FFFh SA122 1110011xxx 64/32 730000h–73FFFFh 398000h–39FFFFh SA82 1001011xxx 64/32 4B0000h–4BFFFFh 258000h–25FFFFh SA123 1110100xxx 64/32 740000h–74FFFFh 3A0000h–3A7FFFh SA83 1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh SA124 1110101xxx 64/32 750000h–75FFFFh 3A8000h–3AFFFFh SA84 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh SA125 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh SA85 1001110xxx 64/32 4E0000h–4EFFFFh 270000h–277FFFh SA126 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh SA86 1001111xxx 64/32 4F0000h–4FFFFFh 278000h–27FFFFh SA127 1111000xxx 64/32 780000h–78FFFFh 3C0000h–3C7FFFh SA87 1010000xxx 64/32 500000h–50FFFFh 280000h–28FFFFh SA128 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh SA88 1010001xxx 64/32 510000h–51FFFFh 288000h–28FFFFh SA129 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh SA89 1010010xxx 64/32 520000h–52FFFFh 290000h–297FFFh SA130 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh SA90 1010011xxx 64/32 530000h–53FFFFh 298000h–29FFFFh SA131 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh SA91 1010100xxx 64/32 540000h–54FFFFh 2A0000h–2A7FFFh SA132 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh SA92 1010101xxx 64/32 550000h–55FFFFh 2A8000h–2AFFFFh SA133 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh SA93 1010110xxx 64/32 560000h–56FFFFh 2B0000h–2B7FFFh SA134 1111111000 64/32 7F0000h–7FFFFFh 3F8000h–3FFFFFh SA94 1010111xxx 64/32 570000h–57FFFFh 2B8000h–2BFFFFh

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

A21–A15

Sector

Size

(KB/

Kwords)

8-bit

Address

Range

16-bit

Address

Range

Ta b le 13 . S29GL064A (Model R5) Sector Addresses (Sheet 1 of 2)

Sector A21–A15

SA0 0000000 000000–007FFF SA21 0010101 0A8000–0AFFFF SA1 0000001 008000–00FFFF SA22 0010110 0B0000–0B7FFF SA2 0000010 010000–017FFF SA23 0010111 0B8000–0BFFFF SA3 0000011 018000–01FFFF SA24 0011000 0C0000–0C7FFF SA4 0000100 020000–027FFF SA25 0011001 0C8000–0CFFFF SA5 0000101 028000–02FFFF SA26 0011010 0D0000–0D7FFF SA6 0000110 030000–037FFF SA27 0011011 0D8000–0DFFFF SA7 0000111 038000–03FFFF SA28 0011100 0E0000–0E7FFF SA8 0001000 040000–047FFF SA29 0011101 0E8000–0EFFFF

SA9 0001001 048000–04FFFF SA30 0011110 0F0000–0F7FFF SA10 0001010 050000–057FFF SA31 0011111 0F8000–0FFFFF SA11 0001011 058000–05FFFF SA32 0100000 200000–207FFF SA12 0001100 060000–067FFF SA33 0100001 208000–20FFFF SA13 0001101 068000–06FFFF SA34 0100010 210000–217FFF SA14 0001110 070000–077FFF SA35 0100011 218000–21FFFF SA15 0001111 078000–07FFFF SA36 0100100 220000–227FFF SA16 0010000 080000–087FFF SA37 0100101 228000–22FFFF SA17 0010001 088000–08FFFF SA38 0100110 230000–237FFF SA18 0010010 090000–097FFF SA39 0100111 238000–23FFFF SA19 0010011 098000–09FFFF SA40 0101000 240000–247FFF SA20 0010100 0A0000–0A7FFF SA41 0101001 248000–24FFFF SA42 0101010 250000–257FFF SA85 1010101 1A8000–1AFFFF

16-bit

Address Range

Sector A21–A15

16-bit

Address Range

28 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

Table 13. S29GL064A (Model R5) Sector Addresses (Sheet 2 of 2)

Sector A21–A15

SA43 0101011 258000–25FFFF SA86 1010110 1B0000–1B7FFF SA44 0101100 260000–267FFF SA87 1010111 1B8000–1BFFFF SA45 0101101 268000–26FFFF SA88 1011000 1C0000–1C7FFF SA46 0101110 270000–277FFF SA89 1011001 1C8000–1CFFFF SA47 0101111 278000–27FFFF SA90 1011010 1D0000–1D7FFF SA48 0110000 280000–287FFF SA91 1011011 1D8000–1DFFFF SA49 0110001 288000–28FFFF SA92 1011100 1E0000–1E7FFF SA50 0110010 290000–297FFF SA93 1011101 1E8000–1EFFFF SA51 0110011 298000–29FFFF SA94 1011110 1F0000–1F7FFF SA52 0110100 2A0000–2A7FFF SA95 1011111 1F8000–1FFFFF SA53 0110101 2A8000–2AFFFF SA96 1100000 300000–307FFF SA54 0110110 2B0000–2B7FFF SA97 1100001 308000–30FFFF SA55 0110111 2B8000–2BFFFF SA98 1100010 310000–317FFF SA56 0111000 2C0000–2C7FFF SA99 1100011 318000–31FFFF SA57 0111001 2C8000–2CFFFF SA100 1100100 320000–327FFF SA58 0111010 2D0000–2D7FFF SA101 1100101 328000–32FFFF SA59 0111011 2D8000–2DFFFF SA102 1100110 330000–337FFF SA60 0111100 2E0000–2E7FFF SA103 1100111 338000–33FFFF SA61 0111101 2E8000–2EFFFF SA104 1101000 340000–347FFF SA62 0111110 2F0000–2F7FFF SA105 1101001 348000–34FFFF SA63 0111111 2F8000–2FFFFF SA106 1101010 350000–357FFF SA64 1000000 100000–107FFF SA107 1101011 358000–35FFFF SA65 1000001 108000–10FFFF SA108 1101100 360000–367FFF SA66 1000010 110000–117FFF SA109 1101101 368000–36FFFF SA67 1000011 118000–11FFFF SA110 1101110 370000–377FFF SA68 1000100 120000–127FFF SA111 1101111 378000–37FFFF SA69 1000101 128000–12FFFF SA112 1110000 380000–387FFF SA70 1000110 130000–137FFF SA113 1110001 388000–38FFFF SA71 1000111 138000–13FFFF SA114 1110010 390000–397FFF SA72 1001000 140000–147FFF SA115 1110011 398000–39FFFF SA73 1001001 148000–14FFFF SA116 1110100 3A0000–3A7FFF SA74 1001010 150000–157FFF SA117 1110101 3A8000–3AFFFF SA75 1001011 158000–15FFFF SA118 1110110 3B0000–3B7FFF SA76 1001100 160000–167FFF SA119 1110111 3B8000–3BFFFF SA77 1001101 168000–16FFFF SA120 1111000 3C0000–3C7FFF SA78 1001110 170000–177FFF SA121 1111001 3C8000–3CFFFF SA79 1001111 178000–17FFFF SA122 1111010 3D0000–3D7FFF SA80 1010000 180000–187FFF SA123 1111011 3D8000–3DFFFF SA81 1010001 188000–18FFFF SA124 1111100 3E0000–3E7FFF SA82 1010010 190000–197FFF SA125 1111101 3E8000–3EFFFF SA83 1010011 198000–19FFFF SA126 1111110 3F0000–3F7FFF SA84 1010100 1A0000–1A7FFF SA127 1111111 3F8000–3FFFFF

16-bit

Address Range

Sector A21–A15

16-bit

Address Range

Ta b le 14 . S29GL064A (Models R6, R7) Sector Addresses (Sheet 1 of 2)

Sector A21–A15

SA0 0000000 000000–007FFF SA21 0010101 0A8000–0AFFFF SA1 0000001 008000–00FFFF S A22 0010110 0B0000–0B7FFF SA2 0000010 010000–017FFF SA23 0010111 0B8000–0BFFFF SA3 0000011 018000–01FFFF S A24 0011000 0C0000–0C7FFF SA4 0000100 020000–027FFF SA25 0011001 0C8000–0CFFFF SA5 0000101 028000–02FFFF S A26 0011010 0D0000–0D7FFF SA6 0000110 030000–037FFF SA27 0011011 0D8000–0DFFFF SA7 0000111 038000–03FFFF S A28 0011100 0E0000–0E7FFF SA8 0001000 040000–047FFF SA29 0011101 0E8000–0EFFFF SA9 0001001 048000–04FFFF S A30 0011110 0F0000–0F7FFF

SA10 0001010 050000–057FFF SA31 0011111 0F8000–0FFFFF SA11 0001011 058000–05FFFF SA32 0100000 200000–207FFF SA12 0001100 060000–067FFF SA33 0100001 208000–20FFFF SA13 0001101 068000–06FFFF SA34 0100010 210000–217FFF SA14 0001110 070000–077FFF SA35 0100011 218000–21FFFF SA15 0001111 078000–07FFFF SA36 0100100 220000–227FFF SA16 0010000 080000–087FFF SA37 0100101 228000–22FFFF SA17 0010001 088000–08FFFF SA38 0100110 230000–237FFF SA18 0010010 090000–097FFF SA39 0100111 238000–23FFFF SA19 0010011 098000–09FFFF SA40 0101000 240000–247FFF SA20 0010100 0A0000–0A7FFF S A41 0101001 248000–24FFFF SA42 0101010 250000–257FFF SA85 1010101 1A8000–1AFFFF

16-bit

Address

Range

Sector A21–A15

16-bit

Address

Range

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 29

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Advance Information

Table 14. S29GL064A (Models R6, R7) Sector Addresses (Sheet 2 of 2)

Sector A21–A15

SA43 0101011 258000–25FFFF SA86 1010110 1B0000–1B7FFF SA44 0101100 260000–267FFF SA87 1010111 1B8000–1BFFFF SA45 0101101 268000–26FFFF SA88 1011000 1C0000–1C7FFF SA46 0101110 270000–277FFF SA89 1011001 1C8000–1CFFFF SA47 0101111 278000–27FFFF SA90 1011010 1D0000–1D7FFF SA48 0110000 280000–287FFF SA91 1011011 1D8000–1DFFFF SA49 0110001 288000–28FFFF SA92 1011100 1E0000–1E7FFF SA50 0110010 290000–297FFF SA93 1011101 1E8000–1EFFFF SA51 0110011 298000–29FFFF SA94 1011110 1F0000–1F7FFF SA52 0110100 2A0000–2A7FFF S A95 1011111 1F8000–1FFFFF SA53 0110101 2A8000–2AFFFF SA96 1100000 300000–307FFF SA54 0110110 2B0000–2B7FFF SA97 1100001 308000–30FFFF SA55 0110111 2B8000–2BFFFF SA98 1100010 310000–317FFF SA56 0111000 2C0000–2C7FFF SA99 1100011 318000–31FFFF SA57 0111001 2C8000–2CFFFF SA100 1100100 320000–327FFF SA58 0111010 2D0000–2D7FFF SA101 1100101 328000–32FFFF SA59 0111011 2D8000–2DFFFF SA102 1100110 330000–337FFF SA60 0111100 2E0000–2E7FFF SA103 1100111 338000–33FFFF SA61 0111101 2E8000–2EFFFF SA104 1101000 340000–347FFF SA62 0111110 2F0000–2F7FFF SA105 1101001 348000–34FFFF SA63 0111111 2F8000–2FFFFF SA106 1101010 350000–357FFF SA64 1000000 100000–107FFF SA107 1101011 358000–35FFFF SA65 1000001 108000–10FFFF SA108 1101100 360000–367FFF SA66 1000010 110000–117FFF SA109 1101101 368000–36FFFF SA67 1000011 118000–11FFFF SA110 1101110 370000–377FFF SA68 1000100 120000–127FFF SA111 1101111 378000–37FFFF SA69 1000101 128000–12FFFF SA112 1110000 380000–387FFF SA70 1000110 130000–137FFF SA113 1110001 388000–38FFFF SA71 1000111 138000–13FFFF SA114 1110010 390000–397FFF SA72 1001000 140000–147FFF SA115 1110011 398000–39FFFF SA73 1001001 148000–14FFFF SA116 1110100 3A0000–3A7FFF SA74 1001010 150000–157FFF SA117 1110101 3A8000–3AFFFF SA75 1001011 158000–15FFFF SA118 1110110 3B0000–3B7FFF SA76 1001100 160000–167FFF SA119 1110111 3B8000–3BFFFF SA77 1001101 168000–16FFFF SA120 1111000 3C0000–3C7FFF SA78 1001110 170000–177FFF SA121 1111001 3C8000–3CFFFF SA79 1001111 178000–17FFFF SA122 1111010 3D0000–3D7FFF SA80 1010000 180000–187FFF SA123 1111011 3D8000–3DFFFF SA81 1010001 188000–18FFFF SA124 1111100 3E0000–3E7FFF SA82 1010010 190000–197FFF SA125 1111101 3E8000–3EFFFF SA83 1010011 198000–19FFFF SA126 1111110 3F0000–3F7FFF SA84 1010100 1A0000–1A7FFF SA127 1111111 3F8000–3FFFFF

16-bit

Address

Range

Sector A21–A15

16-bit

Address

Range

Autoselect Mode

The autoselect mode provides manufacturer and device identifi cation, and sector group protection verification, t hrough identi fie r codes outp ut on DQ7–DQ0. This mode is primarily intended for programming equip me nt to autom atically ma tc h a device to be p rogrammed with its cor responding programming a lgorithm. However, the autoselect codes can also be accessed in-system through the com mand register.

When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 15

on page 31. In addition, when verifying sector prot ection, the sector address

must appear on the appropriate highest ord er address bits (see Ta b l e 7 -Table

25). Table 15 on page 31 shows the remaining address bits that are don’t care.

When all necessary bits are set as required, the prog ramming equipment may then read the corresponding identifier code on DQ7–DQ0.

T o access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 30 on page 54 and

30 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

Table 31 on page 55. This method does not require VID. Refer to the Autoselect

Command Sequence section for more information.

Ta b le 15 . Autoselect Codes, (High Voltage Method)

A22

Description CE# OE# WE#

Manufacturer ID Spansion Products

S29GL064A

S29GL032 A

L L H X X

Cycle 1 Cycle 2 H H L 22 X 0Ch 10h 13h

Cycle 3 H H H 22 X 01h Cycle 1

Cycle 2 H H L 22 X 1Dh 1Ah Cycle 3 H H H 22 X 00h

L L H X X

A15

A14

A9A8toA7A6A5to

A10

X L X L L L 00 X 01h 01h 01h

X L X

toA2A1 A0

L L H 22 X 7Eh 7Eh 7Eh

L L H 22 X 7Eh 7Eh

DQ8 to DQ15

BYTE#

= V

BYTE#

= V

R1, R2,

R8, R9

DQ7 to DQ0

Model Number

R3, R4

00h (-R4, bottom boot) 01h (-R3, top boot)

R5, R6,

01h

Cycle 1 L L H X X

S29GL016A Sector Group Protection Verification

Secured Silicon Sector Indicator Bit (DQ7), WP# protects highest address sector

Secured Silicon Sector Indicator Bit (DQ7), WP# protects lowest address sector

L L H SA X

L L H X X

X X X X L H 22 X

X L X L H L X X

X L X L H H X X

C4h (-R2, bottom boot) 49h (-R1, top boot)

01h (protect ed), 00h (unprotected)

For S29GL064A and S29GL032A: 99h (factory locked), 19h (not factory locked) For S29GL016A: 94h (factory locked), 14h (not factory locked)

For S29GL064A and S29GL032A: 89h (factory locked), 09h (not factory locked) For S29GL016A: 84h (factory locked), 04h (not factory locked)

Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Group Protection and Unprotection

The hardware sector group protection feature disables b oth program and erase operations in any sector group (see Tables unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection can be imple mented via two methods.

Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment.

36 shows the algorithms and Figure 24, on page 80 shows the timing diagram.

This method uses standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle.

14 – 25). The hardware sector group

Figure 2, on page

The device is shipped with all sector groups unprotected. Spansion of fers the option of programming and protecting sector groups at its factory prior to shipping the device through Spansion Programming Service. Contact a Spansion repre

sentative for details. It is possible to determine whether a sector group is protected or unprotected.

Autoselect Mode on page 30 for details.

See

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 31

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Advance Information

Ta b le 16 . S29GL016A (Model R1) Sector Group Protection/Unprotection Addresses

Sector/Sector

Sector A19–A12

SA0-SA3 000XXXXXh 256 (4x64) SA31 11111000h 8 SA4-SA7 001XXXXXh 256 (4x64)

SA8-SA11 010XXXXXh 256 (4x64) SA12-SA15 011XXXXXh 256 (4x64) SA16-SA19 100XXXXXh 256 (4x64) SA20-SA23 101XXXXXh 256 (4x64) SA24-SA27 110XXXXXh 256 (4x64)

SA28-SA30

11100XXXh 11101XXXh 11110XXXh

Block Size

(Kbytes)

192 (3x64)

Sector A19–A12

SA32 11111001h 8 SA33 11111010h 8 SA34 11111011h 8 SA35 11111100h 8 SA36 11111101h 8 SA37 11111110h 8 SA38 11111111h 8

Sector/Sector

Block Size

(Kbytes)

Ta b le 17 . S29GL016A (Model R2) Sector Group Protection/Unprotection Addresses

Sector/Sector

Sector A19–A12

SA0 00000000h 8

SA2 00000010h 8 SA3 00000011h 8 SA4 00000100h 8 SA5 00000101h 8 SA6 00000110h 8 SA7 00000111h 8

Block Size

(Kbytes)

Sector A19–A12

00001XXXh

SA8–SA10

00011XXXh SA11–SA14 001XXXXXh 256 (4x64) SA15–SA18 010XXXXXh 256 (4x64) SA19–SA22 011XXXXXh 256 (4x64) SA23–SA26 100XXXXXh 256 (4x64)

SA27-SA30 101XXXXXh 256 (4x64) SA31-SA34 110XXXXXh 256 (4x64)

Sector/Sector

Block Size

(Kbytes)

192 (3x64) SA1 00000001h 8 00010XXXh

Ta bl e 1 8. S29GL032A (Models R1, R2) Sector Group Protection/Unprotection Addresses

Sector

Sector A20–A15

SA0 000000 64 SA12–SA15 0011xx 256 (4x64) SA36–SA39 1001xx 256 (4x64) SA56–SA59 1110xx 256 ( 4x64) SA1 000001 64 SA16–SA19 0100xx 256 (4x64) SA40–SA43 1010xx 256 (4x64) SA60 111100 64 SA2 000010 64 SA20–SA23 0101xx 256 (4x64) SA44–SA47 1011xx 256 (4x64) SA61 111101 64 SA3 000011 64 SA24–SA27 0110xx 256 (4x64) SA48–SA51 1100xx 256 (4x64) SA62 111110 64

SA4–SA7 0001xx 256 (4x64) SA28–SA31 0111xx 256 (4x64 ) SA52–SA55 1101xx 256 (4x64) SA63 111111 64

SA8–SA11 0010xx 256 (4x64) SA32–SA35 1000xx 256 (4x64)

/Sector

Block Size

(Kbytes)

Sector A20–A15

Sector

/Sector

Block Size

(Kbytes)

Sector A20–A15

Sector

/Sector

Block Size

(Kbytes)

Sector A20–A15

Sector

/Sector

Block Size

(Kbytes)

Ta b le 19 . S29GL032A (Model R3) Sector Group Protection/Unprotection Address Table

Sector A20–A12

SA0-SA3 0000XXXXXh 256 (4x64) SA36–SA39 1001XXXXXh 256 (4x64) SA63 111111000h 8 SA4-SA7 0001XXXXXh 256 (4x64) SA40–SA43 1010XXXXXh 256 (4x64) SA64 111111001h 8

SA8-SA11 0010XXXXXh 256 (4x64) SA44–SA47 1011XXXXXh 256 (4x64) SA65 111111010h 8 SA12-SA15 0011XXXXXh 256 (4x64) SA48–SA51 1100XXXXXh 256 (4x64) SA66 111111011h 8 SA16-SA19 0100XXXXXh 256 (4x64) SA52-SA55 1101XXXXXh 256 (4x64) SA67 111111100h 8 SA20-SA23 0101XXXXXh 256 (4x64) SA56-SA59 1110XXXXXh 256 (4x64) SA68 111111101h 8 SA24-SA27 0110XXXXXh 256 (4x64) SA28-SA31 0111XXXXXh 256 (4x64) 111101XXXh SA70 111111111h 8 SA32–SA35 1000XXXXXh 256 (4x64) 111110XXXh

Sector/Sector

Block Size

(Kbytes)

Sector A20–A12

111100XXXh

SA60-SA62

Sector/Sector

Block Size

(Kbytes)

192 (3x64)

Sector A20–A12

SA69 111111110h 8

Sector/Sector

Block Size

(Kbytes)

32 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

Ta bl e 2 0. S29GL032A (Model R4) Sector Group Protection/Unprotection Address Table

Sector/Sector

Sector A20–A12

SA0 000000000h 8 SA1 000000001h 8 000010XXXh SA39-SA42 1000XXXXXh 256 (4x64) SA2 000000010h 8 000011XXXh SA43-SA46 1001XXXXXh 256 (4x64) SA3 000000011h 8 SA11–SA14 0001XXXXXh 256 (4x64) SA47-SA50 1010XXXXXh 256 (4x64) SA4 000000100h 8 SA15–SA18 0010XXXXXh 256 (4x64) SA51-SA54 1011XXXXXh 256 (4x64) SA5 000000101h 8 SA19–SA22 0011XXXXXh 256 (4x64) SA55–SA58 1100XXXXXh 256 (4x64) SA6 000000110h 8 SA23–SA26 0100XXXXXh 256 (4x64) SA59–SA62 1101XXXXXh 256 (4x64) SA7 000000111h 8 SA27-SA30 0101XXXXXh 256 (4x64) SA63–SA66 1110XXXXXh 256 (4x64)

Block Size

(Kbytes)

Sector A20–A12

000001XXXh

SA8–SA10

SA31-SA34 0110XXXXXh 256 (4x64) SA67–SA70 1111XXXXXh 256 (4x64)

Sector/Sector

Block Size

(Kbytes)

192 (3x64)

Sector/Sector

Sector A20–A12

SA35-SA38 0111XXXXXh 256 (4x64)

Block Size

(Kbytes)

Ta bl e 21 . S29GL064A (Models R1, R2, R8, R9) Sector Group Protection/Unprotection Addresses

Sector/

Sector A21–A15

SA0 0000000 64 SA28–SA31 00111xx 256 (4x64) SA68–SA71 10001xx 256 (4x64) SA108–SA111 11011xx 256 (4x64) SA1 0000001 64 SA32–SA35 01000xx 256 (4x64) SA72–SA75 10010xx 256 (4x64) SA112–SA115 11100xx 256 (4x64) SA2 0000010 64 SA36–SA39 01001xx 256 (4x64) SA76–SA79 10011xx 256 (4x64) SA116–SA119 11101xx 256 (4x64) SA3 0000011 64 SA40–SA43 01010xx 256 (4x64) SA80–SA83 10100xx 256 (4x64) SA120–SA123 11110xx 256 (4x64)

SA4–SA7 00001xx 256 (4x64) SA44–SA47 01011xx 256 (4x64) SA84–SA87 10101xx 256 (4x64) SA124 1111100 64 SA8–SA11 00010xx 256 (4x64) SA48–SA51 01100xx 256 (4x64) SA88–SA91 10110xx 256 (4x64) SA125 1111101 64

SA12–SA15 00011xx 256 (4x64) SA52–SA55 01101xx 256 (4x64) SA92–SA95 10111xx 256 (4x64) SA126 1111110 64 SA16–SA19 00100xx 256 (4x64) SA56–SA59 01110xx 256 (4x64) SA96–SA99 11000xx 256 (4x64) SA127 1111111 64 SA20–SA23 00101xx 256 (4x64) SA60–SA63 01111xx 256 (4x64) SA100–SA103 11001xx 256 (4x64) SA24–SA27 00110xx 256 (4x64) SA64–SA67 10000xx 256 (4x64) SA104–SA107 11010xx 256 (4x64)

Sector

Block Size

(Kbytes)

Sector A21–A15

Sector/

Sector

Block Size

(Kbytes)

Sector A21–A15

Sector/

Sector

Block Size

(Kbytes)

Sector A21–A15

Sector/

Sector

Block Size

(Kbytes)

Table 22. S29GL064A (Model R3) Top Boot Sector Protection/Unprotection Addresses

Sector/Sector

Sector A21–A12

SA0-SA3 00000XXXXX 256 (4x64) SA56-SA59 01110XXXXX 256 (4x64) SA112-SA115 11100XXXXX 256 (4x64) SA4-SA7 00001XXXXX 256 (4x64) SA60-SA63 01111XXXXX 256 (4x64) SA116-SA119 11101XXXXX 256 (4x64)

SA8-SA11 00010XXXXX 256 (4x64) SA64-SA67 10000XXXXX 256 (4x64) SA120-SA123 11110XXXXX 256 (4x64) SA12-SA15 00011XXXXX 256 (4x64) SA68-SA71 10001XXXXX 256 (4x64) SA124-SA126 SA16-SA19 00100XXXXX 256 (4x64) SA72-SA75 10010XXXXX 256 (4x64) SA127 1111111000 8

SA20-SA23 00101XXXXX 256 (4x64) SA76-SA79 10011XXXXX 256 (4x64) SA128 1111111001 8 SA24-SA27 00110XXXXX 256 (4x64) SA80-SA83 10100XXXXX 256 (4x64) SA129 1111111010 8 SA28-SA31 00111XXXXX 256 (4x64) SA84-SA87 10101XXXXX 256 (4x64) SA130 1111111011 8 SA32-SA35 01000XXXXX 256 (4x64) SA88-SA91 10110XXXXX 256 (4x64) SA131 1111111100 8 SA36-SA39 01001XXXXX 256 (4x64) SA92-SA95 10111XXXXX 256 (4x64) SA132 1111111101 8 SA40-SA43 01010XXXXX 256 (4x64) SA96-SA99 11000XXXXX 256 (4x64) SA133 1111111110 8 SA44-SA47 01011XXXXX 256 (4x64) SA100-SA103 11001XXXXX 256 (4x64) SA134 1111111111 8 SA48-SA51 01100XXXXX 256 (4x64) SA104-SA107 11010XXXXX 256 (4x64) SA52-SA55 01101XXXXX 256 (4x64) SA108-SA111 11011XXXXX 256 (4x64)

Block Size

(Kbytes)

Sector A20–A12

Sector/Sector

Block Size

(Kbytes)

Sector A20–A12

1111100XXX 1111101XXX 1111110XXX

Sector/Sector

Block Size

(Kbytes)

192 (3x64)

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 33

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Advance Information

Ta b le 23 . S29GL064A (Model R4) Bottom Boot Sector Protection/Unprotection Addresses

Sector/Sector

Sector A21–A12

SA0 0000000000 8 SA31-SA34 00110XXXXX 256 (4x64) SA87–SA90 10100XXXXX 256 (4x64) SA1 0000000001 8 SA35-SA38 00111XXXXX 256 (4x64) SA91–SA94 10101XXXXX 256 (4x64) SA2 0000000010 8 SA39-SA42 01000XXXXX 256 (4x64) SA95–SA98 10110XXXXX 256 (4x64) SA3 0000000011 8 SA43-SA46 01001XXXXX 256 (4x64) SA99–SA102 10111XXXXX 256 (4x64) SA4 0000000100 8 SA47-SA50 01010XXXXX 256 (4x64) SA103–SA106 1 1000XXXXX 256 (4x64) SA5 0000000101 8 SA51-SA54 01011XXXXX 256 (4x64) SA107–SA110 1 1001XXXXX 256 (4x64) SA6 0000000110 8 SA55–SA58 01100XXXXX 256 (4x64) SA111–SA114 11010XXXXX 256 (4x64) SA7 0000000111 8 SA59–SA62 01101XXXXX 256 (4x64) SA115–SA118 11011XXXXX 256 (4x64)

SA8–SA10

SA11–SA14 00001XXXXX 256 (4x64) SA67–SA70 01111XXXXX 256 (4x64) SA123–SA126 11101XXXXX 256 (4x64) SA15–SA18 00010XXXXX 256 (4x64) SA71–SA74 10000XXXXX 256 (4x64) SA127–SA130 11110XXXXX 256 (4x64) SA19–SA22 00011XXXXX 256 (4x64) SA75–SA78 10001XXXXX 256 (4x64) SA131–SA134 11111XXXXX 256 (4x64) SA23–SA26 00100XXXXX 256 (4x64) SA79–SA82 10010XXXXX 256 (4x64)

SA27-SA30 00101XXXXX 256 (4x64) SA83–SA86 10011XXXXX 256 (4x64)

0000001XXX, 0000010XXX, 0000011XXX,

Block Size

(Kbytes)

192 (3x64) SA63–SA66 01110XXXXX 256 (4x64) SA119–SA122 11100XXXXX 256 (4x64)

Sector A20–A12

Sector/Sector

Block Size

(Kbytes)

Sector A20–A12

Sector/Sector

Block Size

(Kbytes)

Ta b le 24 . S29GL064A (Model R5) Sector Group Protection/Unprotection Addresses

Sector/

Sector A21–A15

SA0–SA3 00000 256 (4x64) SA32–SA35 01000 256 (4x64) SA64–SA67 10000 256 (4x64) SA96–SA99 11000 256 (4x64) SA4–SA7 00001 256 (4x64) SA36–SA39 01001 256 (4x64) SA68–SA71 10001 256 (4x64) SA100–SA103 11001 256 (4x64 )

SA8–SA11 00010 256 (4x64) SA40–SA43 01010 256 (4x64) SA72–SA75 10010 256 (4x64) SA104–SA107 11010 256 (4x64) SA12–SA15 00011 256 (4x64) SA44–SA47 01011 256 (4x64) SA76–SA79 10011 256 (4x64) SA108–SA111 11011 256 (4x64) SA16–SA19 00100 256 (4x64) SA48–SA51 01100 256 (4x64) SA80–SA83 10100 256 (4x64) SA112–SA115 11100 256 (4x64) SA20–SA23 00101 256 (4x64) SA52–SA55 01101 256 (4x64) SA84–SA87 10101 256 (4x64) SA116–SA119 11101 256 (4x64) SA24–SA27 00110 256 (4x64) SA56–SA59 01110 256 (4x64) SA88–SA91 10110 256 (4x64) SA120–SA123 11110 256 (4x64) SA28–SA31 00111 256 (4x64) SA60–SA63 01111 256 (4x64) SA92–SA95 10111 256 (4x64) SA124–SA127 11111 256 (4x64)

Sector

Block Size

(Kbytes)

Sector A21–A15

Sector/

Sector

Block Size

(Kbytes)

Sector A21–A15

Sector/

Sector

Block Size

(Kbytes)

Sector A21–A15

Sector/

Sector

Block Size

(Kbytes)

Ta bl e 2 5. S29GL064A (Models R6, R7) Sector Group Protection/Unprotection Addresses

Sector/

Sector A21–A15

Sector

Block Size

(Kbytes)

Sector A21–A15

Sector/

Sector

Block Size

(Kbytes)

Sector A21–A15

Sector/

Sector

Block Size

(Kbytes)

Sector A21–A15

Sector/

Sector

Block Size

(Kbytes)

34 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

Temporary Sector Group Unprotect

This feature allows temporary unp rotection of previously protected se ctor groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to V groups can be programmed or erased by selecting the sector group addresses. Once V groups are protected

is removed from the RESET# pin, all the previously protected sector

again. Figure 1 shows the alg orithm, and Figure 22, on

page 76 shows the timing diagrams, for this feature.

. During this mode, formerly protected sector

STAR T

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Group Unprotect Completed

(Note 2)

Notes:

1. All protected sector groups unprotected (If WP# = VIL, the highest or lowest address sector remains protected for uniform sector devices; the top or bottom two address sectors remains protected for boot sector devices).

2. All previously protected sector groups are protected once again.

Figure 1. Temporary Sector Group Unprotect Operation

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 35

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Temporary Sector

Group Unprotect

Mode

Increment

PLSCNT

START

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

Set up sector

group address

Sector Group Protect:

Write 60h to sector

group address with

A6–A0 = 0xx0010

Wait 150 µs

Verify Sector Group

Protect: Write 40h

to sector group

address with

A6–A0 = 0xx0010

Yes

START

Protect all sector

groups: The indicated

Reset

PLSCNT = 1

portion of the sector

group protect algorithm

must be performed for all

unprotected sector

groups prior to issuing

the first sector group

unprotect address

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

All sector

protected?

Set up first sector

group address

Sector Group

Unprotect: Write 60h to sector group address with

A6–A0 = 1xx0010

Wait 15 ms

groups

Yes

Temporary Sector

Group Unprotect

Mode

PLSCNT

= 25?

Yes

Device failed

Sector Group

Protect

Algorithm

Read from

sector group address

with A6–A0

= 0xx0010

Data = 01h?

Yes

Protect another

sector group?

Remove V

from RESET#

Write reset

command

Sector Group

Protect complete

Verify Sector Group

Unprotect: Write

40h to sector group

Increment

PLSCNT

Yes

PLSCNT

= 1000?

Yes

Device failed

Sector Group

address with

A6–A0 = 1xx0010

Read from sector group address with

A6–A0 = 1xx0010

Data = 00h?

Last sector

Remove V

from RESET#

group

verified?

Yes

Set up

next sector group

address

Unprotect Algorithm

Write reset

command

Sector Group

Unprotect complete

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

36 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or n ot the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This en sures the security of the ESN once the product is shipped to the field.

The factory offers the device with the Secured Silicon Sector either customer lockable (standard shipping option) or factory locked (contact a Spansion sales representative for ordering information). The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to pro gram the sector after receiving the device. The customer-lockable version also contains the Secured Silicon Sector Indicator Bit permanently se t to a 0. The fac tory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit perman ently set to a 1. Thus, the Se cured Silicon Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. Note that the ACC function and

unlock bypass modes are not available when the Secured Silicon Sector is enabled.

The Secured Silicon sector address space in this device is allocated as follows:

Secured Silicon Sector Address Range

Standard Factory

x16 x8

000000h–000007h 000000h-00000Fh ESN

000008h–00007Fh 000010h-0000FFh Unavailable

Locked

The system accesses the Secured Silicon Sector through a command sequence

Write Protect (WP#) on page 38). After the system writ es the Enter Se-

(see cured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit Secure d Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device rev erts to sending commands to sector SA0.

Customer Lockable: S ecu red Sil ic on Se ctor NOT Pr ogra mm ed or Protected At the Factory

Unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte Secured Silicon sector.

The system may program the Secured Silicon Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command se qu ence. See

Command Definitions on page 43.

ExpressFlash Factory

Locked

ESN or det ermined by

customer

Determined by

customer

Customer Lockable

Determined by

customer

Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way.

The Secured Silicon Sector area can be protected using one of the following procedures:

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 37

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Advance Information

 Write the three-cycle Enter Secured Silicon Sector Region command se-

quence, and then follow the in-system sector protect algorithm as shown in

Figure 2, on page 36, except that RESET# may be at either VIH or VID. This

allows in-system protection of the Secured Silicon Sector without raising an y device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector.

 Write the three-cycle Enter Secured Silicon Sector Region command se-

quence, and then use the alternate method of sector protection described in the

Sector Group Protection and Unprotection on page 31 section.

Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing within the remainder of the array.

Factory Lock ed : Secured Silicon Sec t or Pr o g r ammed and Protected At the Factory

In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory . The Secured Silicon Sec tor c annot be modi fied i n an y way. An ESN Factory Locked device has an 16-byte random ESN at addresses 000000h–000007h. Please contact your sales representative for details on o r dering ESN Factory Locked devices.

Custome rs may o p t to hav e th ei r co de p r ogram m ed b y the fa cto ry th ro ug h th e Spansion programming service (Customer Factory L ocked). The devices are then shipped from the factory with the Secured Silicon Sector permanently locked. Contact your sales representative for details on using th e Spansion program ming service.

Write Protect (WP#)

The Write Protect function provides a hardw are method of protecti ng the first or last sector group without using V vided by the WP#/ACC input.

If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or last sector group independently of whether those sector groups were protected or unprotected. Note that if WP#/ACC is at V when the device is in the standby mode, the maximum input load current is increased. See the table in DC Characteristics on page 64.

If the system asserts V whether the first or last sector was previously set to be protected or un protected using the method described in Sector Group Protection and

Unprotection on page 31. Note that WP# contains an internal pullup;

when unconnected, WP# is at VIH.

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 30 on

page 54 and Table 31 on page 55 for command definitions). In addition, the fol-

lowing hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V

power-up and power-down transitions, or from system noise.

. Write Protect is one of two functions pro-

on the WP#/ACC pin, the device reverts to

Low VCC Write Inhibit

When VCC is less than V protects data during V

, the device does not accept any write cycles. This

LKO

power-up and power-down. The command register and

38 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

all internal program/er ase circuits are disabled, and the devic e resets to the read mode. Subsequent writes are ignored until V must provide the proper signals to the control pins to prevent unintentional writes when V

is greater than V

LKO

is greater than V

Write Pulse Glitch Protection

Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE#

. To initiate a write cycle, CE# and WE# must be a logical zero w h ile OE#

= V

is a logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati cally reset to the read mode on power-up.

Common Flash Memory Interface (CFI)

. The system

LKO

The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft ware algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and back ward-compatible for the specif ied flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mo de when the system writ es the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables terminate reading CFI data, the system must write the reset command.

The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables reset command to return the device to reading array data.

For further information, please refer to the CFI Specification and CFI Publication

100. Alternatively, contact your sales representative for copies of these documents.

26–29. The system must write the

26–29. T o

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 39

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Advance Information

Ta b le 26 . CFI Query Identification String

Addresses

(x16)

10h 11h 12h

13h 14h

15h 16h

17h 18h

19h

1Ah

Addresses

(x16)

Addresses

(x8)

20h 22h 24h

26h 28h

2Ah 2Ch

2Eh 30h

32h 34h

Addresses

(x8) Data Description

1Bh 36h 0027h

1Ch 38h 0036h

Data Description

0051h 0052h

Query Unique ASCII string “QRY”

0059h 0002h

0000h 0040h

0000h 0000h

0000h

Primary OEM Command Set

Address for Prim ary Extended Table

Alternate OEM Command S et (00h = none e xists)

Address for Alternate OEM Extended Table (00h = none exists)

Table 27. System Interface String

VCC Min. (write/erase) D7–D4: volt , D3–D0: 100 milli volt

Max. (write/erase)

D7–D4: volt , D3–D0: 100 milli volt 1Dh 3Ah 0000h V 1Eh 3Ch 0000h V

Min. voltage (00h = no VPP pin present)

Max. voltage (00h = no VPP pin present)

1Fh 3Eh 0007h Reserved for fu ture use

20h 40h 0007h Ty pical timeou t for Min. siz e buffer writ e 2 21h 42h 000Ah Typical timeout per individual block er a s e 2 22h 44h 0000h T ypical timeout for fu ll c hi p erase 2

µs (00h = not supported)

ms (00h = not supported)

23h 46h 0001h Reserved for future use

24h 48h 0005h Max. timeout for buffer write 2 25h 4Ah 0004h Max. timeout per individual block erase 2 26h 4Ch 0000h Max. timeout for full chip erase 2

Note:

CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the Ordering Information tables to obtain the VCC range for particular part numbers. Please consult the Erase and Programming Performance table for typical timeout specifications.

times typical

times typical (00h = not supported)

40 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

Ta bl e 2 8. Device Geometry Definition

Addresses (x16) Addresses (x8 ) Data Description

27h 4Eh 00xxh

28h 29h

50h 52h

000xh 0000h

Device Size = 2N byte 0017h = 64 Mb, 0016h = 32Mb, 0015h = 16Mb

Flash Device Inte rface description (ref er to CFI publication 100) 0000h = x8-only bus de vices

0001h = x16-only bus devices 0002h = x8/x16 bus devices

2Ah 2Bh

2Ch 58h 00xxh

2Dh 2Eh 2Fh 30h

31h 32h 33h 34h

35h 36h 37h 38h

39h 3Ah 3Bh 3Ch

54h 56h

5Ah 5Ch

5Eh 60h

60h 64h 66h 68h

6Ah 6Ch

6Eh 70h

72h 74h 76h 78h

0005h 0000h

00xxh 000xh 00x0h 000xh

00xxh 0000h 0000h 000xh

0000h 0000h 0000h 0000h

Max. number o f byte in multi-byte write = 2N (00h = not sup port e d)

Number of Erase Block Re gions within dev ice (01h = u niform device, 02h = boot device)

Erase Block Region 1 Informatio n (refer to the CFI specification or CFI publication 100)

0000h, 0020h, 0000h, 0007h = 16 Mb (-R1, -R2) 007Fh, 0000h, 0020h, 0000h = 32 M b (-R1, -R2) 003Fh, 0000h, 0001h = 32 Mb (-R3, R4) 007Fh, 0000h, 0020h, 0000h = 64 Mb (-R1, -R2, -R 8, -R9) 007Fh, 0000h, 0000h, 0001h = 64 Mb (-R3, -R4, -R5, -R6, -R7)

Erase Block Region 2 Inform a tion (refer to CFI pu blic a tion 100) 0001h, 0000h, 0000h, 001Eh = 16 Mb (-R1, -R 2) 003Eh, 0000h, 0000h, 0001h = 32 Mb (-R1, -R2) 007Eh, 0000h, 0000h, 0001h = 64 Mb (-R1, -R 2, -R8, -R9) 0000h, 0000h, 0000h, 0000h = all others

Erase Block Region 3 Inform a tion (refer to CFI pu blic a tion 100)

Erase Block Region 4 Inform a tion (refer to CFI pu blic a tion 100)

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 41

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Advance Information

Ta b le 29 . Primary Vendor-Specific Extended Query

Addresses

(x16)

40h 41h 42h

43h 86h 0031h Major version numb er, ASCII 44h 88h 0033h Minor version number, ASCII

45h 8Ah 000xh

46h 8Ch 0002h

47h 8Eh 0001h

48h 90h 0001h

49h 92h 0004h

4Ah 94h 0000h

Addresses

(x8)

80h 82h 84h

Data Description

0050h 0052h 0049h

Query-unique ASCII string “PRI”

Address Sensitive Unlock (Bit s 1 -0) 0 = Required, 1 = Not Required

Process Technology (Bits 7-2) 0010b = 200 nm MirrorBit 0009h = x8-only bus de vices 0008h = all other devices

Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect 0 = Not Supported, X = Number of sectors in smallest sector group

Sector Temporary Unprotect 00 = Not Supporte d, 01 = Supported

Sector Protect/Unprotect scheme 0004h = Standard Mode (Refer to T ext)

Simultaneo us Operation 00 = Not Supported , X = Number of Sectors in Bank

4Bh 96h 0000h

4Ch 98h 0001h

4Dh 9Ah 00B5h

4Eh 9Ch 00C5h

4Fh 9Eh 00xxh

50h A0h 0001h

Burst Mode Type 00 = Not Supporte d, 01 = Supported

Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Sup ply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supp ly Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag 02h = Bottom B oot Device, 03h = Top Boot Device, 04h = Uniform

sectors bottom WP# protect, 05h = Uniform sect ors t op WP# protect Program Suspend

00h = Not Supported, 01h = S up ported

42 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

Command Definitions

Writing specific address and data commands or sequences into the command register initiates device operations.

page 55 define the v alid register command sequences. Writing incorrect address

and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to

reading array da ta. All addresses are latched on the falling edge of WE# or CE#, whichever happens

later. All data is latched on the rising edge of WE# or CE#, whichever happe ns first. Refer to the AC Characteristics section for timing diagrams.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any nonerase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same ex ception. See Erase Suspend/Erase Resume Commands on page 52 for more information.

Table 30 on page 54 and Table 31 on

The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information.

See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations–AC Characteristics on

page 66 pro vide the read parameters, and Figure 13, on page 67 shows t he tim-

ing diagram.

Reset Command

Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program comm and seq uence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ig nores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the re set command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode.

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 43

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Advance Information

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read m ode (or erase-suspend-read mode if the device was in Erase Suspend).

Note that if DQ1 goes high during a Write Buff er Programming operation, the system must write the Write-to-Buffe r-Abort Reset command sequence to reset the device for the next operation.

Autoselect Command Sequence

The autoselect command sequence allows the host system to read several identifier codes at specific addresses:

Identifier Code

Manufacturer ID 00h 00h Device ID, Cycle 1 01h 02h Device ID, Cycle 2 0Eh 1Ch Device ID, Cycle 3 0Fh 1Eh

Secured Silicon Sector Factory Protect 03h 06h

Sector Protect Verify (SA)02h (SA)04h

Note: The device ID is read over three cycles. SA = Sector Address

A7:A0

(x16)

The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence:

The system must write the reset command to return to the read mode (or erasesuspend-read mode if the device was previously in Erase Suspend).

Enter/Exit Secured Silicon Sector Command Sequence

The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte random Electronic Serial Number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Sili con Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal op eration.

page 55 show the address and data requirements for both command sequences.

See also Secured Silicon Sector Flash Memo ry Region on page 37 fo r further information. Note that the ACC function and unlock bypass modes are not available

when the Secured Silicon Sector is enabled.

Table 30 on pa ge 54 and Table 31 on

A6:A-1

(x8)

Word Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com

mand. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides inte rnally generated pro

gram pulses and verifies the programmed cell margin. Table 30 on page 54 and

Table 31 on page 55 show the address and data requirements for the word pro-

gram command sequence, respectively.

44 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

When the Embedded Program algori thm is complete, the device then re turns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Op eration Status section for information on these s tatus bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note

that the Secured Silicon Sector, autoselect, and CFI functions are unavaila ble when a program operation is in progress. Note that a hardware reset immedi

ately terminates the program operation. The pro gram command sequence should be reinitiated once the device returns to the read mode, to ensure data integrity.

Programming is allowed in any sequence of address locations and across sector boundaries. Programming to the same word address multiple times without in tervening erases (incremental bit programming) requires a modified programming method. For such application requirements, please contact your local Spansion representative. Word programming is supported for backward compatibility with existing Flash driver software and for occasional writing of in dividual words. Use of write buffer programming (see below ) is strongly recommended for general programming use when more than a few words are to be programmed. The effective word programming time using write buffer pro gramming is approximately four times shorter than the single word programmi n g time.

Any bit in a word cannot be programmed from 0 back to a 1. Attempting to do so may cause the device to set DQ5=1, or cause DQ7 and DQ6 status bits to indicate the operation was succe ssful. However, a succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pr ogram words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass mode command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program comma nd , A0h; the second cy cle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming

Table 30 on page 54 and Table 31 on page 55 show the requirem ents for

time. the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cy cle must contain the data 90h. The second cycle must contain the data 00h. The de vice then returns to the read mode.

Write Buffer Programming

Write Buffer Programming allows the system write to a maximum o f 16 words/ 32 bytes in one programming operation. This results in faster effective progr am ming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Add ress in which programming occurs. T he fourth cycle

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 45

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Advance Information

writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system programs six unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts.

The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits A data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data p airs into t he writ e buffer. Write buffer loca tions may be loaded in any order.

The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages.) This also means that Write Buffer Programming cannot b e performed across m ultiple sectors. If the system at tempts to load programming data outside of the selected write-buffer page, the operation abor ts .

Note that if a Write Buffer address location is loaded multiple times, the address/ data pair counter is decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique writebuffer-address location. Note also that if a n address location is loaded more than once into the buffer, the final data loaded for that address is programmed.

Once the specified number of write buffer locations are loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming oper ation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming.

MAX–A4

. All subsequent address/

The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command.

The Write Buffer Programming Sequence can be aborted in the following ways:  Load a value tha t is g reater t han the page buffer size d uring th e Num ber of

Locations to Program step.

 Write to an address in a sector different than the one specified during the

Write-Buffer-Load command.

 Write an Address/Data pair to a different write-buffer-page than the one se-

lected by the Starting Address during the write buffer data loading stage of the operation.

 Write data other than the Confirm Command after the specified number of

data load cycles.

The abort condition is indicated by DQ1 = 1, DQ7 = DA TA# (for the last address location loaded), DQ6 = toggle, and DQ5= 0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation.

Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program operation is in progress.This flash device is capable of

handling multiple write buffer programming operations on the same write buffer

46 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

address range without intervening erases. For applications requiring incremental bit programming, a modified programming method is required; please contact your local Spansion representative. Any bit in a write buffer address range cannot be programmed from 0 back to a 1. Attempting to do so may cause the device to set DQ5=1, of cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read shows that the data is still

0. Only erase operations can convert a 0 to a 1.

Accelerated Program

The device offers accelerated program operations through the WP#/ACC or ACC pin depending on the pa rticular product. When the system asserts V WP#/ACC or ACC pin. The device uses the higher voltage on the WP#/ACC or ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at

for operations other than accelerated programming, or device damage may

result. WP# contains an internal pullup; when unconnected, WP# is at V

Figure 3, on page 48 illustrates the algorithm for the program operation. Refer

to the Erase and Program Operations–AC Characterist ics on page 66 for par am- eters, and Figure 14, on page 68 for timing diagrams.

on the

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 47

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Advance Information

Write “Write to Buffer”

command and Sector Address

Ye s

(Note 1)

Write number of addresses

to program minus 1(WC)

and Sector Address

Write first address/data

WC = 0 ?

Abort Write to

Buffer Operation?

Write next address/data pair

WC = WC - 1

Write program buffer to

flash sector address

Read DQ7 - DQ0 at

Last Loaded Address

DQ7 = Data?

Ye s

Part of “Write to Buffer” Command Sequence

Write to a different

sector address

Write to buffer ABORTED. Must write “Write-to-buffer

Abort Reset” command

sequence to return

to read mode.

Ye s

(Note 2)

(Note 3)

Read DQ7 - DQ0 with

address = Last Loaded

DQ5 = 1?DQ1 = 1?

Ye s

Address

DQ7 = Data?

FAIL or ABORT PASS

Ye s

Notes:

1. When Sector Address is specified, any address in the selected sector is accep table. However, when loading W r ite-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page.

2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified.

3. If this flowchart location was reached because DQ5= 1, then the device FAILED. If this flowchart location was reached because DQ1= 1, then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another op e r a tion. If DQ 1 = 1, write the Write-Buffer-Pr o g ramming-Abort-Reset command. if DQ5= 1, write the Reset comm a nd.

4. See Table 30 on page 54 and Table 31 on page 55 for command sequences required for write buffer programming.

Figure 3. Write Buffer Programming Operation

48 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

START

Write Program

Command Sequence

Data Poll

Embedded

Program

algorithm

in progress

from System

Verify Data?

Yes

Increment Address

Note:

See Table 30 on page 54 and Table 31 on page 55 for program command sequence

Last Address?

Yes

Programming

Completed

Figure 4. Program Operation

Program Suspend/Program Resume Command Sequence

The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend comm and is writ ten during a programming process, the device halts the program operation within 15 µs maximum (5µs typical) and updates the status bits. Addresses are not required when writing the Program Suspend command.

After the programming operation is suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from t he Secured Silicon Sector area (One-time Program a rea), t hen user must us e the pr oper co mmand seq uences t o enter and exit this region. Note that the Secured Silicon Sector, autoselect, and CFI func tions are unavailable when a program operation is in progress.

The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the de vice exits the autoselect m ode, the device revert s to the Program Suspend mode, and is ready for another valid operation. See

Au-

toselect Command Sequence on page 44 for more information.

After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 49

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Advance Information

DQ7 or DQ6 status bits, just as in the standard program operation. See Write

Operation Status on page 56 for more information.

The system must write the Program Resume command (address bits are don’t care) to exit the Program Suspend mode and continue the programming opera tion. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device resumes programming.

Program Operation

or Write-to-Buffer

Sequence in Progress

Write address/data

XXXh/B0h

Wait 15 µs

Read data as

required

Done

reading?

Yes

Write address/data

XXXh/30h

Device reverts to

operation prior to

Program Suspend

Figure 5. Program Suspend/Program Resume

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not re quire the system to preprog ram prior to erase. The Emb edded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required t o provide any co n trols or timings during these operations. Table 30 on page 54 and Table 31 on

page 55 show the address and data requirements for the chip erase command

sequence. When the Embedded Erase algorithm is complete, the device returns to the read

mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to

tus on page 56 for information on these status bits.

Write Program Suspend Command Sequence

Command is also valid for Erase-suspended-program operations

Autoselect and SecSi Sector read operations are also allowed

Data cannot be read from erase- o program-suspended sectors

Write Program Resume Command Sequence

Write O perati on Sta -

Any commands written during the ch ip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If this

50 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

occurs, the chip erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity.

Figure 6, on page 52 illustrates the algorithm for the erase operation. Refer to Table 38 on page 70 for parameters, and Figure 18, on page 74 for timing

diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad ditional unlock cycles are written, and are then followed by th e address of the sector to be erased, and the sector erase command.

Table 31 on page 55 shows the address and data requirements for the sector

erase command sequence. The device does not require the system to preprogram prior to erase. The Em-

bedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is no t required to provide any controls or timings during these operations.

After the command sequence is written, a sector eras e time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase com mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor inter rupts be disabled during this tim e to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any

command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. Note that the Secured Silicon

Sector, autosel ect, and CFI functions are unavail able wh en an e rase op eration is in progress. The system must rewrite the command sequence and

any addition al addresses and co m m a n ds . The system can monitor DQ3 to determine if the sector erase timer has timed

out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence.

Table 30 on page 54 and

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector . Refer to the Write Operation Status section for information on these status bits.

Once the sector erase operation begins, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity.

Figure 6, on page 52 illustrates the algorithm for the erase operation. Refer to Table 38 on page 70 for parameters, and Figure 18, on page 74 for timing

diagrams.

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 51

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Advance Information

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

Erasure Completed

Yes

Embedded Erase algorithm in progress

Notes:

1.See Table 30 and Table 31 for program command sequence.

2.See the section on DQ3 for information on the sector erase timer.

Figure 6. Erase Operation

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the syst em to interrupt a sector er ase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, in cluding the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase opera tion or Embedded Program algorithm.

When the Erase Suspend command is written during the sector erase operation, the device requires a typical of 5 µs operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation.

After the erase operation is suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for e ra sure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to

Operation Status on page 56 for information on these status bits.

(maximum of 20 µs) to suspend the erase

Write

52 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the pro gram operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer information.

In the erase-suspend-read mode, the system can also issue the autoselect com mand sequence. Refer to the Autoselect Mode on page 30 and Autoselect

Command Sequence on page 44 sections for details.

To resume the sector erase operation, the syst e m must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip resumes erasing.

Note: During an erase operation, this flash device performs multiple internal operations which are in-

visible to the system. When a n erase operation is suspended, any of the internal operat io ns that were not fully completed must be restarted. As such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress is impeded as a function of the number of suspends. The result is a longer cumulative erase time than without suspends. Note that the additional suspends do not affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases, erase performance is not sig nificantly impacted.

to Write Operation Status on page 56 for more

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 53

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Advance Information

Command Definitions

Ta b le 30 . Command Definitions (x16 Mode, BYTE# = VIH)

Command Sequence

(Note 1)

Read (Not e 5) 1 RA RD Reset (Note 6) 1 XXX F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 0001 Device ID (Note 8) 6 555 AA 2AA 55 555 90 X01 227E X0E (Note 19) X0F (Note 19) Device ID (Note 9) 4 555 AA 2AA 55 555 90 X01 (Note 18) Secured Silicon Sector Factory Protect 4 555 AA 2AA 55 555 90 X03 (Note 10)

Sector Group Protect Verify (Note 11)

Autoselect (Note 7)

Enter Secured Silicon Sect or Region 3 555 AA 2AA 55 555 88 Exit Secured Silicon Sect o r Re g ion 4 555 AA 2AA 55 555 90 XXX 00 Program 4 555 AA 2AA 55 555 A0 PA PD Write to Buff er (Note 12) 3 555 AA 2AA 55 SA 25 SA WC PA PD WBL PD Progra m Buffe r to Flash 1 SA 29 Write to Buffer Abort Reset (Note 13) 3 555 AA 2AA 55 555 F0 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program (Note 14) 2 XXX A0 PA PD Unlock Bypass Reset (Note 15) 2 XXX 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Program/Erase Suspend (Note 16) 1 XXX B0 Program/Erase Resume (Note 17) 1 XXX 30 CFI Query (Note 18) 1 55 98

First Second Third Fourth Fifth Sixth

Cycles

4 555 AA 2AA 55 555 90 (SA)X02 00/01

Bus Cycles (Notes 2–5)

Legend:

X = Don’t care RA = Read Address of memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse, whichever happens later.

PD = Program Data for location PA. Da ta latch es on ri sin g edge of WE# or CE# pulse, whichever happens first.

SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A21–A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within same write buffer page a s PA . WC = Word Count. Number of write buffer locations to load minus 1.

Notes:

1. See Table 4 on page 18 for description of bus operations.

2. All values are in hexad ecimal.

3. Shaded cells indicate read cycles. All others are write cycles.

4. During unlock and command cycles, when lower address bits are 555 or 2AA as shown in table, address bits above A11 and data bits above DQ7 are don’t care.

5. No unlock or command cycles required when device is in read mode.

6. Reset command is required to return to read mode (or to erase-suspend-read mode if previously in Erase Suspend) when device is in autoselect mode, or if DQ5 goes high while device i s p r oviding sta t us informatio n.

7. Fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD and WC. SeeAutoselect Command Sequence on page 44 for more information.

8. For S29GL064A and S29GL032A, Device ID must be read in three cycles.

9. For S29GL016A, Device ID must be read in one cycle.

10. Refer to Table 15 on page 31 for data indicating Secured Silicon Sector factory protect status.

11. Data is 00h for an unprotected sector group and 01h for a protected sector group.

12. Total number of cycles in command sequence is determined by number of words written to write buffer. Maximum number of cycles in command sequence is 21, including Program Buffer to Flash command.

13. Command sequence resets device for next command after aborted write-to-buffer operation.

14. Unlock Bypas s command is required prior to Unlock Bypass Program co mmand.

15. Unlock Bypass Reset command is required to return to read mode when device is in unlock bypass mode.

16. System may read and program in non-erasing sectors, or enter autoselect mode, when in Erase Suspend mode. Erase Suspend command is valid only d uring a sector erase operation.

17. Erase Resume command is valid only during Erase Suspend mode.

18. Command is valid when device is ready to read array data or when device is in autoselect mode.

19. Refer to Table 15 on page 31, for individual Device IDs per device density and model number.

54 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

Ta b le 31 . Command Definitions (x8 Mode, BYTE# = VIL)

Command Sequence

(Note 1)

Read (Not e 6) 1 RA RD Reset (Note 7) 1 XXX F0

Manufacturer ID 4 AAA AA 555 55 AAA 90 X00 01 Device ID (Note 9) 6 AAA AA 555 55 AAA 90 X02 7E X1C (Note 18) X1E (Note 18) Device ID(Note 10) 4 AAA AA 555 55 AAA 90 X02 (Note 11) Secured Silicon Sector Factory

Protect Sector Group Protect Verify

(Note 12)

Autoselect (Note 8)

Enter Secured Silicon Sect or Region 3 AAA AA 555 55 AAA 88 Exit Secured Silicon Sect o r Re g ion 4 AAA AA 555 55 AAA 90 XXX 00 Write to Buff er (Note 13) 3 AAA AA 555 55 SA 25 SA BC PA PD WBL PD Progra m Buffe r to Flash 1 SA 29 Write to Buffer Abort Reset (Note 14) 3 AAA AA 555 55 AAA F0 Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30 Program/Erase Suspend (Note 15) 1 XXX B0 Program/Erase Resume (Note 16) 1 XXX 30 CFI Query (Note 17) 1 AA 98

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

4 AAA AA 555 55 AAA 90 X06 (Note 10)

4 AAA AA 555 55 AAA 90 (SA)X04 00/01

Bus Cycles (Notes 2–5)

Legend:

PD = Program Data for location PA. Da ta latch es on ri sin g edge of WE# or CE# pulse, whichever happens first. SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A21–A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within same write buffer page a s PA . BC = Byte Count. Number of write buffer locations to load minus 1.

Notes:

1. See Table 4 on page 18 for description of bus operations.

2. All values are in hexad ecimal.

3. Shaded cells indicate read cycles. All others are write cycles.

4. During unlock and command cycles, when lower address bits are 555 or AAA as shown in table, address bits above A11 are don’t care.

5. Unless otherwise noted, address bits A21–A11 are don’t cares.

6. No unlock or command cycles required when device is in read mode.

7. Reset command is required to return to read mode (or to erase-suspend-read mode if previously in Erase Suspend) when device is in autoselect mode, or if DQ5 goes high while device i s p r oviding sta t us informatio n.

8. Fourth cycle of autoselect command sequen ce is a read cycle. Data bits DQ15–DQ8 are don’t car e. See Au tos ele ct C omma nd Seque nce on

page 44e or more information.

9. For S29GL064A and S29GL032A Device ID must be read in three cycles.

10. For S29GL016A, Device ID must be read in one cycle.

11. Refer to Table 15 on page 31, for data indicating Secured Silicon Sector facto ry protect status.

12. Data is 00h for an unprotected sector group and 01h for a protected sector group.

13. Total number of cycles in command sequence is determined by number of bytes written to write buffer. Maximum number of cycles in command sequence is 37, including Program Buffer to Flash command.

14. Command sequence resets device for next command after aborted write-to-buffer operation.

15. System may read and program in non-erasing sectors, or enter autoselect mode, when in Erase Suspend mode. Erase Suspend command is valid only d uring a sector erase operation.

16. Erase Resume command is valid only during Erase Suspend mode.

17. Command is valid when device is ready to read array data or when device is in autoselect mode.

18. Refer to Table 15 on page 31, for individual Device IDs per device density and model number.

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 55

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Write Operation Status

The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. ing subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or is completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates t o the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in th e command sequence.

During the Embedded Program algorithm, the de vice outputs on DQ7 the complement of the datum pro grammed to DQ7. This DQ7 status a lso applies to programmi n g du ri ng E r as e Su sp e nd. Wh en th e Emb edd ed Pr ogram algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a pro gram address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read mode.

During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must pro vide an address within any of the sectors selected for erasure to read valid status information on DQ7.

Advance Information

Table 32 on page 61 and the follow-

After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the se lected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is as serted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 appears on successive read cycles.

Table 32 on page 61 shows the outputs for Data# Polling on DQ7. Figure 7, o n page 57 shows the Data# Polling algorithm. Figure 19, on page 74 shows the

Data# Polling timing diagram.

56 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

START

Read DQ15–DQ0

Addr = VA

DQ7 = Data?

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may chan g e simultaneously with DQ5.

DQ5 = 1?

Yes

Read DQ15–DQ0

Addr = VA

DQ7 = Data?

FAIL

Yes

PASS

Figure 7. Data# Polling Algorithm

RY/ BY# : Re ad y/ Bus y#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V

If the output is low (Busy), the device is actively erasing or progra mming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-sus pend-read mode. Table 32 on page 61 shows the outputs for RY/BY#.

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 57

Page 60

DQ6: Toggle Bit I

T oggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete , or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algo rithm erases the unprotected sectors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However , the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alter natively, the system can use DQ7 (see the subsection onDQ7: Data# Polling on

page 56).

Advance Information

If a program address falls within a protecte d sector, DQ6 toggles for a pproximately 1 µs after the program command sequence is written, then returns to reading array da ta.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.

Table 32 on page 61 shows the outputs for Toggle Bit I on DQ6. Figure 8, on page 59 shows the toggle bit algorithm. Figure 20, on page 75 shows the toggle bit

timing diagr ams. Figure 21, on page 75 shows the dif fer ences b etw een DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II on page 60.

58 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

START

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

Note: The system should recheck t he to ggle bit even if DQ5 = 1 because the toggle bit may

stop toggling as DQ5 changes to 1. See the subsections on DQ6 and DQ2 for more information.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not Complete, Write Reset Command

Program/Erase

Operation Complete

Figure 8. Toggle Bit Algorithm

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 59

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Advance Information

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits a re required for sector and mode information. Refer t o

Figure 8, on page 59 shows the toggle bit algorithm in flowchart form, and the

section “DQ2: T oggle Bit II” explains the algorithm. See also the RY/BY#: Ready/ Busy# subsection.

Figure 21, on page 75 shows the differences between DQ2 and DQ6 in graphical

form.

Table 32 on page 61 to compare outp u ts fo r D Q 2 and DQ6.

Figure 20, on page 75 shows the toggle bit timing diagram.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 8, on pa ge 59 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device completed the program or erase oper ation. The system can read arra y data on DQ7–DQ0 on the following re ad cycle .

However, if after the initial two read cycles, the sys tem determines tha t the tog gle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device success fully completed the program or erase operation. If it is still toggling, the device did not completed the operation succe ssfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor t he toggle bit and DQ5 through successive read cycles, determining the status as de scribed in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algo rithm when it returns to determine the status of the operation (top of Figure 8,

on page 59).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program, erase, or write-to-buffer time exc e eded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. indicating that the program or erase cycle was not successfully completed.

The device may output a 1 on DQ5 if the system tries to program a 1 to a locati on that was previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the timing limit is exceeded, DQ5 produces a 1.

60 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 63

Advance Information

In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure began. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a 0 to a 1. If the t ime be tween additional sector erase commands from the system can be assumed to be less than 50 µs, the s ystem need not monitor DQ 3. See also the Sect or Erase Command Sequence section.

After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (T oggle Bit I) to ensure that the device accepted the command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algo rithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To ensure the command is accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted.

Table 32 on page 61 shows the status of DQ3 relative to the other status bits.

DQ1: Write-to-Buffer Abort

DQ1 indicates whether a Write-to-Buffe r operation was aborted. Un der these conditions DQ1 produces a 1. The system must issue the Write-to-Buff er-AbortReset command sequence to return the device to reading array data. See

Buffer on page 20 for more details.

Ta b le 32 . Write Operation Status

Status

Standard Mode

Program Suspend Mode

Erase Suspend Mode

Write-toBuffer

Notes:

1. DQ5 switches to 1 when an Embedded Pr ogram, E mbedde d Eras e, or Wr ite-t o-Bu ffer op eratio n exc eeded the maxi mum timi ng l imits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. The Data# Polling algorithm sho uld be used to monitor the last loaded w rite-buffer address location.

4. DQ1 switches to 1 when the device aborts the write-to-buffer operation.

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 0 Embedded Erase Algorithm 0 Toggle 0 1 Toggle N/A 0

ProgramSuspend Read

EraseSuspend Read

Erase-Suspend-Program (Embedded Program)

Busy (Note 3) DQ7# Toggle 0 N/A N/A 0 0 Abort (Note 4) DQ7# Toggle 0 N/A N/A 1 0

Program-Suspended Sector

Non-Program Suspended Sector

Erase-Suspende d Sector 1 No toggle 0 N/A Toggle N/A 1 Non-Erase Suspended

Sector

DQ7

(Note 2)

DQ7# Toggle 0 N/A N/A N/ A 0

DQ6

DQ5

(Note 1)

Invalid (not allowed) 1

DQ3

Data 1

Write

DQ2

(Note 2)

DQ1 RY/BY#

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 61

Page 64

Advance Information

Absolute Maximum Ratings

Storage Temperature, Plastic Packages. . . . . . . . . . . . . . . . –6 5°C to +150°C

Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground:

VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, ACC and RESET# (Note 2) . . . . . . . . . . . . .–0.5 V to +12.5 V

All other pins (Note 1). . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V

Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Notes:

1. Minimum DC voltage on in put o r I/O s is –0.5 V . Duri ng vo ltage t ransi tions, in puts or I/Os may overshoot V

page 62. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage

transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 10, on page 62.

2. Minimum DC inpu t vo l tage on pins A9, O E#, ACC, and RESET# is –0. 5 V. Dur i n g voltage transitions, A9, OE#, ACC, and RESET# may overshoot V periods of up to 20 ns. See Figure 9, on page 62. Maximum DC input voltage on pin A9, OE#, ACC, and RESET# is +12.5 V which may overshoot to +14.0V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

to –2.0 V for periods of up to 20 ns. See Figure 9, on

to –2.0 V for

20 ns

+0.8 V

–0.5 V –2.0 V

20 ns

Figure 9. Maximum Negative Overshoot Waveform

20 ns

+2.0 V

+0.5 V

2.0 V 20 ns

20 ns

Figure 10. Maximum Positive Overshoot Wavefo rm

62 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 65

Advance Information

Operating Ranges

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to +85°C

Supply Voltages

VCC for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V

VCC for regulated voltage range. . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V

Note:

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Operating ranges define those limi ts between which the functionality of the device is guaranteed

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 63

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DC Characteristics

CMOS Compatible

Advance Information

Parameter

Symbol

LIT

CC1

CC2

CC3

CC4

CC5

CC6

OH1

OH2

LKO

Parameter Description (Notes) Test Conditions Min Typ Max Unit

Input Load Current (Note 1)

A9, ACC Input Load Current

Reset Leakage Current VCC = V

Output Leakage Current

VIN = VSS to VCC, VCC = VCC

VCC = V

12.5 V

OUT

VCC = V

max

; A9 =

CC max

; RESET# = 12.5 V 35 µA

CC max

= VSS to VCC,

CC max

±1.0 µA

-40°C to 0°C 250 0°C to 85°C 35

±1.0 µA

1 MHz 520

VCC Initial Read Current (Notes 2, 3)

CE# = V V

OE# =

IL,

5 MHz 18 25

mA 10 MHz 35 50 10 MHz 520

Intra-Page Read Current (Notes 2, 3) CE# = V

VCC Active Write Current (Note 3) CE# = V

VCC Standby Current (Note 3)

CE#, RESET# = VCC ± 0.3 V, WP# = V

VCC Reset Current (Note 3) RESET# = V

Automatic Sleep Mode (Notes 3, 5)

VIH = V

-0.1< VIL ≤ 0.3 V, WP# = V

OE# = V

IL,

OE# = V

IL,

± 0.3 V;

40 MHz 10 40

± 0.3 V, WP# = V

50 60 mA

15µA

Input Low Voltage 1 (Note 6) –0.5 0.8 V Input High Voltage 1 (Note 6) 0.7 V Voltage for ACC Program

Acceleration Voltage for Autoselect and Temporary

Sector Unprotect Output Low Voltage (Note 6) IOL = 4.0 mA, VCC = V

Output High Voltage

VCC = 2.7 –3.6 V 11.5 12.0 12.5 V

0.45 V

CC min

IOH = –2.0 mA, VCC = V IOH = –100 µA, VCC = V

0.85 V

CC min

VCC–0.4 V

CC min

VCC + 0.5 V

Low VCC Lock-Out Voltage (Note 7) 2.3 2.5 V

µA

Notes:

1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA.

2. The ICC current listed is typically less than 3.5 mA/MHz, with O E# at VIH.

3. Maximum ICC specificat ions are tested with VCC = VCCmax.

4. ICC active while Embedded Erase or Embedded Program is in progress.

5. Automatic sleep mode enable s the low power mode when addresse s remain stable for t

6. VCC voltage re q uirements.

+ 30 ns.

ACC

7. Not 100% tested.

64 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 67

Test Conditions

Output Load 1 TTL gate Output Load Capacitance, C

(including jig capacitance) Input Rise and Fall T im e s 5 ns Input Pulse Le vels 0.0 or V Input timing measuremen t re fere nce levels (S e e N ote ) 0.5 V Output timing measurement reference levels 0.5 V

Advance Information

Device

Under

Test

Note: Diodes are IN3064 or equivalent.

6.2 k

Ω

Figure 11. Te s t S e t up

Table 33. Test Specifications

Test Condition All Speeds Unit

3.3 V

2.7 k

Ω

30 pF

CC CC

V V V

Key to Switching Waveforms

Waveform Inputs Outputs

Don’t Care, Any C ha n ge Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

0.0 V

0.5 V

Figure 12. Input Waveforms and Measurement Levels

Steady

Changing from H to L

Changing from L t o H

0.5 V

OutputMeasurement LevelInput

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 65

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Advance Information

AC Characteristics

Ta b l e 3 4 . Read-Only Operations-S29GL064A Only

Parameter

JEDEC Std. 90 10 11

AVAV

AVQV

ELQV

GLQV

EHQZ

GHQZ

AXQX

Read Cycle Time (Note 1) Min 90 100 110 ns

Address to Output Delay

ACC

Chip Enable to Output Delay

Page Access Time Max 25 30 30 ns

PACC

Output Enable to Output Delay Max 25 30 30 ns

Chip Enable to Output High Z (Note 1) Max 16 ns

Output Enable to Output High Z (Note 1) Max 16 ns

Output Hold Time From Addresses, CE# or OE#, Whichever

Occurs First

Output Enable Hold Time

OEH

(Note 1)

Description Test Setup

CE#, OE# = V

OE# = V

Max 90 100 110 ns

Min 0 ns

Read Min 0 ns

Toggle and Data# Polling

Min 10 ns

Notes:

1. Not 100% tested.

2. See Figure 11, on page 65 and Table 33 on page 65 for test specifications

Ta b l e 3 5 . Read-Only Operations-S29GL032A Only

Speed Options

Unit

Parameter

JEDEC Std. 90 10 11

AVAVtRC

AVQVtACC

ELQVtCE

GLQVtOE

EHQZtDF

GHQZtDF

AXQXtOH

Read Cycle Time (Note 1) Min 90 100 110 ns

Address to Output Delay

Chip Enable to Output Delay

Page Access Time Max 25 30 30 ns

PACC

Output Enable to Output Delay Max 25 30 30 ns

Chip Enable to Output High Z (Note 1) Max 16 ns

Output Enable to Output High Z (Note 1) Max 16 ns

Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First

Description Test Setup

CE#, OE# = V

OE# = V

Speed Options

Max 90 100 110 ns

Min 0 ns

Read Min 0 ns

Output Enable Hold Time (Note 1)

OEH

Toggle and Data# Polling

Min 10 ns

Notes:

1. Not 100% tested.

2. See Figure 11, on page 65 and Table 33 on page 65 for test specifications.

Unit

66 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

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Advance Information

Ta b l e 3 6 . Read-Only Operation-S29GL016A Only

Parameter

JEDEC Std. 90 10

AVAV

AVQV

ELQV

GLQV

EHQZ

GHQZ

AXQX

Read Cycle Time (Note 1) Min 90 100 ns

Address to Output Delay

ACC

Chip Enable to Output Delay

Page Access Time Max 25 30 ns

PACC

Output Enable to Output Delay Max 25 30 ns

Chip Enable to Output High Z (Note 1) Max 16 ns

Output Enable to Output High Z (Note 1) Max 16 ns

Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min 0 ns

Output Enable Hold Time (Note 1)

OEH

Description Test Setup

CE#, OE# = V

OE# = V

Read Min 0 ns Toggle and Data# Polling Min 10 ns

Max 90 100 ns

Speed Options

Notes:

1. Not 100% tested.

2. See Figure 11, on page 65 and Table 33 on page 65 for test specifications.

Addresses

Addresses Stable

ACC

CE#

OE#

OEH

Unit

WE#

HIGH Z

Outputs

HIGH Z

Output Valid

RESET#

RY/BY#

0 V

Figure 13. Read Operation Timings

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 67

Page 70

Advance Information

A23-A2

Data Bus

Note: *

Parameter

JEDEC Std.

Ready

RPD

Same Page

A0*

ACC

Ab Ac

PAC C

Qa Qb Qc Qd

CE#

OE#

Figure shows device in word mode. Addresses are A1–A-1 for byte mode

Figure 14. Page Read Timings

Ta b l e 3 7 . Hardware Reset (RESET#)

Description All Speed Options Unit

RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 µs RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode(See Note) Max 500 ns RESET# Pulse Width Min 500 ns Reset High Time Before Read (See Note) Min 50 ns RESET# Input Low to Standby Mode (See Note) Min 20 µs RY/BY# Output High to CE#, OE# pin Low Min 0 ns

Note:

Not 100% tested

68 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 71

RY/BY#

CE#, OE#

RESET#

RY/BY#

Advance Information

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

Ready

CE#, OE#

RESET#

Notes:

1. Not 100% tested.

2. See the Erase And Programming Performance on page 81 for more informati on .

3. For 1–16 words/1–32 bytes programmed.

Figure 15. Reset Timings

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 69

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Advance Information

Ta b l e 3 8 . Erase and Program Operations-S29GL064A

Parameter

JEDEC Std. 90 10 11

AVAV

AVWL

WLAX

DVWH

WHDX

GHWL

ELWL

WHEH

WLWH

WHDL

ASO

t t

CEPH

OEPH

GHWL

t t

WPH

AHT

Write Cycle Time (Note 1) Min 90 100 110 ns Address Setup Time Min 0 ns Address Setup Time to OE# low during toggle bit polling Min 15 ns Address Hold Time Min 45 ns Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns Data Setup Time Min 35 ns Data Hold Time Min 0 ns CE# High during toggle bit polling Min 20 ns OE# High during toggle bit polling Min 20 ns Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns CE# Setup Time Min 0 ns CE# Hold Time Min 0 ns Write Pulse Width Min 35 ns Write Pulse Width High Min 30 ns

Description

Write Buffer Program Operation (Note 2, Note 3) Typ 240

WHWH1

Accelerated Single Word Program Operation (Note 2) Typ 54

WHWH2

VHH

VCS

BUSY

POLL

Sector Erase Operation (Note 2) Typ 0.5 sec

Rise and Fall Time (Note 1) Min 250 ns

Setup Time Note 1) Min 50 µs

WE# High to RY/BY# Low Min 90 100 110 ns Program Valid before Status Polling Max 4 µs

Notes:

1. Not 100% tested.

2. See the Erase And Programming Performance on page 81 for more informati on .

3. For 1–16 words/1–32 bytes programmed.

4. If a program suspend command is issued within t (that is, the progra m resume command is written). If the suspend command was issued after t after programming resumes. See

Figure 16, on page 73.

, the device requires t

POLL

before reading status data, once programming resumes

POLL

Speed Options

, status data is available immediately

POLL

Unit

µsSingle Word Program Operation (Note 2) Typ 60

70 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 73

Advance Information

Ta b l e 3 9 . Erase and Program Operations-S29GL032A Only

Parameter

JEDEC Std. 90 10 11

AVAV

AVWL

WLAX

DVWH

WHDX

GHWL

ELWL

WHEH

WLWH

WHDL

ASO

AHT

CEPH

OEPH

GHWL

WPH

Write Cycle Time (Note 1) Min 90 100 110 ns

Address Setup Time Min 0 ns

Address Setup Time to OE# low during toggle bit polling Min 15 ns

Address Hold Time Min 45 ns

Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns

Data Setup Time Min 35 ns

Data Hold Time Min 0 ns

CE# High during toggle bit polling Min 20 ns

OE# High during toggle bit polling Min 20 ns

Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns

CE# Setup Time Min 0 ns

CE# Hold Time Min 0 ns

Write Pulse Width Min 35 ns

Write Pulse Width High Min 30 ns

Description

Speed Options

Write Buffer Program Operation (Note 2, Note 3) Typ 240

WHWH1

Accelerated Single Word Program Operation (Note 2) Typ 54

WHWH2

VHH

VCS

BUSY

POLL

Sector Erase Operation (Note 2) Typ 0.5 sec

Rise and Fall Time (Note 1) Min 250 ns

Setup Time (Note 1) Min 50 µs

WE# High to RY/BY# Low Min 90 100 110 ns

Program Valid before Status Polling Max 4 µs

Notes:

1. Not 100% tested.

2. See Erase And Programming Performance on page 81 for more information

3. For 1–16 words/1–32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5. If a program suspend command is issued within t (that is, the progra m resume command is written). If the suspend command was issued after t after programming resumes. See

Figure 16, on page 73.

, the device requires t

POLL

before reading status data, once programming resumes

POLL

, status data is available immediately

POLL

Unit

µsSingle Word Program Operation (Note 2) Typ 60

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 71

Page 74

Advance Information

Ta b l e 4 0 . Erase and Program Operations-S29GL016A Only

Parameter

JEDEC Std. 90 10

AVAV

AVWL

WLAX

DVWH

WHDX

GHWL

ELWL

WHEH

WLWH

WHDL

ASO

AHT

CEPH

OEPH

GHWL

WPH

Write Cycle Time (Note 11) Min 90 100 ns

Address Setup Time Min 0 ns

Address Setup Time to OE# low during toggle bit polling Min 15 ns

Address Hold Time Min 45 ns

Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns

Data Setup Time Min 35 ns

Data Hold Time Min 0 ns

CE# High during toggle bit polling Min 20 ns

OE# High during toggle bit polling Min 20 ns

Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns

CE# Setup Time Min 0 ns

CE# Hold Time Min 0 ns

Write Pulse Width Min 35 ns

Write Pulse Width High Min 30 ns

Description

Speed Options

Write Buffer Program Operation (Note 2, Note 3) Typ 240

WHWH1

Accelerated Single Word Program Operation (Note 2) Typ 54

WHWH2

VHH

VCS

BUSY

POLL

Sector Erase Operation (Note 2) Typ 0.5 sec

Rise and Fall Time (Note 1) Min 250 ns

Setup Time (Note 1) Min 50 µs

WE# High to RY/BY# Low Min 90 100 ns

Program Valid before Status Polling Max 4 µs

Notes:

1. Not 100% tested.

2. See Erase And Programming Performance on page 81 for more information

3. For 1–16 words/1–32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5. If a program suspend command is issued within t (that is, the progra m resume command is written). If the suspend command was issued after t after programming resumes. See

Figure 16, on page 73

, the device requires t

POLL

before reading status data, once programming resumes

POLL

, status data is available immediately

POLL

Unit

µsSingle Word Program Operation (Note 2) Typ 60

72 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 75

Advance Information

Program Command Sequence (last two cycles)

Addresses

555h

CE#

OE#

WE#

Data

A0h

RY/BY#

Notes:

1. PA = program address, PD = program data, D

2. Illustration shows device in word mode.

VCS

Figure 16. Program Operation Timings

PA PA

POLL

WPH

BUSY

is the true data at the program ad dress.

OUT

Read Status Data (last two cycles)

WHWH1

Status

OUT

or V

ACC

VHH

VIL or V

Figure 17. Accelerated Program Timing Diagram

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 73

Page 76

Advance Information

Erase Command Sequence (last two cycles) Read Status Data

555h for chip erase

Addresses

2AAh SA

CE#

55h

WPH

30h

10 for Chip Erase

BUSY

WHWH2

Progress

OE#

WE#

Data

RY/BY#

VCS

Notes:

1. SA = sector addres s (for Sect or Erase ), VA = Vali d Addre ss f or read i ng sta tu s dat a (see Write Operation Status on page 56.)

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

Addresses

POLL

CE#

OE#

WE#

DQ7

OEH

ACC

Complement

VA VA

Complement

Tr ue

Valid Data

Complete

High Z

DQ0–DQ6

RY/BY#

BUSY

Status Data

Tr ue

Valid Data

High Z

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

74 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 77

Advance Information

AHT

Addresses

ASO

AHT

CE#

OEH

CEPH

WE#

OEPH

OE#

DQ6 / DQ2 Valid Data

Valid Data

Valid

Status

Valid

Status

Valid

Status

(first read) (second read) (stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

WE#

Erase

Suspend

Erase Suspend

Enter Erase

Suspend Program

Read

Erase Suspend Program

Resume

Erase Suspend

Read

Erase

Complete

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.

Figure 21. DQ2 vs. DQ6

Ta b l e 4 1 . Temporary Sector Unprotect

Parameter

JEDEC Std

VID Rise and Fall Time (See Note) Min 500 ns

VIDR

RESET# Setup Time for Temporary Sector Unprotect Min 4 µs

RSP

Note: Not 100% tested.

Description All Speed Options Unit

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 75

Page 78

Advance Information

RESET#

RY/BY#

RESET#

SA, A6, A3, A2,

A1, A0

CE#

WE#

VSS, VIL, or V

VIDR

Program or Erase Command Sequence

RSP

Figure 22. Temporary Sector Group Unprotect Timing Diagram

Valid* Valid* Valid*

Sector Group Protect or Unprotect Verify

RRB

VIDR

VSS, VIL,

or V

Data

60h 60h 40h

Sector Group Protect: 150 µs,

Sector Group Unprotect: 15 ms

1 µs

CE#

WE#

OE#

Note: For sector group protect, A6:A0 = 0xx0010. For sector group un protect, A6:A0 = 1xx0010.

Figure 23. Sector Group Protect and Unprotect Timing Diagram

Status

76 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 79

Advance Information

Ta b l e 42 . Alternate CE# Controlled Erase and Program Operations-S29GL064A

Parameter

JEDEC Std. 90 10 11

AVAV

AVWL

ELAX

DVEH

EHDX

GHEL

WLEL

EHWH

ELEH

EHEL

t t t

GHEL

t t

CPH

Write Cycle Time (Note 1) Min 90 100 110 ns Address Setup Time Min 0 ns Address Hold Time Min 45 ns Data Setup Time Min 35 ns Data Hold Time Min 0 ns Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns WE# Setup Time Min 0 ns WE# Hold Time Min 0 ns CE# Pulse Width Min 35 ns CE# Pulse Width High Min 25 ns

Description

Speed Options

Write Buffer Program Operation (Notes 2, 3) Typ 240

WHWH1

Single Word Prog ram Operation ( Note 2) Typ 60 Accelerated Single Word Program Operation (Note 2) Typ 54

WHWH2

POLL

Sector Erase Operation (Note 2) Typ 0.5 sec RESET# High Time Before Write Min 50 ns Program Valid before Status Polling (Note 4) Max 4 µs

Notes:

1. Not 100% tested.

2. See the Erase And Programming Performance on page 81 for more informati on .

3. For 1–16 words/1–32 bytes programmed.

4. If a program suspend command is issued within t (that is, the progra m resume command is written). If the suspend command was issued after t after programming resumes. See

Figure 24, on page 80.

, the device requires t

POLL

before reading status data, once programming resumes

POLL

, status data is available immediately

POLL

Unit

µs

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 77

Page 80

Advance Information

Ta b l e 43 . Alternate CE# Controlled Erase and Program Operations-S29GL032A

Parameter

JEDEC Std. 90 10 11

AVAV

AVWL

ELAX

DVEH

EHDX

GHEL

WLEL

EHWH

ELEH

EHEL

GHEL

CPH

Write Cycle Time (Note 1) Min 90 100 110 ns

Address Setup Time Min 0 ns

Address Hold Time Min 45 ns

Data Setup Time Min 35 ns

Data Hold Time Min 0 ns

Read Recovery Time Before Write (OE# High to WE# Low)

WE# Setup Time Min 0 ns

WE# Hold Time Min 0 ns

CE# Pulse Width Min 35 ns

CE# Pulse Width High Min 25 ns

Description

Min 0 ns

Speed Options

Write Buffer Program Operation (Notes 2, 3) Typ 240

WHWH1

Accelerated Single Word Program Operation (Note 2) Typ 54

WHWH2

POLL

Sector Erase Operation (Note 2) Typ 0.5 sec

RESET# High Time Before Write Min 50 ns

Program Valid before Status Polling (Note 4) Max 4 µs

Notes:

1. Not 100% tested.

2. See Erase And Programming Performance on page 81 for more information

3. For 1–16 words/1–32 bytes programmed.

4. If a program suspend command is issued within t (that is, the progra m resume command is written). If the suspend command was issued after t after programming resumes. See

Figure 24, on page 80.

, the device requires t

POLL

before reading status data, once programming resumes

POLL

, status data is available immediately

POLL

Unit

µsSingle Word Program Operation (Note 2) Typ 60

78 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 81

Advance Information

Ta b l e 4 4 . Alternate CE# Controlled Erase and Program Operations-S29GL016A

Parameter

JEDEC Std. 90 10

AVAV

AVWL

ELAX

DVEH

EHDX

GHEL

WLEL

EHWH

ELEH

EHEL

GHEL

CPH

Write Cycle Time (Note 1) Min 90 100 ns

Address Setup Time Min 0 ns

Address Hold Time Min 45 ns

Data Setup Time Min 35 ns

Data Hold Time Min 0 ns

Read Recovery Time Before Write (OE# High to WE# Low)

WE# Setup Time Min 0 ns

WE# Hold Time Min 0 ns

CE# Pulse Width Min 35 ns

CE# Pulse Width High Min 25 ns

Description

Min 0 ns

Speed Options

Write Buffer Program Operation (Note 2, Note 3) Typ 240

WHWH1

Accelerated Single Word Program Operation (Note 2) Typ 54

WHWH2

POLL

Sector Erase Operation (Note 2) Typ 0.5 sec

RESET# High Time Before Write Min 50 ns

Program Valid before Status Polling (Note 4) Max 4 µs

Notes:

1. Not 100% tested.

2. See Erase And Programming Performance on page 81 for more information

3. For 1–16 words/1–32 bytes programmed.

4. If a program suspend command is issued within t (that is, the progra m resume command is written). If the suspend command was issued after t after programming resumes. See

Figure 24, on page 80

, the device requires t

POLL

before reading status data, once programming resumes

POLL

, status data is available immediately

POLL

Unit

µsSingle Word Program Operation (Note 2) Typ 60

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 79

Page 82

Advance Information

Addresses

WE#

OE#

CE#

Data

RESET#

PBA for program 2AA for erase

SA for program buffer to flash SA for sector erase 555 for chip erase

GHEL

CPH

PBD for program 55 for erase

29 for program buffer to flash 30 for sector erase 10 for chip erase

BUSY

Data# Polling

POLL

WHWH1 or 2

DQ7# D

OUT

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D

4. Illustration shows device in word mode

is the data written to the de vice.

OUT

Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings

80 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 83

Advance Information

Erase And Programming Performance

Parameter Typ (Note 1)

Max

(

Note 2)

Unit Comments

Sector Erase Time 0.5 3.5

Excludes 00h

Chip Erase Time

S29GL016A 17.5 35

sec

S29GL032A 32 64

programming

prior to erasure

(Note 6)

S29GL064A 64 128 Total Write Buffer Progr am Time (Notes 3, 5) 240 Total Accelerated Effective Write Buffe r Program Tim e

(Notes

4, 5)

S29GL016A 16 Chip Program Time

200

µs

Excludes system

level ove r head

(

Note 7)

secS29GL032A 31.5

S29GL064A 63

Notes:

1. Typical prog ra m and erase times assume the following conditi ons: 25°C, VCC = 3.0V, 10,000 cycles; checkerboard data pattern.

2. Under worst case conditions of 90°C; Worst case VCC, 100,000 cycles.

3. Effective programming time (typ) is 15 µs (per word), 7.5 µs (per byte).

4. Effective accelerated programming time (typ) is 12.5 µs (per word), 6.3 µs (per byte).

5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.

6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

7. System-level over head is the ti me requi red t o execut e the command se quenc e(s) for the p rogr am command . See Table 30 on page 54 and

Table 31 on page 55 for further information on command definitions.

Ta b l e 45 . TSOP Pin and BGA Package Capacitance

Parameter Symbol Parameter Description Test Setup Typ Max Unit

TSOP 6 7.5 pF

Input Capacitance VIN = 0

BGA 4.2 5.0 pF

TSOP 8.5 12 pF

OUT

Output Capacitance V

OUT

= 0

BGA 5.4 6.5 pF

TSOP 7.5 9 pF

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

Control Pin C apacitance VIN = 0

BGA 3.9 4.7 pF

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 81

Page 84

Physical Dimensions

SEE DETAIL B

SEE DETAIL A

TS048—48-Pin Standard Thin Small Outline Package (TSOP)

STANDARD PIN OUT (TOP VIEW)

Advance Information

0.10 C

-A-

N 2

PARALLEL TO SEATING PLANE

SEE DETAIL B

SEE DETAIL A

0˚

DETAIL A

GAGE LINE

0.25MM (0.0098") BSC

DETAIL B

-B-

e/2

-X-

X = A OR B

0.08MM (0.0031")

(c)

SECTION B-B

SEATING

PLANE

C A-B

WITH PLATING

BASE METAL

MAX

1.20

0.15

1.05

0.23

0.27

0.16

0.21

20.20

18.50

12.10

0.70 5˚

0.20

NOTES:

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

NOT APPLICABLE.

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF

CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS

0.15MM (.0059") PER SIDE.

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE

0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND

0.25MM (0.0098") FROM THE LEAD TIP.

LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

3325 \ 16-038.10a

Package

Jedec

Symbol

A A1 A2 b1

b c1

e L 0

R N

TS 048

MO-142 (B) EC

MIN

NOM

0.05

0.95

0.17

0.10

19.80

20.00

18.30

18.40

11.90

12.00

0.50 BASIC

0.50 0˚

0.08

1.00

0.20

0.22

0.60

3˚

82 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 85

Advance Information

TS056—56-Pin Standard Thin Small Outline Package (TSOP)

STANDARD PIN OUT (TOP VIEW)

SEE DETAIL B

0.10

0.10 A2

2X (N/2 TIPS)

0.10

REVERSE PIN OUT (TOP VIEW)

N 2

0.25

2X (N/2 TIPS)

PARALLEL TO

SEATING PLANE

SEE DETAIL A

SEATING

PLANE

N 2

0.08MM (0.0031") M C A - B S

WITH PLATING

(c)

BASE METAL

SECTION B-B

θ°

DETAIL A

(c)

GAUGE PLANE

0.25MM (0.0098") BSC

DETAIL B

e/2

X = A OR B

MAX

1.20

0.15

1.05

0.23

0.27

0.16

0.21

20.20

18.50

14.10

0.70 8˚

0.20

NOTES:

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF

CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS

0.15mm (.0059") PER SIDE.

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE

0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND

0.25MM (0.0098") FROM THE LEAD TIP.

LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

3356 \ 16-038.10c

Package

Jedec

Symbol

A A1 A2 b1

e L

0 R N

TS 056

MO-142 (D) EC

MIN

NOM

0.05

1.00

0.95

0.20

0.17

0.22

0.17

0.10

19.80

20.00

18.30

18.40

13.90

14.00

0.50 BASIC

0.50

0.60

0˚

0.08 56

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 83

Page 86

Advance Information

LAA064—64-Ball Fortified Ball Grid Array (BGA)

84 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 87

Advance Information

VBN048—48-Ball Fine-pitch Ball Grid Array (BGA) 10x 6 mm Package

-0.50

+0.20

1.00

+0.20

1.00

-0.50

PACKAGE VBN 048

JEDEC N/A

10.00 mm x 6.00 mm NOM PACKAGE

SYMBOL MIN NOM MAX NOTE

A --- --- 1.00 OVERALL THICKNESS

A1 0.17 --- --- BALL HEIGHT

A2 0.62 --- 0.73 BODY THICKNESS

D 10.00 BSC. BODY SIZE

E 6.00 BSC. BODY SIZE

D1 5.60 BSC. BALL FOOTPRINT

E1 4.00 BSC. BALL FOOTPRINT

MD 8 ROW MATRIX SIZE D DIRECTION

ME 6 ROW MATRIX SIZE E DIRECTION

N 48 TOTAL BALL COUNT

φb 0.35 --- 0.45 BALL DIAMETER

e 0.80 BSC. BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

NONE DEPOPULATED SOLDER BALLS

Ø0.50

A1 ID.

SEATING PLANE

Øb

Ø0.08

Ø0.15

C0.10

C0.08

BCDEFG

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

A1 CORNER

3425\ 16-038.25

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 85

Page 88

Advance Information

VBK048—Ball Fine-pitch Ball Grid Array (BGA) 8.15x 6.15 mm Package

0.10

(4X)

BCDEFG

PIN A1

CORNER

INDEX MARK

TOP VIEW

PACKAGE VBK 048

JEDEC N/A

8.15 mm x 6.15 mm NOM

SYMBOL MIN NOM MAX NOTE

A --- --- 1.00 OVERALL THICKNESS

A1 0.18 --- --- BALL HEIGHT

A2 0.62 --- 0.76 BODY THICKNESS

D 8.15 BSC. BODY SIZE

E 6.15 BSC. BODY SIZE

D1 5.60 BSC. BALL FOOTPRINT

E1 4.00 BSC. BALL FOOTPRINT

MD 8 ROW MATRIX SIZE D DIRECTION

ME 6 ROW MATRIX SIZE E DIRECTION

N 48 TOTAL BALL COUNT

φb 0.35 --- 0.43 BALL DIAMETER

e 0.80 BSC. BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

SEATING PLANE

SIDE VIEW

PACKAGE

--- DEPOPULATED SOLDER BALLS

φb

φ 0.08

φ 0.15

A1 CORNER

BOTTOM VIEW

C0.10

C0.08

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3338 \ 16-038.25 \ 10.05.04

86 S29GL-A MirrorBit™ Flash Family S29GL-A_00_A3 April 22, 2005

Page 89

Advance Information

Revision Summary

Revision A (October 13, 2004)

Initial Release.

Revision A1 (December 17, 2004)s

Secured Silicon Sector Flash Memory Region Updated Secured Silicon Sector address table with addresses in x8-mode. DC Characteristics (CMOS Compatible) I

re-specified over temperature.

LIT

Corrected WP#/ACC input load current footnote.

Revision A2 (January 28, 2005)

Global Added S29GL032A information.

Revision A3 (April 22, 2005)

Added S29GL016A information. Corrected Secured Silicon Sector Indicator Bit in Table 15.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document.

Copyright © 2004 – 2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

April 22, 2005 S29GL-A_00_A3 S29GL-A MirrorBit™ Flash Family 87

Datasheet S29GL064A, S29GL032A, S29GL016A Datasheet (SPANSION)

Specifications and Main Features

Frequently Asked Questions

User Manual