Datasheet S29AL032D Datasheet (SPANSION)

Page 1

查询S29AL032D70BAE000供应商

S29AL032D

32 Megabit CMOS 3.0 Volt-only Flash Memory 4 M x 8-Bit Uniform Sector 4 M x 8-Bit/2 M x 16-Bit Boot Sector

Data Sheet

Notice to Readers: The Advance Information status indicates that this document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.

ADVANCE

INFORMATION

Publication Number S29AL032D_00 Revision A Amendment 3 Issue Date June 13, 2005

Page 2

Advance Information

Notice On Data Sheet Designations

Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, in cluding development, qualification, initial production, and full produc tion. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.

Advance Informatio n

The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to produc tion. Information p resented in a document with this designation is likely to change, and in some cases , development on the prod uct may discontinue. Spansion LLC therefore places the following conditions upon Advance Informa tion content:

“This document contains information on one or more products under development at Spansion LLC. The information is inten ded to help you evaluate this produ ct. Do not de sign in this pro duct withou t contacting the factor y. Spansion LLC reserves the right to chan ge or discontinue wo rk on this proposed product wi t h o u t notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a P reliminar y documen t shoul d be e xpected wh ile keepin g these as pects of production under consideration. Spansion places the following conditions upon Preliminary content:

“This document states the c urrent techni cal spe cific ations rega rding t he Sp ansio n produc t(s ) descr ibe d herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in techni c a l spec if ications.”

Combination

Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with DC Characteristics table and A C Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in product ion for a period of time suc h that no changes or only nomi nal changes are expected, th e Preliminary des ignation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range . C h an g es may also include those needed to clarify a description or to correct a typographical error or incor rect specification. Spansion LLC applies the following conditions to documents in this category:

“This document states the c urrent techni cal spe cific ations rega rding t he Sp ansio n produc t(s ) descr ibe d herein. Spansion LLC deem s the pro du cts to have been in suffi cient prod uc tion volume such tha t subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the val id combinations of f ered may occur.”

Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.

ii S29AL032D S29AL032D_00_A3 June 13, 2005

Page 3

S29AL032D

32 Megabit CMOS 3.0 Volt-only Flash Memory 4 M x 8-Bit Uniform Sector 4 M x 8-Bit/2 M x 16-Bit Boot Sector

Data Sheet

Distinctive Characteristics

Architectural Advantages

 Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write op-

erations for battery-powered applications

 Manufactured on 200 nm process technology

— Fully compatible with 0.23 µm Am29LV320D, 0.32 µm

Am29LV033C, and 0.33 µm MBM29LV320E devices

 Flexible sector architecture

— Boot sector models: Eight 8-Kbyte sectors; sixty-

three 64-Kbyte sectors; top or bottom boot block configurations available

— Uniform sector models: Sixty-four 64-Kbyte sectors

 Sector Protection features

— A hardware method of locking a sector to prevent any

program or erase operations withi n that sect or

— Sectors can be locked in-system or via programming

equipment

— Temporary Sector Unprotect feature allows code

changes in previously locked sectors

 Unlock Bypass Program Command

— Reduces overall programming time when issuing

multiple program command sequences

 Secured Silicon Sector

— 128-word sector for permanent, secure identification

through an 8-word random Electronic Serial Number

— May be programmed and locked at the factory or by

the customer

— Accessible through a command sequence

 Compatibility with JEDEC standards

— Pinout and software compatible with single-power

supply Flash

— Superior inadvertent write protection

Package Options

 48-ball FBGA  48-pin TSOP  40-pin TSOP

Performance Characteristics

 High performance

— Access times as fast as 70 ns

ADVANCE

INFORMATION

 Ultra low power consumption (typical values

at 5 MHz)

— 200 nA Automatic Sleep mode current — 200 nA standby mode current — 9 mA read current — 20 mA program/erase current

 Cycling endurance: 1,000,000 cycles per

sector typical

 Data retention: 20 years typical

Software Feat ures

 CFI (Common Flash Interface) compliant

— Provides device-specific information to the system,

allowing host software to easily reconfigure for different Flash devices

 Erase Suspend/Erase Resume

— Suspends an erase operatio n to read data from, or

program data to, a sector that is n ot bei ng erased, then resumes the erase operation

 Data# Polling and toggle bits

— Provides a software method of detecting program or

erase operation completion

— Unlock Bypass Program Command

Reduces overall programming time when issuing multiple program command sequences

Hardware Features

 Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting program or

erase cycle completion

 Hardware reset pin (RESET#)

— Hardware method to reset the device to reading array

data

 WP#/ACC input pin

— Write protect (WP#) function allows protection of two

outermost boot sectors (boot sector mo dels on ly ), regardless of sector protect status

— Acceleration (ACC) function provides accelerated

program times

Publication Number S29AL032D_00 Revision A Amendment 3 Issue Date June 13, 2005

This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or disconti nue work on this proposed product without notice.

Page 4

General Description

The S29AL032D is a 32 m egabit, 3.0 volt-only flash memory device, org anized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. W ord mode data appears on DQ0-DQ15; byte mode data appears on DQ0-DQ7. The device is designed to be programmed in-sys tem with the standard 3.0 volt VCC supply , and can also be pro grammed in standard EPROM programmers.

The device is available with access times as fast as 70 ns. The devices are offered in 40-pin TSOP, 48-pin TSOP and 48-ball FBGA packages. Standard control pins- chip enable (C E#), write enable (WE#), and output enable (OE #)-control nor mal read and write operations, an d avoid bus con tention issu e s.

The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regul a ted voltages are provided for the pro -gram and erase operations.

S29AL032D Features

The Secured Silicon Sector is an extra sector capable of bei ng permanently loc ked by Spansi on or customers. The Secured Silicon Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Note that the S29AL032D has a Se cured Silicon Sector size of 128 words (256 bytes).

Factory locked pa rts provi de sev eral opt ions. The S ecured Si licon Sec tor may store a se cure, r an dom 16 byte ESN (Electronic Seri al Number), cu stomer code (progr ammed through t he Spansion programming service), or both.

The S29AL032D is entirely command set compatible with the JEDEC single-p ower-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and progra mming circuit ry. W rite cy cles als o internal ly latch addre sses and dat a needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occu rs by executing the pro gram command sequence. Thi s initiates the Em- bedded Program algorithm—an internal algo rith m tha t aut om atica lly ti mes the p rog ram pu lse widths and verifies proper cell margin. The Un lock Bypass mode f aci li tat es f ast er pro gr amm ing times by requiring only two writ e cycles to program data i nstead of four.

Advance Information

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algori thm tha t aut oma tica lly pr epro grams th e array (if it is not al ready programmed) before executing the eras e operation. During erase, the dev ice automatically times the erase pulse widths and verifi es pr oper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. gram or erase cycle has been completed, the devi ce is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatical ly inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase oper ations in an y combination of t he sectors of memory. This can be achieved in-system or via programmin g equipment.

After a pro-

2 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 5

Advance Information

The Erase Suspend/Erase Resume feature en ables the user to put erase on hold for any period of time to rea d data from, or pro gram data to, any se ctor th at is n ot selec ted for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied t o the system reset circ uitry. A sys tem reset would thus also reset the device, enablin g the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the d evice enter s the automatic sleep mode. The system ca n also place th e device into the standby mode. Power consumption is greatly reduced in both these modes.

The Spansion Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of qua lity, reliability and cost effectiveness. The de vice electrically erases al l bi ts wit hin a se cto r s imu lta neo us ly v ia F owl er- Nordheim tunneling. The data is programmed using hot electron injection.

June 13, 2005 S29AL032D_00_A3 S29AL032D 3

Page 6

Table of Contents

Advance Information

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 11

Table 1. S29AL032D Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 11

Word/Byte Configuration (Models 03, 04 Only) . . . . . . . . . . . 11

Requirements for Reading Array Data . . . . . . . . . . . . . . . . . . . 11

Writing Commands/Command Sequences . . . . . . . . . . . . . . . 12

Program and Erase Operation Status . . . . . . . . . . . . . . . . . . . 12

Accelerated Program Operation . . . . . . . . . . . . . . . . . . . . . . . 12

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 2. Model 00 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3. Model 00 Secured Silicon Sector Addresses . . . . . . . . . . . . . . 15

Table 4. Model 03 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Model 03 Secured Silicon Sector Addresses . . . . . . . . . . . . . . 17

Table 6. Model 04 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Model 04 Secured Silicon Sector Addresses . . . . . . . . . . . . . . 19

Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. S29AL032D Autoselect Codes (High Voltage Method) . . . . .20

Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. Sector Block Addresses for Protection/Unprotection

— Model 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10. Sector Block Addresses for Protection/Unprotection

— Model 03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. Sector Block Addresses for Protection/Unprotection

— Model 04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Write Protect (WP#) — Models 03, 04 Only . . . . . . . . . . . . 23

Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 1. Temporary Sector Unprotect Operation . . . . . . . . . . . . . . . . 24

Figure 2. In-System Sector Protect/Unprotect Algorithms. . . . . . . . . . 25

Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . 26

Figure 3. Secured Silicon Sector Protect Verify . . . . . . . . . . . . . . . . . . . 27

Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Common Flash Memory Interface (CFI) . . . . . . . 28

Table 12. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 13. System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 14. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 15. Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . .30

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 31

Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 32

Enter Secured Silicon Sector/Exit Secured Silicon Sector

Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Word/Byte Program Command Sequence . . . . . . . . . . . . . . . 32

Figure 4. Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 34

Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . 35

Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . .35

Figure 5. Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 16. S29AL032D Command Definitions — Model 00 . . . . . . . . . . 37

Table 17. S29AL032D Command Definitions — Models 03, 04 . . . . . . 38

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 39

DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 6. Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 7. Toggle Bit Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . .43

DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 18. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 45

Figure 8. Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . 45

Figure 9. Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . 45

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 45

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 10. I

Automatic Sleep Currents). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 11. Typical I

Current vs. Time (Showing Active and

CC1

vs. Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

CC1

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 12. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 19. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 13. Input Waveforms and Measurement Levels . . . . . . . . . . . . . 49

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 50

Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 14. Read Operations Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 15. RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 16. BYTE# Timings for Read Operations . . . . . . . . . . . . . . . . . . 52

Figure 17. BYTE# Timings for Write Operations . . . . . . . . . . . . . . . . . . 53

Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 18. Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 19. Chip/Sector Erase Operation Timings. . . . . . . . . . . . . . . . . . 56

Figure 20. Back to Back Read/Write Cycle Timing . . . . . . . . . . . . . . . . 56

Figure 21. Data# Polling Timings (During Embedded Algorithms) . . . . 57

Figure 22. Toggle Bit Timings (During Embedded Algorithms) . . . . . . 57

Figure 23. DQ2 vs. DQ6 for Erase and Erase Suspend Operations. . . 58

Figure 24. Temporary Sector Unprotect/Timing Diagram . . . . . . . . . . 58

Figure 25. Accelerated Program Timing Diagram . . . . . . . . . . . . . . . . . 59

Figure 26. Sector Protect/Unprotect Timing Diagram . . . . . . . . . . . . . 59

Figure 27. Alternate CE# Controlled Write Operation Timings. . . . . . 61

Erase and Programming Performance . . . . . . . . 62

TSOP and BGA Pin Capacitance . . . . . . . . . . . . . 62

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 63

TS040—40-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . .63

TS 048—48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . 64

VBN048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

10.0 x 6.0 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 66

4 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 7

Advance Information

Product Selector Guide

Family Part Number

Speed Option Voltage Range: VCC = 2.7–3.6 V Max access time, ns (t

) 70 90

ACC

S29AL032D

70 90

Max CE# access time, ns (tCE) 70 90 Max OE# access time, ns (tOE) 30 35

Note: See AC Characteristic s on page 50 for full specifications.

Block Diagram

DQ0–DQ15 (A-1), (DQ0-DQ7 Model 00)

Input/Output

Buffers

Data

STB

Logic

Latch

RESET#

WE#

BYTE#

CE#

OE#

RY/BY#

State

Control

Command

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

VCC Detector

A0–A20 (A0-A21 Model 00)

Timer

STB

Y-Decoder

X-Decoder

Address Latch

Y-Gating

Cell Matrix

June 13, 2005 S29AL032D_00_A3 S29AL032D 5

Page 8

Connection Diagrams

Advance Information

A16 A15 A14 A13 A12 A11

A9 A8

WE#

RESET#

ACC

RY/BY#

A18

A7 A6 A5 A4 A3 A2 A1

A15 A14 A13 A12 A11 A10

A8 A19 A20

WE#

RESET#

WP#/ACC

RY/BY#

A18 A17

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

40-pin Standard TSOP

48-pin Standard TSOP

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

A17 V

A20 A19 A10 DQ7 DQ6 DQ5 DQ4 V

A21 DQ3 DQ2 DQ1 DQ0 OE#

CE# A0

A16 BYTE# V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE#

CE#

6 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 9

Advance Information

Connection Diagrams

For Model 00 Only

A6 B6 C6 D6 E6 F6 G6 H6

A5 B5 C5 D5 E5 F5 G5 H5

A4 B4 C4 D4 E4 F4 G4 H4

A3 B3 C3 D3 E3 F3 G3 H3

48-ball FBGA Top view balls facing down

A20

DQ6 DQ7A10A19A12A11A8A9

CC DQ4NCDQ5NCNCRESET#WE#

SSNCA17A16A15A13A14

A21DQ3DQ2NCNCACCRY/BY#

A2 B2 C2 D2 E2 F2 G2 H2

NC DQ1NCDQ0A5A6A18A7

A1 B1 C1 D1 E1 F1 G1 H1

OE#

SSCE#A0A1A2A4A3

June 13, 2005 S29AL032D_00_A3 S29AL032D 7

Page 10

For Models 03, 04 Only

48-ball FBGA Top view balls facing down

A6 B6 C6 D6 E6 F6 G6 H6

A5 B5 C5 D5 E5 F5 G5 H5

A4 B4 C4 D4 E4 F4 G4 H4

A3 B3 C3 D3 E3 F3 G3 H3

A2 B2 C2 D2 E2 F2 G2 H2

Advance Information

DQ15/A-1

DQ13 DQ6DQ14DQ7A11A10A8A9

CC DQ4DQ12DQ5A19NCRESET#WE#

DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

SSBYTE#A16A15A14A12A13

A1 B1 C1 D1 E1 F1 G1 H1

Special Handling Instructions

Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be da maged if exposed to ultr asonic cleanin g meth-

ods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for pr olonged periods of time.

OE#

SSCE#A0A1A2A4A3

8 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 11

Advance Information

Pin Configuration

A0–A21 = 22 address inputs A0-A20 = 21 address inputs DQ0–DQ7 = 8 data inputs/outputs DQ0-DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode),

BYTE# = Selects 8-bit or 16-bit mo de CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin WP#/ACC = Hardware Write Pro tect input/Programming

ACC = Hardware Write Protect input RY/BY# = Ready/Busy output VCC = 3.0 volt-only single p ower supply

NC = Pin not connected internally

A-1 (LSB address input, byte mode)

Acceleration input.

see Product Selector Guide on page 5 for speed options and voltage supply tolerances)

=Device ground

Logic Symbol

Model 00 Models 03, 04

A0–A21

CE# OE#

WE# RESET# ACC

DQ0–DQ7

RY/BY#

A0–A20

CE# OE# WE# RESET#

WP#/ACC BYTE#

DQ0–DQ15

(A-1)

RY/BY#

16 or 8

June 13, 2005 S29AL032D_00_A3 S29AL032D 9

Page 12

Ordering Information

S29AL032D Standard Products

Spansion standard products are available in several packages and operating ranges. The order number (V alid Co mbination) is fo rmed by a combination of the elements below.

S29AL032D 70 T A I 00 0

Advance Information

PACKING TYPE

0=Tray 2 = 7” Tape and Reel 3 = 13” Tape and Reel

MODEL NUMBER

00 = x8, V 03 = x8/x16, VCC = 2.7 V to 3.6 V, Top boot sector device, top two address

04 = x8/x16, VCC = 2.7 V to 3.6 V , Bott om boot sector device, bottom two

TEMPERATURE RANGE

I = Industrial (–40°C to +85°C) E = Engineering Samples (a vailable prior to Production Release only)

= 2.7 V to 3.6 V, Uniform sector device

sectors protected when WP#/ACC = V

address sectors protected when WP#/ACC = V

PACKAGE MATERIAL SET

A=Standard F=Pb-Free

PACKAGE TYPE

T = Thin Small Outl ine P a ck age (T SOP ) Stand ard Pinou t B = Fine-pitch Ball-Grid Array Package

SPEED OPTION

See “Product Selector Guid e” and Valid Combinations

DEVICE NUMBER/DESCRIPTION

S29AL032D

3.0 Volt-only, 32 Megabit Standard Flash Memory manufactured using 200 nm process tech nology

S29AL032D Valid Com binations

Device Number

S29AL032D 70, 90

Notes:

1. Type 0 is standard. Specify other options as required.

2. TSOP package marking omits packing type designator from ordering part number.

3. BGA package marki ng omits leading S29 and packing type designator from ordering part number.

Speed

Option

Package Type,

Material, and

Temperature R a nge

TAI, TFI

BAI, BFI 00, 03, 04 0, 2, 3 (Note 1)

Model

Number

03, 04

Packing Type

0, 3 (Note 1)

Package Description

TS040 (Note 2) TSOP TS048 (Note 2) TSOP

VBN048 (Note 3) Fine-Pitch BGA

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sale s office to conf irm avai labilit y of spe cific val id com binatio ns an d to ch eck on newly re leas ed combinations.

10 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 13

Advance Information

Device Bus Operations

This section describes the requiremen ts and use of the dev ice bu s operations, which are i niti ated through the internal command regist er. The command register itself do es not occu py any a ddres sable memory location. The regi ster is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device . the resulting output. The foll owing subsections desc ribe each of these oper ations in further detail.

Operation CE# OE# WE# RESET#

Read LLH H L/H A Write (Note 1) LHL H (Note 4) A Accelerated Program

(Note 6)

Standby Output Disable L H H H L/H X High-Z High-Z High-Z

Reset X X X L L/H X High-Z High-Z High-Z Sector Protect (Note 3) LHL V Sector Unprotect

(Note 3)

Temporary Sector Unprotect

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0. 5 V, X = Don ’ t Car e , AIN = Address In, DIN = Data In, D = Data Out

Notes:

1. When the ACC pin is at V

2. Addresses are A20:A0 in word mode (BYTE# = V

3. The sector protect and sector unprotect functions may also be implemented via programming equipment.

4. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector

protection depends on whether they were last protected or unprotected. If WP#/ACC = V

5. D

or D

as required by command sequence, data polling, or sector protection algorith m.

OUT

6. Models 03, 04 only

Table 1 lists the device bus operations, the inputs and control levels they require, and

Ta b l e 1 . S29AL032D Device Bus Operations

WP#(Note 6)/

ACC

LHL H V

VCC ±

0.3 V

LHL V

XXX V

, the device enters the accelerated program mode. See

0.3 V

), A20:A-1 in byte mode (BYTE# = VIL).

H X High-Z High-Z High-Z

L/H

(Note 4)

(Note 4) A

Addresses

(Note 3)

IN IN

SA, A6 = L,

A1 = H, A0 = L

SA, A6 = H,

A1 = H, A0 = L

DQ0–

DQ7

OUT

(Note 5) (Note 5) (Note 5) (Note 5)

(Note 5) XX

(Note 5) (Note 5) High-Z

, all sectors are unprotected.

DQ8–DQ15 (Note 6)

BYTE#

= V

OUT

BYTE# = V

DQ8–DQ14 =

High-Z, DQ15 =

A-1

OUT

Word/Byte Configuration (Models 03, 04 Only)

The BYTE# pin controls whether the devic e data I/O pins DQ15– DQ0 operate in th e byte or word configuration. If the BYTE# pin is set at logic 1, the device is in word con figu ration , DQ1 5–D Q0 are active and controlled by CE# and OE#.

If the BYTE # pin is set at l ogic 0, the devic e is in byte config ur ation, an d only data I/O pins DQ0– DQ7 are active and controlle d by CE# and O E#. The data I/O pins DQ8–DQ14 are tri-st ated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output contr ol and gates array data to the output pins. WE# should remain at V array data in words or bytes.

June 13, 2005 S29AL032D_00_A3 S29AL032D 11

. The BYTE# pin determines whether the device outputs

Page 14

Advance Information

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This e nsures t hat no spurious alteration of the memory content occurs during th e powe r transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device re mains enabled for read acces s until the command regist er con tents are altered.

See Read i n g A rray D ata on page 31 for more information. Refer to the AC Read Operations on

page 50 table for timing specifications and to Figure 14, on page 50 for the timing diagra m. I

in the DC Characteristics table represents the active current specification for re ading array data.

Writing Commands/Command Sequences

T o write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must driv e WE# and CE# to V

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to information.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The programming data to the device us ing both standard and Unlock Bypass command sequences.

An erase operation c an erase one sector, multiple sectors, or the enti re device. Table 2 on page 14 and Table 4 on page 16 indicate the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a sector. The Command Definitio ns on

page 31 contains details on erasin g a sector or the enti re chip, or suspending/resuming t he erase

operation.

Word/Byte Configuration (Models 03, 04 Only) on page 11 for more

Word/Byte Program Command Sequence on page 32 section has details on

, and OE# to VIH.

CC1

After the system writes the autoselect command sequenc e, the device enters the autoselect mode. The sy stem c an th en rea d auto select codes from the inte rnal regist er (wh ich is sepa rate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to

Autoselect M ode on page 20 and Autoselect Command Sequence on page 32 for more

information. I

in the DC Characteristics table represents the active current specification for the write mode.

CC2

AC Characteristics on page 50 contains timing s pec ific ati on ta bl es and t imi ng d iagr am s for wri te

operations.

Program and Erase Operation Status

During an erase or program oper ation, the system may chec k the status of the operat ion by reading the status bits o n DQ7– DQ0. Stan dard read cycle timings and ICC read specifications appl y. Refer to

page 50 for timing diagrams.

Write Operation Status on page 39 for more information, and to AC Characteristics on

Accelerated Program Operation

The device offers ac celerated pr ogram operati ons throug h the AC C function . This is on e of two functions provided by th e WP#/ACC (ACC on Mod el 00) pi n. Thi s func tion is primari ly int ended to allow faster manufacturing throughput at the factory.

If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle pro gram command sequence as required by t he Unlock Bypas s mode. Removi ng VHH from the WP#/ ACC pin returns th e dev i ce to no r m al ope rati on. No te that the WP#/ACC pin mu st n o t be at V for operations other than accelerated programming, or device damage may result. In addition,

12 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 15

the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may res ult.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when t he CE# and RE SET# pins are both he ld at V ± 0.3 V. (Note that this is a more restricted v oltage r an ge than VIH.) If CE# and RESET# are held

, but not with in V

at V

will be greater. The device requires standard access time (t in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

Advance Information

± 0.3 V, the device will be in the standby mode, but the standby current

) for read access when the device i s

In the DC Characteristics table, I

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en ergy consumption. The devi ce automatically enables this mode when addresses remain stable for t independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I

in DC Characteristics on page 46 represents the automatic sleep

CC4

mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardwa re method of resetting the device to reading array data. When the system drives the RESET# pin to V minates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. T he opera tion that w as interrupt ed should be r einitia ted once the dev ice is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS s tandby curren t (I standby current will be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up fi rmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operatio n is not executing (RY/BY# pin is 1), the reset operation is completed within a time of t The system can read data t

Refer to AC Characteristics on page 50 for RESET# par ameters a nd to F igure 1 5, on page 5 1 for the timing diagram.

after the RESET# pin returns to VIH.

CC3

and I

CC4

represents the standby current specifi cat ion.

CC4

+ 30 ns. The automatic sleep mode is

ACC

for at least a period of tRP, the device immediately ter-

). If RESET# is held at VIL but not within VSS±0.3 V, the

(during Embedded

READY

(not during Embedded Algori thms).

READY

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

June 13, 2005 S29AL032D_00_A3 S29AL032D 13

Page 16

Advance Information

Ta b l e 2 . Model 00 Sector Addresses (Sheet 1 of 2)

Sector A21 A20 A19 A18 A17 A16

SA0 0 0 0 0 0 0 000000–00FFFF SA1 0 0 0 0 0 1 010000–01FFFF SA2 0 0 0 0 1 0 020000–02FFFF SA3 0 0 0 0 1 1 030000–03FFFF SA4 0 0 0 1 0 0 040000–04FFFF SA5 0 0 0 1 0 1 050000–05FFFF SA6 0 0 0 1 1 0 060000–06FFFF SA7 0 0 0 1 1 1 070000–07FFFF SA8 0 0 1 0 0 0 080000–08FFFF

SA9 0 0 1 0 0 1 090000–09FFFF SA10 0 0 1 0 1 0 0A0000–0AFFFF SA11 0 0 1 0 1 1 0B0000–0BFFFF SA12 0 0 1 1 0 0 0C0000–0CFFFF SA13 0 0 1 1 0 1 0D0000–0DFFFF SA14 0 0 1 1 1 0 0E0000–0EFFFF SA15 0 0 1 1 1 1 0F0000–0FFFFF SA16 0 1 0 0 0 0 100000–10FFFF SA17 0 1 0 0 0 1 110000–11FFFF SA18 0 1 0 0 1 0 120000–12FFFF SA19 0 1 0 0 1 1 130000–13FFFF SA20 0 1 0 1 0 0 140000–14FFFF SA21 0 1 0 1 0 1 150000–15FFFF SA22 0 1 0 1 1 0 160000–16FFFF SA23 0 1 0 1 1 1 170000–17FFFF SA24 0 1 1 0 0 0 180000–18FFFF SA25 0 1 1 0 0 1 190000–19FFFF SA26 0 1 1 0 1 0 1A0000–1AFFFF SA27 0 1 1 0 1 1 1B0000–1BFFFF SA28 0 1 1 1 0 0 1C0000–1CFFFF SA29 0 1 1 1 0 1 1D0000–1DFFFF SA30 0 1 1 1 1 0 1E0000–1EFFFF SA31 0 1 1 1 1 1 1F0000–1FFFFF SA32 1 0 0 0 0 0 200000–20FFFF SA33 1 0 0 0 0 1 210000–21FFFF SA34 1 0 0 0 1 0 220000–22FFFF SA35 1 0 0 0 1 1 230000–23FFFF SA36 1 0 0 1 0 0 240000–24FFFF SA37 1 0 0 1 0 1 250000–25FFFF SA38 1 0 0 1 1 0 260000–26FFFF

Address Range

(in hexadecimal)

14 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 17

Advance Information

Table 2. Model 00 Sector Addresses (Sheet 2 of 2)

Sector A21 A20 A19 A18 A17 A16

SA39 1 0 0 1 1 1 270000–27FFFF SA40 1 0 1 0 0 0 280000–28FFFF SA41 1 0 1 0 0 1 290000–29FFFF SA42 1 0 1 0 1 0 2A0000–2AFFFF SA43 1 0 1 0 1 1 2B0000–2BFFFF SA44 1 0 1 1 0 0 2C0000–2CFFFF SA45 1 0 1 1 0 1 2D0000–2DFFFF SA46 1 0 1 1 1 0 2E0000–2EFFFF SA47 1 0 1 1 1 1 2F0000–2FFFFF SA48 1 1 0 0 0 0 300000–30FFFF SA49 1 1 0 0 0 1 310000–31FFFF SA50 1 1 0 0 1 0 320000–32FFFF SA51 1 1 0 0 1 1 330000–33FFFF SA52 1 1 0 1 0 0 340000–34FFFF SA53 1 1 0 1 0 1 350000–35FFFF SA54 1 1 0 1 1 0 360000–36FFFF SA55 1 1 0 1 1 1 370000–37FFFF SA56 1 1 1 0 0 0 380000–38FFFF SA57 1 1 1 0 0 1 390000–39FFFF SA58 1 1 1 0 1 0 3A0000–3AFFFF SA59 1 1 1 0 1 1 3B0000–3BFFFF SA60 1 1 1 1 0 0 3C0000–3CFFFF SA61 1 1 1 1 0 1 3D0000–3DFFFF SA62 1 1 1 1 1 0 3E0000–3EFFFF SA63 1 1 1 1 1 1 3F0000–3FFFFF

Notes:

1. All sectors are 64 Kbytes in size.

Address Range

(in hexadecimal)

Ta b l e 3 . Model 00 Secured Silicon Sector Addresses

Sector Address

A20–A12

111111111 256/128 3FFF00h–3FFFFFh 1FFF80h–1FFFFFh

Sector Size

(bytes/words)

(x8)

Address Range

(x16)

Address Range

June 13, 2005 S29AL032D_00_A3 S29AL032D 15

Page 18

Advance Information

Ta b l e 4 . Model 03 Sector Addresses (Sheet 1 of 2)

Sector

SA0 000000xxx 64/32 000000h–00FFFFh 000000h–07FFFh SA1 000001xxx 64/32 010000h–01FFFFh 008000h–0FFFFh SA2 000010xxx 64/32 020000h–02FFFFh 010000h–17FFFh SA3 000011xxx 64/32 030000h–03FFFFh 018000h–01FFFFh SA4 000100xxx 64/32 040000h–04FFFFh 020000h–027FFFh SA5 000101xxx 64/32 050000h–05FFFFh 028000h–02FFFFh SA6 000110xxx 64/32 060000h–06FFFFh 030000h–037FFFh SA7 000111xxx 64/32 070000h–07FFFFh 038000h–03FFFFh SA8 001000xxx 64/32 080000h–08FFFFh 040000h–047FFFh

SA9 001001xxx 64/32 090000h–09FFFFh 048000h–04FFFFh SA10 001010xxx 64/32 0A0000h–0AFFFFh 050000h–057FFFh SA11 001011xxx 64/32 0B0000h–0BFFFFh 058000h–05FFFFh SA12 001100xxx 64/32 0C0000h–0CFFFFh 060000h–067FFFh SA13 001101xxx 64/32 0D0000h–0DFFFFh 068000h–06FFFFh SA14 001110xxx 64/32 0E0000h–0EFFFFh 070000h–077FFFh SA15 001111xxx 64/32 0F0000h–0FFFFFh 078000h–07FFFFh SA16 010000xxx 64/32 100000h–10FFFFh 080000h–087FFFh SA17 010001xxx 64/32 110000h–11FFFFh 088000h–08FFFFh SA18 010010xxx 64/32 120000h–12FFFFh 090000h–097FFFh SA19 010011xxx 64/32 130000h–13FFFFh 098000h–09FFFFh SA20 010100xxx 64/32 140000h–14FFFFh 0A0000h–0A7FFFh SA21 010101xxx 64/32 150000h–15FFFFh 0A8000h–0AFFFFh SA22 010110xxx 64/32 160000h–16FFFFh 0B0000h–0B7FFFh SA23 010111 xxx 64/32 170000h–17FFFFh 0B8000h–0BFFFFh SA24 011000xxx 64/32 180000h–18FFFFh 0C0000h–0C7FFFh SA25 011001xxx 64/32 190000h–19FFFFh 0C8000h–0CFFFFh SA26 011010xxx 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh SA27 011011xxx 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh SA28 011100xxx 64/32 1C0000h–1CFFFFh 0E0000h–0E7FFFh SA29 011101xxx 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh SA30 011110xxx 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh SA31 011111xxx 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh SA32 100000xxx 64/32 200000h–20FFFFh 100000h–107FFFh SA33 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh SA34 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh SA35 100011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh SA36 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh SA37 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh SA38 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

16 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 19

Advance Information

Table 4. Model 03 Sector Addresses (Sheet 2 of 2)

Sector

SA39 100111 xxx 64/32 270000h–27FFFFh 138000h–13FFFFh SA40 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh SA41 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh SA42 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh SA43 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh SA44 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh SA45 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh SA46 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh SA47 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh SA48 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh SA49 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh SA50 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh SA51 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh SA52 110100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh SA53 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh SA54 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh SA55 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh SA56 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh SA57 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh SA58 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh SA59 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh SA60 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh SA61 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh SA62 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh SA63 111111000 8/4 3F0000h–3F1FFFh 1F8000h–1F8FFFh SA64 111111001 8/4 3F2000h–3F3FFFh 1F9000h–1F9FFFh SA65 111111010 8/4 3F4000h–3F5FFFh 1FA000h–1FAFFFh SA66 111111011 8/4 3F6000h–3F7FFFh 1FB000h–1FBFFFh SA67 111111100 8/4 3F8000h–3F9FFFh 1FC000h–1FCFFFh SA68 111111101 8/4 3FA000h–3FBFFFh 1FD000h–1FDFFFh SA69 111111110 8/4 3FC000h–3FDFFFh 1FE000h–1FEFFFh SA70 111111111 8/4 3FE000h–3FFFFFh 1FF000h–1FFFFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Note: The address ra nge is A 2 0:A-1 in byte mode (BYTE#=VIL) or A20:A0 in w o rd m o d e (B YT E # =VIH).

Ta b l e 5 . Model 03 Secured Silicon Sector Addresses

Sector Address

A20–A12

111111111 256/128 3FFF00h–3FFFFFh 1FFF80h–1FFFFFh

Sector Size

(bytes/words)

(x8)

Address Range

(x16)

Address Range

June 13, 2005 S29AL032D_00_A3 S29AL032D 17

Page 20

Advance Information

Ta b l e 6 . Model 04 Sector Addresses (Sheet 1 of 2)

Sector

SA0 000000000 8/4 000000h-001FFFh 000000h–000FFFh

SA1 000000001 8/4 002000h-003FFFh 001000h–001FFFh

SA2 000000010 8/4 004000h-005FFFh 002000h–002FFFh

SA3 000000011 8/4 006000h-007FFFh 003000h–003FFFh

SA4 000000100 8/4 008000h-009FFFh 004000h–004FFFh

SA5 000000101 8/4 00A000h-00BFFFh 005000h–005FFFh

SA6 000000110 8/4 00C000h-00DFFFh 006000h–006FFFh

SA7 000000111 8/4 00E000h-00FFFFh 007000h–007FFFh

SA8 000001xxx 64/32 010000h-01FFFFh 008000h–00FFFFh

SA9 000010xxx 64/32 020000h-02FFFFh 010000h–017FFFh

SA10 000011xxx 64/32 030000h-03FFFFh 018000h–01FFFFh SA11 000100xxx 64/32 040000h-04FFFFh 020000h–027FFFh SA12 000101xxx 64/32 050000h-05FFFFh 028000h–02FFFFh SA13 000110xxx 64/32 060000h-06FFFFh 030000h–037FFFh SA14 000111xxx 64/32 070000h-07FFFFh 038000h–03FFFFh SA15 001000xxx 64/32 080000h-08FFFFh 040000h–047FFFh SA16 001001xxx 64/32 090000h-09FFFFh 048000h–04FFFFh SA17 001010xxx 64/32 0A0000h-0AFFFFh 050000h–057FFFh SA18 001011xxx 64/32 0B0000h-0BFFFFh 058000h–05FFFFh SA19 001100xxx 64/32 0C0000h-0CFFFFh 060000h–067FFFh SA20 001101xxx 64/32 0D0000h-0DFFFFh 068000h–06FFFFh SA21 001110xxx 64/32 0E0000h-0EFFFFh 070000h–077FFFh SA22 001111xxx 64/32 0F0000h-0FFFFFh 078000h–07FFFFh SA23 010000xxx 64/32 100000h-10FFFFh 080000h–087FFFh SA24 010001xxx 64/32 110000h-11FFFFh 088000h–08FFFFh SA25 010010xxx 64/32 120000h-12FFFFh 090000h–097FFFh SA26 010011xxx 64/32 130000h-13FFFFh 098000h–09FFFFh SA27 010100xxx 64/32 140000h-14FFFFh 0A0000h–0A7FFFh SA28 010101xxx 64/32 150000h-15FFFFh 0A8000h–0AFFFFh SA29 010110xxx 64/32 160000h-16FFFFh 0B0000h–0B7FFFh SA30 010111xxx 64/32 170000h-17FFFFh 0B8000h–0BFFFFh SA31 011000xxx 64/32 180000h-18FFFFh 0C0000h–0C7FFFh SA32 011001xxx 64/32 190000h-19FFFFh 0C8000h–0CFFFFh SA33 011010xxx 64/32 1A0000h-1AFFFFh 0D0000h–0D7FFFh SA34 011011xxx 64/32 1B0000h-1BFFFFh 0D8000h–0DFFFFh SA35 011100xxx 64/32 1C0000h-1CFFFFh 0E0000h–0E7FFFh SA36 011101xxx 64/32 1D0000h-1DFFFFh 0E8000h–0EFFFFh SA37 011110xxx 64/32 1E0000h-1EFFFFh 0F0000h–0F7FFFh SA38 011111xxx 64/32 1F0000h-1FFFFFh 0F8000h–0FFFFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

18 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 21

Advance Information

Table 6. Model 04 Sector Addresses (Sheet 2 of 2)

Sector

SA39 100000xxx 64/32 200000h-20FFFFh 100000h–107FFFh SA40 100001xxx 64/32 210000h-21FFFFh 108000h–10FFFFh SA41 100010xxx 64/32 220000h-22FFFFh 110000h–117FFFh SA42 100011xxx 64/32 230000h-23FFFFh 118000h–11FFFFh SA43 100100xxx 64/32 240000h-24FFFFh 120000h–127FFFh SA44 100101xxx 64/32 250000h-25FFFFh 128000h–12FFFFh SA45 100110xxx 64/32 260000h-26FFFFh 130000h–137FFFh SA46 100111xxx 64/32 270000h-27FFFFh 138000h–13FFFFh SA47 101000xxx 64/32 280000h-28FFFFh 140000h–147FFFh SA48 101001xxx 64/32 290000h-29FFFFh 148000h–14FFFFh SA49 101010xxx 64/32 2A0000h-2AFFFFh 150000h–157FFFh SA50 101011xxx 64/32 2B0000h-2BFFFFh 158000h–15FFFFh SA51 101100xxx 64/32 2C0000h-2CFFFFh 160000h–167FFFh SA52 101101xxx 64/32 2D0000h-2DFFFFh 168000h–16FFFFh SA53 101110xxx 64/32 2E0000h-2EFFFFh 170000h–177FFFh SA54 101111xxx 64/32 2F0000h-2FFFFFh 178000h–17FFFFh SA55 111000xxx 64/32 300000h-30FFFFh 180000h–187FFFh SA56 110001xxx 64/32 310000h-31FFFFh 188000h–18FFFFh SA57 110010xxx 64/32 320000h-32FFFFh 190000h–197FFFh SA58 110011xxx 64/32 330000h-33FFFFh 198000h–19FFFFh SA59 110100xxx 64/32 340000h-34FFFFh 1A0000h–1A7FFFh SA60 110101xxx 64/32 350000h-35FFFFh 1A8000h–1AFFFFh SA61 110110xxx 64/32 360000h-36FFFFh 1B0000h–1B7FFFh SA62 110111xxx 64/32 370000h-37FFFFh 1B8000h–1BFFFFh SA63 111000xxx 64/32 380000h-38FFFFh 1C0000h–1C7FFFh SA64 111001xxx 64/32 390000h-39FFFFh 1C8000h–1CFFFFh SA65 111010xxx 64/32 3A0000h-3AFFFFh 1D0000h–1D7FFFh SA66 111011xxx 64/32 3B0000h-3BFFFFh 1D8000h–1DFFFFh SA67 111100xxx 64/32 3C0000h-3CFFFFh 1E0000h–1E7FFFh SA68 111101xxx 64/32 3D0000h-3DFFFFh 1E8000h–1EFFFFh SA69 111110xxx 64/32 3E0000h-3EFFFFh 1F0000h–1F7FFFh SA70 111111xxx 64/32 3F0000h-3FFFFFh 1F8000h–1FFFFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Note: The address ra nge is A 2 0:A-1 in byte mode (BYTE#=VIL) or A20:A0 in w o rd m o d e (B YT E # =VIH).

Ta b l e 7 . Model 04 Secured Silicon Sector Addresses

Sector Address

A20–A12

000000000 256/128 000000h-0000FFh 00000h-0007Fh

Sector Size

(bytes/words)

(x8)

Address Range

(x16)

Address Range

June 13, 2005 S29AL032D_00_A3 S29AL032D 19

Page 22

Advance Information

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection v erification, through identifie r codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatic ally match a device t o be programmed with it s correspond ing programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in ifying sector prot ection, the sec tor address must a ppear on the a ppropriate highest order address bits (see

Table 2 on page 14 and Table 4 on page 16). Table 8 sh ows the remaining address bits

that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0.

T o acc ess the autosel ect cod es in-sys tem, the hos t system can issue the aut oselect co mmand via the command register, as shown in

Table 17 on page 38. This method do es not require VID. See

“Command Definitions ” for details on using the autoselect mode.

Ta b l e 8 . S29AL032D Autoselect Codes (High Vol ta ge Method)

A19

A11

Description Mode CE# OE# WE#

Manufacturer ID: Spansion LLHXXVIDXLXLLL X 01h Device ID:

S29AL032D (Model 00)

Device ID: S29AL032D (Model 03)

Device ID: S29AL032D (Model 04)

Sector Protection Verification

Secured Silicon Sector Indicator Bit (DQ7) (Model 00)

Secured Silicon Sector Indicator Bit (DQ7) (Model 03)

Secured Silicon Sector Indicator Bit (DQ7) (Model 04)

Byte L L H X X V

Word L L H

Byte L L H XF6h

Word L L H

Byte L L H XF9h

LLHSAXVIDXLXLHL

LLHXXVIDXLXLHH

A12

A10

XXV

XLXLLHN/A A3h

XLXLLH

Table 8. In addition, when ver-

A1 A0

DQ8

DQ15

22h F6h

22h F9h

X 01h (protected)

(unprotected)

85 (factory

05 (not factory

8D (factory

0D (not factory

9D (factory

1D (not factory

DQ7

DQ0

00h

locked)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may also be accessed in-system via command sequences . See Table 17 on page 38.

Sector Protection/Unprotection

The hardware sector protection feature di sables both program and er ase operations in an y sector. The hardware sector unprotection feature re-enables both program and erase operations in pre viously protected se ctors.

20 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 23

Advance Information

The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting sectors at its factory prior to shipping the device through the Spansion Express Flash™ Servi ce. Contact a Spansion representative for fur ther details.

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for detail s.

Sector protection/unprotection can be implemented via two methods. The primary method requires VID on the RESET# pin only, and can be implemented either i n-sys-

tem or via programming equipment. Figure 2, on page 25 shows the algorithms and Figure 26,

on page 59 shows the t imin g di agr a m. T his met hod us es sta ndard mi cro proc es sor bus c ycl e t im -

ing. For sector unprote ct, all unpro tec ted se ctor s must first be prot ected prior to the fir st sect or unprotect write cycle.

The alternate method intended only for programming equipment require s VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devi ces. Detail s on this method are provided in a su pplement, publicati on number

21468. Contact a Spansion represent a tive to request a copy.

Ta b l e 9 . Sector Block Addresses for Protection/Unprotection — Model 00

Sector/Sector Block A21–A16 Sector/Sector Block Size

SA0 000000 64 Kbytes

SA1-SA3

SA4-SA7

SA8-SA11

SA12-SA15

SA16-SA19

SA20-SA23

SA24-SA27

SA28-SA31

SA32-SA35

SA36-SA39

SA40-SA43

SA44-SA47

SA48-SA51

SA52-SA55

SA56-SA59

SA60-SA62

SA63

000001,000010,

000011

000100, 000101,

000110, 000111

001000, 001001,

001010, 001011

001100, 001101,

001110, 001111

010000, 010001,

010010, 010011

010100, 010101,

010110, 010111

011000, 011001,

011010, 011011

011100, 011101,

011110, 011111

100000, 100001,

100010, 100011

100100, 100101,

100110, 100111

101000, 101001,

101010, 101011

101100, 101101,

101110, 101111

110000, 110001,

110010, 110011

110100, 110101,

110110, 110111

111000, 111001,

111010, 111011

111100, 111101,

111110 111111 64 Kbytes

192 (3x64) Kbytes

256 (4x64) Kbytes

192 (4x64) Kbytes

June 13, 2005 S29AL032D_00_A3 S29AL032D 21

Page 24

Advance Information

Ta b l e 1 0 . Sector Block Addresses for Protection/Unprotection — Model 03

Sector / Sector Block A20–A12 Sector/Sector Block Size

000000XXX,

SA0-SA3

SA4-SA7

SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 0111XXXXX 256 (4x64) Kbytes SA32-SA35 1000XXXXX 256 (4x64) Kbytes SA36-SA39 1001XXXXX 256 (4x64) Kbytes SA40-SA43 1010XXXXX 256 (4x64) Kbytes SA44-SA47 1011XXXXX 256 (4x64) Kbytes SA48-SA51 1100XXXXX 256 (4x64) Kbytes SA52-SA55 1101XXXXX 256 (4x64) Kbytes SA56-SA59 1110XXXXX 256 (4x64) Kbytes

SA60-SA62

SA63 111111000 8 Kbytes SA64 111111001 8 Kbytes SA65 111111010 8 Kbytes SA66 111111011 8 Kbytes SA67 111111100 8 Kbytes SA68 111111101 8 Kbytes SA69 111111110 8 Kbytes SA70 111111111 8 Kbytes

000001XXX,

000010XXX

000011XXX 0001XXXXX 256 (4x64) Kbytes 0010XXXXX 256 (4x64) Kbytes 0011XXXXX 256 (4x64) Kbytes 0100XXXXX 256 (4x64) Kbytes 0101XXXXX 256 (4x64) Kbytes 0110XXXXX 256 (4x64) Kbytes

111100XXX, 111101XXX,

111110XXX

256 (4x64) Kbytes

192 (3x64) Kbytes

22 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 25

Advance Information

Ta b l e 1 1 . Sector Block Addresses for Protection/Unprotection — Model 04

Sector / Sector Block A20–A12 Sector/Sector Block Size

111111XXX,

SA70-SA67

SA66-SA63 1110XXXXX 256 (4x64) Kbytes SA62-SA59 1101XXXXX 256 (4x64) Kbytes SA58-SA55 1100XXXXX 256 (4x64) Kbytes SA54-SA51 1011XXXXX 256 (4x64) Kbytes SA50-SA47 1010XXXXX 256 (4x64) Kbytes SA46-SA43 1001XXXXX 256 (4x64) Kbytes SA42-SA39 1000XXXXX 256 (4x64) Kbytes SA38-SA35 0111XXXXX 256 (4x64) Kbytes SA34-SA31 0110XXXXX 256 (4x64) Kbytes SA30-SA27 0101XXXXX 256 (4x64) Kbytes SA26-SA23 0100XXXXX 256 (4x64) Kbytes SA22–SA19 0011XXXXX 256 (4x64) Kbytes SA18-SA15 0010XXXXX 256 (4x64) Kbytes SA14-SA11 0001XXXXX 256 (4x64) Kbytes

SA10-SA8

SA7 000000111 8 Kbytes SA6 000000110 8 Kbytes SA5 000000101 8 Kbytes SA4 000000100 8 Kbytes SA3 000000011 8 Kbytes SA2 000000010 8 Kbytes SA1 000000001 8 Kbytes SA0 000000000 8 Kbytes

111110XXX, 111101XXX,

111100XXX

000011XXX, 000010XXX,

000001XXX

256 (4x64) Kbytes

192 (3x64) Kbytes

Write Protect (WP#) — Models 03, 04 Only

The Write Protect function pr ovides a hardw are method of pr otecting c ertain boot sec tors withou t using V

If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 8 Kbyte boot sectors independent ly of whether those sectors were protec ted or unprotected using the method described in two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-bootconfigured device.

If the system asserts V 8K Byte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in

Note that the WP#/ACC pin must not be le ft floa ting or unconnected ; inconsis tent beha vior of t he device may result.

June 13, 2005 S29AL032D_00_A3 S29AL032D 23

. This function is one of two provided by the WP#/ACC pin.

Sector Protection/Unprotection on page 20. The

on the WP#/ACC pin, the device reverts to whether the two outermost

Sector Protection/Unprotection on page 20.

Page 26

Advance Information

Temporary Sector Unprotect

This feature allows t emporary unpr otection of previ ously protected sectors to ch ange data in-sy stem. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once

is removed from the RESET# pin, all the previously protected sectors are protected again.

shows the algorithm, and

Figure 24, on page 58 shows the timing diagrams, for this feature.

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

24 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 27

Advance Information

Temporary Sector

Unprotect Mode

Increment

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 μs

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

START

Protect all sectors:

The indicated portion

of the sector protect

Reset

PLSCNT = 1

Yes

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 μs

First Write

Cycle = 60h?

All sectors protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Temporary Sector

Unprotect Mode

Set up

next sector

address

Algorithm

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protect/Unprotect Algorithms

June 13, 2005 S29AL032D_00_A3 S29AL032D 25

Page 28

Advance Information

Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector feature provides a 256 byte Flash memory region that enables permanent part identification th rough an Electronic Seri al Number (ESN). The Secured Silicon Sect or uses a Secured Si li co n Se c t o r Indicator Bit ( DQ 7 ) to indicate whethe r o r no t the Secured Silico n Sector is locked when shipped fro m the factory . This bit is permanentl y set at the factory and can not be changed, which prev ents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.

Spansion offers the device with the Secured Silicon Sector eit her factory locked or customer lock able. The factory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a 1. The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lockable version has the Secured Si licon Sect or Ind i cator Bit p ermanently se t to a 0. Thus, the Secured Silicon Sector Indicator Bit prevents customer-lockable devices from bein g used to replace devices that are factory locked.

The system a ccesses the Secur ed Silic on Sector through a comm and sequ ence (s ee Enter Se-

cured Silicon Sector/Exit Secured Silicon Sector Command Sequence on page 32). After the

system writes the En ter Sec ured Si licon Sect or co mmand seque nce, it may rea d the Secur ed Sil icon Sector by using the addres ses normally occupi ed by the boot secto rs. This mode of oper ation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up , or following a hardware reset, the devic e reverts to sending commands to the boot sectors.

Factory Lock ed : Se cured Silicon Sector P rogrammed and Protected at the Factory

In a factory lock ed device, the Secured Si licon Sector i s protected when the devi ce is shipped from the factory . The Secured Silic on Sector cannot be modified in any w ay . The device is av ailable preprogrammed with one of the following:

 A random, secure ESN only  Customer code through the ExpressFlash service  Both a random, secure ESN and customer code through the ExpressFlash service.

In devices that have an ESN, a Bottom Boot device has the 16-byte (8-word) ESN in sector 0 at addresses 00000h–0000Fh in b yte mode (or 00000h–00007h in word mode). In t he Top Boot de vice the ESN is in sector 70 at addresses 3FFF00h–3FFF0Fh in byte mode (or 1FFF80h–1FFF87h in word mode). In the Uniform device the ESN is in sector 63 at addresses 3FFF00h-3FFF0Fh in byte mode (or 1FFF80h-1FFF87h in word mode).

Customers may opt to ha ve their code programmed by Spansion throug h the Spansion ExpressFlash service. Spansion programs the customer’s code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Secured Silicon Sector permanently locked. Contact a Spansion representativ e for details on usin g the Spansion ExpressFlash servi ce.

Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the Factory

The customer lockable versi on allows the Secured Silicon Sector to be progr ammed once and then permanently locke d after i t sh ips fr om Span sion. Note that the acc elerated p rogramm ing ( ACC ) and unlock bypass functions are not available when programming the Secured Sili con Sector.

The Secured Silicon Sector area can be protected using the foll owing procedures:  Write the three-cycle Enter Secured Silicon Region command sequence, and then follow the

in-system sector protect algorithm as shown in

may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector

Figure 2, on page 25, except that RESET#

26 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 29

Advance Information

without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector.

 To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm

shown in

Once the Secur ed Silicon Sector is locked and verified, th e syste m must writ e the Exi t Secured Silicon Sector Regio n comman d sequ ence to return to readin g and wr iting the r emaind er of the array.

The Secured Silicon Sector protection must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way.

Figure 3, on page 27.

START

Figure 3. Secured Silicon Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V power-up and power-down transi tions, or from system noise.

RESET# =

or V

Wait 1 μs

Write 60h to any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove VIH or VID

from RESET#

Write reset

command

SecSi Sector Protect Verify

complete

Table 17 on page 38 for command defini ti on s) . In

Low VCC Write Inhibit

When VCC is less than V

power-up and power-down. The co mmand register and all internal progr am/erase circ uits are

disabled, and the device resets. Su bsequent writes are ignored until V system must provide the proper signals to the control pins to prevent unintentional writes when

is greater than V

, the device does not accept any wri te cycles. This pro tects data during

LKO

is greater than V

LKO

. The

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.

June 13, 2005 S29AL032D_00_A3 S29AL032D 27

Page 30

Advance Information

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Soft ware support c an then be device- independe nt , JEDEC ID- indep en dent, and forward- and backward-co mpatible for the specified flash dev ice families. Flash vendors can standardize their existing interf aces fo r long-term compatibility.

This device enters the CFI Query mode when the system wri tes the CFI Quer y command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.

The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the s ystem can read CFI data at the addresses given in Tables mode.

12–15. The system must wri te the reset command to retu rn the device to the autos elect

12–15. In word

Addresses

10h 11h 12h

13h 14h

15h 16h

17h 18h

19h

1Ah

For further information, please contact a Spansion representative for a copy of this document.

Ta b l e 1 2 . CFI Query Identification String

Addresses

(Models 03, 04

Byte Mode

Only)

20h 22h 24h

26h 28h

2Ah 2Ch

2Eh 30h

32h 34h

Data Description

0051h 0052h 0059h

0002h 0000h

0040h 0000h

0000h 0000h

Query Unique ASCII string QRY

Primary OEM Command Set

Address for Prim ary Extended Table

Alternate OEM Command Se t (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

28 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 31

Addresses

Advance Information

Addresses

(Models 03, 04

Byte Mode

Only)

Ta b l e 1 3 . System Interface String

Data Description

1Bh 36h 0027h

1Ch 38h 0036h

1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)

1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0004h T ypical timeout per s ingle byte/word w rite 2N µs 20h 40h 0000h Typical timeou t for M in . siz e buffer write 2N µs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical tim eo u t for full chip erase 2N ms (00h = not supported) 23h 46h 0005h Max. timeout fo r byt e /word write 2N times typical 24h 48h 0000h Max. timeout for bu ffer write 2N times typical 25h 4Ah 0004h Max. timeout per individu a l block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip er ase 2N times typical (00h = not supported)

VCC Min. (write/erase) D7–D4: volt , D3–D0: 100 millivolt

VCC Max. (write/erase) D7–D4: volt , D3–D0: 100 millivolt

June 13, 2005 S29AL032D_00_A3 S29AL032D 29

Page 32

Advance Information

Ta b l e 1 4 . Device Geometry Definition

Addresses

(Models 03, 04

Byte Mode

Addresses

27h 4Eh 0016h Device Size = 2N byte

Only)

Data Description

28h 29h

2Ah 2Bh

2Ch 58h 000xh

2Dh

2Eh 2Fh 30h

31h 32h 33h 34h

35h 36h 37h 38h

39h 3Ah 3Bh 3Ch

50h 52h

54h 56h

5Ah 5Ch

5Eh 60h

62h 64h 66h 68h

6Ah 6Ch

6Eh 70h

72h 74h 76h 78h

000xh 0000h

0000h 0000h

00xxh 0000h 00x0h 000xh

00xxh 0000h 0020h 000xh

0000h 0000h 0000h 0000h

Flash Device Inte rface description (refer to CFI publication 100) (0 = Model 00, 2 = Models 03, 04)

Max. number o f byte in multi-byte write = 2N (00h = not supported)

Number of Erase Block Regions within dev ice (1 = Model 00, 2 = Models 03, 04)

Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) (003F, 0000, 0000, 0001) = Mo del 00

(0007, 0000, 0020, 0000) = Models 03, 04

Erase Block Region 2 Information (0000, 0000, 0000, 0000) = Model 00

(003E, 0000, 0000, 0001) = Models 03, 04

Erase Block Region 3 Information

Erase Block Region 4 Information

Ta b l e 1 5 . Primary Vendor-Specific Extended Query (Sheet 1 of 2)

Addresses

(Models 03, 04

Byte Mode

Addresses

40h 41h 42h

43h 86h 0031h Major version num ber, ASCII 44h 88h 0031h Minor version number, ASCII

45h 8Ah 000xh

46h 8Ch 0002h

47h 8Eh 0001h

Only)

80h 82h 84h

Data Description

0050h 0052h 0049h

Query-unique ASCII string “PRI”

Address Sensitiv e Unlock 0 = Require d (Models 03, 04), 1 = Not Required (Mo del 00)

Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect 0 = Not Supported, X = Nu m ber of sectors in per group

30 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 33

Addresses

Advance Information

Table 15. Primary Vendor-Specific Extended Query (Sheet 2 of 2)

Addresses

(Models 03, 04

Byte Mode

Only) Data Description

48h 90h 0001h

49h 92h 0004h

4Ah 94h 0000h

4Bh 96h 0000h

4Ch 98h 0000h

4Dh 9Ah 00B5h

4Eh 9Ch 00C5h

4Fh 9Eh 000xh

Command Definitions

Writing specific address and data commands or sequences into the command register initiates device operations. incorrect address and data values or writing them in the improper sequence resets the de - vice to reading arra y data.

All addresses are latched on the fallin g edge o f WE# or C E#, whic hever happens lat er. All data is latched on the risi ng edge of W E# or CE#, whi chever h appens fi rst. R efer to t he appropri ate tim ing diagrams in the “AC Characteristics” section.

Sector Temporary Unprotect 00 = Not Sup porte d, 01 = Supported

Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 m o de, 04 = 29LV800A mode

Simultaneo us Operation 00 = Not Sup porte d, 01 = Supported

Burst Mode Type 00 = Not Sup porte d, 01 = Supported

Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supp ly Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supp ly Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag (0 = Model 00, 2 = Model 03, 3 = Model 04)

Table 17 on page 38 defines the valid register command sequences. Writing

Reading Array Data

The device is a utomatically s et to readi ng array data af ter devi ce power-u p. No commands are required to retrieve data. The device is also ready to read array data after completing an Embed ded Program or Embedded Erase algor ithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an ad dress within erase-suspended sectors, the device outputs status data. After completing a programming operation in th e Er ase Suspend mode, the system may once again read array data with the same exception. See formation on this mode.

The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the

See also Requirements fo r Reading Array Data on pa ge 11 for more information. The Read

Operations on page 50 provides the read parameters , and Figure 14, on page 50 shows the ti ming

diagram.

June 13, 2005 S29AL032D_00_A3 S29AL032D 31

Erase Suspend/Erase Resume Commands on page 35 for more in-

Reset Command on page 32 section, next.

Page 34

Advance Information

Reset Command

Writing the reset co mmand to the device resets the device t o reading arra y data. Address bits are don’t care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This res ets the device to reading array d ata. Once erasure begins, howeve r , the device ignores reset commands until the operation is c omplete.

The reset command may be written between the sequence cycles in a program command sequence before progra mmin g begins. This resets the device to reading array data (also appli es to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to re adin g array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect c ommand se quence allo ws the hos t system to acce ss the manu facturer an d devices codes, and determine whether a sector is protected. Table 17 on page 38 shows the address and data requirements. This method is an alternative to that shown in Table 8 on page 20, which is intended for PROM programmers and requires VID on address bit A9.

The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device t hen enters the aut oselect m ode, and the s ystem may re ad at any address any number of times, without initiating another command sequence.

A read cycle at address 0XXX00h retrieves the manufacturer code. A read cycle at address 0XXX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to

The system must write the reset command to exit the autose lect mode and retu rn to reading array data.

Table 2 on page 14 and Table 4 on page 16 for valid sector addresses.

Enter Secured Silicon Sector/Exit Secured Silicon Sector Command

Sequence

The Secured Silicon Sector region provides a secured data area containing a random, sixteenbyte electronic serial number (ESN). The sys tem can access the Secured Silic on Sector region by issuing the three-c ycle En ter Sec ured Sili con Sector comman d sequence. The device co ntinues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Sili con Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. and Table 17. S29AL032D Command Definitions — Models 03, 04 on page 38 show the addresses and data requirements for both command sequences. Note that the ACC function and unlock bypass modes are not available when the device enters the Secured Silicon Sector. See

Secured Silicon Sector Flash Memory Region on page 26 for further information.

also

Table 16. S29AL032D Command Definitions — Model 00 on page 37

Word/Byte Program Command Sequence

Models 03, 04 may program the device by word or byte, depending on the state of the BYTE# pin. Model 00 may program the device by byte only. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The progra m address and data are written next, which in tur n initiate

32 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 35

Advance Information

the Embedded Program algorithm. The sys tem i s not required to provide further controls or tim- ings. The device automatically generates the program pulses and verifies the programmed cell margin. command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or R Y/BY#. See on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reiniti at e d once the device has reset to r e ading array data, to en sure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be pro- grammed fr om a 0 back to a 1. Attem pting to do s o may ha lt t he oper a tion a nd se t DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a suc ceeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1.

Table 17 on page 38 shows the address and data requirements for the byte program

Write Operation Status on page 39 for information

Unlock Bypass Command Sequence

The unlock bypass feature all ows the syst em to progr am bytes or words to the devi ce faster than using the standard program command sequence. The unlock bypass command sequence is initi ated by first writing two un lock cycles. T his is followed by a th ird write cycle c ontaining the unlo ck bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock by pass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence , resulting in faster t o t al programming time. command sequence.

During the unlock bypass mode, o nly the U nlock Bypass Progr a m and Unlo ck Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cy cles. The device then ret urns to reading arr ay data.

Figure 4, on page 34 illus trat es the algorithm f or the progr am oper ation. See t he Erase/Program Operations on page 54 f or pa rameters, and to Figure 18, on page 55 for timing diagrams.

Table 17 on pa ge 38 shows the requirements for the

June 13, 2005 S29AL032D_00_A3 S29AL032D 33

Page 36

Advance Information

START

Write Program

Command Sequence

Data Poll

Embedded

Program

algorithm

in progress

from System

Increment Address

NOTE: See Table 17 for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiate d by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram pri or to erase. The E mbedded Erase algori thm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not requir ed to pr ovide an y cont rols o r timin gs duri ng th ese oper ations. Table 17 on page 38 shows the address and data requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure dat a i nt egrity.

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

The system can determine the status of the er ase operation b y using DQ7, DQ6, DQ2, or RY/BY#.

Write Operation Status on page 39 for information on these status bit s. When the Embedded

See Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.

Figure 5, on page 36 illustrates the a lgorithm for the erase operation. See Erase/Program Operations on page 54 f or pa rameters, and to Figure 19, on page 56 for timing diagrams.

34 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 37

Advance Information

Sector Erase Command Sequence

Sector erase is a six bus cycle oper ation. The sector er ase command sequence is initiated by writing two unlock cycles, foll owed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command.

page 38 shows the address and data requirements for the sector erase command sequence.

The device does not requi re the system to preprogram the memory prio r to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs begins. During the timeout period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and er asure may begin. It is recommended that processor interrupts be disabled durin g this time to ensure al l commands are accepted. The interrupts can be re-enabled aft er t he last Sector E ras e command is writ ten. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time- out period resets the device to reading array data. T he syst em must rewrite the command sequence and any additional sector addresses and commands.

The system can monitor DQ3 to determine if the sec tor erase timer has timed out . (See the “DQ3: Sector Er as e Tim er” sec tion .) The time-out begins from the risin g edge of the final WE# pulse in the command sequenc e .

Table 17 on

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hard ware rese t during the sector erase operation immedi ately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading a rray data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to status bits.)

Figure 5, on page 36 illustrates the algorithm for the erase operation. Refer to Erase/Program Operations on page 54 f or pa rameters, and to Figure 19, on page 56 for timing diagrams.

“Write Operation Status” for information on these

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector no t select ed for erasure . This comm and is valid only during the sector erase oper ation, including the 50 µs time-out period duri ng the sector erase command sequence. The Erase Suspend command is ignor ed if written durin g the chip erase op eration or Embedded Program algorithm. Wri ting the E r ase Suspend c ommand duri ng th e Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses ar e don’t-cares when writing the Erase Suspend command.

When the Erase Suspend command is writt en during a sector er ase operation, the device requires a maximum of 20 µs to suspend the erase operation. Howev er , when t he Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out pe riod and suspends the erase oper ation.

After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definitions apply . Reading at any address

June 13, 2005 S29AL032D_00_A3 S29AL032D 35

Page 38

Advance Information

within erase-suspended sectors produces st atus data on D Q7–DQ0. The system can u se DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See

Write Operation Status on page 39 for infor mation on the se status bits .

After an erase-suspended program operation is complete, the system can once ag ai n rea d array data within non -suspended sectors. The system can determine the status of the pr ogram opera tion using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write

Operation Status on page 39 for more information.

The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sec tors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation.

Autoselect Command Sequence on page 32 for more information.

See The system must write the Erase R esume command (address bits are don’ t care) to exit the erase

suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 17 for erase command sequence.

2. See DQ3: Sector Erase Timer on page 44 for more information.

Figure 5. Erase Operation

Embedded Erase algorithm in progress

36 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 39

Advance Information

Command Definitions

Ta b l e 1 6 . S29AL032D Command Definitions — Model 00

Command Sequence

(Note 1)

Read (Note 5) 1RA RD Reset (Note 7) 1 XXX F0

Manufacturer ID (Note 8) 4 XXX AA XXX 55 0XXXXX 90 0XXX00 01 Device ID (Note 8) 4 XXX AA XXX 55 0XXXXX 90 0XXX01 A3 Secured Silicon Sector Factory

(Note 15)

Protect

(Note 7)

Autoselect

Sector Protect Verify

(Note 9)

Enter Secured Silicon Sect or Region 3 XXX AA XXX 55 XXX 88 XXX Exit Secured Silicon Secto r Re g ion 4 XXX AA XXX 55 XXX 90 XXX 00 Byte Program 4 XXX AA XXX 55 XXX A0 PA PD Unlock Bypass 3 XXX AA XXX 55 XXX 20 Unlock Bypass Program

(Note 10)

Unlock Bypass Reset

(Note 11)

Chip Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 XXX 10 Sector Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 SA 30 Erase Suspend (Note 12) 1 XXX B0 Erase Resume (Note 13) 1 XXX 30 CFI Query (Note 14) 1 XXX 98

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

4 AAA AA 555 55 AA A 90 X06 85/05

XXX

XXX XXX 01

2 XXX A0 PA PD

2 XXX 90 XXX 00

XXX

Legend:

X = Don’t care, RA = Address of the memory location to be read, RD = Data read from location RA during read operation, PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse. SA = Address of the sector to be erased or verified. Address bits A21–A16 uniquely select any sector.

Notes:

1. See Table 1 on page 11 for descriptions of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are write operations.

4. Address bits are don’t care for unlock and command cycles, except when PA or SA is required.

5. No unlock or command cycles required when device is in read mod e.

6. The Reset command is required to return to the read mode when the device is in the auto select mode or if DQ5 goes high.

7. The fourth cycle of the autoselect command sequence is a read cycle.

8. In the third and fourth cycles of the command sequence, set A21 to 0.

9. In the third cycle of the command sequence, address bit A21 must be set to 0 if verifying sectors 0–31, or to 1 if verifying sectors 32–64. The data in the fourth cycle is 00h for an unprotected sector/sector block and 01h for a protected sector/ sector block.

10.The Unlock Bypass command is required prior to the Unloc k Byp ass Program command.

11.The Unlock Bypass Reset command is requ ired to return to reading array data when the d evice is in the Unlock Bypass mod e.

12.The system may read and program functions in non-e rasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is va lid only during a sector erase operation.

13.The Erase Resume command is valid only during the Erase Suspend mode.

14.Command is valid when device is ready to read array data or when device is in autoselect mode.

15.The data is 85h for factory locked and 05h for not factory locked.

Bus Cycles (Notes 2–4)

0XXXXX

2XXXXX

X02

June 13, 2005 S29AL032D_00_A3 S29AL032D 37

Page 40

Advance Information

Ta b l e 1 7 . S29AL032D Command Definitions — Models 03, 04

Command

Sequence

(Note 1)

Read (Note 6) 1RA RD Reset (Note 7) 1XXX F0

Manufacturer ID Device ID,

Model 03 Device ID,

Model 04 Secured Silicon Sector

Factory Protect Model 03, (Note 9)

Secured Silicon Sector Factory Protect Model 04, (Note 9)

Autoselect (Note 8)

Sector Protect Verify

(Note 10)

Enter Secured Silicon Sector Region

Exit Secured Silicon Sector Region

CFI Query (Note 11)

Program

Unlock Bypass Unlock Bypass Program (Note 12) 2XXX A0 PA PD

Unlock Bypass Reset (Note 13) 2XXX 90 XXX 00 Chip Erase

Sector Erase Erase Suspend (Note 14) 1XXX B0

Erase Resume (Note 15) 1XXX 30

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA X02 F6

Word

Byte AAA 555 AAA X02 F9

Word

Byte AAA 555 AAA X06

Word

Byte AAA 555 AAA X06

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Ad dr Data Addr Data Addr Data

555

2AA

Bus Cycles (Notes 2–5)

555

90 X00 01

X01 22F6

X01 22F9

X03

555

(SA)

X02

(SA)

X04

90 XXX 00

A0 PA PD

555

8D/0D

9D/1D

XX00 XX01

00 01

2AA

55 SA 30

555

Legend:

X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read o p eration. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever

happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector.

38 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 41

Advance Information

Notes:

1. See Table 1 on page 11 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the four th cycle of the autose lect command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.

5. Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required.

6. No unlock or command cycles required when reading array data.

7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data).

8. The fourth cycle of the a utoselect comman d sequence is a read cycle.

9. For Model 03, the data is 8Dh for factory locked and 0Dh for not factory locked. For Model 04, the data is 9Dh for factory locked and 1Dh for not factory locked.

10. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.

11. Command is valid when device is ready to read array data or when device is in autoselect mode.

12. The Unlock Bypass comman d is required prior to the Unlock Bypass Program comman d .

13. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also acceptable.

14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid o nly during a sector erase ope ration.

15. The Erase Resume command is valid only during the Erase Suspend mode.

Write Operation Status

The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. of these bits. DQ7, RY/B Y#, an d DQ6 each of fer a metho d for determin in g wheth er a progr a m or erase operation is complete o r in progress. These three bits are discussed first.

Table 18 on page 44 and the following subsections describe the functions

DQ7: Data# Polling

The Data# Polling bit, DQ 7, indicates to the host syste m whether an Embedde d Algorithm is in progress or completed, or whether th e device is in Er ase Suspend. Data# P olling is v alid after t he rising edge of the final WE# pulse in the program or erase command sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status als o applies to progr amming during E rase Suspend. When the Embedded Program algorithm is comple te, the devic e output s the datum progr ammed to DQ7. The system must provide the progr a m address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approxi mately 1 µs, then the device returns to reading array data.

During the Embedded Erase algorithm, Data# P olli ng produc es a 0 o n DQ7. When the Embedded Erase algorithm is complete, o r if the device enters the Er ase Suspend mode, Data# Polli ng pr o duces a 1 on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is acti ve for approxi mately 100 µs, then the device return s to reading arra y data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro tected sectors, and ignores the selected sectors that are protected.

When the syst e m d e tects DQ7 has chan g e d from the comple m e nt to tr ue d a t a, i t ca n read valid data at DQ7–DQ0 on th e following read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. Timings (During Embedded Algorithms), in the AC Characteristics on page 50 section illustrates this.

Figure 21, on page 57, Data# Polling

June 13, 2005 S29AL032D_00_A3 S29AL032D 39

Page 42

Advance Information

Figure 18, on page 44 shows the outputs for Data# Polling on DQ7. Figure 7, on page 43 shows

the Data# Po lling algorithm.

START

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

FAIL

Yes

PASS

Notes:

1. VA = Valid address fo r programmin g. During a sector erase operation, a valid address is an addres s within any sector se le cted for er asure. Du ring chip er ase, a valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.

Figure 6. Data# Polling Algorithm

RY/ BY # : R ea d y/ Bus y#

The RY/BY# is a dedicated, open -drain output pin th at indicate s whether an Embedded Al gorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V

40 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 43

Advance Information

If the output is low (Busy), the device is actively er asing or progr amming. (This incl udes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

Table 18 on page 44 shows the outputs for RY/B Y#. Fi gures Figure 14, o n page 50, Figure 15, on page 51, Figure 18, on page 55 and Figure 19, on page 56 shows RY/BY# for read, reset, pro-

gram, and erase operations, respectively.

DQ6: Toggle Bit I

T ogg le Bit I on DQ6 indi cates whether an Embedded Progr am or Er ase algo rithm i s in progr ess or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is v alid after the risin g edge of the final WE# pulse i n the command sequence (prior to the program or erase operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the re ad cycles.) When the operation is complete, DQ6 stops toggl ing.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protecte d.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog gling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively , the system can use DQ7 (see the subsection on

page 39).

If a program address falls within a pro tected sect or, DQ6 toggles for approximately 1 µs aft er the program command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once th e Embedded Program algorithm is complete.

Table 18 on page 44 shows the outputs fo r Toggle Bit I on DQ6. Figure 7, on page 43 shows the

toggle bit algorithm in flowchart form, and the sect ion Rea ding Toggle Bits DQ6/DQ2 on page 42 explains the algorithm. Figure 22, on page 57 shows the toggle bit timing diagrams. Figure 23,

on page 58 shows the differences betw een DQ2 and D Q6 in graphi cal form. See als o the s ubsec -

tion on DQ2: To ggle Bit II.

DQ7: Data# Pol ling on

DQ2: Toggle Bit II

The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may us e either OE# or CE# to cont rol the read cy cles.) But DQ2 cannot distinguish whether the sector is actively er asing or is er ase-suspended. DQ6, by comparison, in dicates whether the device is act ively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to

Figure 7, on page 43 shows the toggle bit algorithm in flowchart form, and the section Reading T o ggle Bi ts DQ6 /DQ2 on page 42 explains the algorithm. See also the DQ6: Togg le Bi t I subsec-

June 13, 2005 S29AL032D_00_A3 S29AL032D 41

Table 18 on page 44 to compare outputs for DQ2 and DQ6.

Page 44

Advance Information

tion. Figure 22, on page 57 shows the toggle bit timing diagram. Figure 23, on page 58 shows the differences between DQ2 and DQ6 in graphical f orm.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 7, on page 43 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit i s still tog gling, the system also s hould note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the progr am or erase operation. If it is still toggling, the devi ce did not complete the operation successfully, and the system must write the reset command to return to readi ng a r ray data .

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through suc cessive read cycle s, determining the status as descr ibed in t he previou s para grap h. Alternativ ely, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it ret urns to determine the st atus of the oper ation (top of

43).

Figure 7, on page

42 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 45

Advance Information

START

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

Notes:

1. Read toggle bit twice to determine whether or not it is toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not Complete, Write Reset Command

(Note 1)

(Notes 1,2)

Program/Erase

Operation Complete

Figure 7. Toggle Bit Algorithm

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. Thi s is a failure c ondition that indicates the pro gram or erase cycle was not successfully completed.

The DQ5 failure condition may appear if the system tries to progr am a 1 to a location that is pre- viously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this

June 13, 2005 S29AL032D_00_A3 S29AL032D 43

Page 46

condition, the device halts the operation, and when the oper ation has exceeded the timing limits, DQ5 produces a 1.

Under both these conditions, the system must issue the reset command to return the device to reading array data.

DQ3: Sector Erase Timer

After writing a sector er ase command sequence, t he system may read D Q3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional se ctors are selected fo r erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to

1. The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 μs. See also the

Sequence on page 35 section.

After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle has begun; all further com mands (other than Erase Suspend) are ignore d until the er ase operation is complete. I f DQ3 is 0, the device will accept additional sector erase commands. To ensure the command has been ac cepted, the system software shou ld check the status of DQ3 prior to and follow ing each subsequent sector erase command. If DQ3 is high on the second status check, the last c ommand might not have been accepted.

Advance Information

Sector Erase Command

Table 18 shows the outputs for DQ3.

Ta b l e 1 8 . Write Operation Status

DQ7

Operation

Standard Mode

Erase Suspend Mode

Notes:

1. DQ5 switches to ‘1’ when an Em be dd ed Prog r am or Em bed d ed E ras e op er at io n has ex cee de d th e maxi mu m tim in g limits. See DQ5: Exceeded Timing Limits on page 43 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Embedded Program Algorithm Embedded Erase Algorit hm 0 Toggle 0 1 Toggle 0 Reading within Eras e

Suspended Sector Reading within Non-E rase

Suspended Sector Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

(Note 2) DQ6

DQ7# Toggle 0 N/A No toggle 0

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

44 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 47

Advance Information

Absolute Maximum Ratings

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 5°C to +150°C

Ambient Temperature

with Power Applie d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET# (N o te 2) . . . . . . . . . . . . . . . . –0 .5 V to +12.5 V

All other pins (N o te 1). . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V

Output Short Circuit Curren t (N o te 3). . . . . . . . . . . . . . . . . . . . . . . . 2 00 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 9,

on page 45.

2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. D uring voltage transitions, A9, OE#, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 8, on page 45. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 8, on page 45. Maximum DC voltage on input or I/O pins is VCC +0.5

20 ns

+0.8 V

–0.5 V –2.0 V

Figure 8. Maximum Negative

Overshoot Waveform

Operating Ranges

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85 ° C

VCC Supply Voltages

VCC for standard volt a g e range . . . . . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

20 ns

+2.0 V

+0.5 V

2.0 V 20 ns

Figure 9. Maximum Positive Overshoot Waveform

June 13, 2005 S29AL032D_00_A3 S29AL032D 45

Page 48

Advance Information

DC Characteristics

CMOS Compatible

Parameter Description Test Conditions Min Typ Max Unit

V V

V V V V

LIT

CC1

CC2

CC3

CC4

CC5

ACC

OH1

OH2

LKO

Input Load Current (Note 7)

A9 Input Load Current VCC = V

Output Leakage Current

VCC Active Read Current (Notes 1, 2)

VCC Active Write Current (Notes 2, 3, 5)

VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC±0.3 V 0.2 5 µA VCC Standby Current During Reset

(Notes 2, 4) Automatic Sleep Mode

(Notes 2, 4, 6)

ACC Accelerated Program Current, Word or By te

Input Low Voltage –0.5 0.8 V Input High Voltage 0.7 x V Voltage for WP#/ACC Sector Protect/

Unprotect and Program Acceleration Voltage for Autoselect and Temporary

Sector Unprotect Output Low Voltage IOL = 4.0 mA, VCC = V

Output High Voltage

Low VCC Lock-Out Voltage (Note 4) 2.3 2.5 V

Notes:

1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.

2. Maximum ICC specifications are tested with VCC = VCCmax.

3. ICC active while Embedded Erase or Embedded Program is in progress.

4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA.

5. Automatic sleep mode enables the low power mode when addresses remain stable for t mode current is 200 nA.

6. Not 100% tested.

7. On the ACC pin only, the maximum input load current when ACC = VIL is ±5.0 µA.

VIN = VSS to VCC, VCC = VCC

OUT

VCC = V

max

; A9 = 12.5 V 35 µA

CC max

= VSS to VCC,

CC max

±1.0 µA

10 MHz 15 3 0

CE# = V Byte Mode

IL,

OE#

= VIH,

5 MHz 9 16 1 MHz 2 4

10 MHz 18 3 5

CE# = V Wor d Mode

IL,

OE#

= VIH,

5 MHz 9 16 1 MHz 2 4

CE# = V

RESET# = V

VIH = V V

CE# = VIL, OE# = V

= V

OE# = V

IL,

± 0.3 V;

± 0.3 V

± 0.3 V 0.2 5 µA

15 35 mA

0.2 5 µA

ACC pin 5 10 mA

pin 15 30 mA

VCC + 0.3 V

VCC = 3.0 V ± 10% 11.5 12.5 V

VCC = 3.3 V 11.5 12.5 V

0.45 V

CC min

IOH = -2.0 mA, VCC = V IOH = -100 µA, VCC = V

2.4 V

CC min

VCC–0.4 V

CC min

+ 30 ns. Typical sleep

ACC

46 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 49

Advance Information

DC Characteristics

Zero Power Flash

Supply Current in mA

0 500 1000 1500 2000 2500 3000 3500 4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 10. I

Supply Current in mA

12345

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

3.6 V

2.7 V

Frequency in MHz

Note: T = 25 °C

Figure 11. Typical I

June 13, 2005 S29AL032D_00_A3 S29AL032D 47

vs. Frequency

CC1

Page 50

Test Conditions

Advance Information

3.3 V

Device

Under

Test

Note: Diodes are IN3064 or equivalent

6.2 k

Figure 12. Te s t Se t u p

Ta b l e 1 9 . Test Specifications

2.7 k

Speed Option 70 90 Unit

Output Load 1 TTL gate Output Load Capacita nce, C

(including jig capacitance) Input Rise and Fall Times 5 ns Input Pulse Levels 0.0 or V Input timing me a su re ment

reference levels Output timing m easurement

reference levels

30 100 pF

0.5 V

48 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 51

Advance Information

Key to Switching Waveforms

Waveform Inputs Outputs

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Ch ange Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

0.0 V

0.5 V

OutputMeasurement LevelInput

Figure 13. Input Waveforms and Measurement Levels

June 13, 2005 S29AL032D_00_A3 S29AL032D 49

Page 52

AC Characteristics

Read Operations

Advance Information

Parameter

JEDEC Std Test Setup 70 90 Unit

AVAV

AVQV

ELQV

GLQV

EHQZ

GHQZ

AXQX

Notes:

1. Not 100% tested.

2. See Figure 12, on page 48 and Table 19 on page 48 for test specifications.

Addresses

Description

Read Cycle Time (Note 1) Min 70 90 ns

Address to Output Delay

ACC

Chip Enable to Output Delay OE# = V

Output Enable to Output Delay Max 30 35 ns

Chip Enable to Output High Z (Note 1) Max 25 30 ns

Output Enable to Output High Z (Note 1) Max 25 30 ns

Output Enable

OEH

Hold Time (Note 1) Output Hold Time From Add resses, CE# or OE#,

Whichever Occurs First

Read Min 0 ns Toggle a nd Data# P olling Min 10 ns

(Note 1)

CE# = V

OE# = V

IL IL

Addresses Stable

ACC

Speed Options

Max 70 90 ns

Min 0 ns

CE#

HIGH Z

OE#

WE#

Outputs

OEH

HIGH Z

Output Valid

RESET#

RY/BY#

0 V

Figure 14. Read Operations Timings

50 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 53

Advance Information

AC Characteristics

Hardware Reset (RESET#)

Parameter

Description

READY

RESET# Pin Low (During Embedded A lgorithms) to Read or Write

RESET# Pin Low (NOT During Embedded Algorithms) to Read or W rite

RESET# Pulse Width Min 500 ns

RESET# High T im e Be fore Read (See Note) Min 50 ns

RESET# Low to Stan dby Mode Min 20 µs

RPD

RY/BY# Recovery Time Min 0 ns

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

(See Note)

Ready

(See Note)

All Speed OptionsJEDEC Std Test Setup Unit

Max 20 µs

Max 500 ns

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

Ready

RY/BY#

CE#, OE#

RESET#

Figure 15. RESET# Timings

June 13, 2005 S29AL032D_00_A3 S29AL032D 51

Page 54

AC Characteristics

Word/Byte Configuration (BYTE#) (Models 03, 04 Only)

Parameter Speed Options

Advance Information

JEDEC Std

t t t

BYTE#

Switching

from word

to byte

mode

ELFL/tELFH

FLQZ

FHQV

Description

70 90 Unit

CE# to BYTE# Switching Low or High Max 5 ns BYTE# Switching Low to Output HIGH Z Max 25 30 ns BYTE# Switc hin g H igh to Output Activ e Min 70 90 ns

CE#

OE#

BYTE#

DQ0–DQ14

ELFL

DQ15/A-1

Data Output

(DQ0–DQ14)

DQ15

Output

FLQZ

Data Output (DQ0–DQ7)

Address

Input

ELFH

BYTE#

BYTE# Switching from byte

to word

DQ0–DQ14

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

mode

DQ15/A-1

Address

Input

FHQV

DQ15

Output

Figure 16. BYTE# Timings for Read Operations

52 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 55

Advance Information

AC Characteristics

CE#

WE#

The falling edg e of the last WE# signal

BYTE#

Note: Refer to the Erase/Program Operations tab l e for t

SET

(tAS)

Figure 17. BYTE# Timings for Write Operations

(tAH)

HOLD

and tAH specifications.

June 13, 2005 S29AL032D_00_A3 S29AL032D 53

Page 56

Advance Information

Erase/Program Operations

Parameter Speed Options

JEDEC Std

AVAV

AVWL

WLAX

DVWH

WHDX

GHWL

ELWL

WHEH

WLWH

WHWL

WHWH1

OES

GHWL

WPH

SR/W

WHWH1

Description

70 90 Unit

Write Cycle Time (Note 1) Min 70 90 ns Address Setup Time Min 0 ns Address Hold Time Min 45 45 ns Data Setup Time Min 35 45 ns Data Hold Time Min 0 ns Output Enab le S e tup Time Min 0 ns Read Recovery Time Before Write

(OE# High to WE# Low)

Min 0 ns

CE# Setup Time Min 0 ns CE# Hold Time Min 0 ns Write Pu ls e Width Min 35 35 ns Write Pu ls e Width High Min 30 ns Latency Betwee n Read and Write Operations Min 20 ns

Byte Typ 9

Programmin g Operation (No te 2)

µs

Word Typ 11

Accelerated P rogramming Ope ration, W ord or Byte (Note

Typ 7 µs

WHWH2

VCS

BUSY

Sector Erase Operation (Not e 2) Typ 0.7 sec VCC Setup Time (Note 1) Min 50 µs Recovery Tim e from RY/BY# Min 0 ns Program/Erase V a lid to RY/BY# Delay Max 90 ns

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance on page 62 for more information.

54 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 57

Advance Information

AC Characteristics

Program Command Sequence (last two cycles)

Addresses

555h

Read Status Data (last two cycles)

PA PA

CE#

OE#

WE#

WPH

Data

A0h

RY/BY#

VCS

Notes:

1. PA = program address, PD = program data, D

2. Illustration shows device in word mode.

Figure 18. Program Operation Timings

WHWH1

BUSY

is the true data at the program address.

OUT

Status

OUT

June 13, 2005 S29AL032D_00_A3 S29AL032D 55

Page 58

AC Characteristics

Erase Command Sequence (last two cycles) Read Status Data

Advance Information

555h for chip erase

Addresses

2AAh SA

CE#

OE#

WE#

Data

WPH

55h

30h

10 for Chip Erase

BUSY

WHWH2

Progress

Complete

RY/BY#

VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on

page 39).

2. Illustration shows device in word mode.

Addresses

CE#

OE#

WE#

Data

Figure 19. Chip/Sector Erase Operation Timings

WDH

PA PA PA PA

Valid In Valid Out

SR/W

ACC

GHWL

Figure 20. Back to Back Read/Write Cycle Timing

Valid

CPH

Valid

Out

56 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 59

Advance Information

AC Characteristics

Addresses

ACC

CE#

OE#

WE#

DQ7

OEH

Complement

VA VA

Complement

True

Valid Data

High Z

DQ0–DQ6

BUSY

Status Data

True

Valid Data

High Z

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and

array data read cycle.

Figure 21. Data# Polling Timings (During Embedded Algorithms)

Addresses

CE#

OE#

WE#

DQ6/DQ2

RY/BY#

BUSY

OEH

High Z

ACC

(first read) (second read) (stops toggling)

VA VA

Valid Status

Valid DataValid StatusValid Status

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last

status read cycle, and array data r ead cycle.

Figure 22. Toggle Bit Timings (During Embedded Algorithms)

June 13, 2005 S29AL032D_00_A3 S29AL032D 57

Page 60

Advance Information

AC Characteristics

Enter

Embedded

Erasing

WE#

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Temporary Sector Unprotect

Parameter

Erase

Suspend

Erase Suspend

Read

Enter Erase

Suspend Program

Erase

Erase Suspend

Read

Erase

Resume

Erase

Figure 23. DQ2 vs. DQ6 for Erase and Erase Suspend Operations

Erase

Complete

Note:

Not 100% tested.

RESET#

CE#

WE#

RY/BY#

VIDR

RSP

Description

VID Rise and Fall Time (See Note) Min 500 ns RESET# Setup Time for Temporary Sector

Unprotect

Min 4 µs

All Speed OptionsJEDEC Std

12 V

0 or 3 V

VIDR

Program or Erase Command Sequence

RSP

Figure 24. Temporary Sector Unprotect/Timing Diagram

Unit

58 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 61

Advance Information

AC Characteristics

or V

WP#/ACC

RESET#

IH V

VHH

Figure 25. Accelerated Program Timing Diagram

VHH

or V

SA, A6,

A1, A0

Valid* Valid* Valid*

Sector Protect/Unprotect Verify

Data

60h 60h 40h

1 µs

Sector Protect: 150 µs

Sector Unprotect: 15 ms

CE#

WE#

OE#

Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 26. Sector Protect/Unprotect Timing Diagram

Status

June 13, 2005 S29AL032D_00_A3 S29AL032D 59

Page 62

AC Characteristics

Alternate CE# Controlled Erase/Program Operations

Parameter Speed Options

Advance Information

JEDEC Std

AVAV

AVEL

ELAX

DVEH

EHDX

GHEL

WLEL

EHWH

ELEH

EHEL

WHWH1

OES

GHEL

CPH

SR/W

WHWH1

Description

70 90 Unit

Write Cycle Time (No te 1) Min 70 90 ns Address Setup Time Min 0 ns Address Hold Time Min 45 45 ns Data Setup Time Min 35 45 ns Data Hold Time Min 0 ns Output Enable Setu p Time Min 0 ns Read Re covery Time Before Write

(OE# High to WE# Low)

Min 0 ns

WE# Setup Time Min 0 ns WE# Hold Time Min 0 ns CE# Pulse Width Min 35 35 ns CE# Pulse Width High Min 30 ns Latency Betwee n Read and Write Ope rations Min 20 ns

Byte Typ 9

Programm ing Operation (N ote 2)

µs

Word Typ 11

Accelerated Programming Operation , Word or Byte (Note 2)

Typ 7 µs

WHWH2

Notes:

1. Not 100% tested.

2. See the Erase and Programming Performance on page 62 section for more information.

WHWH2

Sector Erase Operation (Note 2) Typ 0.7 sec

60 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 63

Advance Information

AC Characteristics

Addresses

WE#

OE#

CE#

Data

RESET#

555 for program 2AA for erase

PA for program SA for sector erase 555 for chip erase

GHEL

CPH

A0 for program 55 for erase

BUSY

PD for program 30 for sector erase 10 for chip erase

Data# Polling

WHWH1 or 2

DQ7# D

OUT

RY/BY#

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D written to the device.

2. Figure indicates the last two bus cycles of the command sequence.

3. Word mode address used as an example.

Figure 27. Alternate CE# Controlled Write Operation Timings

OUT

= data

June 13, 2005 S29AL032D_00_A3 S29AL032D 61

Page 64

Advance Information

Erase and Programming Performance

Parameter

Sector Erase Time 0.7 10 s Chip Erase Time 45 s Byte Programming Time 9 300 µs Word Programming Time 11 360 µs Accelerate d Byte/Word Program ming

Time Chip Programming Time

(Note 3)

Notes:

1. Typical program and erase times assume the following conditions: 25°C, V data pattern.

2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 17 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.

Byte Mode 36 108 s

Word Mode 24 72 s

Typ (Note 1) Max (Note 2) Unit Comments

Excludes 00h programming prior to erasure (Note 4)

7 210 µs

= 3.0 V, 100,000 cycles, checkerboard

Excludes system level overhead

(Note 5)

TSOP and BGA Pin Capacitance

Parameter

Symbol

OUT

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

Parameter Description Test Setup Package Typ Max Unit

Input Capacitance VIN = 0

Output Capacitance V

Control Pin Capacitance VIN = 0

OUT

TSOP 6 7.5 pF

BGA 4.2 5.0 pF

TSOP 8.5 12 pF

= 0

BGA 5.4 6.5 pF

TSOP 7.5 9 pF

BGA 3.9 4.7 pF

62 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 65

Advance Information

Physical Dimensions

TS040—40-Pin Standard TSOP

Dwg rev AA; 10/99

June 13, 2005 S29AL032D_00_A3 S29AL032D 63

Page 66

Advance Information

Physical Dimensions

TS 048—48-Pin Standard TSOP

STANDARD PIN OUT (TOP VIEW)

SEE DETAIL B

0.10

2X (N/2 TIPS)

0.10

REVERSE PIN OUT (TOP VIEW)

N 2

0.25

2X (N/2 TIPS)

PARALLEL TO

SEATING PLANE

SEE DETAIL A

SEATING

PLANE

N 2

0.08MM (0.0031") M C A - B S

WITH PLATING

(c)

BASE METAL

SECTION B-B

θ°

DETAIL A

(c)

GAUGE PLANE

0.25MM (0.0098") BSC

DETAIL B

e/2

X = A OR B

NOTES:

Jedec

Symbol

A A1 A2 b1

e L 0 R N

MO-142 (D) DD

MIN

0.05

0.95

0.17

0.10

19.80

20.00

18.30

18.40

11.90

12.00

0.50 BASIC

0.50 0˚

0.08

NOM

1.00

0.20

0.22

0.60

MAX

1.20

0.15

1.05

0.23

0.27

0.16

0.21

20.20

18.50

12.10

0.70 8˚

0.20

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF

CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS

0.15mm (.0059") PER SIDE.

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE

0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND

0.25MM (0.0098") FROM THE LEAD TIP.

LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

* For reference only. BSC is an ANSI standard for Basic Space Centering.

64 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 67

Advance Information

Physical Dimensions

VBN048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

10.0 x 6.0 mm

-0.50

+0.20

1.00

+0.20

1.00

-0.50

PACKAGE VBN 048

JEDEC N/A

10.00 mm x 6.00 mm NOM PACKAGE

SYMBOL MIN NOM MAX NOTE

A --- --- 1.00 OVERALL THICKNESS

A1 0.17 --- --- BALL HEIGHT

A2 0.62 --- 0.73 BODY THICKNESS

D 10.00 BSC. BODY SIZE

E 6.00 BSC. BODY SIZE

D1 5.60 BSC. BALL FOOTPRINT

E1 4.00 BSC. BALL FOOTPRINT

MD 8 ROW MATRIX SIZE D DIRECTION

ME 6 ROW MATRIX SIZE E DIRECTION

N 48 TOTAL BALL COUNT

φb 0.35 --- 0.45 BALL DIAMETER

e 0.80 BSC. BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

NONE DEPOPULATED SOLDER BALLS

Ø0.50

A1 ID.

SEATING PLANE

Øb

Ø0.08

Ø0.15

C0.10

C0.08

BCDEFG

A1 CORNER

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3425\ 16-038.25

June 13, 2005 S29AL032D_00_A3 S29AL032D 65

Page 68

Revision Summary

Revision A (January 31, 2005)

Initial Release.

Revision A1 (March 16, 2005)

Distinctive Characteristics

Revised Secured Silicon Sector with 12 8-word informati o n

Common Flash Memory Interface — (CFI)

Modified Primary Vendor-Specific Extended Query table information for 45h address

Revision A2 (April 19, 2005)

Valid Combinations Table

Clarified available packing types for TSOP and FBGA packages Modified note 1

Device Bus Operations

Added Secured Silicon Sector Addresses—Model 00 ta ble Modified Top Boot Secured Silicon Sector Addresses—Model 03 and Bottom Boot Secured Silicon

Sector Addresses—Model 04 tables

S29AL032D Command De fi nitions Mode l 00 — table

Added Secured Silicon Secto r Factory Protect information

Accelerated Program Operation

Advance Information

Added section

Write Protect (WP#) — Models 03, 04 Only

Added section

Secured Silicon Sector

Added section

AC Characteristics

Added ACC programm i ng timing d iagram

Revision A3 (June 13, 2005)

Autoselect Mode

Updated Ta ble 8 to include models 00, 03, and 04.

Common Flash Memory Interface

Updated table headings in table 12, 13, 14 , and 15.

Absolute Maximum Rating

Updated figure 8.

DC Characteristics

Updated CMOS Compatible table.

AC Characteristics

Updated Erase/Program Oper ations table. Added new figure: Back-to-Back Read/Write Cycle Timing. Updated Alternate CE# Controlled Erase/Program Operations table.

66 S29AL032D S29AL032D_00_A3 June 13, 2005

Page 69

Advance Information

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that

includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document.

Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies

June 13, 2005 S29AL032D_00_A3 S29AL032D 67

Datasheet S29AL032D Datasheet (SPANSION)

Specifications and Main Features

Frequently Asked Questions

User Manual