Datasheet S24163PA, S24163PAT, S24163PB, S24163PBT, S24163S2.7 Datasheet (SUMMIT)

SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com

1

Characteristics subject to change without notice

SUMMIT

MICROELECTRONICS, Inc.

S24163S24163

S24163

FEATURESFEATURES

FEATURES

••

•

Precision Supply Voltage MonitorPrecision Supply Voltage Monitor

Precision Supply Voltage Monitor — Active Low— Active Low

— Active Low— Active Low

— Active Low — Integrated memory write lockout— Integrated memory write lockout

— Integrated memory write lockout— Integrated memory write lockout

— Integrated memory write lockout

••

•

Guaranteed RESET (RESET#) assertionGuaranteed RESET (RESET#) assertion

Guaranteed RESET (RESET#) assertion to Vto V

to Vto V

to V

CC CC

CC

= 1V= 1V

= 1V

••

•

Power-Fail Accuracy GuaranteedPower-Fail Accuracy Guaranteed

Power-Fail Accuracy Guaranteed

••

•

No External ComponentsNo External Components

No External Components

••

•

3V and 5V system versions3V and 5V system versions

3V and 5V system versions

••

•

Low Power CMOSLow Power CMOS

Low Power CMOS ——

——

—

Active current less than 3mAActive current less than 3mA

Active current less than 3mA

——

—

Standby current less than 25µAStandby current less than 25µA

Standby current less than 25µA

••

•

Memory Internally Organized 2k X 8Memory Internally Organized 2k X 8

Memory Internally Organized 2k X 8 ——

——

—

Two Wire Serial Interface (ITwo Wire Serial Interface (I

Two Wire Serial Interface (I

22

2

C™)C™)

C™)

––

–

Bidirectional data transfer protocolBidirectional data transfer protocol

Bidirectional data transfer protocol

––

–

Standard 100KHz and Fast 400KHzStandard 100KHz and Fast 400KHz

Standard 100KHz and Fast 400KHz

PrPr

Pr

ecision RESET Contrecision RESET Contr

ecision RESET Contr

oller with 16K Ioller with 16K I

oller with 16K I

22

2

C MemorC Memor

C Memor

yy

y

••

•

High ReliabilityHigh Reliability

High Reliability ——

——

—

Endurance: 100,000 erase/write cyclesEndurance: 100,000 erase/write cycles

Endurance: 100,000 erase/write cycles

——

—

Data retention: 100 yearsData retention: 100 years

Data retention: 100 years

••

•

8-Pin PDIP or SOIC Packages8-Pin PDIP or SOIC Packages

8-Pin PDIP or SOIC Packages

OVERVIEWOVERVIEW

OVERVIEW The S24163 is a power supervisory device with 16,384-

bits of serial E2PROM. It is fabricated using SUMMIT's advanced CMOS E2PROM technology and is suitable for both 3 and 5 volt systems.

The S24163 is internally organized as 2048 x 8. It features the I2C serial interface and software protocol allowing operation on a simple two-wire bus.

BLOCK DIAGRAMBLOCK DIAGRAM

BLOCK DIAGRAM

3 and 5 Volt Systems

+ –

GND

V

CC

RESET#

V

TRIP

RESET PULSE

GENERATOR

5kHz

OSCILLATOR

RESET

CONTROL

MODE

DECODE

ADDRESS DECODER

WRITE

CONTROL

DATA I/O

E2PROM

MEMORY

ARRAY

1.26V

SCL

6

SDA

5

2

8

2014 T BD 2.0

4

2

S24163S24163

S24163

2014 2.0 3/21/00

ENDURANCE AND DATA RETENTIONENDURANCE AND DATA RETENTION

ENDURANCE AND DATA RETENTION The S24163 is designed for applications requiring up to

100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles.

APPLICATIONSAPPLICATIONS

APPLICATIONS

The S24163 is ideal for applications requiring low voltage and low power consumption. This device provides microcontroller RESET control and can be manually

resettable. This device also uses a cost effective, spacesaving, 8-pin SOIC or PDIP plastic package. Typical

applications include alarm devices, electronic locks, meters, keys, pagers and cellular phones.

RESET CONTROLLER DESCRIPTIONRESET CONTROLLER DESCRIPTION

RESET CONTROLLER DESCRIPTION

The device provides a precise reset output to a microcontroller and it’s associated circuitry ensuring correct system operation during power-up/down conditions and brownout situations. The output is open drain, allowing control of the reset function by multiple devices.

During power-up the reset output remains in a fixed active state until VCC passes through the reset threshold and remains above the threshold for 200ms. The reset output

is valid whenever VCC ≥ 1V. If VCC falls below the threshold for more than t

GLITCH

the device will immediately

generate a reset and drive the output. The reset pin is an I/O; therefore, forcing the pin to the

active state can also manually reset the device. Because the I/O needs to be an open drain, the internal timer can only be triggered by the leading edge of the input. The resulting reset output will either be t

PURST

, or the externally applied reset signal, whichever is longer. This can provide an affective debounce or reset signal extender solution.

CHARACTERISTICS OF THE ICHARACTERISTICS OF THE I

CHARACTERISTICS OF THE I

22

2

C BUSC BUS

C BUS

General DescriptionGeneral Description

General Description The I2C bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (See Figure 1). Data transfer between devices may be initiated with a START condition only when SCL and SDA are HIGH (bus is not busy).

PIN DESCRIPTIONSPIN DESCRIPTIONS

PIN DESCRIPTIONS SCL — Serial Clock: SCL — Serial Clock:

SCL — Serial Clock: SCL — Serial Clock:

SCL — Serial Clock: The SCL input is used to clock data into and out of the device. In the WRITE mode data must remain stable while SCL is HIGH. In the READ mode data is clocked out on the falling edge of SCL.

SDA — SDA —

SDA —

Serial Data: Serial Data:

Serial Data: The SDA pin is a bidirectional pin

used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP

conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector

outputs. RESET# — Reset: RESET# — Reset:

RESET# — Reset: RESET# — Reset:

RESET# — Reset: This is an active low open drain output. It is driven low whenever VCC is below V

TRIP

. It is also an input and can be used to debounce a switch input or perform signal conditioning. The pin has an internal pull-up and should be left unconnected if the signal is not used in the system. However, an external pull-up resistor must be connected when the pin is tied to a system RESET# line.

VV

V

CCCC

CC

— Power — Power

— Power: VCC is the voltage input, typically 2.7 to 5.5

volts. GND — GroundGND — Ground

GND — GroundGND — Ground

GND — Ground: Power return. NCNC

NCNC

NC —

No Connect: No Connect:

No Connect: The no connect inputs are not used. However, to ensure proper operation, they can be unconnected or tied to ground. They must not be tied to VCC.

PIN CONFIGURATIONPIN CONFIGURATION

PIN CONFIGURATION

NC

RESET#

NC

V

SS

V

CC

NC SCL SDA

1 2 3 4

8 7 6 5

SMS24163

8-Pin PDIP

or 8-Pin SOIC

2014 T PCon 2.0

S24163S24163

S24163

3

2014 2.0 3/21/00

FIGURE 1. TYPICAL SYSTEM CONFIGURATIONFIGURE 1. TYPICAL SYSTEM CONFIGURATION

FIGURE 1. TYPICAL SYSTEM CONFIGURATION

FIGURE 3. START AND STOP CONDITIONSFIGURE 3. START AND STOP CONDITIONS

FIGURE 3. START AND STOP CONDITIONS

FIGURE 2. INPUT DATA PROTOCOLFIGURE 2. INPUT DATA PROTOCOL

FIGURE 2. INPUT DATA PROTOCOL

Data must

remain stable

while clock

is HIGH.

Data must

remain stable

while clock

is HIGH.

Change

of data

allowed

SCL

SDA In

t

HD:DAT

t

SU:DAT

t

HD:DAT

2014 ILL4 1.0

SCL

SDA In

START

Condition

STOP

Condition

2014 ILL5 1.0

SDA

SCL

(µC/ µP)(24163)

2014 T fig01 2.0

RESET

V

CC

Master

Transmitter

Slave

Transmitter/

Receiver

Master

Transmitter/

Receiver

Slave

Receiver

Master

Transmitter/

Receiver

4

S24163S24163

S24163

2014 2.0 3/21/00

FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVERFIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER

FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER

Input Data ProtocolInput Data Protocol

Input Data Protocol One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock HIGH time, because changes on the data line while SCL is HIGH will be interpreted as start or stop condition (See Figure 2).

START and STOP ConditionsSTART and STOP Conditions

START and STOP Conditions When both the data and clock lines are HIGH, the bus is said to be not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is defined as the “START” condition. A LOW-to-HIGH transition on the data line, while the clock is HIGH, is defined as the “STOP” condition (See Figure 3).

DEVICE OPERATIONDEVICE OPERATION

DEVICE OPERATION

The S24163 is a 16,384-bit serial E2PROM. The device supports the I2C bidirectional data transmission protocol. The protocol defines any device that sends data onto the bus as a “transmitter” and any device which receives data as a “receiver.” The device controlling data transmission is called the “master” and the controlled device is called the “slave.” Since it never initiates any data transfers the S24163 is always a “slave” device.

Acknowledge (ACK)Acknowledge (ACK)

Acknowledge (ACK) Acknowledge is a software convention used to indicate

successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmit-

ting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKnowledge that it received the eight bits of data (See Figure 4).

The S24163 will respond with an ACKnowledge after recognition of a START condition and its slave address byte. If both the device and a write operation are selected, the S24163 will respond with an ACKnowledge after the receipt of each subsequent 8-bit word.

FIGURE 5. SLAVE ADDRESS BYTEFIGURE 5. SLAVE ADDRESS BYTE

FIGURE 5. SLAVE ADDRESS BYTE

In the READ mode the S24163 transmits eight bits of data, then releases the SDA line, and monitors the line for an ACKnowledge signal. If an ACKnowledge is detected, and no STOP condition is generated by the master, the S24163 will continue to transmit data. If an ACKnowledge is not detected the S24163 will terminate further data transmissions and await a STOP condition before returning to the standby power mode.

Device AddressingDevice Addressing

Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see figure 5). For the S24163 this is fixed as 1010[B

HEX

].

Word AddressWord Address

Word Address The next three bits of the slave address are an extension of the array’s address and are concatenated with the eight

bits of address in the word address field, providing direct access to the 2,048 X 8 array.

Read/Write BitRead/Write Bit

Read/Write Bit The last bit of the data stream defines the operation to be

performed. When set to “1” a read operation is selected; when set to “0” a write operation is selected.

SCL from

Master

Data Output

from

Transmitter

Data Output

from

Receiver

Start Condition

ACKnowledge

t

AA

t

AA

1

8

9

2014 ILL6 1.0

1 0 1 0

A10 A9 A8 R/W

DEVICE

IDENTIFIER

HIGH ORDER

WORD ADDRESS

2014 ILL7 1.0

S24163S24163

S24163

5

2014 2.0 3/21/00

FIGURE 6. PAGE/BYTE WRITE MODEFIGURE 6. PAGE/BYTE WRITE MODE

FIGURE 6. PAGE/BYTE WRITE MODE

WRITE OPERATIONSWRITE OPERATIONS

WRITE OPERATIONS

The S24163 allows two types of write operations: byte write and page write. The byte write operation writes a single byte during the nonvolatile write period (t

WR

). The

page write operation allows up to 16 bytes in the same page to be written during t

WR

.

Byte Byte

Byte

WRITEWRITE

WRITE After the slave address is sent (to identify the slave device, specify high order word address and a read or write operation), a second byte is transmitted which contains the low 8 bit addresses of any one of the 2,048 words in the array.

Upon receipt of the word address, the S24163 responds with an ACKnowledge. After receiving the next byte of data, it again responds with an ACKnowledge. The master then terminates the transfer by generating a STOP condition, at which time the S24163 begins the internal write cycle.

While the internal write cycle is in progress, the S24163 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 6 for the

address, ACKnowledge and data transfer sequence. Page Page

Page Page

Page

WRITEWRITE

WRITE The S24163 is capable of a 16-byte page write operation. It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more words of data. After the receipt of each word, the S24163 will respond with an ACKnowledge.

The S24163 automatically increments the address for subsequent data words. After the receipt of each word, the four low order address bits are internally incremented by one. The high order five bits of the address byte remain

constant. Should the master transmit more than sixteen words, prior to generating the STOP condition, the address counter will “roll over,” and the previously written data will be overwritten. As with the byte-write operation, all inputs are disabled during the internal write cycle. Refer to Figure 6 for the address, ACKnowledge and data transfer sequence.

D7D6D5D4D3D2D1D

0

D7D6D5D4D3D2D1D

0

A7A6A5A4A3A2A1A0D7D5D6D

4

D 0

D3D2D

1

S T A R T

Word Address Data Byte n Data Byte n+15

S T O P

A C K

Acknowledges Transmitted from

24163 to Master Receiver

Slave Address

Device

Type

Address

Read/Write

0= Write

A10,A9,A8

SDA Bus Activity

A C K

Master Sends Read Request to Slave

Master Writes Word Address to Slave

1 0 1 0

0

Data Byte n+1

A C K

Master Writes Data to Slave

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Shading Denotes

24163

SDA Output Active

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

Master Writes Data to Slave

Acknowledges Transmitted from

24163 to Master Receiver

If single byte-write only,

Stop bit issued here.

A10A9R

W

A C K

A 8

2014 T fig06 2.0

6

S24163S24163

S24163

2014 2.0 3/21/00

FIGURE 8. CURRENT ADDRESS BYTE READ MODEFIGURE 8. CURRENT ADDRESS BYTE READ MODE

FIGURE 8. CURRENT ADDRESS BYTE READ MODE

FIGURE 7. ACKNOWLEDGE POLLINGFIGURE 7. ACKNOWLEDGE POLLING

FIGURE 7. ACKNOWLEDGE POLLING

Acknowledge PollingAcknowledge Polling

Acknowledge Polling When the S24163 is performing an internal WRITE operation, it will ignore any new START conditions. Since the device will only return an acknowledge after it accepts the START, the part can be continuously queried until an

acknowledge is issued, indicating that the internal WRITE cycle is complete.

To poll the device, give it a START condition, followed by a slave address for a WRITE operation (See Figure 7).

READ OPERATIONSREAD OPERATIONS

READ OPERATIONS

Read operations are initiated with the R/W bit of the identification field set to “1.” There are four different read

options:

1. Current Address Byte Read

2. Random Address Byte Read

3. Current Address Sequential Read

4. Random Address Sequential Read

Current Address Byte ReadCurrent Address Byte Read

Current Address Byte Read The S24163 contains an internal address counter which

maintains the address of the last word accessed, incremented by one. If the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. When the S24163 receives the slave address field with the R/W bit set to “1,” it issues an acknowledge and transmits the 8-bit word stored at address location n+1.

The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point, the S24163 discontinues data transmission. See Figure 8 for the address acknowledge and data transfer sequence.

Issue Start

Internal WRITE Cycle

In Progress;

Begin ACK Polling

Issue Slave

Address and

R/W = 0

ACK

Returned?

WRITE?

Issue Byte

Address

Proceed with

WRITE

Issue Stop

Await Next Command

Issue Stop

No

Yes (Internal WRITE Cycle is completed)

Yes

2014 ILL 9 1.0

S T A R T

S

T O P

Slave Address

Device

Type

Address

Read/Write

1= Read

A10,A9,A8

SDA Bus Activity

D7D6D5D4D3D2D1D

0

Master sends Read request to Slave

Slave sends Data to Master

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

11100 1

Lack of ACK (low) from Master determines last data byte to be read

1

Shading Denotes

24163

SDA Output Active

A9A

10

R W

A C K

A 8

Data Byte

2014 T fig08 2.0

S24163S24163

S24163

7

2014 2.0 3/21/00

FIGURE 9. RANDOM ADDRESS BYTE READ MODEFIGURE 9. RANDOM ADDRESS BYTE READ MODE

FIGURE 9. RANDOM ADDRESS BYTE READ MODE

Random Address Byte ReadRandom Address Byte Read

Random Address Byte Read Random address read operations allow the master to

access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with the R/W bit set to WRITE) followed by the address of the word it is to read.

This procedure sets the internal address counter of the S24163 to the desired address.

After the word address acknowledge is received by the master, the master immediately reissues a start condition

followed by another slave address field with the R/W bit set to READ. The S24163 will respond with an acknowl-

edge and then transmit the 8-data bits stored at the addressed location. At this point, the master does not

acknowledge the transmission but does generate the stop condition. The S24163 discontinues data transmission

and reverts to its standby power mode. See Figure 9 for the address, acknowledge and data transfer sequence.

D7D6D5D4D3D2D1D

0

A7A6A5A4A3A2A1A

0

S T A R T

Word Address

S T

O

P

A C K

Slave Address

Device

Type

Address

Read/Write

0= Write

Device

Type

Address

A10,A9,A8

SDA Bus Activity

S T A R T

Read/Write

1= Read

A C K

A

C

K

Master sends Read request to Slave

Master Writes Word Address to Slave

Master Requests Data from Slave

Slave sends Data to Master

1010 1010 10

A10A9RWA

8

A9R

W

A10A

8

Lack of ACK (low) from Master determines last data byte to be read

1

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Shading Denotes

24163

SDA Output Active

Slave Transmitter

to

Master Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

Data Byte

2014 T fig09 2.0

8

S24163S24163

S24163

2014 2.0 3/21/00

Sequential READSequential READ

Sequential READ Sequential READs can be initiated as either a current

address READ or random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ); however, the master now responds with an ACKnowledge,

indicating that it requires additional data from the S24163. The S24163 continues to output data for each ACKnowledge received. The master terminates the sequential READ operation by not responding with an

ACKnowledge, and issues a STOP conditions.

During a sequential read operation, the internal address counter is automatically incremented with each acknowledge signal. For read operations, all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address, the address counter will ‘roll-over’ and the memory will continue to output data. See Figure 10 for the address, acknowledge and data transfer sequence.

FIGURE 10. SEQUENTIAL READ OPERATION (starting with a Random Address READ)FIGURE 10. SEQUENTIAL READ OPERATION (starting with a Random Address READ)

FIGURE 10. SEQUENTIAL READ OPERATION (starting with a Random Address READ)

D7D6D5D4D3D2D1D

0

D7D6D5D4D3D2D1D

0

A7A6A5A4A3A2A1A

0

Shading Denotes

24163

SDA Output Active

S

T A R T

Word Address

S T O P

A C K

Acknowledges from 24163

Slave AddressSlave Address

Device

Type

Address

Read/Write

0= Write

Device

Type

Address

A10,A9,A8

A10,A9,A80

SDA Bus Activity

S T A R T

Read/Write

1= Read

A9R

W

A

10

Acknowledge from

Master Receiver

A C K

Master sends Read request to Slave

Master Writes Word Address to Slave

Master Requests Data from Slave

Slave sends Data to Master

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Master Transmitter

to

Slave Receiver

1010 1010 10

Slave sends Data to Master

A10A9RWA

8

A 8

Lack of ACK (low) determines last data byte to be read

1

Lack of

Acknowledge from

Master Receiver

Slave Transmitter

to

Master Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

Slave Transmitter

to

Master Receiver

Last Data Byte

First Data Byte

2014 T fig10 2.0

S24163S24163

S24163

9

2014 2.0 3/21/00

ABSOLUTE MAXIMUM RATINGSABSOLUTE MAXIMUM RATINGS

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias ............................................................................................................... -40°C to +85°C

Storage Temperature ..................................................................................................................... -65°C to +125°C

Soldering Temperature (less than 10 seconds) .............................................................................................. 300°C

Supply Voltage ........................................................................................................................................... 0 to 6.5V

Voltage on Any Pin ...................................................................................................................... -0.3V to V

CC

+0.3V

ESD Voltage (JEDEC method) ...................................................................................................................... 2,000V

NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.

DC ELECTRICAL CHARACTERISTICSDC ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS S24163, TA = -40°C to +85°C, VCC = 5V + 10% S24163-3, TA = -40°C to +85°C, VCC = 2.7V to 5.5V

SymbolSymbol

Symbol

ParameterParameter

Parameter

ConditionsConditions

Conditions

MinMin

Min

MaxMax

Max

UnitsUnits

Units

SCL = CMOS Levels @ 100KHz V

CC

=5.5V 3 mA

I

CC

Supply Current (CMOS) SDA = Open

All other inputs = GND or V

CC

V

CC

=3.3V 2 mA

I

SB

Standby Current (CMOS) SCL = SDA = V

CC

V

CC

=5.5V 50

µA

All other inputs = GND

I

LI

Input Leakage VIN = 0 To V

CC

10 µA

I

LO

Output Leakage V

OUT

= 0 To V

CC

10 µA

V

IL

Input Low Voltage S0, S1, S2, SCL, SDA, RESET 0.3xV

CC

V

IH

Input High Voltage S0, S1, S2, SCL, SDA 0.7xV

CC

V

OL

Output Low Voltage IOL = 3mA 0.4 V

V

CC

=3.3V 25 µA

2014 PGM T1 1.0

2.7V to 4.5V2.7V to 4.5V

2.7V to 4.5V

4.5V to 5.5V4.5V to 5.5V

4.5V to 5.5V

SymbolSymbol

Symbol

ParameterParameter

Parameter

ConditionsConditions

Conditions

MinMin

Min

MaxMax

Max

MinMin

Min

MaxMax

Max

UnitsUnits

Units

fSCL SCL Clock Frequency 0 100 400 KHz tLOW Clock Low Period 4.7 1.3 µs tHIGH Clock High Period 4.0 0.6 µs tBUF Bus Free Time Before New Transmission 4.7 1.3 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs tHD:STA Start Condition Hold Time 4.0 0.6 µs tSU:STO Stop Condition Setup Time 4.7 0.6 µs tAA Clock to Output SCL Low to SDA Data Out Valid 0.3 3.5 0.2 0.9 µs tDH Data Out Hold Time SCL Low to SDA Data Out Change 0.3 0.2 µs tR SCL and SDA Rise Time 1000 300 ns tF SCL and SDA Fall Time 300 300 ns tSU:DAT Data In Setup Time 250 100 ns tHD:DAT Data In Hold Time 0 0 ns

TI Noise Spike Width Noise Suppression Time Constant 100 100 ns

@ SCL, SDA Inputs

tWR Write Cycle Time 10 10 ms

AC ELECTRICAL CHARACTERISTICSAC ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS S24163, TA = -40°C to +85°C, VCC = 5V + 10% S24163-3, TA = -40°C to +85°C, VCC = 2.7V to 5.5V

2014 PGM T2 1.0

10

S24163S24163

S24163

2014 2.0 3/21/00

FIGURE 11. BUS TIMINGFIGURE 11. BUS TIMING

FIGURE 11. BUS TIMING

CAPACITANCECAPACITANCE

CAPACITANCE TA = 25°C, f = 100KHz

SymbolSymbol

Symbol

ParameterParameter

Parameter

MaxMax

Max

UnitsUnits

Units

C

IN

Input Capacitance 5 pF

C

OUT

Output Capacitance 8 pF

2014 PGM T3 1.0

S24163-2.7S24163-2.7

S24163-2.7

S24163–AS24163–A

S24163–A

S24163–B S24163–B

S24163–B

SymbolSymbol

Symbol

ParameterParameter

Parameter

MM

M

inin

in

MaxMax

Max

MinMin

Min

MaxMax

Max

MinMin

Min

Max Max

Max

Unit Unit

Unit

V

TRIP

Reset Trip Point 2.55 2.7 4.25 4.5 4.5 4.75 V

t

PURST

Power-Up Reset Timeout 130 270 130 270 130 270 ms

t

RPD

V

TRIP

to RESET Output Delay 5 5 5 µs

V

RVALID

RESET Output Valid 1 1 1 V

t

GLITCH

Glitch Reject Pulse Width 30 30 30 ns

V

OLRS

RESET Output Low Voltage IOL – 1mA 0.4 0.4 0.4 V

RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICSRESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS

RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS TA = -40°C to +85°C

2014 PGM T4 1.1

SCL

SDA In

SDA Out

t

AA

t

R

t

H IGHtLOW

t

SU:STO

t

BUF

t

SU:DAT

t

HD:DAT

t

HD:SDA

t

SU:SDA

t

DH

2014 ILL 13 1.0

t

F

S24163S24163

S24163

11

2014 2.0 3/21/00

.228 (5.80)

.244 (6.20)

.016 (.40)

.035 (.90)

.020 (.50) .010 (.25)

x45°

.0192 (.49) .0138 (.35)

.061 (1.75) .053 (1.35)

.0098 (.25) .004 (.127)

.05 (1.27) TYP.

.275 (6.99) TYP.

.030 (.762) TYP. 8 Places

.050 (1.27) TYP.

.050 (1.270) TYP. 8 Places

.157 (4.00) .150 (3.80)

.196 (5.00)

1

.189 (4.80)

FOOTPRINT

8pn JEDEC SOIC ILL.2

FIGURE 12. RESET OUTPUT TIMINGFIGURE 12. RESET OUTPUT TIMING

FIGURE 12. RESET OUTPUT TIMING

8 Pin SOIC (Type S) Package JEDEC (150 mil body width) 8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

V

CC

V

RVALID

V

TRIP

t

PURST

RESET

2014 ILL 14 1.0

t

GLITCH

t

RPD

t

PURST

t

RPD

(S24162)

12

S24163S24163

S24163

2014 2.0 3/21/00

NOTICE

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.

I2C is a trademark of Philips Corporation.

ORDERING INFORMATION ORDERING INFORMATION

ORDERING INFORMATION

.375

(9.525)

PIN 1 INDICATOR

.015 (.381) Min.

.130 (3.302)

.100 (2.54)

TYP.

.018 (.457)

TYP.

.060 ± .005

(1.524) ± .127

TYP.

.130 (3.302)

SEATING PLANE

.070 (1.778)

.0375 (0.952)

.300 (7.620)

5°-7°TYP.

(4 PLCS)

.350 (8.89)

.009 ± .002

(.229 ± .051)

0°-15°

.250

(6.350)

8pn PDIP/P ILL.3

8 Pin PDIP (Type P) Package 8 Pin PDIP (Type P) Package

8 Pin PDIP (Type P) Package

Operating V oltage Range

A = 4.5V to 5.5V V

TRIP

min. @ 4.25V

B = 4.5V to 5.5V V

TRIP

min. @ 4.50V

2.7 = 2.7V to 5.5V V

TRIP

min. @ 2.55V

Tape & Reel Option

Blank = Tube T = Tape & Reel

S24163

P

A

T

Base Part Number

Package

P = 8 Lead PDIP S = 8 Lead 150mil SOIC

2014 T ree 2.0

Datasheet S24163PA, S24163PAT, S24163PB, S24163PBT, S24163S2.7 Datasheet (SUMMIT)

Specifications and Main Features

Frequently Asked Questions

User Manual