Page 1
RTL8103E-GR
RTL8103EL-GR
INTEGRATED FAST ETHERNET CONTROLLER
FOR PCI EXPRESS™ APPLICATIONS
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.3
08 August 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
Page 2
RTL8103E & RTL8103EL
Datasheet
COPYRIGHT
©2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
LICENSE
This product is covered by one or more of the following patents:US5,307,459, US5,434,872,
US5,732,094, US6,570,884, US6,115,776, and US6,327,625.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary
1.0 2008/05/28 First Release
1.1 2008/07/08 Corrected typing error
1.2 2008/07/29 Updated licensing information
1.3 2008/08/08 Added Deep Slumber Mode (DSM) power saving to features list on page 2.
Integrated Fast Ethernet Controller for PCI Express ii Track ID: JATR-1076-21 Rev. 1.3
Page 3
RTL8103E & RTL8103EL
Datasheet
Table of Contents
1. GENERAL DESCRIPTION..............................................................................................................................................1
2. FEATURES.........................................................................................................................................................................2
3. SYSTEM APPLICATIONS...............................................................................................................................................2
4. PIN ASSIGNMENTS .........................................................................................................................................................3
4.1. RTL8103E (64-PIN) ....................................................................................................................................................3
4.2. PACKAGE IDENTIFICATION...........................................................................................................................................3
4.3. RTL8103EL (48-PIN)..................................................................................................................................................4
4.4. PACKAGE IDENTIFICATION...........................................................................................................................................4
5. PIN DESCRIPTIONS.........................................................................................................................................................5
5.1. POWER MANAGEMENT/ISOLATION ..............................................................................................................................5
5.2. PCI EXPRESS INTERFACE .............................................................................................................................................5
5.3. EEPROM ....................................................................................................................................................................6
5.4. TRANSCEIVER INTERFACE............................................................................................................................................6
5.5. CLOCK .........................................................................................................................................................................6
5.6. REGULATOR AND REFERENCE......................................................................................................................................6
5.7. LEDS ...........................................................................................................................................................................7
5.8. POWER AND GROUND ..................................................................................................................................................7
5.9. GPIO ...........................................................................................................................................................................7
5.10. NC (NOT CONNECTED) PINS AND TEST PINS ...............................................................................................................8
6. FUNCTIONAL DESCRIPTION.......................................................................................................................................8
6.1. PCI EXPRESS BUS INTERFACE......................................................................................................................................8
6.1.1. PCI Express Transmitter ........................................................................................................................................8
6.1.2. PCI Express Receiver.............................................................................................................................................8
6.2. LED FUNCTIONS..........................................................................................................................................................9
6.2.1. Link Monitor...........................................................................................................................................................9
6.2.2. Rx LED ...................................................................................................................................................................9
6.2.3. Tx LED .................................................................................................................................................................10
6.2.4. Tx/Rx LED ............................................................................................................................................................10
6.2.5. Customizable LED Configuration ........................................................................................................................11
6.3. PHY TRANSCEIVER ...................................................................................................................................................12
6.3.1. PHY Transmitter...................................................................................................................................................12
6.3.2. PHY Receiver .......................................................................................................................................................12
6.4. EEPROM INTERFACE................................................................................................................................................13
6.5. POWER MANAGEMENT...............................................................................................................................................14
6.6. VITAL PRODUCT DATA (VPD)...................................................................................................................................16
6.7. RECEIVE-SIDE SCALING (RSS) ..................................................................................................................................16
6.7.1. Receive-Side Scaling (RSS) Initialization.............................................................................................................16
6.7.2. RSS Operation ......................................................................................................................................................17
7. CHARACTERISTICS......................................................................................................................................................18
7.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................18
7.2. RECOMMENDED OPERATING CONDITIONS .................................................................................................................18
7.3. CRYSTAL REQUIREMENTS..........................................................................................................................................18
7.4. TRANSFORMER CHARACTERISTICS ............................................................................................................................19
7.5. OSCILLATOR REQUIREMENTS ....................................................................................................................................19
7.6. THERMAL CHARACTERISTICS.....................................................................................................................................19
7.7. DC CHARACTERISTICS...............................................................................................................................................20
7.8. AC CHARACTERISTICS...............................................................................................................................................21
Integrated Fast Ethernet Controller for PCI Express iii Track ID: JATR-1076-21 Rev. 1.3
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RTL8103E & RTL8103EL
Datasheet
7.8.1. Serial EEPROM Interface Timing........................................................................................................................21
7.9. PCI EXPRESS BUS PARAMETERS................................................................................................................................22
7.9.1. Differential Transmitter Parameters....................................................................................................................22
7.9.2. Differential Receiver Parameters.........................................................................................................................23
7.9.3. REFCLK Parameters............................................................................................................................................23
7.9.4. Auxiliary Signal Timing Parameters ....................................................................................................................27
8. MECHANICAL DIMENSIONS......................................................................................................................................28
8.1. RTL8103E (64-PIN QFN)..........................................................................................................................................28
8.2. RTL8103EL (48-PIN LQFP)......................................................................................................................................29
8.3. MECHANICAL DIMENSIONS NOTES (RTL8103EL 48-PIN).........................................................................................30
9. ORDERING INFORMATION........................................................................................................................................31
Integrated Fast Ethernet Controller for PCI Express iv Track ID: JATR-1076-21 Rev. 1.3
Page 5
RTL8103E & RTL8103EL
Datasheet
List of Tables
TABLE 1. POWER MANAGEMENT/ISOLATION ...............................................................................................................................5
TABLE 2. PCI EXPRESS INTERFACE..............................................................................................................................................5
TABLE 3. EEPROM .....................................................................................................................................................................6
TABLE 4. TRANSCEIVER INTERFACE ............................................................................................................................................6
TABLE 5. CLOCK ..........................................................................................................................................................................6
TABLE 6. REGULATOR AND REFERENCE ......................................................................................................................................6
TABLE 7. LEDS............................................................................................................................................................................7
TABLE 8. POWER AND GROUND ...................................................................................................................................................7
TABLE 9. GPIO PINS ....................................................................................................................................................................7
TABLE 10. NC (NOT CONNECTED) PINS ........................................................................................................................................8
TABLE 11. LED SELECT (IO REGISTER OFFSET 17H~18H)..........................................................................................................11
TABLE 12. CUSTOMIZED LEDS ...................................................................................................................................................11
TABLE 13. EEPROM INTERFACE ................................................................................................................................................13
TABLE 14. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................18
TABLE 15. RECOMMENDED OPERATING CONDITIONS .................................................................................................................18
TABLE 16. CRYSTAL REQUIREMENTS..........................................................................................................................................18
TABLE 17. TRANSFORMER CHARACTERISTICS ............................................................................................................................19
TABLE 18. OSCILLATOR REQUIREMENTS ....................................................................................................................................19
TABLE 19. THERMAL CHARACTERISTICS.....................................................................................................................................19
TABLE 20. DC CHARACTERISTICS ...............................................................................................................................................20
TABLE 21. EEPROM ACCESS TIMING PARAMETERS ..................................................................................................................21
TABLE 22. DIFFERENTIAL TRANSMITTER PARAMETERS ..............................................................................................................22
TABLE 23. DIFFERENTIAL RECEIVER PARAMETERS.....................................................................................................................23
TABLE 24. REFCLK PARAMETERS .............................................................................................................................................23
TABLE 25. AUXILIARY SIGNAL TIMING PARAMETERS.................................................................................................................27
TABLE 26. ORDERING INFORMATION ..........................................................................................................................................31
List of Figures
FIGURE 1. PIN ASSIGNMENTS (RTL8103E 64-PIN) ......................................................................................................................3
FIGURE 2. PIN ASSIGNMENTS (RTL8103EL 48-PIN)....................................................................................................................4
FIGURE 3. RX LED.......................................................................................................................................................................9
FIGURE 4. TX LED.....................................................................................................................................................................10
FIGURE 5. TX/RX LED...............................................................................................................................................................10
FIGURE 6. SERIAL EEPROM INTERFACE TIMING ......................................................................................................................21
FIGURE 7. SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING ..................................................25
FIGURE 8. SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT ...........................................................................25
FIGURE 9. SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING ........................................................25
FIGURE 10. DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD ...................................................................26
FIGURE 11. DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME ...........................................................................26
FIGURE 12. DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK............................................................................................26
FIGURE 13. REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING .........................................................................27
FIGURE 14. AUXILIARY SIGNAL TIMING......................................................................................................................................27
Integrated Fast Ethernet Controller for PCI Express v Track ID: JATR-1076-21 Rev. 1.3
Page 6
RTL8103E & RTL8103EL
Datasheet
1. General Description
The Realtek RTL8103E(L)-GR Fast Ethernet controller combines an IEEE 802.3 10/100Base-T
compliant Media Access Controller (MAC), PCI Express bus controller, and embedded
One-Time-Programmable (OTP) memory. With state-of-the-art DSP technology and mixed-mode signal
technology, the RTL8103E(L) offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP
(10Mbps only) cable. Functions such as Crossover Detection & Auto-Correction, polarity correction,
adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are
implemented to provide robust transmission and reception capability at high speeds.
The device supports the PCI Express 1.1 bus interface for host communications with power management,
and is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet. It also supports an
auxiliary power auto-detect function, and will auto-configure related bits of the PCI power management
registers in PCI configuration space. The RTL8103E(L) features embedded One-Time-Programmable
(OTP) memory to replace the external EEPROM (93C46/93C56).
Advanced Configuration Power management Interface (ACPI)—power management for modern
operating systems that are capable of Operating System-directed Power Management (OSPM)—is
supported to achieve the most efficient power management possible. PCI MSI (Message Signaled
Interrupt) and MSI-X are also supported.
In addition to the ACPI feature, remote wake-up (including AMD Magic Packet™ and Microsoft
Wake-up frame) is supported in both ACPI and APM (Advanced Power Management) environments. To
support WOL from a deep power down state (e.g., D3cold, i.e., main power is off and only auxiliary
exists), the auxiliary power source must be able to provide the needed power for the RTL8103E(L).
The RTL8103E(L) is fully compliant with Microsoft
Checksum and Segmentation Task-offload (Large send and Giant send) features, and supports IEEE 802
IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above
features contribute to lowering CPU utilization, especially benefiting performance when in operation on a
network server.
®
NDIS5, NDIS6 (IPv4, IPv6, TCP, UDP)
®
The RTL8103E(L) supports Receive Side Scaling (RSS) to hash incoming TCP connections and
load-balance received data processing across multiple CPUs. RSS improves the number of transactions
per second and number of connections per second, for increased network throughput.
The device also features inter-connect PCI Express technology. PCI Express is a high-bandwidth, low pin
count, serial, interconnect technology that offers significant improvements in performance over
conventional PCI and also maintains software compatibility with existing PCI infrastructure. The device
embeds an adaptive equalizer in the PCIE PHY for ease of system integration and excellent link quality.
The equalizer enables the length of the PCB traces to reach 20 inches.
The RTL8103E(L) is suitable for multiple market segments and emerging applications, such as desktop,
mobile, workstation, server, communications platforms, and embedded applications.
Built-in linear regulators provide the RTL8103E(L)’s core power, as well as reducing layout area and
external BOM costs. The RTL8103E supports the Deep Slumber Mode (DSM) power saving feature. See
the separate DSM application notes for details (the RTL8103EL does not support the DSM feature).
Note: RTL8103 model differences are listed in section 9 Ordering Information, page 31.
Integrated Fast Ethernet Controller for PCI Express 1 Track ID: JATR-1076-21 Rev. 1.3
Page 7
2. Features
RTL8103E & RTL8103EL
Datasheet
Integrated 10/100 transceiver
Auto-Negotiation with Next Page
capability
Supports PCI Express™ 1.1
Supports pair swap/polarity/skew
correction
Crossover Detection & Auto-Correction
Wake-on-LAN and remote wake-up
support
Customizable LEDs
®
Microsoft
NDIS5, NDIS6 Checksum
Offload (IPv4, IPv6, TCP, UDP) and
Segmentation Task-offload (Large send
and Giant send) support
Supports Full Duplex flow control
(IEEE 802.3x)
Fully complies with IEEE 802.3,
IEEE 802.3u
Supports IEEE 802.1Q VLAN tagging
Serial EEPROM
Embedded OTP memory can replace
the external EEPROM
Transmit/Receive on-chip buffer
support
Supports power down/link down power
saving
Built-in Regulator
Supports PCI MSI (Message Signaled
Interrupt) and MSI-X
Supports Receive-Side Scaling (RSS)
Embeds an adaptive equalizer in PCI
express PHY (PCB traces can reach up
to 20 inches)
Supports Deep Slumber Mode (DSM)
power saving feature (RTL8103E
64-pin QFN only)
Supports IEEE 802.1P Layer 2 Priority
Encoding
64-pin QFN (RTL8103E) & 48-pin
LQFP (RTL8103EL) Green package
3. System Applications
PCI Express™ Fast Ethernet on Motherboard, Notebook, or Embedded system
Integrated Fast Ethernet Controller for PCI Express 2 Track ID: JATR-1076-21 Rev. 1.3
Page 8
4. Pin Assignments
4.1. RTL8103E (64-Pin)
K
S
EEDI/AUX
VDD33
EEDO
EE
RTL8103E & RTL8103EL
Datasheet
DVDD12
EECS
TEST3
TEST4
TEST5
NC
TEST2
VDD33
ISOLATEB
TEST0
TEST1
CLKREQB
DVDD 12
GPI
GPO
NC
VDD 33
LED3
LED 2
LED 1
LED 0
DVDD 12
NC
CKXTAL 1
CKXTAL 2
NC
VCTRL12 D
RSET
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
123456789
65 GND (Exposed Pad)
RTL8103 E
10 11 12 13 14 15 16
3
31
30
29
28
27
26
25
24
23
22
21
20
19
18
1
2
7
NC
EGND
HSON
HSOP
EVDD12
REFCLK_M
REFCLK_P
EGND
HSIN
HSIP
NC
DVDD12
PERSTB
LANWAKEB
MAPIN 1
MAPIN 0
VCTRL12A
NC
MDIP0
MDIN0
AVDD33
MDIP1
MDIN1
NC
NC
NC
NC
NC
NC
NC
VDD33
DVDD12
Figure 1. Pin Assignments (RTL8103E 64-Pin)
4.2. Package Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 1.
The version is shown in the location marked ‘V’.
Integrated Fast Ethernet Controller for PCI Express 3 Track ID: JATR-1076-21 Rev. 1.3
Page 9
4.3. RTL8103EL (48-Pin)
RTL8103E & RTL8103EL
Datasheet
VDD33
LED0
NC
NC
CKXTAL1
CKXTAL2
NC
NC
37
38
39
40
41
42
43
44
/AUX
LED1/EESK
DVDD12
36 35 34 33 32 31 30 29 28 27 26
LED3/EEDO
LED2/EEDI
GND
EECS
VDD33
DVDD12
ISOLATEB
PERSTB
B
E
K
LANWA
25
B
Q
E
CLKR
24
23
22
21
20
19
18
17
NC
NC
GNDTX
HSON
HSOP
VDDTX
REFCLK_M
REFCLK _ P
VCTRL12D
RSET
GND
VCTRL12A
45
46
47
48
1 2 3 4 5 6 7 8 9 101112
NC
MDIN0
MDIP0
AVDD33
Figure 2. Pin Assignments (RTL8103EL 48-Pin)
MDI P1
ND
NC
G
MDIN1
NC
12
DDVD
NC
4.4. Package Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.
The version is shown in the location marked ‘V’.
NC
16
15
14
13
HSIN
HSIP
GND
DVDD 12
Integrated Fast Ethernet Controller for PCI Express 4 Track ID: JATR-1076-21 Rev. 1.3
Page 10
5. Pin Descriptions
The signal type codes below are used in the following tables:
I: Input S/T/S: Sustained Tri-State
O: Output O/D: Open Drain
T/S: Tri-State bi-directional input/output pin
5.1. Power Management/Isolation
Table 1. Power Management/Isolation
Symbol Type Pin No
(64-Pin)
LANWAKEB O/D 19 26
ISOLATEB I 36 28
Pin No
(48-Pin)
Description
Power Management Event: Open drain, active low.
Used to reactivate the PCI Express slot’s main power rails and
reference clocks.
Isolate Pin: Active low.
Used to isolate the RTL8103E(L) from the PCI Express bus. The
RTL8103E(L) will not drive its PCI Express outputs (excluding
LANWAKEB) and will not sample its PCI Express input as long as the
Isolate pin is asserted.
RTL8103E & RTL8103EL
Datasheet
5.2. PCI Express Interface
Table 2. PCI Express Interface
Symbol Type Pin No
(64-Pin)
REFCLK_P I 26 17
REFCLK_M I 27 18
HSOP O 29 20
HSON O 30 21
HSIP I 23 15
HSIN I 24 16
PERSTB I 20 27
CLKREQB O/D 33 25
Pin No
(48-Pin)
Description
PCI Express Differential Reference Clock Source: 100MHz ± 300ppm.
PCI Express Transmit Differential Pair.
PCI Express Receive Differential Pair.
PCI Express Reset Signal: Active low.
When the PERSTB is asserted at power-on state, the RTL8103E(L)
returns to a pre-defined reset state and is ready for initialization and
configuration after the de-assertion of the PERSTB.
Reference Clock Request Signal.
This signal is used by the RTL8103E(L) to request starting of the PCI
Express reference clock.
Integrated Fast Ethernet Controller for PCI Express 5 Track ID: JATR-1076-21 Rev. 1.3
Page 11
RTL8103E & RTL8103EL
5.3. EEPROM
Table 3. EEPROM
Symbol Type Pin No
(64-Pin)
EESK O 48 35 Serial Data Clock.
EEDI/AUX OI 47 34
EEDO I 45 33 Input from Serial Data Output Pin of EEPROM.
EECS O 44 32 EECS: EEPROM chip select.
Pin No
(48-Pin)
Description
EEDI: Output to serial data input pin of EEPROM.
AUX: Input pin to detect if Aux. Power exists or not on initial power-on.
This pin should be connected to EEPROM. To support wakeup from
ACPI D3cold or APM power-down, this pin must be pulled high to Aux.
Power via a resistor. If this pin is not pulled high to Aux. Power, the
RTL8103E(L) assumes that no Aux. Power exists.
5.4. Transceiver Interface
Table 4. Transceiver Interface
Symbol Ty pe Pin No
(64-Pin)
MDIP0 IO 3 2
MDIN0 IO 4 3
MDIP1 IO 6 5
MDIN1 IO 7 6
Pin No
(48-Pin)
Description
In MDI mode, this pair acts as the BI_DA+/- pair, and is the transmit pair
in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the
receive pair in 10Base-T and 100Base-TX.
In MDI mode, this pair acts as the BI_DB+/- pair, and is the receive pair
in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the
transmit pair in 10Base-T and 100Base-TX.
Datasheet
5.5. Clock
Table 5. Clock
Symbol Ty pe Pin No (64-Pin) Pin No (48-Pin) Description
CKXTAL1 I 60 41 Input of 25MHz Clock Reference.
CKXTAL2 O 61 42 Output of 25MHz Clock Reference.
5.6. Regulator and Reference
Table 6. Regulator and Reference
Symbol Ty pe Pin No (64-Pin) Pin No (48-Pin) Description
RSET I 64 46 Reference. External resistor reference.
Integrated Fast Ethernet Controller for PCI Express 6 Track ID: JATR-1076-21 Rev. 1.3
Page 12
5.7. LEDs
Symbol Type Pin No
(64-Pin)
Pin No
(48-Pin)
RTL8103E & RTL8103EL
Datasheet
Table 7. LEDs
Description
LED0 O 57 38
LED1 O 56 35
LED2 O 55 34
LED3 O 54 33
Note 1: During power down mode, the LED signals are logic high.
Note 2: LEDS1-0’s initial value comes from the 93C46.
If there is no 93C46, the default value of the (LEDS1, LEDS0)=(0, 0).
LEDS1-0 00 01 10 11
LED0 Tx/Rx Tx/Rx Tx Tx
LED1 LINK100 LINK LINK LINK100
LED2 LINK10 FULL Rx LINK10
LED3 NA NA NA NA
5.8. Power and Ground
Table 8. Power and Ground
Symbol Ty pe Pin No
(64-Pin)
VDD33 Power 16, 37, 46, 53 29, 37 Digital 3.3V Power Supply.
DVDD12 Power 15, 21, 43, 49, 58 10, 13, 30, 36 Digital 1.2V Power Supply.
EVDD12 Power 28 - Analog 1.2V power supply.
AVDD33 Power 2 1 Analog 3.3V Power Supply.
GNDTX Power - 22 Analog Ground.
EGND Power 25, 31 - Analog Ground.
GND Power - 7, 14, 31, 47 Ground.
GND Power 65 - Ground (Exposed Pad).
VDDTX O - 19 1.2V Output.
VCTRL12D O 63 45 1.2V Output Supplies Power to DVDD12 Power Pin.
VCTRL12A O 1 48 1.2V Output.
Note: Refer to the most updated schematic circuit for correct configuration.
Pin No
(48-Pin)
Description
5.9. GPIO
Table 9. GPIO Pins
Symbol Type Pin No
(64-Pin)
GPI I 50 - Input GPIO Pin.
GPO O 51 -
Integrated Fast Ethernet Controller for PCI Express 7 Track ID: JATR-1076-21 Rev. 1.3
Pin No
(48-Pin)
Description
Output GPIO Pin. This pin reflects the link up or link
down state.
High: Link up.
Low: Link down.
Page 13
RTL8103E & RTL8103EL
5.10. NC (Not Connected) Pins and Test Pins
Table 10. NC (Not Connected) Pins
Symbol Type Pin No (64-Pin) Pin No (48-Pin) Description
NC -
MAPIN0 IO 17 - Realtek Internal Use Only
MAPIN1 IO 18 - Realtek Internal Use Only
TEST0 - 34 - Realtek Internal Use Only
TEST1 - 35 - Realtek Internal Use Only
TEST2 - 39 - Realtek Internal Use Only
TEST3 - 40 - Realtek Internal Use Only
TEST4 - 41 - Realtek Internal Use Only
TEST5 - 42 - Realtek Internal Use Only
5, 8, 9, 10, 11, 12, 13, 14,
22, 32, 38, 52, 59, 62
4, 8, 9, 11, 12, 23, 24,
39, 40, 43, 44
Not Connected.
6. Functional Description
Datasheet
6.1. PCI Express Bus Interface
The RTL8103E(L) complies with PCI Express Base Specification Revision 1.1, and runs at a 2.5GHz
signaling rate with X1 link width, i.e., one transmit and one receive differential pair. The RTL8103E(L)
supports four types of PCI Express messages: interrupt messages, error messages, power management
messages, and hot-plug messages. To ease PCB layout constraints, PCI Express lane polarity reversal and
link reversal are also supported.
6.1.1. PCI Express Transmitter
The RTL8103E(L)’s PCI Express block receives digital data from the Ethernet interface and performs
data scrambling with Linear Feedback Shift Register (LFSR) and 8B/10B coding technology into 10-bit
code groups. Data scrambling is used to reduce the possibility of electrical resonance on the link, and
8B/10B coding technology is used to benefit embedded clocking, error detection, and DC balance by
adding an overhead to the system through the addition of 2 extra bits. The data code groups are passed
through its serializer for packet framing. The generated 2.5Gbps serial data is transmitted onto the PCB
trace to its upstream device via a differential driver.
6.1.2. PCI Express Receiver
The RTL8103E(L)’s PCI Express block receives 2.5Gbps serial data from its upstream device to generate
parallel data. The receiver’s PLL circuits are re-synchronized to maintain bit and symbol lock. Through
8B/10B decoding technology and data de-scrambling, the original digital data is recovered and passed to
the RTL8103E(L)’s internal Ethernet MAC to be transmitted onto the Ethernet media.
Integrated Fast Ethernet Controller for PCI Express 8 Track ID: JATR-1076-21 Rev. 1.3
Page 14
RTL8103E & RTL8103EL
Datasheet
6.2. LED Functions
The RTL8103E(L) supports four LED signals in four different configurable operation modes. The
following sections describe the various LED actions.
6.2.1. Link Monitor
The Link Monitor senses link integrity, such as LINK10, LINK100, or LINK10/100. Whenever link
status is established, the specific link LED pin is driven low. Once a cable is disconnected, the link LED
pin is driven high, indicating that no network connection exists.
6.2.2. Rx LED
In 10/100Mbps mode, blinking of the Rx LED indicates that receive activity is occurring.
Figure 3. Rx LED
Integrated Fast Ethernet Controller for PCI Express 9 Track ID: JATR-1076-21 Rev. 1.3
Page 15
RTL8103E & RTL8103EL
6.2.3. Tx LED
In 10/100Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring.
Datasheet
Figure 4. Tx LED
6.2.4. Tx/Rx LED
In 10/100Mbps mode, blinking of the Tx/Rx LED indicates that both transmit and receive activity is
occurring.
Figure 5. Tx/Rx LED
Integrated Fast Ethernet Controller for PCI Express 10 Track ID: JATR-1076-21 Rev. 1.3
Page 16
RTL8103E & RTL8103EL
Datasheet
6.2.5. Customizable LED Configuration
The RTL8103E(L) supports customizable LED operation modes via IO register offset 17h~18h. Table 11
describes the different LED actions.
Table 11. LED Select (IO Register Offset 17h~18h)
Bit Symbol RW Description
15:12 LEDSEL3 RW LED Select for PINLED3
11:8 LEDSEL2 RW LED Select for PINLED2
7:4 LEDSEL1 RW LED Select for PINLED1
3:0 LEDSEL0 RW LED Select for PINLED0
When implementing customized LEDs:
1. Set IO register offset 0x55 bit 6 to 1h to enable the customized LED function
2. Configure IO register offset 17h~18h to support your own LED signals. For example, if the value in the
IO offset 0x17 is 0x8C51h (1000110010100001b), the LED actions are:
• LED 0 is only on in 10M mode, with no blinking of TX/RX
• LED 1 is only on and with TX/RX blinking in 100M mode
• LED 2 is only on and with TX/RX blinking in 100M full duplex mode
• LED 3 is only on in full duplex mode
Table 12. Customized LEDs
LINK ACT/Full
Speed Link 10M Link100M Not Defined -
LED 0 Bit 0 Bit 1 Bit 2 Bit 3
LED 1 Bit 4 Bit 5 Bit 6 Bit 7
LED 2 Bit 8 Bit 9 Bit 10 Bit 11
LED 3 Bit 12 Bit 13 Bit 14 Bit 15
LED Pin ACT=0 ACT=1
LINK=0 Floating LED On when Full Duplex Mode
LINK>0 LED On when Selected Speed is Linked LED Blinking when Selected Speed TX/RX
Note1: ACT means blinking TX and RX. LINK indicates Link 10M and Link 100M.
Note2: There are two special modes:
Æ
Mode A: LED OFF Mode
Mode B: TX/RX Mode
LED 0 = Blinking TX/RX.
LED 1 = Follow Customized LED rule.
LED 2 = Follow Customized LED rule.
LED 3= Follow Customized LED rule.
Set all bits to 0.
Æ
Set LED 0=0, and either LED 1, LED 2, or LED 3 >0
Integrated Fast Ethernet Controller for PCI Express 11 Track ID: JATR-1076-21 Rev. 1.3
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RTL8103E & RTL8103EL
Datasheet
6.3. PHY Transceiver
6.3.1. PHY Transmitter
Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the
RTL8103E(L) operates at 10/100Mbps over standard CAT.5 UTP cable (100Mbps), and CAT.3 UTP
cable (10Mbps).
MII (100Mbps) Mode
The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into
5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are
converted to 125MHz NRZ and NRZI signals. After that, the NRZI signals are passed to the MLT3
encoder, then to the D/A converter and transmitted onto the media.
MII (10Mbps) Mode
The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into
10Mbps serial data. The 10Mbps serial data is converted into a Manchester-encoded data stream and is
transmitted onto the media by the D/A converter.
6.3.2. PHY Receiver
MII (100Mbps) Mode
The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing
recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the MII
interface in 4-bit-wide nibbles at a clock speed of 25MHz.
MII (10Mbps) Mode
The received differential signal is converted into a Manchester-encoded stream first. Next, the stream is
processed with a Manchester decoder and is de-serialized into 4-bit-wide nibbles. The 4-bit nibbles are
presented to the MII interface at a clock speed of 2.5MHz.
Integrated Fast Ethernet Controller for PCI Express 12 Track ID: JATR-1076-21 Rev. 1.3
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RTL8103E & RTL8103EL
Datasheet
6.4. EEPROM Interface
The RTL8103E(L) can use internal eFUSE memory or an external EEPROM. The 93C46/93C56 is a
1K-bit/2K-bit EEPROM. The EEPROM interface permits the RTL8103E(L) to read from, and write data
to, an external serial EEPROM device.
Note: The RTL8103EL only supports 93C46 EEPROM.
Values in the internal eFUSE memory or external EEPROM allow default fields in PCI configuration
space and I/O space to be overridden following a power-on or software EEPROM auto-load command.
The RTL8103E(L) will auto-load values from the eFUSE or EEPROM. If the EEPROM is not present
and eFUSE auto-load is bypassed, the RTL8103E(L) initialization uses default values for the appropriate
Configuration and Operational Registers. Software can read and write to the EEPROM using bit-bang
accesses via the 9346CR Register, or using PCI VPD (Vital Product Data). The interface consists of
EESK, EECS, EEDO, and EEDI.
The correct EEPROM (i.e., 93C46/93C56) must be used in order to ensure proper LAN function.
Table 13. EEPROM Interface
EEPROM Description
EECS 93C46/93C56 Chip Select.
EESK EEPROM Serial Data Clock.
Input data bus/Input pin to detect whether Aux. Power exists on initial power-on.
EEDI/Aux
EEDO Output Data Bus.
This pin should be connected to EEPROM. To support wakeup from ACPI D3cold or APM
power-down, this pin must be pulled high to Aux. Power via a resistor. If this pin is not pulled high
to Aux. Power, the RTL8103E(L) assumes that no Aux. Power exists.
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RTL8103E & RTL8103EL
Datasheet
6.5. Power Management
The RTL8103E(L) is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), PCI
Express Active State Power Management (ASPM), and Network Device Class Power Management
Reference Specification (V1.0a), such as to support an Operating System-directed Power Management
(OSPM) environment.
The RTL8103E(L) can monitor the network for a Wakeup Frame, a Magic Packet, and notify the system
via a PCI Express Power Management Event (PME) Message, Beacon, or LANWAKEB pin when such a
packet or event occurs. Then the system can be restored to a normal state to process incoming jobs.
When the RTL8103E(L) is in power down mode (D1 ~ D3):
• The Rx state machine is stopped. The RTL8103E(L) monitors the network for wakeup events such as
a Magic Packet and Wakeup Frame in order to wake up the system. When in power down mode, the
RTL8103E(L) will not reflect the status of any incoming packets in the ISR register and will not
receive any packets into the Rx on-chip buffer.
• The on-chip buffer status and packets that have already been received into the Rx on-chip buffer
before entering power down mode are held by the RTL8103E(L).
• Transmission is stopped. PCI Express transactions are stopped. The Tx on-chip buffer is held.
• After being restored to D0 state, the RTL8103E(L) transmits data that was not moved into the Tx
on-chip buffer during power down mode. Packets that were not transmitted completely last time are
re-transmitted.
The D3cold_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in
PCI configuration space depend on the existence of Aux power. If aux. power is absent, the above 4 bits
are all 0 in binary.
Example:
If EEPROM D3c_support_PME = 1:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC
(if EEPROM PMC = C3 FF, then PCI PMC = C3 FF)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the
above 4 bits are all 0’s (if EEPROM PMC = C3 FF, then PCI PMC = 03 7E)
In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM
PMC be set to C3 FF (Realtek EEPROM default value).
If EEPROM D3c_support_PME = 0:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC
(if EEPROM PMC = C3 7F, then PCI PMC = C3 7F)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the
above 4 bits are all 0’s (if EEPROM PMC = C3 7F, then PCI PMC = 03 7E)
In the above case, if wakeup support is not desired when main power is off, it is suggested that the
EEPROM PMC be set to 03 7E.
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RTL8103E & RTL8103EL
Datasheet
Magic Packet Wakeup occurs only when the following conditions are met:
• The destination address of the received Magic Packet is acceptable to the RTL8103E(L), e.g., a
broadcast, multicast, or unicast packet addressed to the current RTL8103E(L) adapter.
• The received Magic Packet does not contain a CRC error.
• The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the
corresponding wake-up method (message, beacon, or LANWAKEB) can be asserted in the current
power state.
• The Magic Packet pattern matches, i.e., 6 * FFh + MISC (can be none) + 16 * DID (Destination ID)
in any part of a valid Ethernet packet.
A Wakeup Frame event occurs only when the following conditions are met:
• The destination address of the received Wakeup Frame is acceptable to the RTL8103E(L), e.g., a
broadcast, multicast, or unicast address to the current RTL8103E(L) adapter.
• The received Wakeup Frame does not contain a CRC error.
• The PMEn bit (CONFIG1#0) is set to 1.
• The 16-bit CRC* of the received Wakeup Frame matches the 16-bit CRC of the sample Wakeup
Frame pattern given by the local machine’s OS. Or, the RTL8103E(L) is configured to allow direct
packet wakeup, e.g., a broadcast, multicast, or unicast network packet.
Note: 16-bit CRC: The RTL8103E(L) supports eight long wakeup frames (covering 128 mask bytes from
offset 0 to 127 of any incoming network packet).
The corresponding wake-up method (message, beacon, or LANWAKEB) is asserted only when the
following conditions are met:
• The PMEn bit (bit0, CONFIG1) is set to 1.
• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
• The RTL8103E(L) may assert the corresponding wake-up method (message, beacon, or LANWAKEB)
in the current power state or in isolation state, depending on the PME_Support (bit15-11) setting of
the PMC register in PCI Configuration Space.
• A Magic Packet, LinkUp, or Wakeup Frame has been received.
• Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears
this bit and causes the RTL8103E(L) to stop asserting the corresponding wake-up method (message,
beacon, or LANWAKEB) (if enabled).
When the RTL8103E(L) is in power down mode, e.g., D1-D3, the IO and MEM accesses to the
RTL8103E(L) are disabled. After a PERSTB assertion, the device’s power state is restored to D0
automatically if the original power state was D3
. There is almost no hardware delay at the device’s
cold
power state transition. When in ACPI mode, the device does not support PME (Power Management
Enable) from D0 (this is the Realtek default setting of the PMC register auto-loaded from EEPROM). The
setting may be changed from the EEPROM, if required.
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RTL8103E & RTL8103EL
Datasheet
6.6. Vital Product Data (VPD)
Bit 31 of the Vital Product Data (VPD) capability structure in the RTL8103E(L)’s PCI Configuration
Space is used to issue VPD read/write commands and is also a flag used to indicate whether the transfer
of data between the VPD data register and the 93C46/93C56/93C66 has completed or not.
Note: The RTL8103EL only supports 93C46 EEPROM.
Write VPD register: (write data to the 93C46/93C56/93C66)
Set the flag bit to 1 at the same time the VPD address is written to write VPD data to EEPROM. When
the flag bit is reset to 0 by the RTL8103E(L), the VPD data (4 bytes per VPD access) has been transferred
from the VPD data register to EEPROM.
Read VPD register: (read data from the 93C46/93C56/93C66)
Reset the flag bit to 0 at the same time the VPD address is written to retrieve VPD data from EEPROM.
When the flag bit is set to 1 by the RTL8103E(L), the VPD data (4 bytes per VPD access) has been
transferred from EEPROM to the VPD data register.
Note1: Refer to the PCI 2.3 Specifications for further information.
Note2: The VPD address must be a DWORD-aligned address as defined in the PCI 2.3 Specifications.
VPD data is always consecutive 4-byte data starting from the VPD address specified.
Note3: Realtek reserves offset 60h to 7Fh in EEPROM mainly for VPD data to be stored.
Note4: The VPD function of the RTL8103E is designed to be able to access the full range of the
93C46/93C56/93C66 EEPROM, however, the RTL8103EL only supports the 93C46 EEPROM.
6.7. Receive-Side Scaling (RSS)
The RTL8103E(L) is compliant with the Network Driver Interface Specification (NDIS) 6.0 Receive-Side
Scaling (RSS) technology for the Microsoft Windows family of operating systems. RSS allows packet
receive-processing from a network adapter to be balanced across the number of available computer
processors, increasing performance on multi-CPU platforms.
6.7.1. Receive-Side Scaling (RSS) Initialization
During RSS initialization, the Windows operating system will inform the RTL8103E(L) to store the
following parameters: hash function, hash type, hash bits, indirection table, BaseCPUNumber, and the
secret hash key.
Hash Function
The default hash function is the Toeplitz hash function.
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RTL8103E & RTL8103EL
Datasheet
Hash Type
The hash types indicate which field of the packet needs to be hashed to get the hash result. There are
several combinations of these fields, mainly, TCP/IPv4, IPv4, TCP/IPv6, IPv6, and IPv6 extension
headers.
• TCP/IPv4 requires hash calculations over the IPv4 source address, the IPv4 destination address, the
source TCP port and the destination TCP port.
• IPv4 requires hash calculations over the IPv4 source address and the IPv4 destination address.
• TCP/IPv6 requires hash calculations over the IPv6 source address, the IPv6 destination address, the
source TCP port and the destination TCP port.
• IPv6 requires hash calculations over the IPv6 source address and the IPv6 destination address
(Note: The RTL8103E(L) does not support the IPv6 extension header hash type in RSS).
Hash Bits
Hash bits are used to index the hash result into the indirection table.
Indirection Table
The Indirection Table stores values that are added to the BaseCPUNumber to enable RSS interrupts to be
restricted from some CPUs. The OS will update the Indirection Table to rebalance the load.
BaseCPUNumber
The lowest number CPU to use for RSS. BaseCPUNumber is added to the result of the indirection table
lookup.
Secret Hash Key
The key used in the Toeplitz function. For different hash types, the key size is different.
6.7.2. RSS Operation
After the parameters are set, the RTL8103E(L) will start hash calculation on each incoming packet and
forward each packet to its correct queue according to the hash result. If the incoming packet is not in the
hash type, it will be forwarded to the primary queue. The hash result plus the BaseCPUNumber will be
indexed into the indirection table to get the correct CPU number. The RTL8103E(L) uses three methods
to inform the system of incoming packets: inline interrupt, MSI, and MSIX. Periodically the OS will
update the indirection table to rebalance the load across the CPUs.
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RTL8103E & RTL8103EL
Datasheet
7. Characteristics
7.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability will be affected. All voltages are specified reference to GND unless
otherwise specified.
Table 14. Absolute Maximum Ratings
Symbol Description Minimum Maximum Unit
VDD33, AVDD33 Supply Voltage 3.3V -0.3 +0.3 V
DVDD12 Supply Voltage 1.2V -0.12 +0.12 V
EVDD12 Supply Voltage 1.2V -0.12 +0.12 V
DCinput Input Voltage -0.3 Corresponding Supply Voltage + 0.5 V
DCoutput Output Voltage -0.3 Corresponding Supply Voltage + 0.5 V
N/A Storage Temperature -55 +125
Note: Refer to the most updated schematic circuit for correct configuration.
°C
7.2. Recommended Operating Conditions
Table 15. Recommended Operating Conditions
Description Pins Minimum Typical Maximum Unit
VDD33, AVDD33 3.0 3.3 3.6 V
Supply Voltage VDD
Ambient Operating Temperature TA - 0 - 70
Maximum Junction Temperature - - - 125
Note: Refer to the most updated schematic circuit for correct configuration.
DVDD12 1.08 1.2 1.32 V
EVDD12 1.08 1.2 1.32 V
°C
°C
7.3. Crystal Requirements
Table 16. Crystal Requirements
Symbol Description/Condition Minimum Ty pica l Maximum Unit
F
ref
F
Stability
ref
F
Tolerance
ref
F
Duty Cycle Reference Clock Input Duty Cycle. 40 - 60 %
ref
ESR Equivalent Series Resistance. - - 30
DL
Parallel Resonant Crystal Reference Frequency,
Fundamental Mode, AT-Cut Type.
Parallel Resonant Crystal Frequency Stability,
Fundamental Mode, AT-Cut Type.
= 0°C ~ +70°C.
T
a
Parallel Resonant Crystal Frequency Tolerance,
Fundamental Mode, AT-Cut Type.
= 25°C.
T
a
Drive Level. - - 0.5 mW
- 25 - MHz
-30 - +30 ppm
-50 - +50 ppm
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RTL8103E & RTL8103EL
Datasheet
7.4. Transformer Characteristics
Table 17. Transformer Characteristics
Parameter Transmit End Receive End
Turn Ratio 1:1 CT 1:1
Inductance (min.) 350µH @ 8mA 350µH @ 8mA
7.5. Oscillator Requirements
Table 18. Oscillator Requirements
Parameter Condition Minimum Typ ical Maximum Unit
Frequency - - 25 - MHz
Frequency Stability
Frequency Tolerance
Duty Cycle - 40 - 60 %
Jitter - - - 50 ps
Vp-p - 3.15 3.3 3.45 V
Rise Time
Fall Time - - - 10 ns
Operation Temp Range -
T
= 0°C ~ +70°C
a
T
= 25°C.
a
- - - 10 ns
-30 - +30 ppm
-50 - +50 ppm
0 - 70
°C
7.6. Thermal Characteristics
Table 19. Thermal Characteristics
Parameter Minimum Maximum Units
Storage Temperature -55 +125
Ambient Operating Temperature
0 70
°C
°C
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RTL8103E & RTL8103EL
Datasheet
7.7. DC Characteristics
Table 20. DC Characteristics
Symbol Parameter Conditions Minimum Typi cal Maximum Units
VDD33, AVDD33 3.3V Supply Voltage - 3.0 3.3 3.6 V
EVDD12 1.2V Supply Voltage - 1.08 1.2 1.32 V
DVDD12 1.2V Supply Voltage - 1.08 1.2 1.32 V
Voh
Vo l
Vih
Vil
Iin
Icc33
Icc12
Note: Refer to the most updated schematic circuit for correct configuration.
Minimum High Level
Output Voltage
Maximum Low Level
Output Voltage
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Input Current Vin=VDD33 or GND 0 - 0.5 µA
Maximum Operating
Supply Current from 3.3V
Maximum Operating
Supply Current from 1.2V
Ioh = -4mA 0.9*VDD33 - VDD33 V
Iol = 4mA 0 - 0.1*VDD33 V
- 1.8 - - V
- - - 0.8 V
- - - 201 mA
- - - 127 mA
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7.8. AC Characteristics
7.8.1. Serial EEPROM Interface Timing
93C46(64*16)/93C56(128*16)
EESK
RTL8103E & RTL8103EL
Datasheet
EECS
EEDI
EEDO
EESK
EECS
EEDI
EEDO
EESK
EECS
EEDI
EEDO
EEDO
(Read)
(Read)
High Impedance
(Write)
(Write)
High Impedance
(Read)
(Program)
11
110
tcss
tdis tdih
tsv
0
An A2 A0A1
...
An A0
tsk
tskh tskl
0
Dn D1 D0
tcs
...
Dn
tdos tdoh
STATUS VALID
D0
Figure 6. Serial EEPROM Interface Timing
tcs
BUSY READY
twp
tcsh
Table 21. EEPROM Access Timing Parameters
Symbol Parameter EEPROM Type Min. Max. Unit
tcs Minimum CS Low Time 9346 1000 - ns
twp Write Cycle Time 9346 - 10 ms
tsk SK Clock Cycle Time 9346 4 - µs
tskh SK High Time 9346 1000 - ns
tskl SK Low Time 9346 1000 - ns
tcss CS Setup Time 9346 200 - ns
tcsh CS Hold Time 9346 0 - ns
tdis DI Setup Time 9346 400 - ns
tdih DI Hold Time 9346 400 - ns
tdos DO Setup Time 9346 2000 - ns
tdoh DO Hold Time 9346 - 2000 ns
tsv CS to Status Valid 9346 - 1000 ns
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RTL8103E & RTL8103EL
Datasheet
7.9. PCI Express Bus Parameters
7.9.1. Differential Transmitter Parameters
Table 22. Differential Transmitter Parameters
Symbol Parameter Min Ty pica l Max Units
UI
V
TX-DIFFp-p
V
TX-DE-RATIO
T
TX-EYE
T
TX-EYE-MEDIAN-
to-MAX-JITTER
T
V
V
IDLEDELTA
V
DELTA
V
V
, T
TX-RISE
TX-CM-ACp
TX-CM-DCACTIVE-
TX-FALL
TX-CM-DCLINE-
TX-IDLE-DIFFp
TX-RCV-DETECT
Electrical Idle Differential Peak Output Voltage 0 - 20 mV
Unit Interval
Differential Peak to Peak Output Voltage 0.800 - 1.2 V
De-Emphasized Differential Output Voltage (Ratio) -3.0 -3.5 -4.0 dB
Minimum Tx Eye Width 0.75 - - UI
Maximum Time between The Jitter Median And
Maximum Deviation from The Median
D+/D- Tx Output Rise/Fall Time 0.125 - - UI
RMS AC Peak Common Mode Output Voltage - - 20 mV
Absolute Delta of DC Common Mode Voltage
During L0 and Electrical Idle
Absolute Delta of DC Common Mode Voltage
between D+ and D-
The Amount of Voltage Change Allowed During
Receiver Detection
V
TX-DC-CM
I
TX-SHORT
T
TX-IDLE-MIN
T
TX-IDLE- SETTO-IDLE
The TX DC Common Mode Voltage 0 - 3.6 V
TX Short Circuit Current Limit - - 90 mA
Minimum Time Spent in Electrical Idle 50 - - UI
Maximum Time to Transition to A Valid Electrical Idle
after Sending An Electrical Idle Ordered Set
T
TX-IDLE-TOTO-
DIFF-DATA
RL
RL
Z
L
TX-DIFF
Common Mode Return Loss 6 - - dB
TX-CM
TX-DIFF-DC
TX-SKEW
Differential Return Loss 10 - - dB
DC Differential TX Impedance 80 100 120
Lane-to-Lane Output Skew - - 500+2*UI ps
Maximum Time to Transition to Valid TX Specifications
after Leaving An Electrical Idle Condition
CTX AC Coupling Capacitor 75 - 200 nF
T
Crosslink Random Timeout 0 - 1 ms
crosslink
Note1: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter.
Note2: The data rate can be modulated with an SSC (Spread Spectrum Clock) from +0 to -0.5% of the nominal data rate
frequency, at a modulation rate in the range not exceeding 30kHz – 33kHz. The +/-300ppm requirement still holds, which
requires the two communicating ports be modulated such that they never exceed a total of 600ppm difference.
399.88 400 400.12 ps
- - 0.125 UI
0 - 100 mV
0 - 25 mV
- - 600 mV
- - 20 UI
- - 20 UI
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RTL8103E & RTL8103EL
Datasheet
7.9.2. Differential Receiver Parameters
Table 23. Differential Receiver Parameters
Symbol Parameter Min. Typi cal Max. Units
UI Unit Interval 399.88 400 400.12 ps
V
RX-DIFFp-p
T
RX-EYE
T
RX-EYE-MEDIAN-to-
MAX-JITTER
V
RX-CM-ACp
RL
RL
Z
RX-DIFF-DC
Z
RX--DC
Z
RX-HIGH-IMP-DC
V
RX-IDLE-DET-DIFFp-p
T
RX-IDLE-DET-
DIFFENTERTIME
L
RX-SKEW
Differential Return Loss 10 - - dB
RX-DIFF
RX-CM
DC Differential Input Impedance 80 100 120
DC Input Impedance 40 50 60
Powered Down DC Input Impedance 200 k - -
Total Skew - - 20 ns
Note: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter.
Differential Input Peak to Peak Voltage 0.175 - 1.200 V
Minimum Receiver Eye Width 0.4 - - UI
Maximum Time between The Jitter Median and
- - 0.3 UI
Maximum Deviation from The Median
AC Peak Common Mode Input Voltage - - 150 mV
Common Mode Return Loss 6 - - dB
Electrical Idle Detect Threshold 65 - 175 mV
Unexpected Electrical Idle Enter Detect Threshold
- - 10 ms
Integration Time
7.9.3. REFCLK Parameters
Table 24. REFCLK Parameters
Symbol Parameter 100MHz Input
Min Max
Rise Edge Rate Rising Edge Rate 0.6 4.0 V/ns 2, 3
Fall Edge Rate Falling Edge Rate 0.6 4.0 V/ns 2, 3
VIH Differential Input High Voltage +150 - mV 2
V
IL
V
CROSS
V
CROSS DELTA
Differential Input Low Voltage - -150 mV 2
Absolute Crossing Point Voltage +250 +550 mV 1, 4, 5
Variation of V
Over All Rising Clock Edges - +140 mV 1, 4, 9
CROSS
VRB Ring-Back Voltage Margin -100 +100 mV 2, 12
T
STABLE
T
PERIOD AVG
T
PERIOD ABS
T
CCJITTER
V
MAX
V
MIN
Average Clock Period Accuracy -300 +2800 ppm 2, 10, 13
Absolute Period (Including Jitter and Spread Spectrum) 9.847 10.203 ns 2, 6
Cycle to Cycle Jitter -
Absolute Max Input Voltage - +1.15 V 1, 7
Absolute Min Input Voltage - -0.3 V 1, 8
Time before V
is Allowed 500 - ps 2, 12
RB
150
Duty Cycle Duty Cycle 40 60 % 2
Units Note
ps 2
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RTL8103E & RTL8103EL
Datasheet
Symbol Parameter 100MHz Input
Min Max
Rise-Fall Matching
Z
Clock Source DC Impedance 40 60 1, 11
C-DC
Note1: Measurement taken from single ended waveform.
Note2: Measurement taken from differential waveform.
Note3: Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The
signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is
centered on the differential zero crossing. See Figure 10, page 26.
Note4: Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the
falling edge of REFCLK-. See Figure 7, page 25.
Note5: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement. See Figure 7, page 25.
Note6: Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative ppm
tolerance, and spread spectrum modulation. See Figure 9, page 25.
Note7: Defined as the maximum instantaneous voltage including overshoot. See Figure 7, page 25.
Note8: Defined as the minimum instantaneous voltage including undershoot. See Figure 7, page 25.
Note9: Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the
maximum allowed variance in VCROSS for any particular system. See Figure 7, page 25.
Note10: Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding ppm
considerations.
Note11: System board compliance measurements must use the test load card described in Figure 13, page 27. REFCLK+
and REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements
requiring single ended measurements. Either single ended probes with math or differential probe can be used for
differential measurements. Test load CL=2pF.
Note12: T
edges before it is allowed to droop back into the V
Note13: ppm refers to parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000
100.000000MHz exactly or 100Hz. For 300ppm then we have an error budget of 100Hz/ppm*300ppm=30kHz. The period
is to be measured with a frequency counter with measurement window set to 100ms or greater. The ±300ppm applies to
systems that do not employ Spread Spectrum or that use common clock source. For systems employing Spread Spectrum
there is an additional 2500ppm nominal shift in maximum period resulting from the 0.5% down spread resulting in a
maximum average period specification of +2800ppm
Note14: Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a
±75mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross
point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge
Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 8, page 25.
Note15: Refer to PCI Express Card Electromechanical Specification, rev.1.1, for correct measurement environment setting
of each parameter.
STABLE
Rising Edge Rate (REFCLK+) to Falling Edge Rate
(REFCLK-) Matching
is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling
±100mV differential range. See Figure 12, page 26.
RB
- 20 % 1, 14
Units Note
th
of
Integrated Fast Ethernet Controller for PCI Express 24 Track ID: JATR-1076-21 Rev. 1.3
Page 30
RTL8103E & RTL8103EL
Datasheet
Figure 7. Single-Ended Measurement Points for Absolute Cross Point and Swing
Figure 8. Single-Ended Measurement Points for Delta Cross Point
Figure 9. Single-Ended Measurement Points for Rise and Fall Time Matching
Integrated Fast Ethernet Controller for PCI Express 25 Track ID: JATR-1076-21 Rev. 1.3
Page 31
RTL8103E & RTL8103EL
Datasheet
Figure 10. Differential Measurement Points for Duty Cycle and Period
Figure 11. Differential Measurement Points for Rise and Fall Time
Figure 12. Differential Measurement Points for Ringback
Integrated Fast Ethernet Controller for PCI Express 26 Track ID: JATR-1076-21 Rev. 1.3
Page 32
RTL8103E & RTL8103EL
Datasheet
Figure 13. Reference Clock System Measurement Point and Loading
7.9.4. Auxiliary Signal Timing Parameters
Table 25. Auxiliary Signal Timing Parameters
Symbol Parameter Min Max Units
T
T
T
T
T
Power Stable to PERSTB Inactive 100 - ms
PVPERL
PERST-CLK
PERST
FAI L
WKRF
REFCLK Stable before PERSTB Inactive 100 - µs
PERSTB Active Time 100 - µs
Power Level Invalid to PWRGD Inactive - 500 ns
LANWAKEB Rise – Fall Time - 100 ns
Figure 14. Auxiliary Signal Timing
Integrated Fast Ethernet Controller for PCI Express 27 Track ID: JATR-1076-21 Rev. 1.3
Page 33
8. Mechanical Dimensions
8.1. RTL8103E (64-Pin QFN)
RTL8103E & RTL8103EL
Datasheet
NOTE: The RTL8103E Exposed Pad Size is type 3.
Integrated Fast Ethernet Controller for PCI Express 28 Track ID: JATR-1076-21 Rev. 1.3
Page 34
8.2. RTL8103EL (48-Pin LQFP)
RTL8103E & RTL8103EL
Datasheet
Integrated Fast Ethernet Controller for PCI Express 29 Track ID: JATR-1076-21 Rev. 1.3
Page 35
RTL8103E & RTL8103EL
Datasheet
8.3. Mechanical Dimensions Notes (RTL8103EL 48-Pin)
Notes:
Symbol
A1 0.000 0.004 0.008 0.00 0.1 0.20 4. Exact shape of each corner is optional.
A2 0.051 0.055 0.059 1.30 1.40 1.50 5. These dimensions apply to the flat section of the lead
D1 0.276 BSC 7.00 BSC
E1 0.276 BSC 7.00 BSC
L1 0.039 REF 1.00 REF
θ1 0°
θ2 12° TYP 12° TYP
θ3 12° TYP 12° TYP
Dimension in
Inchs
Min Nom Max Min Nom Max 3. Dimension b does not include dambar protrusion.
A - - 0.067 - - 1.70 Dambar cannot be located on the lower radius of the foot.
b 0.006 0.009 0.011 15 0.22 0.29 between 0.10 mm and 0.25 mm from the lead tip.
b1 0.006 0.008 0.010 0.15 0.20 0.25 6. A1 is defined as the distance from the seating plane to
c1 0.004 - 0.006 0.09 - 0.16 the lowest point of the package body.
D 0.354 BSC 9.00 BSC
E 0.354 BSC 9.00 BSC
e
L 0.016 0.024 0.031 0.40 0.60 0.80
θ
0.020 BSC 0.50 BSC
0° 3.5° 9° 0° 3.5° 9°
- -
Dimension in
Millimeters
0°
- -
1. To be determined at seating plane -c-
2. Dimensions D1 and E1 do not include mold protrusion.
D1 and E1 are maximum plastic body size dimensions including
mold mismatch.
7. Controlling dimension: millimeter.
8. Reference document: JEDEC MS-026, BBC
PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm
APPROVE
CHECK
TITLE: 48LD LQFP ( 7x7x1.4mm)
LEADFRAME MATERIAL:
DOC. NO.
VERSION 1
PAGE OF
DWG NO. SS048 - P1
DATE
REALTEK SEMICONDUCTOR CORP.
Integrated Fast Ethernet Controller for PCI Express 30 Track ID: JATR-1076-21 Rev. 1.3
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RTL8103E & RTL8103EL
9. Ordering Information
Table 26. Ordering Information
Part Number Package Status
RTL8103E-GR 64-Pin QFN ‘Green’ Package
RTL8103EL-GR 48-Pin LQFP ‘Green’ Package
Note: See page 3 (RTL8103E) and page 4 (RTL8103EL) for package identification information.
Datasheet
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
Integrated Fast Ethernet Controller for PCI Express 31 Track ID: JATR-1076-21 Rev. 1.3
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