Page 1
ULTRA-COMPA CT SERIAL REAL-TIME CLOCK ICs
WITH 32.768kHz
RS5C321A/B
ELECTRONIC DEVICES DIVISION
NO.EA-040-9908
APPLICATION MANUAL
Page 2
NOTICE
1. The products and the product specifications described in this application manual are subject to change or discontinuation of production without notice for reasons such as improvement. Therefore, before deciding to use
the products, please refer to Ricoh sales representatives for the latest information thereon.
2. This application manual may not be copied or otherwise reproduced in whole or in part without prior written consent of Ricoh.
3. Please be sure to take any necessary formalities under relevant laws or regulations before exporting or otherwise taking out of your country the products or the technical information described herein.
4. The technical information described in this application manual shows typical characteristics of and example
application circuits for the products. The release of such information is not to be construed as a warranty of or a
grant of license under Ricoh's or any third party's intellectual property rights or any other rights.
5. The products listed in this document are intended and designed for use as general electronic components in
standard applications (office equipment, computer equipment, measuring instruments, consumer electronic
products, amusement equipment etc.). Those customers intending to use a product in an application requiring
extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of
the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic
control system, automotive and transportation equipment, combustion equipment, safety devices, life support
system etc.) should first contact us.
6. We are making our continuous effort to improve the quality and reliability of our products, but semiconductor
products are likely to fail with certain probability. In order prevent any injury to persons or damages to property
resulting from such failure, customers should be careful enough to incorporate safety measures in their design,
such as redundancy feature, fire-containment feature and fail-safe feature. We do not assume any liability or
responsibility for any loss or damage arising from misuse or inappropriate use of the products.
7. Anti-radiation design is not implemented in the products described in this application manual.
8. Please contact Ricoh sales representatives should you have any questions or comments concerning the products or the technical information.
June 1995
Page 3
OUTLINE
......................................................................................................
1
FEATURES
....................................................................................................
1
BLOCK DIAGRAM
.........................................................................................
2
APPLICATIONS
.............................................................................................
2
PIN CONFIGURATION
...................................................................................
2
PIN DESCRIPTIONS
......................................................................................
3
ABSOLUTE MAXIMUM RATINGS
...................................................................
4
RECOMMENDED OPERATING CONDITIONS
.................................................
4
DC CHARACTERISTICS
................................................................................
5
AC CHARACTERISTICS
................................................................................
5
TIMING CHARTS
...........................................................................................
6
FUNCTIONAL DESCRIPTIONS
......................................................................
7
1. Addressing
.................................................................................................
7
2. Registers
...................................................................................................
8
3. Counters
..................................................................................................
11
USAGES
......................................................................................................
13
1. Read Data (For the RS5C321A)
......................................................................
13
2. Write Data (For the RS5C321A)
.......................................................................
14
3. Read Data (For the RS5C321B)
......................................................................
15
4. Write Data (For the RS5C321B)
.......................................................................
16
5. CE Pin
....................................................................................................
17
6. Configuration of Oscillating Circuit
....................................................................
18
7. Oscillator Halt Sensing
.................................................................................
19
8. Typical Power Supply Circuit
...........................................................................
20
9. Oscillation Frequency Adjustment
.....................................................................
20
10. 32.768kHz Clock Output
..............................................................................
22
RS5C321A/B
APPLICATION MANUAL
CONTENTS
Page 4
11. Typical Application
.....................................................................................
22
12. Typical Characteristic Measurements
...............................................................
23
13. Typical Software-based Operations
.................................................................
25
PACKAGE DIMENSIONS
..............................................................................
28
TAPING SPECIFICATION
..............................................................................
28
Page 5
URTRA-COMPACT ALARM REAL-TIME
CLOCK ICs WITH 32.768kHz
1
RS5C321A/B
OUTLINE
The RS5C321A/B are CMOS type real-time clock ICs which are connected to the CPU via three signal lines and
capable of serial transmission of clock and calendar data to the CPU.
The RS5C321A/B can generate 32.768kHz clock pulse controled by register. Driving an oscillation circuit at constant voltage, the circuit presents less fluctuations in frequency and current consumption thank to its minimal voltage fluctuations consequently realizes low current consumption (0.6µA at 3V). It also provides an oscillator halt
sensing function for application to data validity at power-on and other occasions. Integrated into an ultra compact
and ultra thin 8pin SSOP (0.65mm pitch), the RS5C321A/B are the optimum choice for equipment requiring small
size and low power consumption.
The RS5C321A and the RS5C321B reads/writes data at falling and rising edge of serial clock respectively.
• Time keeping voltage 1.6V to 6.0V
• Lowest supply current 0.6µA TYP. (1.5µA MAX.) at 3V
• Connection to the CPU via only three pins: CE, SCLK/SCLK and SIO for addressing and data read/write
• A clock counter (counting hours, minutes, and seconds) and a calendar counter (counting leap years, years,
months, days, and days of the week) in BCD code
• 32.768kHz clock pulse controled by register.
• Oscillator halt sensing to judge internal data validity
• Second digit adjustment by ±30 seconds
• 12-hour or 24-hour time display selectable
• Automatic leap year recognition up to the year 2099
• CMOS logic
• Package: 8pin SSOP (0.65mm pitch)
FEATURES
Page 6
APPLICATIONS
• Communication equipment (Multi-function telephone, portable telephone, PHS, pager)
• Business machines (Facsimile, portable facsimile)
• Personal computer (Desktop type, notebook type, word processor, PDA, electronic notebook, TV games)
• Audio visual equipment (Portable audio equipment, video camera, camera, digital camera, remote control equipment)
• Home use (Rice cooker, microwave range)
PIN CONFIGURATION
• 8pin SSOP (0.65mm pitch)
CE
1
SCLK
2
SIO
3
VSS
VDD
OSCIN
OSCOUT
RS5C321A RS5C321B
32KOUT
4
8
7
6
5
CE
1
SCLK
2
SIO
3
VSS
VDD
OSCIN
OSCOUT
32KOUT
4
8
7
6
5
RS5C321A/B
2
BLOCK DIAGRAM
OSC DIV
ADDRESS
DECODER
ADDRESS
REGISTER
TIME COUNTER
(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)
32kHz CLOCK
CONTORL
SHIFT REGISTER
I/O
CONTROL
OSC
DETECT
OSCIN
OSCOUT
SIO
SCLK/SCLK*
CE
32KOUT
*
) RS5C321A: SCLK RS5C321B: SCLK
Page 7
RS5C321A/B
3
Pin No.
1
2
3
5
7
6
8
4
PIN DESCRIPTIONS
Symbol
CE
SCLK
(RS5C321A)
SCLK
(RS5C321B)
SIO
32KOUT
OSCIN
OSCOUT
VDD
VSS
Name
Chip enable input
Serial clock input
Serial input/output
32.768kHz clock
output
Oscillator circuit
input/output
Positive/Negative
power supply input
Description
The CE pin is used to interface the CPU and is accessible when held at the high
level. This pin is connected to a pull-down resistor. It should be switched to the
low level or opened when not accessed or when powering off the system.
This pin is used to input shift clock pulses to synchronize data input to, and output
from, the SIO pin. SCLK and SCLK are for writing data at falling and rising edge of
clock pulses respectively and also reading data at rising and falling edge of clock
pulses respectively.
The SIO pin inputs and outputs written or read data in synchronization with shift
clock pulses from the SCLK/SCLK pin. The SIO pin causes high impedance when
CE pin is held at the low level (CMOS input/output). After the CE pin is switched
to the high level and the control bits and the address bits are input from the SIO,
the SIO pin performs serial input and output operations.
The 32KOUT pin outputs 32.768kHz clock pulses when activated. This pin functions as an Nch open drain output.
These pins configure an oscillator circuit by connecting a 32.768kHz crystal oscillator between the OSCIN and OSCOUT pins and by connecting a capacitor between
the OSCIN and Vss pins. (Any other oscillator circuit components are built into
the RS5C321A/B.)
The VDD pin and V
SS pin are connected to the positive power supply and to the
ground level respectively.
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RS5C321A/B
4
ABSOLUTE MAXIMUM RATINGS
ABSOLUTE MAXIMUM RATINGS
(VSS=0V)
Symbol Item Conditions Ratings Unit
VDD Supply voltage –0.3 to +7.0 V
VI Input voltage –0.3 to VDD+0.3 V
VO1 Output voltage 1 SIO –0.3 to VDD+0.3 V
VO2 Output voltage 2 32KOUT –0.3 to +12 V
PD Power dissipation Topt=25°C 300 mW
Topt Operating temperature –40 to +85 ˚C
Tstg Storage temperature –55 to +125 ˚C
Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under
any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation
above these absolute maximum ratings may cause degradation or permanent damage to the device. These
are stress ratings only and do not necessarily imply functional operation below these limits.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V, Topt=–40 to +85˚C)
Symbol Item Conditions MIN. TYP. MAX. Unit
VDD Supply voltage 2.5 6.0 V
VCLK Time keeping voltage 1.6 6.0 V
fXT Oscillation frequency 32.768 kHz
CG External oscillation capacitance CL value of crystal=6 to 8pF 5 10 24 pF
V
PUP Pull-up voltage 32KOUT 10 V
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RS5C321A/B
5
Symbol Item Pin name Conditions MIN. TYP. MAX. Unit
VIH “H” input voltage CE, SCLK/SCLK, SIO 0.8VDD VDD V
VIL “L” input voltage CE, SCLK/SCLK, SIO 0 0.2VDD V
IOH “H” output current SIO VOH=VDD –0.5V –0.5 mA
IOL1
“L” output current
SIO V
OL1=0.5V 0.5
mA
IOL2 32KOUT VOL2=0.4V 1
RDN Pull-down resistance CE 45 150 450 kΩ
IILK Input leakage current SCLK/SCLK VI=VDD or VSS –1 1 µA
IOZ1 Output off-state SIO VO=VDD or VSS –2 2
µA
IOZ2 leakage current 32KOUT VO=10V –5 5
I
DD1 Standby current 1* VDD
VDD=3V
0.6 1.5 µA
Input/Output: open
I
DD2 Standby current 2* VDD
VDD=6V
0.8 2.0 µA
Input/Output: open
C
D
Internal oscillation
OSCOUT 10 pF
capacitance
DC CHARACTERISTICS
Unless otherwise specified: VSS=0V, VDD=3V, Topt=–40 to +85˚C, Oscillation frequency=32.768kHz,(CL=6pF, R1=30kΩ), CG=10pF
AC CHARACTERISTICS
(VSS=0V, Topt=–40 to +85˚C, CL=50pF)
Symbol Item
V
DD≥4.5V VDD≥4.0V VDD≥2.5V
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
tCES CE set-up time 175 200 400 ns
tCEH CE hold time 175 200 400 ns
tCR CE inactive time 350 400 800 ns
tSCK SCLK clock cycle time 350 400 800 ns
tCKH SCLK high time 175 200 400 ns
tCKL SCLK low time 175 200 400 ns
tCKS SCLK to CE set-up time 60 80 120 ns
tRE
Data output start time (from rising
120 135 300 ns
of SCLK) (from falling of SCLK)
tRR
Data output delay time (from rising
120 135 300 ns
of SCLK) (from falling of SCLK)
tRZ Output floating time 120 135 300 ns
tDS Input data set-up time 50 60 120 ns
tDH Input data hold time 50 50 80 ns
*
) IDD1, IDD2 is specified when 32kHz output is off (CLEN=1)
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RS5C321A/B
6
tSCKtCES
tCKS
tCEH
tCR
tRE
tRZ
tCKHtCKL
tRR
Read Data
Write Data
t
DS tDH
CE
SCLK
SIORead cycle
Write cycle
SIO
tSCKtCES
tCKS
tCEH
tCR
tRE
tRZ
tCKHtCKL
tRR
Read Data
Write Data
t
DS tDH
CE
SCLK
SIORead cycle
Write cycle
SIO
Input/Output conditions: VIH=0.8×VDD, VIL=0.2×VDD, VOH=0.8×VDD, VOL=0.2×VDD
• RS5C321A
• RS5C321B
TIMING CHARTS
*
) Any SCLK/SCLK state is allowed in the hatched area.
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RS5C321A/B
7
FUNCTIONAL DESCRIPTIONS
1. Addressing
Address
Registers
Data *
1
A3 A2 A1 A0
D3 D2 D1 D0
0 0 0 0 0 1-second counter (BANK=0) S8 S4 S2 S1
1 0 0 0 1 10-second counter (BANK=0) —*
2
S40 S20 S10
2 0 0 1 0 1-minute counter (BANK=0) M8 M4 M2 M1
3 0 0 1 1 10-minute counter (BANK=0) — M40 M20 M10
4 0 1 0 0 1-hour counter (BANK=0) H8 H4 H2 H1
5 0 1 0 1 10-hour counter (BANK=0) — — P/A, H20 H10
6 0 1 1 0 Day of the week counter (BANK=0) — W4 W2 W1
7 0 1 1 1 Scratch register*
8
(BANK=0, 1) Scratch*8Scratch*8Scratch*8Scratch*
8
8 1 0 0 0 1-day counter (BANK=0) D8 D4 D2 D1
9 1 0 0 1 10-day counter (BANK=0) — — D20 D10
A 1 0 1 0
1-month counter (BANK=0) MO
8 MO4 MO2 MO1
32kHz clock pulse control register (BANK=1) — — — CLEN*
7
B 1 0 1 1 10-month counter (BANK=0) — — — MO10
C 1 1 0 0 1-year counter (BANK=0) Y8 Y4 Y2 Y1
D 1 1 0 1 10-year counter (BANK=0) Y80 Y40 Y20 Y10
E 1 1 1 0 Control register 1 (BANK=0, 1) — —
WTEN
*
6
/XSTP
*
4
ADJ/BSY *
3
F 1 1 1 1 Control register 2 (BANK=0, 1) 12/24 — BANK *5TEST *
6
*
1) All the listed data can be read and written.
*
2) The “—” mark indicates data which can be read only and set to “0” when read.
*
3) The ADJ/BSY bit of the control register is set to ADJ for write operation and BSY for read operation.
*
4) The WTEN/XSTP bit of the control register is set to WTEN for write operation and XSTP for read operation.
*
5) The clock/calendar counter and the 32kHz clock pulse control register can be selected when the BANK=0 and BANK=1 respectively. To designate
the BANK is unnecessary for scratch register and control register 1/2.
*
6) The WTEN bit and TEST bit are set to “1” when CE is “L”.
*
7) The CLEN bit is set to 0, when initial power-on or XSTP is set to 1.
*
8) Data may be written and read into/from the Scratch register, which actually is not used.
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RS5C321A/B
8
2. Registers
2.1 Control Register 1 (at Eh)
D3 D2 D1 D0
0
0 XSTP BSY
— — WTEN ADJ
(For write operation)
(For read operation)
±30-second Adjustment Bit
ADJ
Description
0
1
Ordinary operation
Second digit adjustment
BSY
Description
0
1
Ordinary operation
Second digit carry or adjustment
Clock/Counter Busy-state Indication Bit
WTEN
Description
0
1
Disabling of 1-second digit carry for clock counter
Enabling of 1-second digit carry for clock counter
Clock Counter Enable/Disable Setting Bit
XSTP
Description
0
1
Ordinary oscillation
Oscillator halt sensing
Oscillator Halt Sensing Bit
2.1-1 (ADJ)
The following operations are performed by setting the ADJ bit to 1.
After this bit is set to 1, the BSY bit is set to 1 for the maximum duration of 122.1µs.
If the WTEN bit is 0, these adjustment operations are started after the WTEN bit is set to 1.
1) For second digits ranging from “00” to “29” seconds:
Time counters smaller than seconds are reset and second digits are set to “00”.
2) For second digits ranging from “30” to “59” seconds:
Time counters smaller than seconds are reset and second digits are set to “00”. Minute digits are incremented by 1.
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RS5C321A/B
9
2.1-2 (BSY)
When the BSY bit is 1, the clock and calendar counter are being updated. Consequently, write operation should
be performed for the counters when the BSY bit is 0. Meanwhile, read operation is normally performed for the
counters when the BSY bit is 0, but can be performed without checking the BSY bit as long as appropriate software
is provided for preventing read errors. (Refer to 13. Typical Software-based Operations.) The BSY bit is set to 1 in
the following three cases:
2.1-3 (WTEN)
The WTEN bit should be set to 0 to check that the BSY bit is 0 when performing read and write operations for
the clock and calendar counters. For read operation, the WTEN bit may be left as 1 without checking the BSY bit as
long as appropriate measures such as read repetition are provided for preventing read errors. The WTEN bit
should be set to 1 after completing read and write operations, or will automatically be set to 1 by switching the CE
pin to the low level. If 1-second digit carry occurs when the WTEN bit is 0, a second digit increment by 1 occurs
when the WTEN bit is set to 1. There may be a possibility causing a time delay when it takes 1/1024 second or
more to set WTEN bit from 0 to 1, Read data in state of WTEN=1 in such a case. (Refer to the item 13.3)
2.1-4 (XSTP)
The XSTP bit senses the oscillator halt. When the CE pin is held at the low level, the XSTP bit is set to 1 once
the crystal oscillator is stopped after initial power-on or supply voltage drop and left to be 1 after it is restarted.
When the CE pin is held at the high level, the XSTP bit is left as it was when the CE pin was held at the low level
without checking oscillation stop. As such, the XSTP bit can be used to validate clock and calendar count data after
power-on or supply voltage drop. When the XSTP is set to 1, CLEN is set to 0 and 32.768kHz clock pulse is output
from 32KOUT pin. The XSTP bit is set to 0 when any data is written to the control register 1 (at Eh) with ordinary
oscillation.
MAX.122.1 µs
Setting of the
ADJ bit to 1
Completion of second
digit adjustment
(I) Adjustment of second digits
by ±30 second
(II) Second digits increment by 1
(Subject to 1-sec digit carry when
the WTEN bit is switched from 0 to 1)
(III) Ordinary 1-sec digit carry
MAX.91.6 µs
Setting of the
WTEN bit to 1
End of second digit
increment by 1
91.6 µs
End of second digit carry pulse
Page 14
RS5C321A/B
10
2.2 Control Register 2 (at Fh)
D3 D2 D1 D0
12/24
0 BANK TEST
12/24 — BANK TEST
(For write operation)
(For read operation)
Bit for Testing
*
1
TEST
Description
0
1
Testing mode
Ordinary operation mode
BANK
Description
0
1
Clock/calendar counter
CLEN bit
Bank Selection Bit
*
2
12/24
Description
0
1
12-hour time display system (separate for mornings and afternoons)
24-hour time display system
12/24-hour Time Display System Selection Bit
*
3
*
1) (TEST) Set the TEST bit to 1 in ordinary operation. TEST bit is set automatically to 1 when the CE pin is “L”.
*
2) (BANK) There is no need to designate BANK bit for scratch register and Control register 1/2.
*
3) (12/24) The 12/24 bit specifies time digit display in BCD code.
Either the 12-hour or 24-hour time display system should be selected before time setting.
24-hour time display system 12-hour time display system 24-hour time display system 12-hour time display system
00 12 (AM12) 12 32 (PM12)
01 01 (AM 1) 13 21 (PM 1)
02 02 (AM 2) 14 22 (PM 2)
03 03 (AM 3) 15 23 (PM 3)
04 04 (AM 4) 16 24 (PM 4)
05 05 (AM 5) 17 25 (PM 5)
06 06 (AM 6) 18 26 (PM 6)
07 07 (AM 7) 19 27 (PM 7)
08 08 (AM 8) 20 28 (PM 8)
09 09 (AM 9) 21 29 (PM 9)
10 10 (AM10) 22 30 (PM10)
11 11 (AM11) 23 31 (PM11)
Page 15
RS5C321A/B
11
2.3 32kHz clock pulse Control Register (BANK1, at Ah)
D3 D2 D1 D0
* * *
CLEN
(For read/write operation)
*
1) The “*” mark indicates data which are set to 0 for read cycle and not written for write cycle.
*
2) (CLEN)
32kHz clock pulse control bit
When the CLEN bit is set to 0, 32.768kHz clock pulse is output from 32KOUT pin.
When the CLEN bit is set to 1, 32KOUT pin is high impedance.
The CLEN bit is set to 0 when the XSTP=1 (Oscillator halt sensing).
D3 D2 D1 D0
*
W4 W2 W1
(For read/write) Day-of-the-week counter
*
1) The “*” mark indicates data which are set to 0 for read cycle and not set for write cycle.
*
2) Day-of-the-week digits are incremented by 1 when carried to 1-day digits.
*
3) Day-of-the-week digits display (incremented in septimal notation):
(W
4, W2, W1)=(000) → (001) → ····· → (110) → (000)
The relation between days of the week and day-of-the-week digits is user changeable (e.g. Sunday=000).
*
4) The (W4, W2, W1) should not be set to (111).
3.2 Day-of-the-week counter (BANK 0, at 6h)
D3 D2 D1 D0
S8 S4 S2 S1
(For read/write) 1-second time digit (at 0h)
*
S40 S20 S10 (For read/write) 10-second time digit (at1h)
M8 M4 M2 M1 (For read/write) 1-minute time digit (at 2h)
*
M40 M20 M10 (For read/write) 10-minute time digit (at3h)
H8 H4 H2 H1
(For read/write) 1-hour time digit (at4h)
* *
P/A or H20 H10
(For read/write) 10-hour time digit (at5h)
3. Counters
3.1 Clock counter (BANK 0, at 0h-5h)
*
1) The “*” mark indicates data which are set to 0 for read cycle and not set for write cycle.
*
2) Any carry to 1-second digits from the second counter is disabled when the WTEN bit (of the control register 1) is set to 0.
*
3) Time digit display (BCD code):
Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00.
Minute digits : Range from 00 to 59 and carried to hour digits when incremented from 59 to 00.
Hour digits : Range as shown in the section on the 12/24 bit and carried to day and day-of-the-week digits when incremented from 11 p.m. to 12
a.m. or 23 to 00.
*
4) Any registered imaginary time should be replaced with actual time as carrying to such registered imaginary time digits from lower-order ones cause
the clock counter to malfunction.
Page 16
RS5C321A/B
12
D3 D2 D1 D0
D8 D4 D2 D1 (For read/write) 1-day calendar digit (at8h)
* *
D20 D10 (For read/write) 10-day calendar digit (at9h)
MO8 MO4 MO2 MO1
(For read/write) 1-month calendar digit (atAh)
* * *
MO10 (For read/write) 10-month calendar digit (atBh)
Y8 Y4 Y2 Y1 (For read/write) 1-year calendar digit (atCh)
Y
80 Y40 Y20 Y10 (For read/write) 10-year calendar digit (atDh)
3.3 Calendar counter (BANK 0, at 8h-Dh)
*
1) The “*” mark indicates data which are set to 0 for read cycle and not set for write cycle.
*
2) The automatic calendar function provides the following calendar digit displays in BCD code.
Day digits : Range from 1 to 31 (for January, March, May, July, August, October, and December).
Range from 1 to 30 (for April, June, September, and November).
Range from 1 to 29 (for February in leap years).
Range from 1 to 28 (for February in ordinary years).
Carried to month digits when cycled to 1.
Month digits: Range from 1 to 12 and carried to year digits when cycled to 1.
Year digits : Range from 00 to 99 and counted as 00, 04, 08, ..., 92, and 96 in leap years.
*
3) Any registered imaginary time should be replaced with actual time as carrying to such registered imaginary time digits from lower-order ones cause
the clock counter to malfunction.
Page 17
RS5C321A/B
13
USAGES
1. Read Data (For the RS5C321A)
The real-time clock becomes accessible by switching the CE pin from the low level to high level to enable interfacing with the CPU and then inputting setting data (control bits and address bits) to the SIO pin in synchronization
with shift clock pulses from the SCLK pin. The input data are registered in synchronization with the falling edge of
the SCLK. When the data is read, the read cycle shall be set by control bits then registered data can be read out
from SIO pin in synchronization with the rising edge of the SCLK.
• Control bits R/W: Establishes the read mode when set to 1, and the write mode when set to 0.
AD: Writes succeeding addressing bits (A3-A0) to the address register when set to 1 with the
DT bit set to 0 and performs no such write operation in any other case.
DT: Writes data bits to counter or register specified by the address register set just before
when set to 1 with the R/W and AD bits set equally to 0 and performs no such write operation in any other case.
• Address bits A3-A0: Inputs the bits MSB to LSB in the address table describing the functions.
1.1 Read Cycle Flow
1. The CE pin is switched from “L” to “H”.
2. Four control bits (with the first bit ignored) and four read address bits are input from the SIO pin. At this time,
control bits R/W and AD are set equally to 1 while a control bit DT is set to 0. (see the SCLK 1A-8A)
3. The SIO pin enters the output mode at the rising edge of the shift clock pulse 2B from the SCLK pin while the
four read bits (MSB → LSB) at designated addresses are output at the rising edge of the shift clock pulse 5B.
(see the figure below)
4. Then, the SIO pin returns to the input mode at the rising edge of the shift clock pulse 1C. Afterwards control bits
and address bits are input at the shift clock pulses 1C in the same manner as at the shift clock pulse 1A.
5. At the end of read cycle, the CE pin is switched from “H” to “L” (after
tCEH from the falling edge of the eighth
shift clock pulse from the SCLK pin). Following on read cycle, write operation can be performed by setting con-
trol bits in the write mode at the shift clock pulse 1C and later with the CE pin held at “H”.
1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C
R/W
AD DT A3 A2 A1 A0
– – – D3 D2 D1 D0
R/W
AD
* *
CE
SCLK
Input to
SIO pin
Output
from SIO
pin
Writing to shift
register
Writing to address
register
Setting of
control bits
Control bits
(Hiz) (Hiz)
(Hiz)
Read data
Setting of SIO
pin in output
mode
Shifting data Setting of SIO
pin in input
mode
(Internal processing)
Address bits
*
) In the above figure, the “*” mark indicates arbitrary data; the “–” mark indicates unknown data.
The “ ” mark indicates data which are available when the SIO pin is held at “H”, “L”, or Hiz level.
The diagonally shaded area of the CE and the SCLK pins indicate “H” or “L”.
Page 18
RS5C321A/B
14
2. Write Data (For the RS5C321A)
Writing data to the real-time clock requires inputting setting data (control bits, address bits and data bits) to the
SIO pin and then establishing the write mode by using a control bit R/W in the same manner as in read operation.
• Data bits D3-D0: Inputs the data bits MSB to LSB in the addressing table describing the functions.
2.1 Write Cycle Flow
1. The CE pin is switched from “L” to “H”.
2. Four control bits (with the first bit ignored) and four write address bits are input from the SIO pin. At this time,
control bits R/W and DT are set equally to 0 while a control bit AD is set to 1. (see the SCLK 1A-8A)
3. Four control bits and four bits of data to be written are input in the descending order of their significance.
At this time, control bits R/W and AD are set equally to 0 while a control bit DT is set to 1. (see the clock 1B-8B)
4. When write cycle is continued, control bits and address bits are input at the shift clock pulse 1C and later in the
same manner as at the shift clock pulse 1A.
5. At the end of write operation, control bits R/W, AD, and DT are set equally to 0 (at the falling edge of shift clock
pulse 5A and later from the SCLK pin) or the CE pin is switched from “H” to “L” (after
tCEH from the falling edge
of the eighth shift clock pulse from the SCLK pin). Following on write cycle, read operation can be performed by
setting control bits in the read mode at the shift clock pulse 1C and later with the CE pin held at “H”.
1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C
R/W
AD DT A3 A2 A1 A0
R/W AD DT D3 D2 D1 D0
R/W
AD
* * *
*
CE
(Internal processing)
SCLK
Input to
SIO pin
Output
from
SIO pin
Writing to shift
register
Writing to address
register
Setting of
control bits
End of write
operation
Setting of
control bits
Control bits Address bits
Control bits Data bits
(Hiz) (Hiz)
*
) In the above figure, the “*” mark indicates arbitrary data; and the diagonally shaded area of CE and SCLK indicates “H” or “L”.
*
) Control bits and address bits are described in the previous section on read cycle.
Page 19
RS5C321A/B
15
3. Read Data (For the RS5C321B)
The real-time clock becomes accessible by switching the CE pin from the low level to high level to enable interfacing with the CPU and then inputting setting data (control bits and address bits) to the SIO pin in synchronization
with shift clock pulses from the SCLK pin. The input data are registered in synchronization with the rising edge of
the SCLK. When the data is read, the read cycle shall be set by control bits then registered data can be read out
from SIO pin in synchronization with the falling edge of the SCLK.
• Control bits R/W: Establishes the read mode when set to 1, and the write mode when set to 0.
AD: Writes succeeding addressing bits (A3-A0) to the address register when set to 1 with the
DT bit set to 0 and performs no such write operation in any other case.
DT: Writes data bits to counter or register specified by the address register set just before
when set to 1 with the R/W and AD bits set equally to 0 and performs no such write operation in any other case.
• Address bits A3-A0: Inputs the bits MSB to LSB in the address table describing the functions.
3.1 Read Cycle Flow
1. The CE pin is switched from “L” to “H”.
2. Four control bits (with the first bit ignored) and four read address bits are input from the SIO pin. At this time,
control bits R/W and AD are set equally to 1 while a control bit DT is set to 0. (see the SCLK 1A-8A)
3. The SIO pin enters the output mode at the falling edge of the shift clock pulse 2B from the SCLK pin while the
four read bits (MSB → LSB) at designated addresses are output at the falling edge of the shift clock pulse 5B.
(see the figure below)
4. Then, the SIO pin returns to the input mode at the falling edge of the shift clock pulse 1C. Afterwards control
bits and address bits are input at the shift clock pulses 1C in the same manner as at the shift clock pulse 1A.
5. At the end of read cycle, the CE pin is switched from “H” to “L” (after
tCEH from the rising edge of the eighth
shift clock pulse from the SCLK pin). Following on read cycle, write operation can be performed by setting con-
trol bits in the write mode at the shift clock pulse 1C and later with the CE pin held at “H”.
1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C
R/W
AD DT A3 A2 A1 A0
– – – D3 D2 D1 D0
R/W
AD
*
*
CE
SCLK
Input to
SIO pin
Output
from SIO
pin
Writing to shift
register
Writing to address
register
Setting of
control bits
Control bits Address bits
(Hiz) (Hiz)
(Hiz)
Read data
(Internal processing)
Shifting data Setting of SIO
pin in input
mode
Setting of SIO
pin in output
mode
*
) In the above figure, the “*” mark indicates arbitrary data; the “–” mark indicates unknown data.
The “ ” mark indicates data which are available when the SIO pin is held at “H”, “L”, or Hiz level.
The diagonally shaded area of the CE and the SCLK pins indicate “H” or “L”.
Page 20
RS5C321A/B
16
4. Write Data (For the RS5C321B)
Writing data to the real-time clock requires inputting setting data (control bits, address bits and data bits) to the
SIO pin and then establishing the write mode by using a control bit R/W in the same manner as in read operation.
• Data bits D3-D0: Inputs the data bits MSB to LSB in the addressing table describing the functions
4.1 Write Cycle Flow
1. The CE pin is switched from “L” to “H”.
2. Four control bits (with the first bit ignored) and four write address bits are input from the SIO pin. At this time,
control bits R/W and DT are set equally to 0 while a control bit AD is set to 1. (see the SCLK 1A-8A)
3. Four control bits and four bits of data to be written are input in the descending order of their significance.
At this time, control bits R/W and AD are set equally to 0 while a control bit DT is set to 1. (see the SCLK 1B-8B)
4. When write cycle is continued, control bits and address bits are input at the shift clock pulse 1C and later in the
same manner as at the shift clock pulse 1A.
5. At the end of write operation, control bits R/W, AD, and DT are set equally to 0 (at the rising edge of shift clock
pulse 5A and later from the SCLK pin) or the CE pin is switched from “H” to “L” (after t
CEH from the rising edge
of the eighth shift clock pulse from the SCLK pin). Following on write cycle, read operation can be performed by
setting control bits in the read mode at the shift clock pulse 1C and later with the CE pin held at “H”.
R/W
AD DT A3 A2 A1 A0
R/W AD DT D3 D2 D1 D0
R/W
AD
* * *
*
CE
(Internal process)
SCLK
Input to
SIO pin
Output
from SIO
pin
Writing to shift
register
Writing to address
register
Setting of
control bits
End of write
operation
Setting of
control bits
Control bits Address bits
Control bits Data bits
(Hiz) (Hiz)
1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C
*
) In the above figure, the “*” mark indicates arbitrary data; and the diagonally shaded area of CE and SCLK indicates “H” or “L”.
*
) Control bits and address bits are described in the previous section on read cycle.
Page 21
RS5C321A/B
17
5. CE Pin
1) Switching the CE pin to the high level enables the SCLK/SCLK and SIO pins, allowing data to be serially read
from and written to the SIO pin in synchronization with shift clock pulses input from the SCLK/SCLK pin.
2) Switching the CE pin to the low level or opening disables the SCLK/SCLK and SIO pins, causing high impedance and resetting the internal interfacing circuits such as the shift register. While data of the address register
and bank bit which have been written just before should be preserved.
3) The CE pin should be held at the low level or open state when no access is made to the RS5C321A/B.
The CE pin incorporates a pull-down resistor.
4) During system power-down (being back-up battery powered), the low-level input of the CE pin should be brought
as close as possible to the VSS level to minimize the loss of charge in the battery.
5) The CE pin should be held at the low level in order to be enable oscillator halt sensing. Holding the CE pin at
the high level, therefore, disables oscillator halt sensing, retaining the value of the XSTP (oscillator halt sensing)
bit which exists immediately before the CE pin is switched to the high level.
*
) RS5C321A: SCLK
RS5C321B: SCLK
Considerations
When the power turns on from 0V, the CE pin should be set low or open once.
SCLK/SCLK
*
SIO
CE
Shift clock pulses
Address Data
Write Data
Read Data
Read control bit
Control bit
Page 22
RS5C321A/B
18
1) When applying an external input of clock pulses (32.768kHz) to the OSCIN pin:
DC coupling ............Prohibited due to mismatching input levels.
AC coupling.............Permissible except that unpredictable results may occur in oscillator halt sensing due
to possible sensing errors caused by noises, etc.
2) Avoid using the oscillator output of the RS5C321A/B (from the OSCOUT pin) to drive any other IC for the
purpose of ensuring stable oscillation.
1) Mount the crystal oscillators and C
G in the closest possible position to the IC.
2) Avoid laying any signal or power line close to the oscillation circuit (particularly in the area marked with
“← A →” in the above figure).
3) Apply the highest possible insulation resistance between the OSCIN or OSCOUT pin and the PCB.
4) Avoid using any long parallel line to wire the OSCIN or OSCOUT pin.
5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt.
6. Configuration of Oscillating Circuit
RF
RD
CD
OSCIN
OSCOUT
32.768kHz
V
DD
VDD
CG
VSS
A
Typical external device:
X'tal : 32.768kHz
(R
1=30kΩ TYP.)
(C
L=6pF to 8pF)
C
G=8pF to 20pF
Typical values of internal devices
R
F=15MΩ (TYP.)
R
D=60kΩ (TYP.)
C
D=10pF (TYP.)
Considerations in Mounting Components Surrounding Oscillating Circuit
Other Relevant Considerations
*
) The oscillation circuit is driven at a constant voltage of about 1.5V relative to the Vss level.
Consequently, it generates a wave form having a peak-to-peak amplitude of about 1.5V on the positive side of the Vss level.
Page 23
RS5C321A/B
19
Considerations in Use of XSTP Bit
7. Oscillator Halt Sensing
Oscillation Halt can be sensed through monitoring the XSTP bit with preceding setting of the XSTP bit to 0 by
writing any data to the control register 1. Upon oscillator halt sensing, the XSTP bit is switched from 0 to 1. This
function can be applied to judge clock data validity. The CLEN bit is set to 0 when XSTP=1, and 32KOUT pin is
forced to output 32.768kHz clock pulses.
*
1) While the CE pin is held at the low level, the XSTP bit is set to 1 upon power-on from 0V.
Note that any instantaneous power disconnection may cause operational failure. When the CE pin is held at the high level, oscillation halt is not
sensed and the value of the XSTP bit when the CE pin is held at the low level is retained.
*
2) Once oscillation halt has been sensed, the XSTP bit is held at 1 even if oscillation is restarted.
Ensure error-free oscillation halt sensing by preventing the following:
1) Instantaneous disconnection of VDD
2) Condensation on the crystal oscillator
3) Generation of noise on the PCB in the crystal oscillator
4) Application of voltage exceeding prescribed maximum ratings to the individual pins of the IC
Power-on from 0V
*
1
XSTP
Oscillation haltWriting of data to
control register 1
(in the presence of oscillation)
Oscillation restart
*
2
Page 24
RS5C321A/B
20
8. Typical Power Supply Circuit
1) Connect the capacitance of the oscillation circuit to the Vss pin.
2) Mount the high-and low-frequency by-pass capacitors in parallel and very close to the RS5C321.
3) Connect the pull-up resistor of the 32KOUT pin to two different positions depending on whether the resistor is in use during battery back-up.
• When not in use during battery back-up
...........Position A in the left figure
• When in use during battery back-up
...........Position B in the left figure
4) Timing of power-on, power-off and CE pin refer to following figure.
5) When a diode are in use in place of the components surrounded by dotted lines, note that applying voltage to any input pins
should be less than the rating of V
DD +0.3V by using of schot-
tky diode.
OSCIN
OSCOUT
VDD
RS5C321
VSS
B
A
System
supply
voltage
32KOUT
C
0V
VDD
CE
D
0.2V
DD
MIN. 0µs MIN. 0µs MIN. 0µs
C, D, E: Minimum operating voltage for CPU
0.2V
DD 0.2VDD
Battery voltage
System supply voltage
E
9. Oscillation Frequency Adjustment
9.1 Oscillation Frequency Measurement
1) After initial power-on (XSTP=1), 32KOUT pin outputs
32.768kHz clock pulse, which is measured with a frequency counter.
2) Ensure that the frequency counter has more than six
digits (on the order of 1 ppm).
3) Place the C
G between the OSCIN pin and the VSS lev-
el and pull up the 32KOUT pin output to the VDD.
32KOUT
OSCOUT
OSCIN
VDD
CE
VSS
32.768kHz
+5V or +3V
Frequency
counter
C
G
Page 25
RS5C321A/B
21
Any rise or fall in ambient temperature from its reference value ranging from 20 to 25 degrees Celsius causes
a time delay for a 32.768kHz crystal oscillator. It is recommendable, therefore, to set slightly high oscillation
frequency at room temperature.
9.2 Oscillation Frequency Adjustment
After adjustment, oscillation frequency is subject to fluctuations of an ambient temperature and supply voltage. See
“12. Typical Characteristic Measurements”.
Select crystal oscillator
NO
OK
OK
NO
Fix CG
(For fixed capacitance) (For variable capacitance)
Change C
L
value of crystal
Optimize CG
END
END
Fix the capacitance of CG
Optimize central
variable capacitance value
Make fine frequency adjustment
with variable capacitance.
Change CL
value of crystal
*
1
*
3
*
3
*
2
*
1) To ensure that the crystal is matched to the IC, inquire its crystal supplier about its CL (load capacitance) and R1 (equivalent series resistance) values.
It is recommended that the crystal should have the C
L value range of 6 to 8pF and the typical R1 value of 30kΩ.
*
2) To allow for the possible effects of floating capacitance, select the optimum capacitance of the CG on the mounted PCB. The standard and recommendable capacitance values of the C
G range from 5 to 24pF and 8 to 20pF, respectively. When you need to change the frequency to get higher
accuracy, change the C
L value of the crystal.
*
3) Collate the central variable capacitance value of the CG with its oscillation frequency by adjusting the angle of rotation of the variable capacitance of
the C
G in such a manner that the actual variable capacitance value is slightly smaller than the central variable capacitance value. (It is recommended
that the central variable capacitance value should be slightly less than one half of the actual variable capacitance value because the smaller is variable capacitance, the greater are fluctuations in oscillation frequency.) In the case of an excessive deviation of the oscillation frequency from its
required value, change the C
L value of the crystal.
Note
Page 26
RS5C321A/B
22
11. Typical Application
*
1) Connect the capacitance of the oscillation circuit to the VSS pin.
*
2) Mount the high-and low-frequency by-pass capacitors in parallel and very close to the RS5C321.
*
3) Connect the pull-up resistor of the 32KOUT pin to two different positions depending on whether the resistor is in use during battery back-up:
(I) When not in use during battery back-up.............Position A in the above figure
(II) When in use during battery back-up...................Position B in the above figure
*
4) When using a “D” circuit in place of “C”, note that forward voltage of diode should be minimized to eliminate applying excess voltage to input pins.
(Take the utmost care on system powering-ON and-OFF).
VCC
VSS
OSCIN
OSCOUT
VDD
VSS
32KOUT
CE
SCLK/SCLK
SIO
CPU RS5C321A/B
System power
supply
B A
System power supply
VDD
D
C
or
System
power
supply
10. 32.768kHz Clock Output
32KOUT outputs 32.768kHz clock pulse, the pin switches to high impedance when no output is made. 32.768kHz
clock is controllable by CLEN bit. Set the CE pin to “L” after power-on.
CLEN bit 32KOUT pin
0 32.768kHz clock pulse
1 High Inpedance
CLEN bit is set to 0 when XSTP is set to 1. (oscillation halt detecting or initial power on)
MAX. 61.0µs
CLEN bit
32KOUT pin
MAX. 91.6µs
Page 27
RS5C321A/B
23
12. Typical Characteristic Measurements
12.3 Operational Current vs. SCLK/SCLK Frequency
12.1 Standby Current vs. C
G 12.2 Standby Current vs. VDD
12.4 Standby Current vs. Temperature
Standby Current IDD (µA)
Topt = 25°C
C
G (pF)
0
0.0
1.0
2.0
10 155 20 25 30
VDD = 5V
VDD = 3V
32K output off
32K output on
Standby Current IDD (µA)
Topt=25°C, 32KOUT=Open
V
DD (V)
0
0.0
1.0
2.0
2 4 6
VDD = 3V
VDD = 5V
Operational Current IOPR (mA)
Topt = 25°C
SCLK/SCLK Frequency (MHz)
0.01
0.001
0.01
0.1
1
0.1 1 10
Standby Current IDD (µA)
32KOUT=Open
Temperature Topt (°C)
–60 –40 –20
0.0
1.0
2.0
0 20 40 60 80 100
VDD =3V,32K output on
VDD=6V,32K output off
VDD=3V,32K output off
CG=10pF
X'tal : R
1=30kΩ
Topt=25˚C
Input Pin : VDD or VSS
Output Pin : Open
OSCIN
OSCOUT
32KOUT
VSS
VDD
A
C
G
X'tal
V
DD
Frequency counter
Page 28
RS5C321A/B
24
12.7 Oscillation Frequency Deviation
vs. Temperature (f0: Topt=25°C reference)
12.5 Oscillation Frequency Deviation vs. C
G
(f0: CG=10pF reference)
12.6 Oscillation Frequency Deviation vs. V
DD
(f0: VDD=4V reference)
12.8 Oscillation Start Time vs. V
DD
Oscillation Frequency Deviation
∆f/f0 (ppm)
VDD = 3V, Topt = 25°C
C
G (pF)
0
–40
–20
0
20
40
60
80
10 155 20 25 30
Oscillation Frequency Deviation
∆f/f0 (ppm)
CG = 10pF, Topt = 25°C
V
DD (V)
0
–4
–3
–2
–1
0
1
2 31 4 5 6
Oscillation Frequency Deviation
∆f/f0 (ppm)
VDD = 3V, CG = 10pF
Temperature Topt (°C)
–40
–80
–70
–60
–50
–40
–30
–20
–10
0
10
0 20–20 40 60 10080
CG = 20pF
CG = 10pF
Oscillation Start Time (s)
Topt = 25°C
V
DD (V)
0
0.0
0.5
1.0
2 31 4 5 6
12.9 VDS vs. IDS for Nch Open Drain Output
VDD = 3V
VDD = 5V
Nch Open Drain Output
I
DS (mA)
Topt = 25°C
V
DS (V)
0.0
0
10
20
30
40
50
1.0 1.50.5 2.0
Page 29
RS5C321A/B
25
Ensure stable oscillation by preventing the following:
1) Condensation on the crystal oscillator
2) Instantaneous disconnection of power
3) Generation of clock noises, etc, in the crystal
oscillator
4) Charge of voltage exceeding prescribed maximum ratings to the individual pins of the IC
13. Typical Software-based Operations
13.1 Initialization upon Power-on
13.2 Write Operation to Clock and Calendar Counters
Start
XSTP=0?
BSY=0?
Control register 2←3h
(BANK←1)
32kHz clock pulse control
register←1h
(
CLEN
=1)
Control register 1←3h
Control register 2←1h, 9h
Set clock and calendar
counters and interrupt cycles.
Wait or
other
operations.
Power-on
YES
NO
YES
NO
*
1
*
2
*
3
*
4
*
6
*
5
BSY=0?
Write to clock and
calendar
counters.
CE=L
Wait or
other
operations.
CE=L
Control register 1←0h
CE=H
YES
NO
*
1
*
2
*
3
*
4
*
1) Switch the CE pin to the low level immediately after power-on.
*
2) When not making oscillation halt sensing (data validity), the XSTP bit
need not be checked.
*
3) On powering on from 0V, 32KOUT pin outputs 32.768kHz clock pulses.
Set CLEN
←1 when turning 32.768kHz off during initialization.
*
4) Set the ADJ bit to 1. When writing control register 1, if the oscillator has
operated, the XSTP bit is changed from 1 to 0.
*
5) It takes about 0.1 to 2 seconds to be set the BSY bit to 0 from oscillation
starting upon power-on from 0V. Provide an exit from an oscillation start
loop to prepare for oscillation failure.
*
6) Set the XSTP bit to 0 by writing data to the control register 1, and set to
the control register 2,
0h for the 12-hour time display system.
4h for the 24-hour time display system.
*
1) After switching the CE pin to the high level, hold it at the high level until
any subsequent operation requires switching it to the low level. (Note
that switching the CE pin to the low level sets the WTEN bit to 1.)
*
2) WTEN bit is set to 0.
*
3) The BSY bit is held at 1 for a maximum duration of 122.1µs.
*
4) Switch the CE pin to the low level to set the WTEN bit to 1. During write
operation to the clock and calendar counters, one 1-second digit carry
causes a 1-second increment while two 1-second digit carries also cause
only a 1-seconds increment, which, in turn, causes a time delay.
When Using the XSTP Bit
Page 30
RS5C321A/B
26
Note
13.3 Read Operation from Clock and Calendar Counters
13.3-1 13.3-2
BSY=0?
Read from clock and
calendar
counters.
CE=L
Wait or
other
operations.
CE=L
Control register 1←0h
CE=H
YES
NO
*
1
*
2
*
3
*
4
Read from clock and
calendar
counters.
Again read 1-second
digit of clock
counter.
Two 1-second
digit
readings
match?
Read 1-second
digit of clock
counter.
NO
YES
*
5
*
5
*
5
Read data as described in 13.3-2 when it takes (1/1024) sec or more to set the WTEN bit from 0 to 1 (CE=L),
the read operation described in 13.3-1 is prohibited as such a case.
*
1) to *4) These notes are the same as 13.2 notes *1) to *4).
*
5) When needing any higher-order digits than the minute digits, replace
second digits with minute digits. (Reading LSD one of the required digits
twice.)
Page 31
RS5C321A/B
27
Control register 1←3h
*
1
XSTP=0?
Oscillation start
Wait or
other
operations.
Power-on
Control register 1←2h
YES
NO
*
1
*
2
13.4 Second-digit Adjustment by ±30 seconds
*
1) Set the ADJ bit to 1.
(The BSY bit is held at 1 for a maximum duration of 122.1µs after the
ADJ bit is set to 1.)
13.5 Oscillation Start Judgment
*
1) The XSTP bit is set to 1 upon power-on from 0V.
*
2) It takes approximately 0.1 to 2 seconds to start oscillation. Provide an
exit from an oscillation start loop to prepare for oscillation failure.
Ensure stable oscillation by preventing the following:
1) Condensation on the crystal oscillator
2) Instantaneous disconnection of power
3) Generation of clock noises, etc, in the crystal
oscillator
4) Charge of voltage exceeding prescribed maximum ratings to the individual pins of the IC
When Using the XSTP Bit
Page 32
RS5C321A/B
28
0.15
+0.1
-
0.05
0.5±0.3
0° to 10°
0.1±0.1
0.15
0.1
M
0.22±0.1
1.15±0.1
0.775TYP.
0.65
1
4
6.4±0.3
4.4±0.2
8
5
3.5±0.3
0.3
2.7 MAX.
4.0±0.1
2.0±0.05
8.0±0.1
1.75
±
0.1
5.5±0.05
3.9
6.7
12.0±0.3
User Direction of Feed.
ø1.5
+0.1
–0
PACKAGE DIMENSIONS(Unit: mm)
TAPING SPECIFICATION (Unit: mm)
• RS5C321A/B (8pin SSOP, 0.65mm pitch)
The RS5C321A/B have one designated taping direction. The product designations for the taping components are
“RS5C321A-E2” and “RS5C321B-E2”.
Page 33
RICOH COMPANY, LTD.
ELECTRONIC DEVICES DIVISION
HEADQUARTERS
13-1, Himemuro-cho, Ikeda City, Osaka 563-8501, JAPAN
Phone +81-727-53-6003 Fax +81-727-53-2120
YOKOHAMA OFFICE (International Sales)
3-2-3, Shin-Yokohama, Kohoku-ku, Yokohama City, Kanagawa 222-8530,
JAPAN
Phone +81-45-477-1697 Fax +81-45-477-1694 · 1695
http://www.ricoh.co.jp/LSI/english/
RICOH CORPORATION
ELECTRONIC DEVICES DIVISION
SAN JOSE OFFICE
1996 Lundy Avenue, San Jose, CA 95131, U.S.A.
Phone +1-408-944-3306 Fax +1-408-432-8375
http://www.ricoh-usa.com/semicond.htm
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