Datasheet RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Datasheet (Intersil)

RFD12N06RLE, RFD12N06RLESM,

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j

/

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RFP12N06RLE

July 1999 File Number 2407.4Data Sheet

[ /Title
(RFD1
2N06R
LE,
RFD12
N06RL
ESM,
RFP12
N06RL
E)

Sub-

ect
(12A,
60V,

0.135
Ohm,
N­Chan­nel,
Logic
Level,
Power
MOS­FETs)

Autho
r ()

Key­words
(Inter­sil
Corpo­ration,
N­Chan­nel,
Logic
Level,
Power
MOS-

12A, 60V, 0.135 Ohm, N-Channel, Logic
Level, Power MOSFETs

These N-Channel logic level ESD protected power
MOSFETs are manufactured using the MegaFET process.
This process, which uses featuresizesapproachingthoseof
LSI integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. They were designed
for use with logic level (5V) driving sources in applications
such as programmable controllers, automotive switching,
switching regulators, switching converters, motor drivers,
relay drivers, and emitter switches for bipolar transistors.
This performance is accomplished through a special gate
oxide design which provides full rated conductance at gate
biases in the 3V to 5V range, thereby facilitating true on-off
power control directly from logic circuit supply voltages.

Formerly developmental type TA09861.

Ordering Information

PART NUMBER PACKAGE BRAND

RFD12N06RLE TO-251AA 12N6LE
RFD12N06RLESM TO-252AA 12N6LE
RFP12N06RLE TO-220AB 12N06RLE

NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain theTO-252AAvariant in tape and reel, i.e., RFD12N06RLESM9A.

Packaging

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

(FLANGE)

DRAIN

GATE

DRAIN (FLANGE)

JEDEC TO-220AB

Features

• 12A, 60V

•r

• Electrostatic Discharge Protected

• UIS Rating Curve (Single Pulse)

• Design Optimized for 5V Gate Drive

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

= 0.135Ω

DS(ON)

Components to PC Boards”

Symbol

D

G

S

DRAIN

GATE

SOURCE

SOURCE

DRAIN

GATE

(FLANGE)

6-12

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFD12N06RLE,

RFD12N06RLESM,

RFP12N06RLE UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

D

DM

GS

D

60 V
60 V
12

26

-5 to10 V
40 W

A
A

Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.32 W/oC

Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E

AS

Electrostatic Discharge Rating ESD, MIL-STD-883, Category B(2)

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ,T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

Refer to UIS SOA Curve

2kV

-55 to 150

300
260

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V
Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

DSSID

GS(TH)VGS

DSS

GSS

= 250µA, VGS = 0V 60 - - V

= VDS, ID = 250µA1-2V
VDS = Rated BV
VDS= 0.8 x Rated BV

, VGS = 0V - - 1 µA

DSS

DSS,VGS

= 0V, TC= 150oC- - 25 µA

VGS = -5 to 10V - - ±10 µA

= 12A, VGS = 5V (Figures 7, 8) - - 0.135 Ω

ID = 12A, VGS = 4V - - 0.160 Ω

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

(OFF)
g(TOT)VGS

Gate Charge at 5V Q
Threshold Gate Charge Q
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

(ON)

g(TH)VGS

VDD = 30V, I
VGS= 5V, (Figures 15, 16)

r

≈ 6A, R

D

= 5Ω, RGS = 6.25Ω,

L

- - 60 ns

-12- ns

-20- ns

-24- ns

f

-12- ns

- - 60 ns

= 0V to 10V VDD = 48V, ID = 12A,
VGS = 0V to 5V - - 20 nC

g(5)

= 0V to 1V - - 1.5 nC

θJC

TO-251AA and TO-252AA - - 100

θJA

RL = 4Ω,
I

= 0.25mA

G(REF)

(Figures 17, 18)

- - 40 nC

- - 3.125oC/W

TO-220AB - - 62

o
o

C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V

SD

Reverse Recovery Time t

NOTES:

2. Pulse test: pulse width ≤ 300ms, duty cycle ≤ 2%.

3. Repetitive rating: pulse width is limited by maximum junction temperature.

6-13

ISD = 12A - - 1.2 V
ISD = 12A, dISD/dt = 100A/µs - - 200 ns

rr

RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

125

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

100

TJ = MAX RATED

= 25oC

T

C

ID MAX CONTINUOUS

10

DC OPERATION

OPERATION IN THIS
AREA MAY BE LIMITED

1

BY r

, DRAIN CURRENT, (A)

D

I

DS(ON)

15

10

5

, DRAIN CURRENT (A)

D

I

0

25 75 125

50 100

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

100

If R = 0
t

= (L)(Ias) / (1.3 RATED BV

av

If R ≠ 0
t

= (L/R) In ((Ias x R) / (1.3 RATED BV

av

Idm

10

, AVALANCHE CURRENT (A)

AS

I

- VDD)

DSS

- VDD) + 1)

DSS

STARTING TJ = 25oC
STARTING T

= 150oC

J

150

0.1
1 10 100

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

1

0.01 0.1 1 10
t

, TIME IN AVALANCHE (ms)

AV

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 3. FORWARD BIAS SAFE OPERATING AREA

FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

30

VGS = 10V

20

10

, DRAIN CURRENT (A)

D

I

0

0 1.5 3 4.5 6 7.5

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

VGS = 5V

VGS = 4V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 25oC

T

C

VGS = 3V

VGS = 2V

30

PULSE DURATION = 80µs
DUTY CYCLE = 0.5 % MAX
VDS = 15V

20

10

, DRAIN TO SOURCE CURRENT (A)

DS(ON)

I

0

0 1.5 3 4.5 6 7.5

V

GS

-55oC

, GATE TO SOURCE VOLTAGE (V)

FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS

25oC

150oC

6-14

RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE

Typical Performance Curves

1.4
VDS = 15V, ID = 12A

PULSE DURATION = 80µs

1.3
DUTY CYCLE = 0.5% MAX

1.2

1.1

1.0

0.9

0.8

ON RESISTANCE

0.7

NORMALIZED DRAIN TO SOURCE

0.6

4.0 4.5 5.0 5.5 6.0 6.5 7.0

FIGURE 7. NORMALIZED DRAIN TO SOURCE ON

1.4
VGS = VDS, ID = 250µA

1.3

1.2

VGS, GATE TO SOURCE VOLTAGE (V)

RESISTANCE vs GATE TO SOURCE VOLTAGE

Unless Otherwise Specified (Continued)

2.5

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-50 0 50

FIGURE 8. NORMALIZED DRAIN TO SOURCE ON

1.4

1.3

1.2

ID = 12A, VGS = 5V
PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

100

, JUNCTION TEMPERATURE (oC)

T

J

RESISTANCE vs JUNCTION TEMPERATURE

ID = 250µA

150 200

1.1

1.0

0.9

0.8

0.7

0.6

NORMALIZED GATE THRESHOLD VOLTAGE

-50 0 50 100 150 200
, JUNCTION TEMPERATURE (oC)

T

J

FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

1500

1250

1000

750

500

C, CAPACITANCE (pF)

250

0

01020

515

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

C

C

ISS

OSS

RSS

VGS = 0V, f = 1MHz
C

= CGS + C
C
C

ISS
RSS
OSS

= C

≈ CDS + C

GD

GD

GD

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

1.1

1.0

0.9

0.8

BREAKDOWN VOLTAGE

0.7

NORMALIZED DRAIN TO SOURCE

0.6

-50 0 50 100 150 200
T

, JUNCTION TEMPERATURE (oC)

J

FIGURE 10. NORMALIZED DRAIN TOSOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

60

PLATEAU VOLTAGES IN
DESCENDING ORDER:

= BV

V

DD

SOURCE

VOLTAGE

RL = 5.0Ω

G(REF)

V

DSS

GATE

= 0.25mA

= 5V

GS

DSS
DSS

DSS

I

G(REF)

80t, TIME (µs)

I

G(ACT)

45

30

15

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

25

0

I

G(REF)

20

I

G(ACT)

VDD = 0.75 BV
VDD = 0.50 BV
VDD = 0.25BV

I

DRAIN SOURCE VOLTAGE

10

5

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 12. NORMALIZED SWITCHING WAVEFORMSFOR

CONSTANT GATE CURRENT

6-15

RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY tP TO OBTAIN
REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS

t

P

I

AS

t

AV

V

DS

V

DD

t

ON

t

d(ON)

90%

10%

t

r

R

L

V

DS

V

GS

V

GS

+

-

V

DS

0

t

d(OFF)

0V

R

GS

DUT

V

GS

10%

0

50%

PULSE WIDTH

90%

FIGURE 15. SWITCHING TIME TEST CIRCUIT FIGURE 16. RESISTIVE SWITCHING WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

VGS= 1V

0

Q

g(TOT)

V

DS

Q

g(5)

V

GS

Q

g(TH)

VGS= 5V

t

OFF

50%

t

f

10%

VGS= 10V

90%

I

g(REF)

0

FIGURE 17. GATE CHARGE TEST CIRCUIT FIGURE 18. GATE CHARGE WAVEFORMS

6-16

RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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6-17

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