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RFD10P03L
Datasheet (Intersil)
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Datasheet RFD10P03L, RFP10P03L Datasheet (Intersil)

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Page 1
RFD10P03L, RFD10P03LSM, RFP10P03L
Data Sheet July 1999 File Number
10A, 30V, 0.200 Ohm, Logic Level, P-Channel Power MOSFET
Formerly developmental type TA49205.
Ordering Information
P AR T NUMBER P ACKAGE BRAND
RFD10P03L TO-251AA 10P03L RFD10P03LSM TO-252AA 10P03L RFP10P03L TO-220AB F10P03L
NOTE: When ordering, use the entire part number. Add the suffix, 9A, to obtain the TO-252AAvariant in tape andreel,i.e.RFD10P03LSM9A..
Features
• 10A, 30V
DS(ON)
= 0.200Ω
•r
• Temperature Compensating PSPICE
• PSPICE Thermal Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
o
C Operating Temperature
• 175
Symbol
D
G
S
®
Model
3515.2
Packaging
DRAIN (FLANGE)
JEDEC TO-251AA JEDEC TO-252AA
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
JEDEC TO-220AB
SOURCE
DRAIN
GATE
GATE
SOURCE
DRAIN (FLANGE)
7-3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
Page 2
RFD10P03L, RFD10P03LSM, RFP10P03L
Absolute Maximum Ratings T
= 25oC Unless Otherwise Specifie
C
RFD10P03L, RFD10P03LSM,
RFP10P03L UNITS
Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (R
= 20KΩ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
DGR
GS
-30 V
-30 V
±10 V
Drain Current
RMS Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
, T
J
STG
Maximum Lead Temperature for Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
DM
AS
D
10
See Figure 5
Refer to UIS Curve
D
65
0.43
-55 to 175
L
300
A
W
W/oC
o
C
o
C
(0.063in (1.6mm) from case for 10s)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ= 25oC to 150oC
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV Gate Threshold Voltage V Zero Gate Voltage Drain Current I
DSS
GS(TH)
DSS
ID = 250µA, VGS = 0V (Figure 11) -30 - - V VGS = VDS, ID = 250µA (Figure 12) -1 - -2 V VDS = -30V, TC = 25oC---1µA
VGS = 0V TC = 150oC - - -50 µA Gate to Source Leakage Current I Drain to Source On Resistance
r
DS(ON)ID
(Note 1) Turn-On Time t
Turn-On Delay Time t
d(ON)
Rise Time t Turn-Off Delay Time t
d(OFF)
Fall Time t Turn-Off Time t Total Gate Charge Q
g(TOT)
Gate Charge at -5V Q Threshold Gate Charge Q
Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Thermal Resistance, Junction to Case R Thermal Resistance, Junction to Ambient R
GSS
ON
r
f
OFF
g(-5)
g(TH)
ISS OSS RSS
θJC
θJA
VGS = ±10V - - ±100 nA
= 10A, VGS = -5V (Figures 9, 10) - - 0.200 Ω ID = 10A, VGS = -4.5V (Figures 9, 10) 0.220 Ω VDD = 15V, ID≅ 10A, RL = 1.5Ω,
RGS = 5Ω, VGS = -5V (Figure 13)
- - 100 ns
-15-ns
-50-ns
-35-ns
-20-ns
- - 80 ns VGS = 0 to -10V VDD = -24V, ID≅ 10A, VGS = 0 to -5V - 13 16 nC VGS = 0 to -1V - 1.2 1.5 nC
RL = 2.4Ω I
= -0.25mA
g(REF)
(Figure 14)
VDS = -25V, VGS = 0V, f = 1MHz (Figure 15)
-2530nC
- 1035 - pF
- 340 - pF
-35-pF
- - 2.30 RFD10P03L, RFD10P03LSM - - 100 RFP10P03L 80
o o o
C/W C/W C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Forward Voltage V Reverse Recovery Time t
NOTE:
2. Pulse Test: Pulse width ≤ 300µs, Duty Cycle ≤ 2%.
7-4
SD
rr
ISD = -10A - - -1.5 V ISD = -10A, dISD/dt = -100A/µs--75ns
Page 3
RFD10P03L, RFD10P03LSM, RFP10P03L
Typical Performance Curves
Unless Otherwise Specified
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 175
125
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZEDPOWER DISSIPATION vs CASE
TEMPERATURE
2.0
1.0
0.5
150
-12
-10
-8
-6
-4
, DRAIN CURRENT (A)
D
I
-2
0
25 50 75 100
125
150
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUMCONTINUOUSDRAIN CURRENT vs
CASE TEMPERATURE
175
0.2
0.1
0.1
0.05
0.02
0.01
, NORMALIZED THERMAL IMPEDANCE
θJC
Z
0.01 10
SINGLE PULSE
-5
-100
-10
, DRAIN CURRENT (A)
D
I
OPERATION IN THIS AREA MAY BE LIMITED BY r
-1
-1 -10
DS(ON)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTES: DUTY FACTOR: D = t1/t PEAK TJ = PDM x Z
-4
10
-3
10
-2
10
-1
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-100
VGS = -10V
VGS = -5V
-10
, PEAK CURRENT CAPABILITY (A)
DM
I
-5
-5
10
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
-4
10
-3
10
t, PULSE WIDTH (s)
V
DSS
MAX = -30V
TJ = MAX RATED
= 25oC
T
C
100µs
1ms
10ms 100ms
DC
-100
P
DM
t
1
t
2
2
xR
θJC
+ T
C
10
θJC
0
10
TC = 25oC
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS:
175 TC–

II
=
----------------------- -

25
150

-2
10
-1
10
0
10
1
1
10
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
7-5
Page 4
RFD10P03L, RFD10P03LSM, RFP10P03L
Typical Performance Curves
-50
-10 STARTING TJ = 150oC
If R = 0
, AVALANCHE CURRENT (A)
t
= (L) (IAS)/(1.3 RATED BV
AV
AS
I
IF R ≠ 0
= (L/R) ln [(IAS*R)/(1.3 RATED BV
t
AV
-1
0.01 0.1 1 10 , TIME IN AVALANCHE (ms)
t
AV
DSS
Unless Otherwise Specified (Continued)
STARTING TJ = 25oC
- VDD)
- VDD) + 1]
DSS
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
-25
PULSE DURATION = 250µs DUTY CYCLE = 0.5% MAX VDD= -15V
-20
-15
-10
-55oC 25oC
175oC
-25
PULSE DURATION = 250µs DUTY CYCLE = 0.5% MAX
= 25oC
T
C
-20
= -10V
V
-15
-10
, DRAIN CURRENT (A)
D
I
-5
0
0-1
GS
-2
VDS, DRAIN TO SOURCE VOLTAGE (V)
-3 -5
FIGURE 7. SATURATION CHARACTERISTICS
400
300
200
DRAIN TO SOURCE
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
T
C
ID = -20A
= -10A
I
D
I
= -5A
D
= -2.5A
I
D
VGS = -5V
VGS = -4V
VGS = -3.5V
VGS = -3V
-4
= 25oC
100
-5
, ON-STATE DRAIN CURRENT (A)
D(ON)
I
0
0 -3.0 -4.5 -6.0-1.5
VGS, GATE TO SOURCE VOLTAGE (V)
ON RESISTANCE (mΩ)
DS(ON),
r
0
-2 -4 -6 -8 -10 , GATE TO SOURCE VOLTAGE (V)
V
GS
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TOSOURCEON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
2.0
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = -5V, ID = -10A
1.5
1.0
ON RESISTANCE
0.5
NORMALIZED DRAIN TO SOURCE
0
-40 0
-80
80
40
, JUNCTION TEMPERATURE (oC)
T
J
120
160 200
1.2 ID =- 250uA
1.1
1.0
0.9
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
0.8
-80 160 200
-40 0 40 , JUNCTION TEMPERATURE (oC)
T
J
80
120
FIGURE 10. NORMALIZEDDRAINTO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
7-6
FIGURE 11. NORMALIZED DRAIN TOSOURCEBREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Page 5
RFD10P03L, RFD10P03LSM, RFP10P03L
Typical Performance Curves
Unless Otherwise Specified (Continued)
1.2 VGS = VDS,ID = -250µA
1.0
0.8
NORMALIZED GATE
0.6
THRESHOLD VOLTAGE
0.4
-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZEDGATETHRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
-30
-22.5
-15
-7.5
, DRAIN TO SOURCE VOLTAGE (V)
DS
V
VDD =BV
DSS
VDD = BV
DSS
RL = 3.0Ω
= -0.25mA
I
G(REF)
0.75 BV
0.50 BV
0.25 BV
0
20
I
G(REF)
I
G(ACT)
0.75 BV
DSS
0.50 BV
DSS
0.25 BV
DSS
V
= -5V
GS
t, TIME ( µs)
DSS DSS DSS
I
G(REF)
80
I
G(ACT)
-5.00
-3.75
-2.50
-1.25
0.00
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
200
, GATE TO SOURCE VOLTAGE (V)
GS
V
150
VDD = -15V, ID = -10A, RL= 1.50Ω
125
t
r
100
t
d(OFF)
75
t
t
d(ON)
f
50
SWITCHING TIME (ns)
25
0
10
20 30 40 500
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 13. SWITCHING TIME vs GATE RESISTANCE
1200
1000
800
600
400
C, CAPACITANCE (pF)
200
0
0 -5 -10 -15 -20 -25
C
ISS
VGS = 0V, f = 0.1MHz
= CGS + C
C
ISS
C
= C
RSS
C
≈ CDS + C
OSS
C
OSS
C
RSS
VDS, DRAIN TO SOURCE VOLTAGE (V)
GD
GD
GD
FIGURE 15. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
VARY t
TO OBTAIN
P
REQUIRED PEAK I
0V
V
GS
t
P
AS
L
R
G
-
V
DD
+
DUT
I
AS
0.01Ω
0
V
DD
I
AS
t
P
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
7-7
BV
t
AV
DSS
V
DS
Page 6
RFD10P03L, RFD10P03LSM, RFP10P03L
Test Circuits and Waveforms
DUT
R
V
GS
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
V
GS
I
G(REF)
G
V
DS
(Continued)
R
L
R
L
DUT
t
ON
t
d(ON)
t
0
-
V
DD
+
V
DS
V
GS
0
10%
r
10%
90%
50%
t
d(OFF)
t
OFF
50%
90%
t
f
10%
PULSE WIDTH
90%
V
Q
0
g(TH)
DS
VGS= -1V
­V
DD
+
-V
GS
Q
g(-5)
V
DD
Q
0
I
g(REF)
VGS= -5V
VGS= -10V
g(TOT)
FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS
7-8
Page 7
RFD10P03L, RFD10P03LSM, RFP10P03L
PSpice Electrical Model
.SUBCKT RFD10P03L 2 1 3 REV 22 Aug 96
CA 12 8 1.29e-9 CB 15 14 9.90e-10 CIN 6 8 1.01e-9
DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DPLCAP 10 6 DPLCAPMOD
EBREAK 5 11 17 18 -36.49 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9 LGATE 1 9 3.40e-9 LSOURCE 3 7 3.22e-9
MMED 16 6 8 8 MmedMOD MSTRO 16 6 8 8 MstroMOD MWEAK 16 21 8 8 MweakMOD
RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 68.25e-3 RGATE 9 20 2.54 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RSourceMOD 25.00e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD
GATE
LGATE
1
RLGATE
RGATE
9
CA
10
DPLCAP
EVTEMP
-
+
18 22
20
S1A
12
13
8
S1B
EGS EDS
13
RSLC2
6
14 13
+
+
6 8
-
-
ESG
+-
8 6
EVTHRES
+
19
8
S2A
S2B
15
CB
CIN
-
+
-
5
51
5
51
MSTRO
14
5 8
RSLC1
+
ESLC
-
50 RDRAIN
16
21
8
EBREAK
MMED
IT
8
+
17 18
-
MWEAK
DBREAK
RSOURCE
17 18
11
7
RBREAK
-
+
RVTHRES
22
LDRAIN
RLDRAIN
DBODY
LSOURCE
RLSOURCE
RVTEMP 19
VBAT
DRAIN
2
SOURCE
3
VBAT 22 19 DC 1
ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*33),5.0))}
.MODEL DBODYMOD D (IS=9.15e-13 RS=3.25e-2 IKF=0.05 N=0.97 TRS1=4.11e-5 TRS2=2.03e-6 CJO=1.13e-9 M=0.40 TT=3.72e-8) .MODEL DBREAKMOD D ( RS=2.62e-1 TRS1=1.74e-3 TRS2=-3.81e-6) .MODEL DPLCAPMOD D (CJO=1.46e-10 IS=1e-30 N=10 M=0.50) .MODEL MSTRONGMOD PMOS (VTO=-1.95 KP=11.60 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MMEDMOD PMOS (VTO=-1.65 KP=1.00 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.54) .MODEL MWEAKMOD PMOS (VTO=-1.43 KP=0.09 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=25.4 RS=0.1) .MODEL RBREAKMOD RES (TC1=9.17e-4 TC2=-2.74e-7) .MODEL RDRAINMOD RES (TC1=6.35e-3 TC2=1.98e-5) .MODEL RSOURCEMOD RES (TC1=0 TC2=0) .MODEL RSCLMOD RES (TC1=2e-3 TC2=0) .MODEL RVTHRESMOD RES (TC1=1.23e-3 TC2=1.97e-6) .MODEL RVTEMPMOD RES (TC1=-1.18e-3 TC2=1.44e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.80 VOFF=1.80) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.80 VOFF=4.80) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.40 VOFF=-3.40) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.40 VOFF=-0.40) ENDS
For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFet Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley.
7-9
Page 8
RFD10P03L, RFD10P03LSM, RFP10P03L
PSpice Thermal Model
REV 29 Aug 96
RFP10P03L
CTHERM1 7 6 5.00e-7 CTHERM2 6 5 5.35e-4 CTHERM3 5 4 5.50e-4 CTHERM4 4 3 1.75e-3 CTHERM5 3 2 1.25e-2 CTHERM6 2 1 0.45
RTHERM1 7 6 1.00e-2 RTHERM2 6 5 2.05e-2 RTHERM3 5 4 5.39e-2 RTHERM4 4 3 5.45e-1 RTHERM5 3 2 1.01 RTHERM6 2 1 0.50
RFD10P03L, RFD10P03LSM
CTHERM1 7 6 5.00e-7 CTHERM2 6 5 5.35e-4 CTHERM3 5 4 5.50e-4 CTHERM4 4 3 1.75e-3 CTHERM5 3 2 1.25e-2 CTHERM6 2 1 0.11
RTHERM1 7 6 1.00e-2 RTHERM2 6 5 2.05e-2 RTHERM3 5 4 5.39e-2 RTHERM4 4 3 5.45e-1 RTHERM5 3 2 1.01 RTHERM6 2 1 0.50
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
JUNCTION
7
CTHERM1
6
CTHERM2
5
CTHERM3
4
CTHERM4
3
CTHERM5
2
RTHERM6
CASE
1
CTHERM6
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications atan ytime with­out notice. Accordingly,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240
EUROPE
Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05
ASIA
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7-10
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