Page 1
RF9986
8
Typical Applications
• CDMA/TDMA/DCS1900 PCS Systems
• PHS 1500/WLAN 2400 Systems
• General Purpose Down Converter
Product Description
The RF9986 is a monolithic integrated receiver front-end
for PCS, PHS, and WLAN applications. The IC contains
all of the required components to implement the RF functions of the receiver front-end except for the passive filtering and LO generation. It contains an LNA (low-noise
amplifiers), a double-balanced Gilbert cell mixer, a balanced IF output, an LO isolation buffer amplifier, and an
LO output buffer amplifier for providing the buffered LO
signal as an output. The IC is designed to operate from a
single 3.6V power supply.
PCS LOW NOISE AMPLIFIER/MI XER
• Micro-Cell PCS Base Stations
• Portable Battery-Powered Equipment
0.344
0.337
8°MAX
0°MIN
0.157
0.150
1
0.2440
0.2284
0.012
0.008
0.025
0.0098
0.0040
0.0688
0.0532
8
Optimum Technology Matching® Applied
Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS
LO BUFF EN
VCC1
VCC2
GND1
LNA IN
GND2
GND3
GND4
VCC3
LO IN
ü
SiGe HBT
NC
1
2
3
4
5
6
7
NC
8
9
10
11
12
Si CMOS
NC
24
GND9
23
VCC4
22
GND8
21
LNA OUT
20
GND7
19
MIX RF IN
18
GND6
17
IF-
16
IF+
15
GND5
14
LO BUFF OUT
13
Functional Block Diagram
0.050
0.0098
0.016
0.0075
Package Style: SSOP-2 4
Features
• Complete Receiver Front-End
• Extremely High Dynamic Range
• S ingle 3.6V Power Supply
• External LNA IP3 Adjustment
• 1500MHz to 2500MHz Operation
Ordering Information
RF9986 PCS Low Noise Amplifier/Mixer
RF9986 PCBA Fully Assembled EvaluationBoard
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
FRONT-ENDS
Rev B1 010717
8-131
Page 2
RF9986
Absolute Maximum Ratings
Parameter Rating Unit
Supply Voltage -0.5 to 7.0 V
Input LO and RF Levels +6 dBm
Ambient Operating Temperature -40 to +85 °C
Storage Temperature -40 to +150 °C
DC
Caution! ESD sensitive device.
RF Micro Devices believes thefurnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
8
Parameter
Min. Typ. Max.
Overall
RF Frequency Range 1500 2500 MHz
LO Frequency Range 1200 2500 MHz
IF Frequency Range DC to 500 MHz
Cascaded Performance
Cascade Conversion Gain 22 25 dB
Cascade Input IP3 -15.0 -10.0 dBm
Cascade Noise Figure 2.5 dB Single Sideband
First Section (LNA)
Noise Figure 1.4 dB
Input VSWR <2:1 Input isinternally matched foroptimum noise
Input IP3 +5.5 dBm IP3 may be increased 10dB by connecting
Gain 12 dB
FRONT-ENDS
Reverse Isolation 23 dB
Output VSWR <1.5:1
Second Section (Mixer)
Noise Figure 5.5 dB Single Sideband
Input VSWR 1.5:1
Input IP3 -0.5 dBm
Conversion Gain 15.5 dB
Output Impedance 1 kΩ Balanced
Specification
Unit Condition
T=25°C, VCC=3.6V, RF=1959MHz,
LO=1749MHz @ -2dBm
1kΩ balanc ed load, 2.5dB Image Filter Loss.
The LNA section may be left unused. Power
is not conne cted to pin 1. The performance
is then as specified for the Second Section
(Mixer).
figure from a 50Ω source.
pin22toV
The LNA’s current then increases by 10mA.
Other in-between IP3 vs. ICCtrade-offs may
be made. See pin description for pin 20.
With 1 kΩ balanced load.
through the matching inductor.
CC
LO Input
LO Input Range -5 to +3 dBm
LO Output Level -4 +1 dBm Buffer On, -2dBm input
-25 -20 dBm Buffer Off, -2dBm input
LO to RF (Mix In) Rejection 30 dB
LO to IF1, IF2 Rejection 20 dB
LO Input VSWR <2:1 Single ended
Power Supply
Voltage 2.7 3.6±5% 5.0 V
Current Consumption 5 mA LNA only
52 mA LNA + Mixer, LO Buffer On
48 mA LNA + Mi xer, LO Buffer Off
8-132
Rev B1 010717
Page 3
RF9986
Pin Function Description Interface Schematic
1NC
2VCC1
3VCC2
4GND1
5LNAIN
6GND2
7GND3
8NC
9GND4
10 VCC3
11 LO BUFF
EN
No connection. This pin may be grounded (recommended) or left open.
Supply voltage for the mixer and RF buffer amplifier.External RF
bypassing is required. The tracelengthbetweenthe pin and the bypass
capacitor should be minimized. The ground side of the bypass capacitor should con nect immediately to ground plane.
Supply voltage for the LNA. External RF bypassing is required. The
trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane.
Ground connection for the LNA. For best performance, keep traces
physically short and connect immediately to ground plane.
RF Input pin for the LNA. This pin is internally DC-blocked and internally matched for minimum noise figure (NOT for minimum VSWR),
given a 50Ω source impedance.
Same as pin 4.
Ground connection for the RF buffer amplifier. For best performance,
keep traces physically short and connect immediately to ground plane.
No connection. This pin may be grounded (recommended) or left open.
Same as pin 7.
Supply voltage for both LO buffer amplifiers. External RF bypassing is
required. The trace length between the pin and the bypass capacitor
should be minimized. The ground side o f the bypass capacitor should
connect immediately to ground plane.
Enable pin for the LO output buff er amplifier. This is a digitally controlled input. A logic "high" (≥3.1V) turnsthebuffer amplifie r on, and the
current consumption increases by 3mA (with -2dBm LO input). A logic
"low" (≤0.5V) turns the buffer amplifier off.
150
7.5 k
Ω
BIAS
Ω
VCC1 VCC4
LO
BUFF
EN
8
12 LO IN
13 LO BUFF
OUT
14 GND5
15 IF+
16 IF17 GND6
18 MIX RF IN
19 GND7
Mixer LO input pin. This pin is internally DC-blocked and matched to
50Ω.
Optional buffered LO output. This pin is internally DC-blocked and
matched to 50Ω. The buffer amplifier is switched on or off by the voltage level at pin 11.
Ground connection for both LO buffer amplifiers. Forbest perform ance,
keep traces physically short and connect immediately to ground plane.
Open-collector IF output pin. This is a balanced output. The output
impedance is set by an internal 1000Ω resistor to pin 16. Thus the differential IF output impedance is 1000Ω. The resistor sets the operating
impedance, but an external choke or matching inductor to V
supplied in order to bias this output. This inductor is typically incorporated in thematching network between the output andIF filter. Because
thispinisbiasedtoV
filter input has a DC path to ground.
Same as pin 15, except complementary output. See pin 15.
Ground connection for the mixer. For best performance, keep traces
physically short and connect immediately to ground plane.
Mixer RF Input Pin. This pin is internally DC-blocked and matched to
50Ω.
Same as pin 17.
, a DC blocking capacitor must be used if the IF
CC
CC
must be
IF- IF+
1k
Ω
FRONT-ENDS
Rev B1 010717
8-133
Page 4
RF9986
Pin Function Description Interface Schematic
20 LNA OUT
21 GND8
22 VCC4
23 GND9
24 NC
LNA output pin. This is an open-collector output. This pin is typically
connected to pin 22 through a bias/matching inductor.This inductor, in
conjunction with a series blocking/matching capacitor, forms a matching network to the 50Ω image filter and provides bias (see Application
Schematic). The LNA’s IP3 may be increased 10dB by connecting pin
20 to V
10mA. Other in-between IP 3 vs. I
nectingresistancevalues betweenV
through the inductor. The LNA’s current then increases by
CC
trade-offs may be made by con-
CC
and the matching inductor. The
CC
two reference points for consideration are with 150Ω used, which is
what connection to pin 22 achieves,the Input IP3 is + 5.5dBm and the
LNA I
the LNA I
is 5mA. Using no resistance, the Input IP3 is +15.5 dBm and
CC
is 15 mA. Desired operating poin ts in between these val-
CC
ues may be interpolated, roughly.
Same as pin 17.
Output supply voltage for the LNA output (pin 20). This pin is typically
connected to pin 20 through a bias/matching inductor (see application
schematic). External RF bypassing is required. The trace length
between the pin and the bypass cap acitor should be minimized. The
ground side of the bypass capacitor should connect immediately to
ground plane.
Same as pin 17.
No connection. This pin may be grounded (recommended) or left open.
See pin 2.
LNA
OUT
8
FRONT-ENDS
RF IN
LO BUFF EN
(On: ≥3.1 V;
Off: ≤0.5 V)
LO IN
Application Schematic
1
V
CC
22 pF
V
CC
22 pF C2
2
3
4
5
6
7
8
9
10
11
12
24
23
22 pF
22
1nF
22 pF
22 pF
1nF
2.7 nH
1.8 pF
C1
C1
Filter, 50 Ω
V
CC
L1
C2
L1
V
CC
Z
RF Image
Z
FILTER
=1kΩ
OUT
=1kΩ
Filter
IF-
IF+
Measurement
Reference Plane
LO BUFF OUT
21
20
19
18
17
16
15
14
13
8-134
L1 and C2 serve dual purposes. L1 serves as an output bias choke, and C2 serves as a series DC block. In addition, the
values of L1 and C2 may be chosen to form an impedance matching network if the IF filter's input impedance is not 1000 Ω.
Otherwise, the values of L1 and C1 are chosen to form a parallel-resonant tank circut at the IF when the I F filter's input
impedance is 1000 Ω.
Rev B1 010717
Page 5
Evaluation Board Schemati c
(IF=210MHz)
(Download Bill of Materials from www.rfmd.com.)
RF9986
P1-1
C17
1nF
J1
LNA IN
P1-1
P1-3
J2
LO IN
P1-1 VCC
P1-3 BUFFER ENABLE
50 Ωµstrip
R2
1kΩ
50 Ωµstrip
P1
1
2
3
GND
C19
1nF
C23
1nF
C16
22 pF
C18
22 pF
C20
22 pF
1
2
3
4
5
6
7
8
9
10
11
12
Drawing 9986400, Rev -
Notes:
1. C11 is selected to fine tune L4 for IF output match at 210 MHz.
2. R3 is not normally populated. For applications requiring additional LNA IP3, see the datasheet for
recommended resistance values.
3. C2 and C3 are not normally populated. If C2 and C3 are populated, the LNA and mixer can be tested
independently; in this case, C1 and C5 should be removed.
24
23
22
21
20
19
18
17
16
15
14
13
C10
22 pF
L3
470 nH
C22
1nF
R3
SeeNote2
L1
2.7 nH
C4
1pF
C29
100 pF
L5
220 nH
C30
100 pF
L2
470 nH
C21
22 pF
50 Ωµstrip
50 Ωµstrip
T1
5.5:1
C24
4.7 µF
C1
22 pF
C5
22 pF
C2
22 pF
FL1
C3
22 pF
C11
1.5 pFL447 nH
50 Ωµstrip
50 Ωµstrip
C8
5pF
50 Ωµstrip
P1-1
J6
LNA OUT
J5
MIXER IN
J4
IF OUT
J3
LO OUT
P1-1
8
FRONT-ENDS
Rev B1 010717
8-135
Page 6
RF9986
Evaluation Board Layout
3” x 3”
Assembly
8
FRONT-ENDS
Top layer
8-136
Rev B1 010717
Page 7
Bottom Layer
RF9986
Internal Ground
8
FRONT-ENDS
Rev B1 010717
8-137
Page 8
RF9986
8
FRONT-ENDS
8-138
Rev B1 010717
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