The RF5176 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is
manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been
designed for use as the final RF amplifier in 3V
CDMA-2000 and W-CDMA handsets as well as other
applications in the 1850MHz to 2000MHz band. The
device is self-contained, and the output can be easily
matched to obtain optimum power, efficiency, and linearity characteristics over all recommended supply voltages.
The device has a continuously variable bias circuit to
allow idle current to be optimized for a given output
power.
3V W-CDMA POWER 1900MHZ/
3V LINEAR POWER AMPLIFIE R
• Commercial and Consumer Systems
• Portable Battery-Powered Equipment
1.00
0.90
0.60
0.24 typ
0.20
3
12°
MAX
0.05
Dimensions inmm.
NOTES:
1
Shaded lead is Pin 1.
2
Pin 1 identifier must exist on top surface of package byidentification
mark or feature on the package body. Exact shape and sizeis optional.
Dimension applies to plated terminal: to be measured between 0.02 mm
3
and 0.25 mm from terminal end.
4
Package Warpage: 0.05 mm max.
5
Die Thickness Allowable: 0.305 mm max.
0.75
0.50
4.00
sq.
0.50
Note orientation of package.
2.10
0.23
0.13
4 PLCS
2
0.65
0.30
4 PLCS
sq.
POWER AMPLIFIERS
Optimum Technology Matching® Applied
Si BJTGaAs MESFETGaAs HBT
Si Bi-CMOS
VREG1
VCC BIAS
VREG2
VS2
BIAS GND
ü
SiGe HBT
NC
NC
20191817
1
2
Bias
3
5
678910
NC
Q1B
NC
RF OUT
Si CMOS
NC
16
RF OUT
RF IN
15
NC
14
NC
VCC1
13
124
VCC1
11
NC
RF OUT
Functional Block Diagram
Package Style: LCC, 20-Pin, 4x4
Features
• Single 3V Supply
• 27dBm Linear Output Power
• 26dB Linear Gain
• 40% Linear Efficiency
• On-board Power Down Mode
Ordering Information
RF51763V W-CDMAPower 1900MHZ/ 3V Linear Power
RF5176 PCBAFully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA
Amplifier
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Rev A0 010910
2-197
Page 2
2
RF5176
Absolute Maximum Ratings
ParameterRatingUnit
Supply Voltage (RF off)+8.0V
Supply Voltage (P
Bias Voltage (V
Control Voltage (V
Input RF Power+6dBm
Operating Case Temperature-30 to +100°C
Storage Temperature-30 to +150°C
≤31dBm)+5.0V
OUT
)+3.0V
BIAS
)+3.0V
REG
DC
DC
DC
DC
Preliminary
Caution! ESD sensitive device.
RF Micro Devices believesthe furnishedinformation is correctand accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice.RF Micro Devices does not
assume responsibility for the use of the described product(s).
Parameter
POWER AMPLIFIERS
Overall
Usable Frequency Range18502000MHz
Typical Frequency Range1850 to 1910MHz
Linear Gain26dB
Second Harmonic (including
second harmonic trap)
Third Harmonic-50dBc
Maximum Linear Output Power
T=25°C, VCC=3.4V,
Freq=1920MHz to 19 80MHz, V
unless othe rwise specified
OUT
OUT
3GPP 3.2 03-00 DPCCH + 1 DPDCH
OUT
3GPP 3.2 03-00 DPCCH + 1 DPDCH
OUT
Rx Band 2110MHz to 2170MHz
Power Supply
Power Supply Voltage3.03.45.0V
Idle Current80mAV
VREG Current10µATotal pins 1 and 3, V
Turn On/Off timens
Total Current (Power down)10µAV
“Low” Voltage00.2V
V
REG
“High” Voltage2.5VS ee Alternative Biasing Network table follow-
V
REG
REG
REG
ing the application schematic.
REG
=27dBm
=27dBm, W-CDMA Modulation,
=27dBm, W-CDMA Modulation,
=+27dBm,
=2.5V
=2.5V
REG
=Low
=2.5V,
2-198
Rev A0 010910
Page 3
Preliminary
RF5176
PinFunctionDescriptionInterface Schematic
1VREG1
2VCC BIAS
3VREG2
4VS2
5BIASGND
6NC
7NC
8RFOUT
9RFOUT
10RF OUT
11NC
12VCC1
13VCC1
14NC
15NC
16RF IN
17NC
18Q1B
19NC
20NC
Pkg
GND
Base
Bias control for the first stage. Needs to be divided down from its nominal value of 2.5V using a resistive divider network of 240kΩ and
360kΩ.V
a given outputpower.AlternativeV
defined on the application schematic.
Supply for bias circuits.
Bias control for the second stage. Needs to be divided down from its
nominal value of 2.5V using a resistive divider network of 240kΩ and
240kΩ.AlternativeV
cation schematic.
Second stage bias circuit source. For best linearity, decouple with
bypassing capaci tors of 15pF and 100 nF.
Connect to ground p lane via a 15nH inductor. DC return forthe second
stage bias circuit.
Not currently used.
Not currently used.
RF output and power supply for the final stage. Thi s is the unmatched
collector of the final stage. It requires an output matching network,
including a DC blocking capacitor.
Same as pin 8.
Same as pin 8.
Not currently used.
Powersupply for the first stage and interstage match. Requires a shunt
capacitor of 12pF close to the pin for optimum match.
Same as pin 12.
Not currently used.
Not currently used.
RF input. Requires a blocking capacitor and shunt inductor to provide
2:1 VSWR.
Not currently used.
Base bias for first stage. For best linearity, decouple with 15pF and
100nF capacitors.
Not currently used.
Not currently used.
Ground connection. The backside of the package should be soldered
to a top side ground pad which is connected to the ground plane with
multiple vias. The pad should have a short thermal path to the ground
plane.