Page 1
Preliminary
RF3322
3
Typical Applications
• Euro-DOCSIS/DOCSIS Cable Modems
• CATV Set-Top Boxes
• Telephony Over Cable
Product Description
The RF3322 is a variable gain amplifier for use in CATV
reverse path (upstream) applications. It is DOCSIS-compliant for use in cable modems. The gain control covers a
58 dB range and is serially programmable via three-wire
digital bus for compatibility with standard baseband
chipsets. Amplifier shutdown and transmit disable modes
are software- and hardware-controlled. The device is
placed into sleep mode via the serial control bus. The
device operates over the frequency band of 5MHz to
65 M Hz for use in current U.S. and European systems.
The amplifier delivers up to 60dBmV at the output of the
balun. Gain is controllable in accurate 1dB steps. The
device is provided in an industry-standard QSOP-20
package.
CABLE REVERSE PATH
PROGRAMMABLE GAIN AMPLIFIER
•HomeNetworks
• Automotive/Mobile Multimedia
• Coaxial and Twisted Pair Line Driver
0.157
0.150
0.0098
0.340
0.333
0.244
0.228
8° MAX
0° MIN
NOTES:
1. Shaded lead is Pin 1.
2. All dimensions are excluding mold flash and protrusions.
3. Lead coplanarity: 0 to0.004max.
4. Deviation from package center andleadframe center: 0.004 max.
5. Misalignment from top and bottompackage centers: 0.004 max.
6.Endflashnottoexceed0.006perside.
0.050
0.016
0.0040
0.025
0.010
0.006
Dimensionsin inches.
0.0098
0.0040
0.0688
0.0532
3
LINEAR CATV
AMPLIFIERS
Optimum Technology Matching® Applied
Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS
ü
SiGe HBT
1
GND
2
VCC1
3
GND
4
GND1
5
VIN+
6
VIN-
7
GND
8
CS
9
SDA
SCLK GND
and Serial Bus
10
Control
Gain Control
Power
Si CMOS
20
GND2
19
VCC2
18
TXEN
17
NC
16
VOUT+
15
VOUT-
14
RAMP
13
NC
12
SHDN
11
Functional Block Diagram
Package Style: QSOP-20
Features
• Single 5V Supply
• Differential Input and Output
• -30dB to +28dB Voltage Gain Range
•5MHzto65MHzOperation
• Sophisticated Power Management
• DOCSIS 1.1 RF Compliant
Ordering Information
RF3322 Cable Reverse Path ProgrammableGain Amplifier
RF3322 PCBA Fully Assembled Evaluation Board
RF Micro Devices, Inc.
7625 ThorndikeRoad
Greensboro,NC 27409, USA
Tel (336)664 1233
Fax (336) 664 0454
http://www.rfmd.com
Rev A2 010518
3-27
Page 2
3
RF3322
Absolute Maximum Ratings
Parameter Rating Unit
Supply Voltage (V
Input RF Level 12 dBm
Operating Ambient Temperature -40 to +85 °C
Storage Temperature -40 to +150 °C
Humidity 80 %
Maximum Power Dissipation 0.5 W
Maximum T
J
CC1
and V
) -0.5 to +6.0 V
CC2
150 °C
DC
Preliminary
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time ofthis printing. However, RFMicro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility forthe useof the described product(s).
LINEAR CATV
Specification
Unit Condition
VCC=4.75V to 5.25V, TXEN=SHDN=1,
V
=30dBmV (rms) differential, output
IN
impedance=75Ω through a 2: 1 transformer.
Typical performance is at TA=+25°C,
V
=5V.
CC
AMPLIFIERS
Overall
Parameter
Min. Typ. Max.
DC Specifications
SupplyVoltage 4.75 5.0 5.25 V
Supply Current
Maximum Gain 130 160 mA Gain Control Word=58
Low Gain 65 105 mA G ain Control Word<35
Transmit Disable 25 35 mA TXEN=0
Software-Shutdown 3 5 mA Bit 7 of gain control word FALSE
Sleep 0.05 mA SHDN=0
Logic High Voltage 2 V
Logic Low Voltage 0.8 V
Logic Leakage Current -1 1 µA
AC Specifications
Voltage Gain
Maximum 27 28 dB 5MHz to 42MHz; Gain Control Word=58
26 dB 42MHz to 65MHz; Gain Control Word=58
Minimum -30 -26 dB 5MHz to 42MHz; Gain Control Word=0
-28 dB 42MHz to 65MHz; Gain Control Word=0
3dB Bandwidth 100 MHz Intended operating range is 5MHz to
1dB Compression Point 66 dBmV
Maximum Input Level 34 dBmV(rms) Modulated. To meet distortion specifications.
Maximum Output Level 60 dBmV(rms) Modulated. Into 75Ω loadat balun output, all
ACPR -59 -47 dBc V
Output IM3 -58 -55 dBc Tones at 40MHz and 40.2MHz,
Output Third Harmonic
Distortion
F=20MHz, V
F=65MHz, V
Output Second Harmonic
Distortion
F=20MHz, V
F=65MHz, V
=59dBmV -60 -55 dBc Maximum Gain, CW
OUT
=59dBmV -55 -50 dBc Maximum Gain, CW
OUT
=59dBmV -70 -60 dBc Maximum Gain
OUT
=59dBmV -70 -60 dBc Maximum Gain
OUT
65MHz.
distortion tones <-50dBc.
=34dBmV (r m s); QPSK modulation;
IN
Symbol rate=160ksps (2 bits per symbol);
20-bit PRBS (pseudo-random bit stream);
0.25 alpha root cosine filter
=+54dBmV/tone, maximum gain, OIP3
V
OUT
is therefore +84dBmV, IIP3 is 58dBmV.
3-28
Rev A2 010518
Page 3
Preliminary
RF3322
Parameter
Min. Typ. Max.
Specification
Unit Condition
AC Specifications, cont’d
Output Step Size 0.8 1.0 1.1 dB
Isolation in Transmit Disable
Mode
Output Noise
Maximum Gain -37 -30 dBmV/
MinimumGain -55 -50 dBmV/
Transmit Disabled -75 -70 dBmV/
TX EN Enable Time 0.5 1.0 µS Time for gain to reach 99% of final value.
TX EN Transient Duration 2.4 3.0 µSSeeNote1.
Output Switching Transients 5 10 mV
Output Impedance 255 300 345 Ω Chip output impedance is nominally 300Ω.
Input Impedance 75 Ω Differential
-80 -95 dBc Maximum Gain, 20MHz
160kHz
160kHz
160kHz
35mV
-96dBc for a 59dBmV carrier in a 160kHz
bandwidth.
-64dBc for an 8dBmV carrier in a 160kHz
bandwidth.
TXEN=0
SeeNote1.
Maximum Gain
P-P
Minimum Gain
P-P
Differential to single-ended output conversion to 75Ω is performed in a balun w ith a
2:1 turns ratio,corresponding toa 4:1 impedance ratio.
Thermal
Theta
JC
28 °C/W
Note 1: The enable time is determined by the value of the capacitor on pin 14 (RAMP). A higher c apacitor value will
increase the enable time, but will reduce the transient voltage.
3
LINEAR CATV
AMPLIFIERS
Rev A2 010518
3-29
Page 4
3
LINEAR CATV
RF3322
Preliminary
Pin Function Description Interface Schematic
1GND
2 VCC1
3GND
4 GND1
5VIN+
6VIN-
7GND
8CS
9SDA
10 SCLK
AMPLIFIERS
11 GND
12 SHDN
13 NC
14 RAMP
15 V OUT16 V OUT+
17 NC
18 TXEN
19 VCC2
20 GND2
Connect to ground.
This pin is connected to the supply voltage, and should be decoupled
as close to GND1 as pos sible.
Connect to ground.
PGA RF ground.
Input pin. This should be externally AC-coupled to signal source.
Complementary input pin. This should be externally coupled to signal
source. For single-ended use, this pin should be AC-coupled to ground
through an impedance equivalent to the impedance driving V IN+.
Connect to ground.
Serial bus enable.
Serial bus data input.
Serial bus clock input.
Connect to ground.
Ship shutdown pin. Forcing a logic low causes all ci rc u its to switch off
andgainsettingstobelost.
Not connected.
Turn-on time iscontrolled by an external capacitorbetween thispin and
ground.
Open collector output. Connect to VCCvia balun primary.
Open collector output. Connect to VCCvia balun primary.
Not connected.
Signal path enable pin. Logic high turns on signal path. Logic low turns
off signal path, but leaves serial bus active.
This pin is connected to the supply voltage, and should be decoupled
as close to GND2 as pos sible.
Power amplifier bias ground.
Serial Bus Block Diagram
CS
SDA
SCLK
3-30
D0 D1 D2 D3 D4 D5 D6
D
CK
CLR
D
Q
CK
CLR
D
Q
CK
CLR
D
Q
CK
CLR
D
Q
CK
CLR
D
Q
Q
CK
CLR
D
Q
CK
CLR
D7
D
Q
CK
CLR
POR
CLR
D
Q
CK
CLR
D
Q
Q
CK
CLR
D
CK
CLR
D
Q
CK
CLR
D
Q
CK
CLR
D
Q
CK
CLR
D
Q
CK
CLR
D
Q
CK
Rev A2 010518
Page 5
Preliminary
Table 1. Serial Interface Control Word Format
Bit Mnemonic Description
MSB 7 D7 Sleep Mode (Software Shutdown)
6D6TestBit
5 D5 Gain Control, Bit 5
4 D4 Gain Control, Bit 4
3 D3 Gain Control, Bit 3
2 D2 Gain Control, Bit 2
1 D1 Gain Control, Bit 1
LSB 0 D0 Gain Control, Bit LSB
Serial Bus Timing D iagram
RF3322
3
TES TDS TDH TEH
D7
TDATAH,TDATAL
D6
Table 2. Timing Data
Parameter Symbol Min Typ Max Units
SCLK Pulsewidth T
SCLK Period T
Setup Time, SDA versus S CLK T
Setup Time, CS versus S CLK T
Hold Time, SDA versus S CLK T
Hold Time, CS versus S CLK T
SCLK Pulsewidth, High T
SCLK Pulsewidth, Low T
WH
C
DS
ES
DH
EH
DAT AH
DATAL
TWH
TC
50 ns
100 ns
10 ns
10 ns
20 ns
20 ns
50 ns
50 ns
AMPLIFIERS
LINEAR CATV
D0D1D2D3D4D5
Table 3. Programming State
TX SHDND MSB6
Enter Sleep Mode X H L H=High Voltage Logic
Exit Sleep Mode X H H* L=Low Voltage Logic
Enter Shutdown X L X X=Don’t Care
Exit Shutdown X H H* *Gain Control Data Must be Re-Sent
TX Enable H X X
TX Disable L X X
Rev A2 010518
3-31
Page 6
RF3322
Preliminary
Typical Application Schematic
3
LINEAR CATV
V
CC1
10 nF
VIN+
10 nF
VIN-
AMPLIFIERS
CS
SDA
SCLK
1
2
3
4
5
6
7
8
9
10
Gain Control
and Serial Bus
Power
Control
20
19
18
17
16
15
100 pF
14
13
220 pF
12
11
4:1
V
CC2
SHDNB
VOUT
TXEN
3-32
Rev A2 010518
Page 7
Preliminary
RF3322
Evaluation Board Schemati c
VCC
R1
100 kΩ
R2
100 kΩ
VCC
VCC1
VCC2
VCC3
VCC1
J2
RF IN
CS
SDA
SCLK
L2 (Ferrite)
30 Ω
L3 (Ferrite)
30 Ω
L4 (Ferrite)
30 Ω
L5 (Ferrite)
30 Ω
J1
1
NC
2
CS
SDA
SCLK
J5-1
J3-1
CS
3
SDA
4
SCLK
5
SHDN
6
TXEN
7
NC
8
NC
9
NC
10
VCC
11
NC
12
13
NC
14
NC
15
VCC
16
NC
17
NC
18
GND
19
GND
20
GND
21
GND
22
GND
23
GND
24
GND
25
GND
Notes:
1. 4-layer board. 2nd layeris ground plane.
2. Place C5 and C6 asclose to pinas possible.
3. C1 is tantalum,size code Y.
4. All other componentsare 0603 size.
5. Replace R6 with0 Ω resistor if 75 Ωconnector is used.
L1 (Ferrite)
30 Ω
+
C2
1nF
C5
0.1 µF
R4
75 Ω
R5
75 Ω
C3
1nF
C4
1nF
T1
1:1
C1
10 µF
(10 V)
1
2
3
4
5
6
7
8
9
10
JP1
1
VCC
GND
2
Gain Control
and SerialBus
3322410-
Power
Control
J3
1
2
3
20
19
18
17
16
15
14
220 pF
13
12
11
C6
0.1 µF
C10
15 pF
C11
15 pF
C7
T2
4:1
C9
100 pF
J5
1
2
3
J1-6
TXEN
R6
24 Ω
J1-5
SHDN
J4
1
VCC
2
GND
3
VCC2
3
VCC3
J7
RF OUT
AMPLIFIERS
LINEAR CATV
J6
1
VCC
2
GND
3
PCB Layout Considerations
The RF3322 evaluation board c an be used as a guide for the layout in your application. Care should be taken in laying
out the RF3322 in other applications. The RF3322 will have similar results if the following guidelines are taken into consideration:
• Make sure underside of package is soldered to a good ground on the PCB.
• Move C2, C9, C10, and C11 as close to T1 as possible.
• Keep input and output traces as short as possible.
• Ensure a good ground plane by using multiple vias to the ground plane.
Use a low noise power supply along with decoupling capacitors.
Rev A2 010518
3-33
Page 8
3
LINEAR CATV
RF3322
Preliminary
Evaluation Board Layout
Board Size 2.5” x 2.5”
Board T hickness 0.058”, Board Material FR-4, Multi-Layer
AMPLIFIERS
3-34
Rev A2 010518
Page 9
Preliminary
RF3322
Gain versus Frequency
30.0
20.0
Gain Control Word=58
10.0
0.0
Voltage Gain(dB)
-10.0
-20.0
-30.0
0 50 100 150 200 250
Gain Control Word=29
Gain Control Word=0
Frequency (MHz)
Current versus Gain Control Word
135
125
115
Current (mA)
105
95
Gain versus GainControl Word
28.0
18.0
8.0
-2.0
Voltage Gain(dB)
-12.0
-22.0
-32.0
0 102030405060
GainControlWord
Second Harmonic versus Frequency
0
65 MHz
42 MHz
5MHz
Second Harmonic(dBc)
-10
-20
-30
-40
-50
-60
-70
3
LINEAR CATV
AMPLIFIERS
85
0 102030405060
0
-10
-20
-30
-40
-50
Third Harmonic(dBc)
-60
-70
-80
30 35 40 45 50 55 60
Rev A2 010518
GainControlWord
Third Harmonic versus Frequency
Frequency (MHz)
-80
30 35 40 45 50 55 60
Frequency (MHz)
65 MHz
42 MHz
5MHz
3-35
Page 10
RF3322
Preliminary
Evaluation Kit
3
General Description
The RF3322 PCBA is a fully assembled evaluation
board of the RF3322 reverse path high output power
programmable gain amplifier, useful for providing a
demonstration of the RF3322’s functionality. The
RF3322 PCBA is a digitally controlled variable gain
amplifiercapable of driving a 75Ω source. The RF3322
is designed to send cable modem data with QPSK or
QAM modulated format at frequencies between 5 MHz
and 65MHz. The gain is controlled by an 7-bit serial
data word which adjusts the output gain from -30dB to
+28dB.
The kit includes a fully functional evaluation board
AMPLIFIERS
LINEAR CATV
along with a serial data cable and software. The cable
connects directly to the parallel port of a standard PC.
The software is used to control the serially programmable gain through a s imple, easy to understand user
interface.
Input and output to the evaluation board is provided
through 50Ω SMA connectors. The input and output of
the evaluation board is matched to 50Ω and connected
through a balun for single-ended operation. This allows
easy connection to test equipment, but the evaluation
board can easily be converted to a 75Ω input and output, or for differential input and output. The output circuit is matched using a 24Ω series resistor which is
used to bring the load impedance up to 75Ω when
using standard 50Ω test equipment. This will introduce
a loss which must be accounted for in all measurements (see measurementsection and evaluation board
schematic for more detail.)
PCBA Details
Input Circuit
The input to the RF3322 is differential and the impedance is 75Ω; However, for ease of testing, the evaluation board has been changed to single-ended and the
impedance has been matched to 50Ω.Ifa75Ω input is
required, simply replace the 50Ω SMA connector with
a75Ω F-style connector and remove R4 and R5.
device to 75Ω. This introduces a voltage loss of 3.5dB
which must be accounted for in all measurements.
Some spectrum analyzershave a setting to account for
this method of 75Ω testing (e.g., on a Rhode &
Schwartz spectrum analyzer the input can be set to
'”75Ω RAZ” and the loss is accounted for automatically). A more accurate way of making this measurement is to use a 75Ω spectrum analyzer, or use a
matching transformer or minimum loss pad. This
ensures that the s ource impedance seen by the equipment is also 75Ω.Ifa75Ω output is required, simply
replace the 50Ω SMA connector (J7) with a 75Ω Fstyle connector and replace R5 with a 0Ω jumper. The
evaluation board is tested with a Coilcraft balun; however, additional baluns may be used as long as care is
taken in modifying the decoupling capacitors around
the balun. These capacitors can greatly affect the harmonic s uppression. Other baluns may be used but
should be tested for second and third order harmonic
suppression.
Transmit Enable
The transmit enable can be set to “continuous on” by
placing the TXEN jumper in the right-hand position
(right-hand position when viewing the top of the evaluation board with the 25-pin connector closest to the
viewer) and placing the associated GND/VCC jumper
in the “VCC” position. The transmit enable can be set
to “continuous off” by placing the GND/VCC jumper in
the “GND” position. If a computer controlled signal is
used (J1), place the TXEN jumper in the left-handposition.
TX EN
Continuous ON
VCC
GND
A
TX EN
Continuous OFF
VCC
GND
B
TX EN
Software Controlled
VCC
GND
C
Figure 1. TX Enable Configuration
Output Circuit
The output of the RF3322 is differential and the impedance is 300Ω. In nor m al applications this is converted
into a single-ended 75Ω output using a 2:1 (voltage
ratio) transformer with a center-tap on the secondary
which supplies power to the output stage. The evaluation board is configured for use with 50Ω test equipment. This has been achieved with a 24Ω resistor in
series with the output to increase the load seen by the
3-36
Rev A2 010518
Page 11
Preliminary
RF3322
Shutdown Enable
Shutdown enable can be set to be “continuous on”
(chip enabled) by placing the SHDN jumper in the
right-hand position and placing the associated GND/
VCC jumper in the “VCC” position. Shutdown enable
can be set to “continuousoff”(chipdisabled) byplacing
the associated GND/VCC jumper in the “GND” position. If a computer controlled signal is used (J1), place
the SHDN jumper in the left-hand position.
SHDN
Continuous ON
GND
VCC
A
SHDN
Continuous OFF
B
GND
VCC
SHDN
Software Controlled
C
GND
VCC
Figure 2. SHDN Enable Configuration
V
Settings
CC
should be set to 5.0VDC.
V
CC1
Evaluation Board Setup
Equipment Needed
• Signal Generator
• Spectrum Analyzer
• Power Supply (5.0V@300mA)
• RF3322 PCBA
• Serial Cable (included with kit)
• Standard PC
• Three-Wire Bus Software
Optional Equipment
• Variable Low-Pass or Band-PassFilters
• Power Meter
• Second SignalGenerator withModulation forACPR
and IP2, IP3 Testing
• Arbitrary Wave Generator
• Two-Channel Oscilloscope
Unzip the file using WinZip 7.0 or higher (http://
www.winzip.com). Unzip to a temporary directory and
run RF3322.exe.
The 7-bit Gain Control Word (GCW) in the data latch
determines the gain setting in the RF3322. The gain
control data (SDA) load sequence is initiated by a falling edge on CS. The SDA is serially loaded (MSB first)
into the 7-bit shift register at each rising edge of the
clock. W hile CS is low, the data latch holds the previous data word allowing the gain level to remain
unchanged. After seven clock cycles the new data
word is fully loaded and CS is switched high. This
enables the data latch and the loaded register data is
passed to the gain control block with the updated gain
value. Also at this CS transition, the internal clock is
disabled, thus inhibiting new serial input data.
Software and Cable
Figure 3 shows the cable configuration. Connect the
cable into the LPT1 port of the computer running the
software. Connect the other end of the cable to the 25pin connector of the evaluation board. Executing the
software (RF3322.exe) will produce the screen shown
in Figure 4. The user may set the gain of the evaluation
board by sliding the gain control switch to the desired
gain setting. Pressing the Preset Gain Value buttons
automatically sets the gain of the unit to the value
shown on the button. The Automatic Gain Adjustment
when set to “Cycle” will automatically cycle through all
of the gain steps (0-58) in seconds (at the rate set by
the user). The user may place the unit in sleep, shutdown and transmit enable/disable m odes by checking
the corresponding box. The bit pattern being sent to
the PCBA is shown at the bottom of the screen. See
README_3322.txt file for proper pin/signal mapping
for the 25 pin interface.
3
LINEAR CATV
AMPLIFIERS
Software Setup
To install the software, you need a computer with the
following.
• 133MHz Pentium processor
•16MBRAM
• Hard Drive with 5MB free space
• Free 25-pin LPT port
• VGA Monitor
The software may be downloaded from www.rfmd.com
by following these steps.
Select the “Product Support” tab;
Select “Evaluation Board Information”;
Select “RF3322”.
Rev A2 010518
3-37
Page 12
3
RF3322
Preliminary
RF3322 PCBA Cable
AMPLIFIERS
LINEAR CATV
Figure 3. Cable Configuration
Hardware Setup
Gain and Harmonic Distortion Test Setup
To test the gain of the RF3322 PCBA, connect a lowpass or band-pass filter to the output of the signal generator. Use a filter just above thefrequencyyouwant to
test. The filter is used to attenuate any harmonics output by the signal generator. Connect the signal generator to the power meter and measure the power.
Compare with modulation enabled and disabled to
make sure the meter was measuring average rather
than peak power. No more than 0.2dB difference in
powershouldbeobserved. An offset on the signalgenerator may be needed to match the level shown on the
power meter. The signal generator should then be connected directly to a spectrum analyzer. Make sure the
output of the signal generator is the same as the input
read by the spectrum analyzer. Adjust the offset of the
spectrum analyzer until the signal out is the same as
the signal in on the spectrum analyzer. Turn off the RF
and modulation. Check positioning of the jumpers on
the board. Refer to the PCBA section of this application note to verify proper positions. Connect the output
of the signal generator to J2: RFIN of the PCB. Connect J7: RFOUT to the spectrum analyzer. Ensure that
18Ground
25 Pin D-Connector (Back View)
6 TX Enable Line
5SHUTDOWNLine
4 CLK Line
3DataLine
2CSLine
Figure 4. On-Screen Display
you are accounting correctly for the losses in the 75Ω
to 50Ω conversion at the output of the device; there is
an output voltage loss of 3.5 dB for the evaluation
board in its standard configuration (see output stage
circuit description).Connect one end of the serial cable
into the computer and the other end into J1 of the PCB.
Connect +5.0V
Turn on the DC power and turn on RF from the signal
generator. Set the GCW to 58 and make sure TX
Enable is checked. The amplified signal should be displayed on the spectrum analyzer. The harmonics can
also be viewed with this setup. As you change the
GCW from 58 to 0 (in s teps of one), there will be a 1dB
change in the output of the PCB.
ACPR Test Setup
To test the ACPR of the RF3322 PCBA set modulation
to:
•QPSK
• 2Bits/Sym
• 160ksps
• α=0.25
• PRBS-20bit Data
into V+ and ground into GND(JP1).
DC
3-38
Rev A2 010518
Page 13
Preliminary
RF3322
Set signal generator to:
•45MHz,
• -13.0 dBm output power,
• 0dB offset.
Connect 50MHz coaxial filter to output, then to output
cable.
Zero and calibrate the power meter. Connect signal
generator to power meter and set offset on signal generator until power meter reads -13.0dBm. Make sure
power meter reads the same (±0.2dBm) with modulation enabled and disabled to verify power meter is
measuring average power rather than peak power.
Check positioning of the jumpers on the board. Refer
to the PCBA section of this application note to verify
proper positions. Connect the output of the signal generator to J2: RFIN of the PCB. Connect J7: RFOUT to
the power meter. Connect one end of the serial cable
into the computer and the other end into P1 of the
PCB. Connect+5.0V
Turn on the DC power and turn on RF and modulation
from the signal generator. Set the GCW to 58 and
make sure TX Enable is checked. Measure and record
channel power at RFOUT using the power meter
(accounting for 75/50 conversion losses). Connect
RFOUT to spectrum analyzer and adjust offset of the
spectrum analyzer until the channel power displayed
by the spectrum analyzerisequaltothe channelpower
recorded in the previous step (Channel bandwidth=
200 kHz). Now use the spectrum analyzer to measure
relative ACP (this way the uncertainties in the spectrum analyzer power measurement are immaterial).
The ACP is measured in 200 kHz channel bandwidths
at a 220kHz offset (i.e., from 20kHz to 220kHz outside
the channel). As you increase the input power, you will
notice a degradation of the ACP upper and lower
bands. Datasheet performance is measured at an
input level of 34dBmV.
into VCCand ground into GND.
DC
will be displayed on the oscilloscope. Measure the
amount of time between 90% of the TXEN turn-on to
where the output signal reaches 90% of full turn-on.
This is defined as the transmit turn-on time.
To measure the transient pulse, replace the signal generator input with a 50Ω terminator and repeat the steps
above. Measure the size of the transient. This can be
affected by the C
balun and capacitor values around the balun. Larger
values of C
and increase the TX enable time.
PCB Layout Considerations
The RF3322 Evaluation board can be used as a guide
for the layout in your application. Care should be taken
in laying out the RF3322 in other applications. The
RF3322 will have similar results if the following guidelines are taken into consideration:
• Make sure underside of package is soldered to a
good ground on the PCB.
• Move C2, C9, C10, and C11 as close to T1 as possible.
• Keep input and output traces as short as possible.
• Ensure a good ground plane by using multiple vias
to the ground plane.
• Use a low noise power supply along with decoupling capacitors.
RAMP
capacitor (C7), and the output
RAMP
will decrease the transient voltage
3
LINEAR CATV
AMPLIFIERS
Transmit Turn-On and Turn-Off Transients
UseanArbitraryWaveformGeneratorsettoa3V
square wave, 5% duty cycle, 120Hz as the input to the
transmit enable. Set a signal generator to 10MHz,
-13.0d bm output power, 0dB offset. Connect output of
the signal generator to J2, RFIN of the PCB. Remove
the TXEN jumper and connect the arbitrary wave generator square wave output to the center pin of the
TXEN 3-pin header. Connect the output of the evaluation board to the oscilloscope (channel 1). Connect the
TXEN signal from the arbitrary wave generator to
channel 2 of the oscilloscope and trigger off of the risingedge.AstheTXENlineissent,theoscilloscope
will trigger and capture the pulsed RFOUT signal. This
Rev A2 010518
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Page 14
3
RF3322
Special Handling Information for S hrunk Small
Outline Package (SSOP1-EPP) Products
These packages are considered JEDEC Level 5 for
moisture sensitivity and require special handling to
assure reliable performance.
The exposedcopper slug on the bottom of the package
improves both thermal and electrical performance.
Since the RFIC is mounted directly on the thermal
slug, and the slug is soldered directly on the PCB, the
thermal resistance to the PCB is minimized. Also, the
RF ground for the amplifier is established through this
copper slug as it is soldered to the ground plane on the
PCB. This offers the least inductance ground path
available.
Care must be taken when soldering these packages to
AMPLIFIERS
LINEAR CATV
the PCB. They are currently considered JEDEC Level
5 for moisture sensitivity. Therefore the parts must be
handled in a dry environment prior to soldering, as is
specified in the JEDEC specification. Specifically,
RFMD recommends the following procedure prior to
assembly:
1. Dry-bake the parts at 125°C for 24 hours minimum.
Note: the shipping tubes cannot withstand 125°C
baking temperature.
2. Parts delivered on tape and reel are already drybaked and dry-packed. These may be stored for up
tooneyear,butmustbeassembledwithin48hours
after opening the bag.
3. Assemble the dry-baked parts within two days of
removal from the oven.
4. During this two-dayperiod, the parts must be stored
in humidity less than 60%.
Preliminary
IMPORTANT!
If the two-day period is exceeded, then this procedure
must be repeated prior to assembly.
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Rev A2 010518
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