Page 1
Preliminary
RF3321
2
Typical Applications
• Euro-DOCSIS/DOCSIS Cable Modems
• CATV Set-Top Boxes
• Telephony Over Cable
Product Description
The RF3321 is a variable gain amplifier for use in CATV
reverse path (upstream) applications. It is designed to be
DOCSIS-compliant for use in cable modems. The gain
control covers a 56dB range and is serially programmable v ia three-wire digital bus for compatibility with standard baseband chipsets. Amplifier shutdown and transmit
disable modes are hardware-controlled. The device operates over the frequency band of 5MHz to 65MHz for use
in current U.S. and European systems. The amplifier
delivers up to +69dBmV at the output of the balun. Gain
iscontrollableinaccurate1dBsteps.Thedeviceisprovided in a thermally enhanced, exposed die flag package.
REVERSE PATH HIGH OUTPUT POWER
PROGRAMMABLE GAIN AMPLIFIER
•HomeNetworks
• Automotive/Mobile Multimedia
• Coaxial and Twisted Pair Line Driver
-A-
0.05
+ 0.05
Note 3
NOTES:
1. Shaded lead ispin1.
2. Lead coplanarity -0.10with
3. Lead standoff isspecifiedfrom
2.286
respect to datum "A".
the lowest point onthepackage
underside.
4.90
+ 0.20
8° MAX
0° MIN
3.90
+ 0.10
6.00
+ 0.20
0.60
+ 0.15
0.24
0.20
0.25
+ 0.05
0.65
1.40
+ 0.10
3.302
EXPOSED DIE
FLAG
3
LINEAR CATV
AMPLIFIERS
Optimum Technology Matching® Applied
Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS
ü
SHDNB
TX EN
NC
VIN
VINB
VCC1
VCC1
RAMP
SiGe HBT
1
2
3
4
5
6
7
8
Power
Control
Gain Control
and Serial Bus
Si CMOS
16
15
14
13
12
11
10
9
GND
NC
NC
VOUT
VOUTB
SDA
CS
SCLK
Functional Block Diagram
Package Style: SSOP16 EDF Slug
Features
• Differential Input and Output
• 31dB Maximum V oltage Gain
• -25dB Minimum Voltage Gain
•5MHzto65MHzOperation
• Sophisticated Power Management
• DOCSIS 1.1 RF Compliant
Ordering Information
RF3321 ReversePath HighOutput Power Programmable
RF3321 PCBA Fully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 ThorndikeRoad
Greensboro,NC 27409, USA
Gain Amplifier
Tel (336)664 1233
Fax (336) 664 0454
http://www.rfmd.com
Rev A10 010516
2-1
Page 2
3
RF3321
Absolute Maximum Ratings
Parameter Rating Unit
Supply Voltage (V
Supply Voltage (V
Input RF Level 12 dBm
Operating Ambient Temperature -40 to +85 °C
Storage Temperature -40 to +150 °C
Humidity 80 %
Maximum Power Dissipation 0.5 W
Maximum T
J
) -0.5 to +5.5 V
CC1
) -0.5 to +7.5 V
CC2
150 °C
DC
DC
Preliminary
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correctand accurate
at thetime ofthis printing. However, RFMicro Devices reservesthe right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
LINEAR CATV
Specification
Unit Condition
V
=5V,V
CC1
V
=38dBmV (rms) differential, output
IN
impedance=75Ω through a 2: 1 transformer.
Typical performance is at TA=+25°C,
V
=5V.
CC
=7V, TXEN=SHDNB=1,
CC2
AMPLIFIERS
Overall
Parameter
Min. Typ. Max.
DC Specifications
Supply Voltage 1 (VCC1) 4.75 5.0 5.25 V Main chip supply
Supply Voltage 2 (VCC2) 6.65 7.0 7.35 V Output stage supply
Supply Current
Maximum Gain, SV1 85 100 mA Gain Control Word=56, V
Maximum Gain, SV2 135 150 mA Gain Control Word=56, V
Low Gain, SV1 75 90 mA Gain Control Word<28, V
Low Gain, SV2 55 70 mA Gain Control Word<28, V
Transmit Disable 25 35 mA TXEN=0, V
Shut Down 5 mA SHDNB=0, V
Logic High Voltage 2 V
Logic Low Voltage 0.8 V
Logic Leakage Current -1 1 µA
=5Vor 7V
CC2
CC2
CC2
CC2
CC2
CC2
=5Vor 7V
AC Specifications
Voltage Gain
Maximum 29 31 dB Gain Control Word=56, V
Minimum -25 -23 dB Gain Control Word=0, V
Bandwidth 100 MHz Intended operating range is 5MHz to
Maximum Input Level 40 dBmV(rms)
Maximum Output Level 69 dBmV(rms) Into 75Ω load at balun output (CW),
65 dBmV V
Output Harmonic Distortion -56 -50 dBc Output Level=68dBmV (rms) (CW)
Output Step Size 0.8 1.0 1.1 dB
Output Noise
Maximum Gain -35 -30 dBmV/
160kHz
Minimum Gain -50 -45 dBmV/
160kHz
Transmit Disabled -75 -70 dBmV/
160kHz
TX EN Enable Time 0.5 1.0 µS Time for gain to reach 99% of final value.
TX EN Transient Duration 2.4 3.0 µS See Note 1.
65MHz.
=7V
V
CC2
=5V
CC2
Maximum Gain, V
V
=5Vor 7V
CC2
=5Vor 7V
V
CC2
TXEN=0, V
See Note 1.
=5Vor 7V
CC2
=5Vor 7V
CC2
CC2
CC2
=5V or 7V
=5V or 7V
=5V or 7V
=5V or 7V
=5V or 7V
=5Vor 7V
2-2
Rev A10 010516
Page 3
Preliminary
RF3321
Parameter
AC Specifications, cont’d
Output Switching Transients
Maximum Gain 10 20 mV
MinimumGain 5 7 mV
Output Impedance 300 Ω Chip output impedance is nominally 300Ω.
Input Impedance 75 Ω Differential
Thermal
Theta
JC
Note 1: The enable time is determined by the value of the capacitor on pin 8 (RAMP). A higher capacitor value will
increase the enable time, but will reduce the transient voltage
Min. Typ. Max.
Specification
28 °C/W
Unit Condition
P-P
P-P
Differential to single-ended output conversion to 75Ω is performed in a balun w ith a
2:1 turns ratio,corresponding toa 4:1 impedance ratio.
.
3
LINEAR CATV
AMPLIFIERS
Rev A10 010516
2-3
Page 4
3
RF3321
Preliminary
Pin Function Description Interface Schematic
1 SHDNB
2TXEN
3NC
4VIN
Chip shutdown pin. Forcing a logic low causes all circuits to switch off
andgainsettingstobelost.
Signal path enable pin. Logic high turns on signal path. Logic low turns
off signal path, but leaves serial bus active.
Not connected.
Input pin. This should be externally AC-coupled to signal source.
V
CC
550 Ω 550 Ω
500 Ω 500 Ω
V
IN
V
INB
5VINB
LINEAR CATV
AMPLIFIERS
6 VCC1
7 VCC1
8 RAMP
9SCLK
10 CS
11 SDA
12 VOUTB
13 VOUT
14 NC
15 NC
16 GND
PKG
BASE
Serial Bus Block Diagram
GND
Complementary input pin. This should be externally coupled to signal
See pin 4.
source. For single-ended use, this pin should be AC-coupled to ground.
ThispinisconnectedtoVCC1.
Same as pin 6.
External capacitor to ground controls start-up time.
Serial bus clock input.
Serial bus enable.
Serial bus data input.
Open collector output. Connect to VCC2 via balun primary.
Open collector output. Connect to VCC2 via balun primary. See pin 12.
Same as pin 3.
Same as pin 3.
Connect to ground.
Die is mounted ona heat sink slug that shouldbe connected to ground.
Device grounds are internally bonded to the slug.
V
OUTVOUTB
300 Ω
RE
2-4
CS
SDA
SCLK
DCKQ
CLR
DCKQ
CLR
DCKQ
CLR
DCKQ
CLR
DCKQ
CLR
DCKQ
CLR
DCKQ
CLR
DCKQ
CLR
DCKQ
CLR
DCKQ
CLR
DCKQ
CLR
DCKQ
CLR
DCKQ
CLR
D0D1D2D3D4D5D6
DCKQ
CLR
POR
Rev A10 010516
Page 5
Preliminary
Table 1. Serial Interface Control Word Format
Bit Mnemonic Description
MSB 6 D6 Sleep Mode (Software Shutdown)
5 D5 Gain Control, BitMSB
4 D4 Gain Control, Bit 4
3 D3 Gain Control, Bit 3
2 D2 Gain Control, Bit 2
1 D1 Gain Control, Bit 1
LSB 0 D0 Gain Control, Bit LSB
RF3321
Serial Bus Timing D iagram
TES TDS TDH TEH
CS
SCLK
SDA
(Data)
TDATAH,TDATAL
D0 D1
D2
TWH
TC
D3 D4 D5 D6
3
LINEAR CATV
AMPLIFIERS
Table 2. Timing Data
Parameter Symbol Min T yp Max Units
SCLK Pulsewidth T
SCLK Period T
Setup Time, SDA versus S CLK T
Setup Time, CS versus S CLK T
Hold Time, SDA versus S CLK T
Hold Time, CS versus S CLK T
SCLK Pulsewidth, High T
SCLK Pulsewidth, Low T
Table 3. Programming State
WH
C
DS
ES
DH
EH
DAT AH
DATAL
50 ns
100 ns
10 ns
10 ns
20 ns
20 ns
50 ns
50 ns
TX SHDND MSB6
Enter Sleep Mode X H L H=High Voltage Logic
Exit Sleep Mode X H H* L=Low Voltage Logic
Enter Shutdown X L X X=Don’t Care
Exit Shutdown X H H* *Gain Control Data Must be Re-Sent
TX Enable H X X
TX Disable L X X
Rev A10 010516
2-5
Page 6
RF3321
Preliminary
Application Schematic
3
LINEAR CATV
SHDNB
TXEN
10 nF
VIN
10 nF
VINB
V
CC1
AMPLIFIERS
220 pF
1
2
3
4
5
6
7
8
Power
Control
Gain Control
and Serial Bus
PACKAGE BASE
16
15
14
13
12
100 pF
11
10
9
4:1
V
CC2
VOUT
SDA
CS
SCLK
2-6
Rev A10 010516
Page 7
Preliminary
J1
1
2
CS
3
SDA
4
SCLK
5
J5-1
6
J3-1
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Notes:
1. 4-layer board.
2. Underside of package must solder to ground.
3. Place C5and C6 as close to pin aspossible.
4. C1 andC10 are tantalum, size code Y.
5. All other componentsare 0603size.
6. ReplaceR6with0Ω resistor if 7 5 Ω connector is used.
VCC
R1
100 kΩ
R2
100 kΩ
NC
CS
SDA
SCLK
SHDNB
TXEN
NC
NC
NC
VCC
NC
NC
NC
VCC
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
Evaluation Board Schemati c
(Download Bill of Materials from www.rfmd.com.)
VCC2
VCC
VCC1
Power
Control
GainControl
and Serial Bus
L4 (Ferrite)
30 Ω
L2 (Ferrite)
30 Ω
L3 (Ferrite)
30 Ω
J6
RF IN
VCC1
J1-6
TXEN
J1-5
SHDNB
T1
1:1
3
2
1
R5
75 Ω
4
5
6
R4
75 Ω
C5
0.1 µF
J2
1
2
3
J4
1
2
3
C3
1nF
C4
1nF
C6
220 pF
VCC
GND
VCC
GND
1
2
3
4
5
6
7
8
PACKAGEBASE
3321400C
J3
1
2
3
J5
1
2
3
RF3321
R7
R8
L5 (Ferrite)
30 Ω
+
C11
1nF
L1 (Ferrite)
30 Ω
+
C2
1nF
16
15
14
13
12
11
10
9
15 pF
VCC
15 pF
C7
C8
C10
10 µF
(10 V)
C1
10 µF
(10 V)
T2
4:1
3
2
1
C9
100 pF
Q1
JP1
1
VCC 9V
2
VCC2
VCC1
3
GND
4
R6
24 Ω
4
5
6
VCC2
J7
RF OUT
SDA
CS
SCLK
3
LINEAR CATV
AMPLIFIERS
Rev A10 010516
2-7
Page 8
3
LINEAR CATV
RF3321
Preliminary
Evaluation Board Layout
Board Size 2.5” x 2.5”
Board T hickness 0.058”, Board Material FR-4, Multi-Layer
AMPLIFIERS
2-8
Rev A10 010516
Page 9
Preliminary
RF3321
Gain versus Frequency
30.0
20.0
10.0
0.0
-10.0
Voltage Gain(dB)
-20.0
-30.0
-40.0
0 50 100 150 200 250
Frequency (MHz)
Gain versus Supply Voltage (V
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
Voltage Gain(dB)
-1.4
-1.6
-1.8
-2.0
4.70 4.80 4.90 5.00 5.10 5.20 5.30
at Gain Control Word =25
SupplyVoltage V
Gain Control Word=56
Gain Control Word=25
Gain Control Word=0
CC1
(V)
CC1
)
5MHz
42 MHz
65 MHz
Gain versus Supply Voltage (V
29.2
29.1
29.0
28.9
28.8
28.7
28.6
Voltage Gain(dB)
28.5
28.4
28.3
28.2
4.70 4.80 4.90 5.00 5.10 5.20 5.30
at Gain Control Word =56
Supply Voltage V
CC1
Gain versus Supply Voltage (V
29.2
29.1
29.0
28.9
28.8
28.7
Voltage Gain(dB)
28.6
28.5
28.4
28.3
6.65 6.75 6.85 6.95 7.05 7.15 7.25 7.35
at Gain Control Word =56
Supply Voltage V
CC2
(V)
(V)
CC1
CC2
)
)
5MHz
42 MHz
65 MHz
5MHz
42 MHz
65 MHz
3
LINEAR CATV
AMPLIFIERS
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
Voltage Gain(dB)
-1.4
-1.6
-1.8
-2.0
6.65 6.75 6.85 6.95 7.05 7.15 7.25 7.35
Rev A10 010516
Gain versus Supply Voltage (V
at Gain Control Word =25
SupplyVoltage V
CC2
(V)
CC2
)
5MHz
42 MHz
65 MHz
2-9
Page 10
RF3321
Preliminary
3
LINEAR CATV
Gain versus Gain Control Word at 5 MHz
30.0
20.0
10.0
0.0
Voltage Gain(dB)
-10.0
-20.0
AMPLIFIERS
-30.0
01020304050
GainControlWord
Voltage Gain(dB)
30.0
20.0
10.0
0.0
-10.0
-20.0
-30.0
Gain versus Gain Control Word at 65 MHz
-30
-40
-50
-60
Second Harmonic(dBc)
-70
Voltage Gain(dB)
30.0
20.0
10.0
0.0
-10.0
-20.0
Gain versus Gain Control Word at 42 MHz
01020304050
GainControlWord
Second Harmonic versus Frequency andOutput Level
65 MHz
42 MHz
5MHz
2-10
-30.0
01020304050
GainControlWord
Third Harmonic versus Frequency andOutput Level
-50
-55
-60
-65
-70
Third Harmonic(dBc)
-75
-80
30 35 40 45 50 55 60
PowerOut (dBmV)
65 MHz
42 MHz
5MHz
-80
30 35 40 45 50 55 60
Output Level (dBmV)
Rev A10 010516
Page 11
Preliminary
RF3321
-1 dBCompression Point
72.0
70.0
68.0
66.0
Power Out(dBmV)
64.0
62.0
60.0
33.0 35.0 37.0 39.0 41.0 43.0 45.0
at Gain Control Word =56
Gain Control Word=56
Trend
Power In(dBmV)
-1 dBCompression Point
44.0
43.0
42.0
41.0
40.0
39.0
Power Out(dBmV)
38.0
37.0
36.0
35.0
38.0 39.0 40.0 41.0 42.0 43.0 44.0 45.0 46.0 47.0
at Gain Control Word =29
GainControl Word=29
Trend
Power In(dBmV)
3
LINEAR CATV
AMPLIFIERS
Rev A10 010516
2-11
Page 12
RF3321
Preliminary
Evaluation Kit
3
General Description
The RF3321 PCBA is a fully assembled evaluation
board of the RF3321 reverse path high output power
programmable gain amplifier, useful for providing a
demonstration of the RF3321’s functionality. The
RF3321 PCBA is a digitally controlled variable gain
amplifiercapable of driving a 75Ω source. The RF3321
is designed to send cable modem data with QPSK or
QAM modulated format at frequencies between 5 MHz
and 65MHz. The gain is controlled by an 7-bit serial
data word which adjusts the output gain from -25dB to
+31dB.
The kit includes a fully functional evaluation board
AMPLIFIERS
LINEAR CATV
along with a serial data cable and software. The cable
connects directly to the parallel port of a standard PC.
The software is used to control the serially programmable gain through a s imple, easy to understand user
interface.
Input and output to the evaluation board is provided
through 50Ω SMA connectors. The input and output of
the evaluation board is matched to 50Ω and connected
through a balun for single-ended operation. This allows
easy connection to test equipment, but the evaluation
board can easily be converted to a 75Ω input and output, or for differential input and output. The output circuit is matched using a 24Ω series resistor which is
used to bring the load impedance up to 75Ω when
using standard 50Ω test equipment. This will introduce
a loss which must be accounted for in all measurements (see measurementsection and evaluation board
schematic for more detail.)
device to 75Ω. This introduces a voltage loss of 3.5dB
which must be accounted for in all measurements.
Some spectrum analyzershave a setting to account for
this method of 75Ω testing (e.g., on a Rhode &
Schwartz spectrum analyzer the input can be set to
'”75Ω RAZ” and the loss is accounted for automatically). A more accurate way of making this measurement is to use a 75Ω spectrum analyzer, or use a
matching transformer or minimum loss pad. This
ensures that the s ource impedance seen by the equipment is also 75Ω.Ifa75Ω output is required, simply
replace the 50Ω SMA connector (J7) with a 75Ω Fstyle connector and replace R5 with a 0Ω jumper. The
evaluation board is tested with a Coilcraft balun; however, additional baluns may be used as long as care is
taken in modifying the decoupling capacitors around
the balun. These capacitors can greatly affect the harmonic s uppression. Other baluns may be used but
should be tested for second and third order harmonic
suppression.
Transmit Enable
The transmit enable can be set to “continuous on” by
placing the TXEN jumper in the up position (up position
when viewing the top of the evaluation board with the
25-pin connector closest to the viewer) and placing the
associated GND/VCC jumper in the “VCC” position.
The transmit enable can be set to “continuous off” by
placing the GND/VCC jumper in the “GND” position. If
a computer controlled signal is used (J1), place the
TXEN jumper in the down position.
GND VCC
GND VCC
GND VCC
PCBA Details
Input Circuit
The input to the RF3321 is differential and the impedance is 75Ω; However, for ease of testing, the evaluation board has been changed to single-ended and the
impedance has been matched to 50Ω.Ifa75Ω input is
required, simply replace the 50Ω SMA connector with
a75Ω F-style connector and remove R4 and R5.
Output Circuit
The output of the RF3321 is differential and the impedance is 300Ω. In nor m al applications this is converted
into a single-ended 75Ω output using a 2:1 (voltage
ratio) transformer with a center-tap on the secondary
which supplies power to the output stage. The evaluation board is configured for use with 50Ω test equipment. This has been achieved with a 24Ω resistor in
series with the output to increase the load seen by the
2-12
TX EN
Continuous ON
A
TX EN
Continuous OFF
B
Figure 1. TX Enable Configuration
TX EN
Software Controlled
C
Rev A10 010516
Page 13
Preliminary
RF3321
Shutdown Enable
Shutdown enable can be set to be “continuous on”
(chip enabled) by placing the SHDN jumper in the up
position and placing the associated GND/VCC jumper
in the “VCC” position. Shutdown enable can be set to
“continuous off” (chip disabled) by placing the associated GND/VCC jumper in the “GND” position. If a computer controlled signal is used (J1), place the SHDN
jumper in the down position.
GNDVCC
C
SHDN
Continuous OFF
A
GNDVCC
SHDN
GNDVCC
Continuous ON
B
SHDN
Software Controlled
Figure 2. SHDN Enable Configuration
V
Settings
CC
V
should be set to 5.0VDC.
CC1
should be set to 7.0VDC.
V
CC2
Evaluation Board Setup
Equipment Needed
• Signal Generator
• Spectrum Analyzer
• Power Supply (5.0V@300mA)
• RF3321 PCBA
• Serial Cable (included with kit)
• Standard PC
• Three-Wire Bus Software
Optional Equipment
• Variable Low-Pass or Band-Pass Filters
• Power Meter
• Second Signal Generatorwith ModulationforACPR
and IP2, IP3 Testing
• Arbitrary Wave Generator
• Two-Channel Oscilloscope
Unzip the file using WinZip 7.0 or higher (http://
www.winzip.com). Unzip to a temporary directory and
run RF3321.exe.
The 7-bit Gain Control Word (GCW) in the data latch
determines the gain setting in the RF3321. The gain
control data (SDA) load sequence is initiated by a falling edge on CS. The SDA is serially loaded (LSB first)
into the 7-bit shift register at each rising edge of the
clock. W hile CS is low, the data latch holds the previous data word allowing the gain level to remain
unchanged. After seven clock cycles the new data
word is fully loaded and CS is switched high. This
enables the data latch and the loaded register data is
passed to the gain control block with the updated gain
value. Also at this CS transition, the internal clock is
disabled, thus inhibiting new serial input data.
Software and Cable
Figure 3 shows the cable configuration. Connect the
cable into the LPT1 port of the computer running the
software. Connect the other end of the cable to the 25pin connector of the evaluation board. Executing the
software (RF3321.exe) will produce the screen shown
in Figure 4. The user may set the gain of the evaluation
board by sliding the gain control switch to the desired
gain setting. Pressing the Preset Gain Value buttons
automatically sets the gain of the unit to the value
shown on the button. The Automatic Gain Adjustment
when set to “Cycle” will automatically cycle through all
of the gain steps (0-56) in seconds (at the rate set by
the user). The user may place the unit in sleep, shutdown and transmit enable/disable m odes by checking
the corresponding box. The bit pattern being sent to
the PCBA is shown at the bottom of the screen. See
README_3321.txt file for proper pin/signal mapping
for the 25 pin interface.
3
LINEAR CATV
AMPLIFIERS
Software Setup
To install the software, you need a computer with the
following.
• 133MHz Pentium processor
•16MBRAM
• Hard Drive with 5MB free space
• Free 25-pin LPT por t
• VGA Monitor
The software may be downloaded from www.rfmd.com
by following these steps.
Select the “Product Support” tab;
Select “Evaluation Board Information”;
Select “RF3321”.
Rev A10 010516
2-13
Page 14
Preliminary
RF3321
RF3321 PCBA Cable
3
6 TX Enable Line
18Ground
5SHUTDOWNLine
4 CLK Line
3DataLine
2CSLine
25 Pin D-Connector (Back View)
Figure 3. Cable Configuration
Hardware Setup
Gain and Harmonic Distortion Test Setup
To test the gain of the RF3321 PCBA, connect a lowpass or band-pass filter to the output of the signal generator. Use a filter just above the frequency youwantto
test. The filter is used to attenuate any harmonics output by the signal generator. Connect the signal generator to the power meter and measure the power.
Compare with modulation enabled and disabled to
make sure the meter was measuring average rather
than peak power. No more than 0.2dB difference in
powershouldbeobserved.An offset on the signal generator may be needed to match the level shown on the
power meter. The signal generator should then be connected directly to a spectrum analyzer. M ake sure the
output of the signal generator is the same as the input
read by the spectrum analyzer. Adjust the offset of the
spectrum analyzer until the signal out is the same as
the signal in on the spectrum analyzer. Turn off the RF
and modulation. Check positioning of the jumpers on
the board. Refer to the PCBA section of this application note to verify proper positions. Connect the output
of the signal generator to J6: RFIN of the PCB. Connect J7: RFOUT to the spectrum analyzer. Ensure that
Figure 4. On-Screen Display
you are accounting correctly for the losses in the 75 Ω
to 50Ω conversion at the output of the device; there is
an output voltage loss of 3.5dB for the evaluation
board in its standard configuration (see output stage
circuit description). Connect one end of the serial cable
into the computer and the other end into J1 of the PCB.
Connect +5.0V
Turn on the DC power and turn on RF from the signal
generator. Set the GCW to 56 and make sure TX
Enable is checked. The amplified signal should be displayed on the spectrum analyzer. The harmonics can
also be viewed with this setup. As you change the
GCW from 56 to 0 (in steps of one), there will be a 1dB
change in the output of the PCB.
into V+ and ground into GND(JP1).
DC
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Preliminary
RF3321
ACPR Test Setup
To test the ACPR of the RF3321 PCBA set modulation
to:
•QPSK
• 2Bits/Sym
• 160ksps
• α=0.25
• PRBS-20bit Data
Set signal generator to:
•45MHz,
• - 13.0dBm output power,
• 0dB offset.
Connect 50MHz coaxial filter to output, then to output
cable.
Zero and calibrate the power meter. Connect signal
generator to power meter and set offset on signal generator until power meter reads -13.0dBm. Make sure
power meter reads the same (±0.2dBm) with modulation enabled and disabled to verify power meter is
measuring average power rather than peak power.
Check positioning of the jumpers on the board. Refer
to the PCBA section of this application note to verify
proper positions. Connect the output of the signal generator to J6: RFIN of the PCB. Connect J7: RFOUT to
the power meter. Connect one end of the serial cable
into the computer and the other end into P1 of the
PCB. Connect+5.0V
Turn on the DC power and turn on RF and modulation
from the signal generator. Set the GCW to 56 and
make sure TX Enable is checked. Measure and record
channel power at RFOUT using the power meter
(accounting for 75/50 conversion losses). Connect
RFOUT to spectrum analyzer and adjust offset of the
spectrum analyzer until the channel power displayed
by the spectrum analyzerisequaltothe channelpower
recorded in the previous step (Channel bandwidth =
200 kHz). Now use the spectrum analyzer to measure
relative ACP (this way the uncertainties in the spectrum analyzer power measurement are immaterial).
The ACP is measured in 200 kHz channel bandwidths
at a 220kHz offset (i.e., from 20kHz to 220kHz outside
the channel). As you increase the input power, you will
notice a degradation of the ACP upper and lower
bands.
into VCCand ground into GND.
DC
Transmit Turn-On and Turn-Off Transients
UseanArbitraryWaveformGeneratorsettoa3V
square wave, 5% duty cycle, 120Hz as the input to the
transmit enable. Set a signal generator to 10 MHz,
-13.0 dbm output power, 0dB offset. Connect output of
the signal generator to J6, RFIN of the PCB. Remove
the TXEN jumper and connect the arbitrary wave generator square wave output to the center pin of the
TXEN 3-pin header. Connect the output of the evaluation board to the oscilloscope (channel 1). Connect the
TXEN signal from the arbitrary wave generator to
channel 2 of the oscilloscope and tr igger off of the rising edge. As the TXEN line is sent, the oscilloscope
will trigger and capture the pulsed RFOUT signal. This
will be displayed on the oscilloscope. Measure the
amount of time between 90% of the TXEN turn-on to
where the output signal reaches 90% of full turn-on.
This is defined as the transmit turn-on time.
To measure the transient pulse, replace the signal generator input with a 50Ω terminator and repeat the steps
above. Measure the size of the transient. This can be
affected by the C
balun and capacitor values around the balun. Larger
values of C
and increase the TX enable time.
PCB Layout Considerations
The RF3321 Evaluation board can be used as a guide
for the layout in your application. Care should be taken
in laying out the RF3321 in other applications. The
RF3321 will have similar results if the following guidelines are taken into consideration:
• Make sure underside of package is soldered to a
good ground on the PCB.
• Move C2, C7, C8, and C9 as close to T1 as possible.
• Keep input and output traces as short as possible.
• Ensure a good ground plane by using multiple vias
to the ground plane.
• Use a low noise power supply along with decoupling capacitors
RAMP
capacitor (C6), and the output
RAMP
will decrease the transient voltage
3
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Preliminary
Special Handling Information for Shrunk Small
Outline Package (SSOP1-EPP) Products
These packages are considered JEDEC Level 5 for
moisture sensitivity and require special handling to
assure reliable performance.
The exposed copperslugonthebottomofthepackage
improves both thermal and electrical performance.
Since the RFIC is mounted directly on the thermal
slug, and the slug is soldered directly on the PCB, the
thermal resistance to the PCB is minimized. Also, the
RF ground for the amplifier is established through this
copper slug as it is soldered to the ground plane on the
PCB. This offers the least inductance ground path
available.
RF3321
3
Care must be taken when soldering these packages to
the PCB. They are currently considered JEDEC Level
5 for moisture sensitivity. Therefore the parts must be
handled in a dry environment prior to soldering, as is
specified in the JEDEC specification. Specifically,
RFMD recommends the following procedure prior to
assembly:
1. Dr y-bake the par ts at 125°C for 24 hours minimum.
Note: the shipping tubes cannot withstand 125°C
baking temperature.
2. Parts delivered on tape and reel are already drybaked and dry-packed. These may be stored for up
to one year, but must be assembledwithin 48 hours
after opening the bag.
3. Assemble the dry-baked parts within two days of
removal from the oven.
4. During this two-dayperiod, the parts mustbestored
in humidity less than 60%.
IMPORTANT!
If the two-day period is exceeded, then this procedure
must be repeated prior to assembly.
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