Page 1
2-459
Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching® Applied
Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS
SiGe HBT
Si CMOS
InGaP/HBT
GaN HEMT SiGe Bi-CMOS
VCC OUT
DCS OUT
VCC2
DCS IN
BAND SELECT
VREG
VRAMP
TX ENABLE
VBATT
GSM OUT
VCC2
GSM IN
10
11
12
1
3
2
6
5
4
9
8
7
RF3133
QUAD-BAND GSM850/GSM/DCS/PCS
POWER AMP MODULE
• 3V Quad-Band GSM Handsets
• Commercial and Consumer Systems
• Portable Battery-Powered Equipment
• GSM850, EGSM900, DCS/PCS Products
• GPRS Class 12 Compatible
The RF3133 is a high-power, high-efficiency power amplifier module with integrated power control. The device is
self-contained with 50Ω input and output ter minals. The
power control function is also incorporated, eliminating
the need for directional couplers, detector diodes, power
control ASICs and other power control circuitry; this
allows the module to be driven directly from the DAC output. The device is designed for use as the fin al RF amp lifier in GSM850, EGSM900, DCS and PCS handheld
digital cellular equipment and other applications in the
824 MHz to 849 MHz, 880 MHz to 915 MHz, 1710 MHz to
1785 MHz, and 1850 MHz to 1910 MHz bands. On-board
power control provides over 37dB of control range with an
analog voltage input; and, power down with a logic “low”
for standby operation.
• Complete Power Control Solution
• Single 2.9V to 5.5V Supply Voltage
• +35dBm GSM Output Power at 3.5V
• +33dBm DCS/PCS Output Power at 3.5V
• 55% GSM and 52% DCS/PCS
η
EFF
RF3133 Quad-Band GSM850/GSM/DCS/PCS Power Amp
Module
RF3133 PCBA Fully Assembled Evaluation Board
0
Rev A4 030527
NOTES:
Shaded areas represent pin 1 location.
1
7.00
± 0.10
10.00
± 0.10
1
1.40
1.25
0.450
± 0.075
1
8.40 TYP
7.60 TYP
6.00
5.40 TYP
4.60 TYP
4.00
2.40 TYP
1.60 TYP
0.00
5.50
3.00
6.30 TYP
6.70 TYP
0.00
0.10 TYP
0.90 TYP
1.50
3.10 TYP
3.90 TYP
6.10 TYP
6.90 TYP
8.50
9.10 TYP
9.90 TYP
0.10 TYP
1.10 TYP
1.70 TYP
2.50 TYP
3.10 TYP
3.90 TYP
4.60 TYP
5.40 TYP
6.10 TYP
6.90 TYP
Package Style: Module
!
!
查询RF3133供应商
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RF3133
Rev A4 030527
Absolute Maximum Ratings
Parameter Rating Unit
Supply Voltage -0.3 to +6.0 V
DC
Power Control Voltage (V
RAMP
) -0.3 to +1.8 V
Input RF Power +11.5 dBm
Max Duty Cycle 50.0 %
Output Load VSWR 10:1
Operating Temperature -20 to +85 °C
Storage Temperature -55 to +150 °C
Parameter
Specification
Unit Condition
Min. Typ. Max.
Power Control V
RAMP
Power Control “ON” 1.5 V Max. P
OUT
, Voltage supplied to the input
Power Control “OFF” 0.2 0.25 V Min. P
OUT
, Voltage supplied to the input
Power Control Range 35 dB V
RAMP
=0.2V to V
RAMP MAX
V
RAMP
Input Capacitance 15 20 pF DC to 2MHz
V
RAMP
Input Current 10 µAV
RAMP=VRAMP MAX
Turn On/Off Time 2 µSV
RAMP
=0V to V
RAMP MAX
Overall Power Supply
Power Supply Voltage 3.5 V Specifications
3.0 5.5 V Nominal operating limits
3.0 4.3 V 50% duty cycle, Pulse width=2308µs
V
RAMP
0.2 1.33 V 50% duty cycle, 824MH z to 915MHz
0.2 1.28 50% duty cycle, 1710MHz to 1910MHz
Powe r Supply Current 1 10 µAP
IN
<-30dBm, TXEnable=Low,
Temp=-20°C to +85°C
V
REG
Voltage 2.7 2.8 2.9 V
V
REG
Current 7 8 mA TX Enable=High
10 µA TX Enable=Low
Overall Control Signals
Band Select “Low” 0 0 0.5 V
Band Select “High” 1.3 2.0 3.0 V
Band Select “High” Current 20 50 µA
TX Enable “Low” 0 0 0.5 V
TX Enable “High” 1.3 2.0 3.0 V
TX Enable “High” Current 1 2 µA
Note: V
RAMP
Max=3/8*V
BATT
+0.18<1.5V
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Page 3
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RF3133
Rev A4 030527
Parameter
Specification
Unit Condition
Min. Typ. Max.
Overall (GSM850 Mode)
Temp= +25 °C, V
BATT
=3.5V, PIN=+2dBm,
V
REG
=2.8V, V
RAMP=VRAMP MAX
,
Freq=824MHz to 849MHz, 25% Duty Cycle,
Pulse Width=1154µs
Operating Frequency Range 824 to 849 MHz
Maximum Output Power +33.8 +35.0 dBm Temp = 25°C, V
BATT
=3.5V,
V
RAMP=VRAMP MAX
+31.5 +32.5 dBm Temp=+85°C, V
BATT
=3.0V,
V
RAMP=VRAMP MAX
Total Current 1.3 A P
OUT
=+31dBm
Total Efficiency 40 50 % At P
OUT MAX
, V
BATT
=3.5V
Input Power Range 0 +2 +5 dBm Full output power guaranteed at minimum
drive level
Output Noise Power -86 -82 dBm RBW=100kHz, 869MHz to 879MHz,
P
OUT
> +5dBm
-87 -83 dBm RBW=100kHz, 879MHz to 894MHz,
P
OUT
> +5dBm
Forward Isolation 1 -30 dBm TXEnable=Low, 0V, P
IN
=+5dBm
Forward Isolation 2 -2 dBm TXEnable=High, P
IN
=+5dBm, V
RAMP
=0.2V
Cross Band Isolation at 2f
O
-18 -13 dBm V
RAMP
=0.2V to V
RAMP MAX
Second Harmonic -18 -5 dBm V
RAMP
=0.2V to V
RAMP MAX
Third Harmonic -28 -15 dBm V
RAMP
=0.2V to V
RAMP MAX
All Other
Non-Harmonic Spurious
-36 dBm V
RAMP
=0.2V to V
RAMP MAX
Input Impedance 50 Ω
Input VSWR 2.5:1 V
RAMP
=0.2V to V
RAMP MAX
Output Load VSWR Stability 8:1 Spurious<-36dBm, RBW=3M Hz, Set V
RAMP
where P
OUT
<34.0dBm into 50Ω load
Output Load VSWR Ruggedness 10:1 Set V
RAMP
where P
OUT
<34.0dBm into 50Ω
load. No damage or permanent degradation
to part.
Output Load Impedance 50 Ω Load impedance presented at RF OUT pad
Note: V
RAMP
Max=3/8*V
BATT
+0.18<1.5V
Page 4
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RF3133
Rev A4 030527
Parameter
Specification
Unit Condition
Min. Typ. Max.
Overall (EGSM900 Mode)
Temp= +25 °C, V
BATT
=3.5V, V
RAMP
Max,
P
IN
=+2dBm, V
RAMP=VRAMP
Max,
V
REG
=2.8V, Freq=880MHz to 915MHz,
25% Duty Cycle, Pulse Width=1154µs
Operating Frequency Range 880 to 915 MHz
Maximum Output Power +34.2 +35.0 dBm Temp = 25°C, V
BATT
=3.5V,
V
RAMP=VRAMP
Max
+32.0 +32.8 dBm Temp=+85°C, V
BATT
=3.0V,
V
RAMP=VRAMP
Max
Total Efficiency 47 53 % At P
OUT,MAX
, V
BATT
=3.5V
Input Power Range 0 +2 +5 dBm
Output Noise Power -86 -74 dBm RBW=100kHz, 925MHz to 935MHz,
P
OUT
> +5dBm
-88 -82 dBm RBW=100kHz, 935MHz to 960MHz,
P
OUT
> +5dBm
-80 dBm RBW=100kHz, 1805MHz to 1880MHz and
1930MHz to 1990MHz, P
OUT
>0dBm
-73 dBm f=925MHz to 960MHz,
RBW=VBW=100kHz
Forward Isolation 1 -35 -30 dBm TX_ENABLE=0V, P
IN
=+5dBm
Forward Isolation 2 -2 dBm TX_ENABLE=High, P
IN
=+5dBm,
V
RAMP
=0.2V
Crossband Isolation at 2f
0
-28 -20 V
RAMP
=0.2V to V
RAMP
Max
Second Harmonic -10 -5 dBm V
RAMP
=0.2V to V
RAMP MAX
Third Harmonic -21 -15 dBm V
RAMP
=0.2V to V
RAMP MAX
All other Non-Harmonic Spurious -36 dBm V
RAMP
=0.2V to V
RAMP MAX
Input Impedance 50 Ω
Input VSWR 2.5:1 V
RAMP
=0.2V to V
RAMP MAX
Output Load VSWR Stability 8:1 Spurious<-36dBm, RBW=3MHz, Set V
RAMP
where P
OUT
<34.2dBm into 50Ω load
Output Load VSWR Ruggedness 10:1 Set V
RAMP
where P
OUT
<34.2dBm into 50Ω
load. No damage or permanent degradation
to part.
Output Load Impedance 50 Ω Load impedance presented at RF OUT pad
Note: V
RAMP
Max=3/8*V
BATT
+0.18<1.5V
Page 5
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RF3133
Rev A4 030527
Parameter
Specification
Unit Condition
Min. Typ. Max.
Overall (DCS/PCS Mode)
Temp= 25°C, V
BATT
=3.5V, PIN=+2dBm,
V
REG
=2.8V, V
RAMP =VRAMP
Max,
Freq=1710MHz to 1910MHz,
25% Duty Cycle, Pulse Width=1154µs
Operating Frequency Range 1710 to 1910 MHz
Maximum Output Power +32.0 +34.0 dBm Temp=+25°C, V
BATT
=3.5V, V
RAMP =VRAMP
Max, 1710MHz to 1785MHz
+31.7 +32.7 dBm 1850MHz to 1910MHz
+31.0 +31.8 dBm Temp=+85°C, V
BATT
=3.0V,
V
RAMP
= V
RAMP
Max, 1710MHz to 1785MHz
+29.5 +30.5 dBm 1850MHz to 1910MHz
Total Efficiency 45 50 % At P
OUT,MAX, VBATT
=3.5V, 1710-1785MHz
44 48 1850MHz to 1910MHz
Input Power Range 0 +2 +5 dBm
Output Noise Power -77 dBm RBW=100kHz, 1805MHz to 1880MHz and
1930MHz to 1990MHz, P
OUT
> 5dBm,
V
BATT
=3.5V
Forward Isolation 1 -37 -30 dBm TX_ENABLE=0V, P
IN
=+5dBm
Forward Isolation 2 -1 dBm TX_ENABLE=High, P
IN
=+5dBm,
V
RAMP
=0.2V
Second Harmonic -25 -5 dBm V
RAMP
=0.2V to V
RAMP MAX
Third Harmonic -30 -15 dBm V
RAMP
=0.2V to V
RAMP MAX
All other Non-Harmonic Spurious -36 dBm V
RAMP
=0.2V to V
RAMP MAX
Input Impedance 50 Ω
Input VSWR - 2.5 V
RAMP
=0.2V to V
RAMP MAX
Output Load VSWR Stability 8:1 Spurious<-36dBm, RBW=3M Hz, Set V
RAMP
where P
OUT
<32.0dBm into 50Ω load
Output Load VSWR Ruggedness 10:1 Set V
RAMP
where P
OUT
<32.0dBm into 50Ω
load. No damage or permanent degradation
to part.
Output Load Impedance 50 Ω Load impedance presented at RF OUT pin
Note: V
RAMP
Max=3/8*V
BATT
+0.18<1.5V
Page 6
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RF3133
Rev A4 030527
Pin Function Description Interface Schematic
1 DCS/PCS IN
RF input to the DCS band. This is a 50Ω input.
2 BAND
SELECT
Allows external control to select the GSM or DCS band with a logic high
or low . A logic lo w enabl es the GSM band whereas a logic hi gh enab les
the DCS band.
3 TX ENABLE
This signal enables the P A module for operation with a logic high. Once
TX Enable is asserted the RF output level will increase to -2dBm.
4VBATT
Power supply for the module. This should be connected to the battery.
5VREG
Regulated voltage input for power control function. (2.8V nom)
6 VRAMP
Ramping signal from DAC. A simple RC filter may need to be connected between the DAC output and the VRAMP input depending on
the baseband selected.
7 GSM IN
RF input to the GSM band. This is a 50Ω input.
8VCC2
Controlled voltage input to driver stage for GSM bands. This voltage is
part of the power control function for the module. This node must be
connected to V
CC
out.
9GSM OUT
RF output for the GSM band. This is a 50Ω output. The output load line
matching is contained internal to the package.
10 VCC OUT
Controlled voltage output to feed V
CC2
. This voltage is part of the
power control function for the module. It can not be connected to anything other than V
CC2
, nor can any component be placed on this node
(i.e., decoupling capacitor).
11 DCS/PCS
OUT
RF output for the DCS band . Thi s i s a 50Ω output. The output load line
matching is contained internal to the package.
12 VCC2
Controlled voltag e inpu t to DCS driv e r stag e . Thi s v ol tag e is part of the
power control function for the module. This node must be connected to
V
CC
out.
Pkg
Base
GND
Page 7
2-465
RF3133
Rev A4 030527
Pin Out
VCC2
DCS/PCS IN
BAND SELECT
TX EN
VBATT
VREG
VRAMP
GSM IN
VCC2
GSM OUT
VCC OUT
DCS/PCS OUT
PIN #1
7.00
10.00
Page 8
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RF3133
Rev A4 030527
Application Schematic
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
10
11
12
1
3
2
6
5
4
9
8
7
50 Ω µstrip
50 Ω µstrip
50 Ω µstrip
50 Ω µstrip
DCS/PCS IN
BAND SELECT
TX ENABLE
VBATT
VREG
VRAMP
GSM IN
DCS/PCS OUT
GSM OUT
15 kΩ**
** Used to filter noise and spurious from baseband.
2.2 nF
10
11
12
1
3
2
6
5
4
9
8
7
50 Ω µstrip
50 Ω µstrip
50 Ω µstrip
50 Ω µstrip
BAND SELECT
TX ENABLE
VBATT
VREG
VRAMP
3.3 µF*
1 nF*
*Not required in most applications.
GND
P1
1
CON1
DCS/PCS IN
GSM IN
DCS/PCS OUT
GSM OUT
** Used to filter noise and spurious from baseband.
15 kΩ**
VCC
P2
1
CON1
P2-1
2.2 nF
Page 9
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RF3133
Rev A4 030527
Evaluation Board Layout
Board Size 2.0” x 2.0”
Board Thickness 0.032”, Board Material FR-4, Multi-Layer
Page 10
2-468
RF3133
Rev A4 030527
Theory of Operation
Overview
The RF3133 is a quad-band GSM/DCS/PCS power amplifier module that incorporates an indirect closed loop method of
power control. This simplifies the phone design by eliminating the need for the complicated control loop design. The indirect closed loop is fully self contained and req uired does no t requir e loop optimiz ation. It can be dr iven directly from the
DAC output in the baseband circuit.
Theory of Operation
The indirect closed loop is essentially a closed loop method of power control that is invisible to the user. Most power control systems in GSM sense eith er for wa rd power or collector/dra in cu rrent. The RF 3133 d oes not use a po w er de tector. A
high-speed control loop is incor porated to regulate the collector voltages of the amplifier while the stages are held at a
constant bias. The V
RAMP
signal is multiplied and the collector voltages are regulated to the multiplied V
RAMP
volta ge.
The basic circuit is shown in the following diagram.
By regulating the power, the stages are held in saturation across all power levels. As the required output power is
decreased from full power down to 0 dBm, the collector voltage is also decreased. This regulation of output power is
demonstrated in Equation 1 where the relationship between collector voltage and output power is shown. Although load
impedance affects output power, supply fluctuations are the dominate mode of power variations. With the RF3133 regulating collector voltage, the dominant mode of power fluctuations is eliminated.
(Eq. 1)
There are several key factors to consider in the implementati on of a transmitter solution for a mobile phone. Some of
them are:
• Effective efficiency (η
eff
)
• Current draw and system efficiency
• Power variation due to Supply Voltage
• Po wer variation due to frequency
• Po wer variation due to temperature
• Input impedance variation
• Noise power
• Loop stability
• Loop bandwidth variations across power levels
• Burst timing and transient spectrum trade offs
• Harmonics
RF IN
TX ENABLE
RF OUT
H(s)
VRAMP
TX ENABLE
VBATT
P
dBm
10
2 V
CCVSAT
–⋅()
2
8 R
LOAD
10
3–
⋅⋅
-------------------------------------------
log⋅=
Page 11
2-469
RF3133
Rev A4 030527
Talk time and power management are key concerns in transmitter design since the power amplifier has the highes t current draw in a mobile terminal. Considering only the power amplifier’s efficiency does not provide a true picture for the
total system efficiency. It is important to consider effe ctive efficiency which is represented by η
EFF
. (η
EFF
considers the
loss between the PA and antenna and is a more accurate measurement to determine how much current will be drawn in
the application). η
EFF
is defined by the following relationship (Equation 2):
(Eq. 2)
Where P
N
is the sum of all positive and negative RF power, PIN the input power and PDC is the delivered DC power . In dB
the formula becomes (Equation 3):
(Eq. 3)
Where P
PA
is the output power from the PA, P
LOSS
the insertion loss, PIN the input power to the PA and PDC the deliv-
ered DC power.
The RF3133 improves the effective efficiency by minimizing the P
LOSS
term in the equation. A directional coup ler may
introduce 0.4dB to 0.5dB loss to the transit path. To demonstrate the improvement in effective efficiency consider the following example:
Conventional PA Solution:
RF3133 Solution:
The RF3133 solution improves effective efficiency 5%.
Output power does not vary due to supply voltage under normal operating conditions if V
RAMP
is sufficiently lower than
V
BATT
. By regulating the collector voltage to the PA the voltage sensitivity is essentially eliminated. This covers most
cases where the PA will be operated. However, as the battery discharges and approach es its lower power range the
maximum output power from the PA will also drop slightly. In this case it is important to also decrease V
RAMP
to prevent
the power control from inducing switching transients. These transients occur as a result of the control loop slowing down
and not regulating power in accordance with V
RAMP
.
η
EFF
PNPIN–
n 1=
m
∑
P
DC
--------------------------------
100⋅=
η
EFF
10
PPAP
LOSS
+
10
----------------------------- -
10
P
IN
10
------- -
–
V
BATIBAT
10⋅⋅
------------------------------------------------ -
=
PPA = +33 dBm
P
IN
= +2 dBm
P
LOSS
= -0.4 dB
V
BAT
= 3.5 V
I
BAT
= 1.1 A
η
EFF
= 47.2%
P
PA
= +33 dBm
P
IN
= +2 dBm
P
LOSS
= 0 dB
V
BAT
= 3.5 V
I
BAT
= 1.1 A
η
EFF
= 51.72%
Page 12
2-470
RF3133
Rev A4 030527
The switching transients due to low battery conditions are regulated by incorporating the following relationship limiting
the maximum V
RAMP
voltage (Equation 2). Although no compensation is required for typica l batter y conditions, the bat-
tery compensation required for extreme conditions is covered by the relationship in Equation 4 . This sh ould b e add ed to
the terminal software.
(Eq. 4)
Note: Output power is limited by battery voltage. The relationship in Equation 4 does not limit output power. Equation 4
limits the V
RAMP
voltage to correspond with the battery voltage.
Due to reactive output matches, there are output power variations across frequency. There are a number of components
that can make the effects greater or less.
The components following the power amplifier often have insertion loss variation with respect to frequency. Usually, there
is some length of microstrip that follo ws the p o wer amplifier. Ther e is als o a freque ncy re sponse f ound in dir ectiona l cou plers due to variation in the coupling factor over frequency, as well as the sensitivity of the detector diode. Since the
RF3133 does not use a directional coupler with a diode detec to r, these variations do not occur.
Input impedance variation is found in most GSM power amplifiers. This is due to a device phenomena where C
BE
and
C
CB
(CGS and CSG for a FET) vary over the bias voltage. The same principle used to make varactors is present in the
power amplifiers. The junction capacitance is a function of the bias across the junction. This produces input impedance
variations as the Vapc voltage is swept. Although this could present a problem with frequency pulling the transmit VCO
off frequency, most synthesizer designers use very wide loop bandwidths to quickly compensate for frequency variations
due to the load variations presented to the VCO.
The RF3133 presents a very cons tant load to the VCO. This is because all stages of the RF3133 are run at constant
bias. As a result, there is constant reacta nce at the base emitter and base collector junction of the input stage to the
power amplifier.
Noise power in PA's where output power is controlled by c hanging the bia s v oltage is often a pr ob lem when b ac king off of
output power. The reason is that the gain is changed in all stages and according to the noise formula (Equation 5),
(Eq. 5)
the noise figure depends on noise factor and gain in all stages. Because the bias point of the RF3133 is kept constant
the gain in the first stage is always high and the overall noise power is not increased when decreasing output power.
Power control loop stability often presents many challenges to transmitter design. Designing a proper power control loop
involves trade-offs affecting stability, transient spectrum and burst timing.
In conventional architectures the PA gain (dB/ V) varies across different power levels, and as a result the loop bandwidth
also varies. With some power amplifiers it is possible for the PA g ain (contr ol slope) to change from 100dB/V to as high
as 1000dB/V. The challenge in this scenario is keeping the loop bandwidth wide enough to meet the burst mask at low
slope regions which often causes instability at high slope regions.
The RF3133 loop bandwidth is determine d by internal bandwidth and the RF output load and does not change with
respect to power levels. This makes it easier to maintain loop stability with a high bandwidth loop since the bias voltage
and collector voltage do not vary.
An often overlooked problem in PA control loops is that a delay not only decreases loop stability it also affects the burst
timing when, for instance the input power from the VCO decreases (o r increases ) with resp ect to temperature or s upply
voltage. The burst timing then appears to shift to the right especially at low power levels. The RF3133 is insensitive to a
change in input power and the burst timing is constant and requires no software compensation.
V
RAMP
3
8
-- -
V
BATT
0.18+⋅≤
F
TOT
F1
F21–
G1
--------------- -
F31–
G1 G2⋅
-------------------
++=
Page 13
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RF3133
Rev A4 030527
Switching transients occur when the up and down ramp of the burst is not smooth enough or suddenly changes shape. If
the control slope of a PA has an inflection point within the output power range or if the slop e is simply to stee p it is difficult
to prevent switching transients. Controlling the output power by changing the collector voltage is as earlier described
based on the physical relationship between voltage swing and output power. Further mo re all stages are kept constantly
biased so inflection points are nonexistent.
Harmonics are natural produ cts of high efficiency power amplifier design. An ideal class “E” saturated power amplifier
will produce a perfect square wave. Looking at the Fourier transform of a square wave reveals high harmonic content.
Although this is common to all power amplifiers, there are other factors that contribute to conducted harmonic content as
well. With most pow er cont rol me th ods a pea k power diode detector is used to rect ify an d sens e f orward power. Through
the rectification process there is additional squaring of the wa v e form resulting in higher harmonics. The RF3 133 addre ss
this by eliminating the need for the detector diode. Therefore the har monics coming ou t of the PA should represent the
maximum power of the harmonics throughout the transmit chain. This is based up on pro per ha rmonic termination of the
transmit port. The receive port termination on the T/R switch as well as the harmonic impedance from the switch itself
will have an impact on harmonics. Should a problem arise, these terminations should be explored.
The RF3133 incorporates many circuits that had previously been required external to the power amplifier. The shaded
area of the diagram below illustrates those components and the following table itemizes a comparison between the
RF3133 Bill of Materials and a conventional solution:
Note: Output power is limited by battery voltage. The relationship in Equation 4 does not limit output power. Equation 4
limits V
RAMP
to correspond with the battery voltage.
Component Conventional
Solution
RF3133
Power Control ASIC $0.80 N/A
Directional Coupler $0.20 N/A
Buffer $0.05 N/A
Attenuator $0.05 N/A
Various Passives $0.05 N/A
Mounting Yield
(other than PA)
$0.12 N/A
Total $1.27 $0.00
From DAC
*Shaded area eliminated with Indirect Closed Loop using RFMD's Integrated Power Control Solution
Traditional Triple-Band PA
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RF3133
Rev A4 030527
PCB Design Requirements
PCB Surface Finish
The PCB surface finish used for RFMD’s qualification process is Electroless Nickel, immersion Gold. Typical thickness is
3µinch to 8µinch Gold over 180µinch Nickel.
PCB Land Pattern Recommendation
PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and
tested for optimized assembly at RFMD; however, it may require some modifications to address company specific
assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances.
PCB Metal Land and Solder Mask Pattern
Metal Land Pattern
0.00
0.00
1.50 (mm)
5.90 (mm) Typ.
2.20 (mm) Typ.
5.00 (mm) Typ.
0.80 (mm)
3.70 (mm)
1.50 (mm)
3.00 (mm)
4.50 (mm) Typ.
6.00 (mm)
7.50 (mm)
9.00 (mm) Typ.
5.30 (mm)
8.20 (mm)
8.30 (mm)
0.70 (mm)
0.70 (mm)
A = 0.80 (mm) Sq. Typ.
B = 1.00 x 0.80 (mm) T y p .
Pin 1
AB
A
A
A
A
A
AA
A
B
B
Solder Mask Pattern
0.00
0.00
1.50 (mm)
3.00 (mm)
4.40 (mm) Typ.
5.90 (mm)
2.25 (mm)
1.50 (mm) Typ.
3.00 (mm) Typ.
4.50 (mm) Typ.
6.00 (mm) Typ.
7.50 (mm) Typ.
9.00 (mm) Typ.
4.50 (mm)
Pin 1
0.05 (mm) Typ.
9.05 (mm) Typ.
B
CDE
E
E
E
D
D
A
B
BB
C
C
C
C
A
A
A
A
A
AA
A
F
A = 1.00 (mm) Sq. Typ.
B = 0.90 x 0.80 (mm) Ty p.
C = 0.80 (mm) Sq. Typ.
D = 1.00 x 1.20 (mm) Typ.
E = 0.80 x 1.10 (mm) T y p.
F = 7.00 x 2.50 (mm) Typ.
Figure 1. PCB Metal Land and Solder Mask Pattern (Top View)
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Thermal Pad and Via Design
The PCB land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of
the device.
Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern shown
has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies.
The Via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size
on a 0.5 mm to 1.2mm grid patter n with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested
that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
Stencil Design Recommendation
The stencil aperture are typically designed to match the pad size shown in the PCB Solder Mask pattern and are
reduced for an overall 20 percent reduction in pad area for each pad. This has yielded good solder joint results based on
volumes assembled during product introduction phase.
Critical parameters to consider for successful solder paste application include:
Accurate registration of the stencil to the PCB during printing.
Good release of stencil from the PCB after paste applied. This is improved with laser cut trapezoidal openings.
Proper storage and handling of solder paste based on solder paste vendor guidelines.
Frequent cleaning of the solder paste stencil to remove residual solder paste.
Stencil material recommendations: 5mil (0.127mm) thick stainless steel, laser cut stencils with trapezoidal open ings to
promote easy release of solder paste.
Vias
0.203 mm to 0.330 mm
Finished Hole
0.5 mm to 1.2 mm Grid
Figure 2. Thermal Pad and Via Design (RFMD Qualification)
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Pin 1
0.00
0.00
1.50 (mm) Typ.
3.00 (mm) Typ.
4.40 (mm) Typ.
5.90 (mm) Typ.
2.25 (mm)
1.50 (mm) Typ.
3.00 (mm) Typ.
4.50 (mm) Typ.
6.00 (mm) Typ.
6.09 (mm)
2.91 (mm)
7.50 (mm) Typ.
9.00 (mm) Typ. 9.05 (mm) Typ.
0.05 (mm) Typ.
A
A
A
A
A
A
AA
A
A
A
A
A
A
BB
BB
C
C
C
D
D
D
D
E
E
D = 0.64 x 0.88 (mm) Typ.
E = 2.42 x 2.00 (mm) Typ.
A = 0.64 (mm) Sq. Typ.
B = 0.72 x 0.64 (mm) Typ.
C = 0.64 x 0.80 (mm) Typ.
Figure 3. Stencil Recommendation
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