Datasheet RF2968 Datasheet (RF Micro Devices)

Preliminary

RF2968

11

Typical Applications

• Bluetooth G SM/GPRS/EDGE Cellular
Phones

• Bluetooth Wireless LAN

Product Description

The RF2968 is a monolithic integrated circuit intended for
use as a low-cost FSK transceiver in Bluetooth applica­tions. The device is provided in 32-lead plastic LPCC
packaging and is designed to provide a fully-functional
FSK transceiver. The chip is intended for Bluetooth appli­cations in the 2.4GHz to 2.5GHz ISM band. The IF and
demodulation sections of the chip require no external fil­ters or discriminators. The chip also features an image
reject front end and a fully programmable synthesizer
with integrated oscillator circuitry. Self-calibrating RX and
TX IF circuitry optimizes link performance and eliminates
manufacturing variations.

BLUETOOTH isatrademark owned by the Bluetooth SIG, Inc., and licensed
to RF Micro Devices,Inc.

BLUETOOTHTM TRANSCEIVER

• Cordless P hones

• Battery-Powered Portable Devices

5.00

±0.10

4.75

±0.10

1.0

MAX

11° ± 1°

(4X)

0.50

NOTES:

1. Shaded lead indicates Pin 1.

2. Package surface roughness at 1.5 µm±0.30.

-A-

4.75

±0.10

See Detail A

0.70 ± 0.08

-C-

Seating

Plane

5.00

±0.10

-B-

0.40 ± 0.10

Detail A

5 µm-20µm

0.20

0.70 ±

0.08

1.00

MAX

-C-

Optimum Technology Matching® Applied

Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS

ü

1VCC1

2VCC2

3TXOUT

4RXIN

5VCC3

6VCC4

7LPO

8DVDDH

APPF LO

SiGe HBT

IFDGND

VREG

30

TX
DATA
SYNC

FSKDemodulator

60MHz

11D112

TX DATA

RESNTR+28RESNTR-27RSHUNT26DO

29

Voltage

Regulator

VCO

LO

x2

Prescaler

16/17

LPF/

Equalizer

Clock/Data

Recovery

BPKTCTL

VCC7

31

32

BT =0.5

Transmitter

Filter

4MHz

LOOP

/4

ICO

1MHzIF

FILTER

Phase

Detector /

/4

Charge

Pump

1MHz

Receiver

9

10

IREF

VCC5

Σ

APPF LO

Σ

Synthesizer

RXDAT A

Address 7

16

16

16

Phase Detecto r/

ChargePump

RX DATA

13

BDATA1

TX DATA

500kHz

Address4

Address5

Address6

500kHz

1MHz

60M Hz

10M Hz
12M Hz

14

RECCLK

Si CMOS

25

Address 30

Address 31

Address3

5

25-BitLatch

25

/2

DivR

/60

/6

Phase Detecto r/

/5

ChargePu mp

15

RECDATA

VCC6

BDATA1

10 MHz

BPKTCTL

BXTLEN

DBus

16-BitShift

Register

(ReadOnly)

25

25-BitShift

Register

(Write Only)

Ref.Osc.

Div R

16

BXTLEN

Functional Block Diagram

Package Style: LCC, 32-Pin, 5x5

Features

11

• Fully Monolithic Integrated Transceiver

• Self-Calibrating Transceiver

24 PLLGND

Chip

Control

23 BnPWR

22 BDCLK

21 BDDATA

20 BnDEN

19 OSCI

18 OSCO

17 BRCLK

• Image Reject Receiver

• Bluetooth and BlueRF compatible

• Supports Reference Clocks to 40MHz

• Smallest Footprint Bluetooth Transceiver

Ordering Information

TBD

RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA

Tel [phone]

Fax [phone]

http://www.rfmd.com

TRANSCEIVERS

Rev A13 010912

11-117

RF2968

Absolute Maximum Ratings

Parameter Ratings Unit

Supply Voltage -0.5 to +3.6 V
Control Voltages -0.5 to V
Input RF Level +10 dBm

Operating Ambient Temperature -40 to +85 ° C
Storage Temperature -55 to +125 °C

CC

DC

V

DC

Preliminary

Caution! ESD sensitive device.

RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).

11

Parameter

Min. Typ. Max.

Overall

RF Frequency Range 2400 to 2500 MHz

Specification

Unit Condition

T=25°C, VCC=3.0V

VCO and PLL Section

VCO Frequency Range 1100 to 1350 MHz
Frequency Tolerance -50 50 kHz 20ppm crystal; -40°C to +85°C
RF Channels 79
Step Size 1 MHz Freq=2.4G Hz
SSB Phase Noise -90 dBc/Hz Freq=2.4GHz, 500kHz Offset

-110 dBc/Hz Freq=2.4GHz, 2MHz Offset

-124 dBc/Hz Freq=2.4GHz, 3MHz Offset

Reference Frequency 10 13 20 MHz 10, 11, 12, 13, 20MHz

20 26 40 MHz Div2ENB=0; 20, 22, 24, 26, 40MHz.

Hop Time 130 175 µs DualBW=75kHz and 25kHz; BW switch
K

VCO

85 MHz/V VCO Freq=1.2GHz

delay=100µs

Tr ansmit Section

Data Rate 1 Mbps
Output Power 0 4 dBm
Power Control Range 28 dB
Power Control Step Size 4 dB
Gain Step Switching Time 4 µs From-28dB to 0dB
Output Impedance 25 50 100 Ω VSWR<2:1
Deviation 140 160 175 kHz Peak, Data Sequence 00001111

115 kHz Peak, Data Sequence 01010101

Transmit ISI Data Sequence 1010

Min Freq Dev,% EYE Open 80 100 % Reference Data Sequence 00001111
Zero Crossing Error -125 125 ns +

In-Band Spurious Measurement BW=100kHz

TRANSCEIVERS

Adjacent Channel Power -20 dBc
Second Channel Power -20 dBm
>

Third Channel Power -40 dBm

Out-of-Band Spurious Measurement BW=100kHz

Operation -36 dBm 30MHz to 1GHz

-30 dBm 1GHz to 12.75GHz

-47 dBm 1.8GHz to 1.9GHz

-47 dBm 5.15GHz to 5.3GHz

Idle -57 dBm 30MHz to 1 GHz

-47 dBm 1GHz to 12.75 GHz

-47 dBm 1.8GHz to 1.9GHz

-47 dBm 5.15GHz to 5.3GHz

1/8 Symbol

11-118

Rev A13 010912

Preliminary

RF2968

Parameter

Min. Typ. Max.

Specification

Unit Condition

Overall Receive S ection

Cascaded Voltage Gain 18 64 dB
Cascaded Noise Figure 8 dB
Cascaded Input IP

RX Sensitivity -85 dBm
Image Rejection 30 dB

RX Input Im pedance 25 50 100 Ω 2:1 VSWR max.
Interference Performance

Co-Channel Interference,

C/I

CO-Channel

Adjacent (1MHz) Interference,

C/I

1MHz

Adjacent (2MHz) Interference,

C/I

2MHz

Adjacent (>

ence,C/I

Image Frequency Interfer-

ence, C/I

Adjacent (1MHz) Interference

to In-Band Image,
C/I

image+1MHz

Out-of-Band Blocking

Interfering Signal Frequency
30MHz to 2000MHz -10 dBm
2000MHz to 2400M Hz -27 dBm
2500MHz to 3000M Hz -27 dBm
3000MHz to 12 .75GHz -10 dBm

Intermodulation Characteristic

f1, f2 -39 dBm f0=-64dBm BT signal

Maximum Usable Level -20 dBm
Spurious Emissions Measurement BW=100kHz

30MHz to 1GHz -57 dB m

1GHz to 12.75G Hz -47 dBm
RSSI Operating Range -80 -20 dBm Power level at RX IN pin
RSSI Resolution 1 dB
RSSI Absolute Accuracy -4 4 dB -60dBm input power

3

3MHz)Interfer-

>3MHz

image

-14 dBm

14 dB C= -60dBm

+4 dB C=-60 dB m

-30 dB C=-60dBm

-40 dB C=-67dBm

-9 dB C=-67dBm

-20 dB C=-67dBm

IF BW =1MHz, BER=10

BER<10

BER<10
tion board schematic

BER<10

f1=sine
f2=BT signal
|f2-f1|=3MHz, 4MHz or 5MHz
f0=2f1-f2

BER<10

-3

(C =Desired Signal/I=Interferer)

-3

, C=-67dBm, tested per evalua-

-3

(BT=Bluetooth Modulated Signal)

-3

-3

Front End

VoltageGain 25.5 27.5 29.5 dB
Power Gain 20 dB
Noise Figure 6 8.5 dB
IIP3 -14 dBm

IF Section

IF Frequency 1 MHz
Voltage Gain -9.5 37 dB Followed by 1 bit A/D
Noise Figure 25 dB

11

TRANSCEIVERS

Rev A13 010912

11-119

RF2968

Preliminary

Parameter

Data Voltages

Logic Low 0.3 V
Logic High V

Power Supply

Voltage 2.5 3.3 3.6 V
TX Current Consumption 49 mA Transmit mode, +4dBm output power
RX Current Consumption 49 mA Receive mode
Sleep Modes 1 µA Sleep mode, no low power clock

Min. Typ. Max.

Specification

-0.3 V

CC

250 µA Sleep mode, low power clock, 12MHz refer­750 µA Sleep mode, low power clock, other refer-

Unit Condition

>10kΩ

Z

LOAD

ence
ence

11

TRANSCEIVERS

11-120

Rev A13 010912

Preliminary

RF2968

Pin Function Description Interface Schematic

1VCC1
2VCC2
3TXOUT

Supply voltage for the VCO doubler and LO amplifier circuits.
Supply voltage for the RX mixers, TX PA, and LNA bias circuits.
Transmitter output. TX OUT output impedance is 50Ω (nominal) when

the transmitter is enabled. TX OUT is a high impedance when the
transmitter is disabled. Because this pin is DC-biased, an external cou­pling capacitor is required.

10 Ω

V

CC

TX OUT

4RXIN

5VCC3

6VCC4
7LPO

8DVDDH
9IREF

10 VCC5
11 D1

12 BPKTCTL

13 BDATA1

14 RECCLK
15 RECDATA
16 BXTLEN

Receiver input. RX IN input impedance is a low impedance wh en the
receiver is enabled. RX IN is a high impedance when the receiver is
disabled. An internal series inductor is used to tune the input imped­ance.

Supply voltage for the RX input stage (LNA).

Supply voltage for the TX mixers and bias circuits of the LO amp lifier,
LNA, and RX mixers.

Low frequency clock output for low power mode. In sleep mode, this pin
may provide either a 3.2kHz or 32kHz clock having a 50% duty cycle to
the baseband. In other modes, the output is disabled.

Supply voltage for the RX IF VGA circuit.
Connects an external precision resistor (1% tolerance) for generation

of a constant current reference.
Supply voltage for the analog IF circuits.

This is the output of the charge pump for clock recovery c ircuit. A RC
network from this pin to ground is used to establish the PLL bandwidth.

In transmit mode, this pin is used as a strobe to enable the PA stage. In
receive mode, the baseband has the option to use this pin to signal the
detection of the sync word. The baseband drives this pin high at the
end of the sync word, at which time a second DC estimation is per­formed by sampling the trailer bits. If baseband control is not desired to
signal the second DC estimation, then an internal timer is used to mark
the end of the sync word. The BBC bit is used to select the baseband
control option; the default setting uses the internal timer.

Input data to transmitter/output data from receiver. The input data is
unfiltered data at 1MHz data rate. The pin is bidirectional, switching
between data in and data out modes during Transmit and Receive
modes respectively.

Recovered clock output. See pin 17.
Recovered data output. See pin 17.
This pin is part of the chip power control circuit. It is used to enable/dis-

able “sleep” mode of chip.

RX IN

V

See pin 26.

See pin 23.

RXDATA

TX DATA

VCC3

CC3

11

BDATA1

V

CC

TRANSCEIVERS

Rev A13 010912

BXTLEN

11-121

RF2968

Preliminary

Pin Function Description Interface Schematic

17 BRCLK

Reference clock output. This is a crystal controlled referen ce clock in
the 10-40MHz range, typically 13MHz.

V

CC

BRCLK

11

18 OSC O
19 OSC I

20 BnDEN
21 BDDATA

22 BDCLK

23 BnPWR

24 PLL GND
25 VCC6

26 D0

TRANSCEIVERS

27 RSHUNT
28 RESNTR-

Same as pin 19. See pin 19.
The OSC pins are used to produce the reference frequency by means

of negative feedback. A crystal and resistor are placed in parallel from
OSC I to OSC O to provide the feedback path and establish the reso­nant frequency. A shunt capacitor is placed on each OSC pin to provide
the proper loading of the crystal. If an external reference is used, it is
connected to OSC I through a DC-blocking capacitor, and OSC O is
connected to OSC I through a 470kΩ resistor.

Latches data entered into the serial port. Data is clocked into the latch
on the rising edge of BnDEN.

Serial data port. Read/write data is sent through this pin into / out of the
on chip shift register. Read data is transferred on the rising edge of
BDCLK. Write data is transferred on the falling e dge of BDCLK.

Serial port input clock.This pin is used to clock data into the serial port.
To minimize the hop frequency programming time, a BDCLK frequency
of 10-20MHz is recommended.

This pin is part of the chip power control circuit. It is used to power up
the chip from the “off” state.

Ground connection for the R F synthesizer, crystal oscillator, and serial
port.

Supply voltage for the RF synthesizer, crystal oscillator, and serial port.
This is the output of the charge pump for the RF PLL. An RC network

from this pin to ground is used to establish the PLL bandwidth. To mini­mize synthesizer settling time and phase noise, a dual loop bandwidth
scheme is implemented. Durin g the initial period of frequency acquisi­tion, a wide loop bandwidth is used. RSHUNT is used to switch to a
narrow loop bandwidth near the end of the frequency acquisition, pro­viding improved VCO phase noise. The time at which the bandwidth
switches is set by the PLLDel bits.

Switches the loop filter from wide to narrow bandwidth by shunting the
midpoint of two external series resistors to ground.

The RESNTR pins are used to supply DC voltage to the VCO as well
as to tune the center frequency of the VCO. Two inductors are required
between RESN TR- and RESNTR+ to resonate with the internal capac­itance. Inductance of traces from the RESNTR pins to the inductor
should be taken into account in the board layout.

See pin 23.

READ DATA

WRITE DATA

See pin 23.

BnPWR

D0

4kΩ

OSC OOSC I

Pin 21

V

CC

V

CC

D0

RESNTR-RESNTR+

11-122

Rev A13 010912

Preliminary

RF2968

Pin Function Description Interface Schematic

29 RESNTR+
30 VREG

See pin 28.
Voltage Regulator Output (2.2V). A bypass capacitor from this pin to

ground is required. This voltage is used to bias the VCO through the
tank circuit t ied to pins 28 and 29.

V

CC

VREG

31 IFDGND
32 VCC7

ESD

Die

GND

Flag

Ground connection for the digital IF circuits.
Supply voltage for the digital IF circuits.
This diode st ructure is used to provide electrostatic discharge protec-

tion to 3kV using the Human body model. The following pins are pro­tected: 6-7, 9-17, 20-27, 30-32.

Ground connection for all circuits other than those grounded through
dedicated pins. The die flag must be conne cted to the ground plane
with very low inductance for be st performance.

V

CC

11

Rev A13 010912

TRANSCEIVERS

11-123

RF2968

Preliminary

Theory of Operation

The RF2968 is the first in a family of 2.4G Hz transceivers developed specifically for Bluetooth applications. It operates
as a Power Class 2 (+4dBm) or Class 3 (0dBm) Bluetooth device and is fully compliant to Version 1.0b of the Bluetooth
Radio Specification. For Power Class 1 (+20dBm) applications,the RF2968 may be used with a power amplifier such as
the RF2172. Processed in 0.35um silicon Bi-CMOS and packaged in a 5mm-square, industry-standard 32-pin leadless
plastic package, the RF2968 provides high performance at a very low cost. With integrated IF filtering, the RF2968
requires minimal external components and eliminates the need for costly components such as IF SAW filters and baluns.
The high impedance 'off' states of the receiver input and transmitter output also eliminate the need for an external trans­mit/receive (T/R) switch. A complete Bluetooth solution may be implemented with the RF2968 in conjunction with an
antenna, RF bandpass filter, and baseband controller.In addition to the RF signal processing, the RF2968 also performs
the baseband functions of data demodulation, DC compensation, and data and clock recovery while access code corre­lation takes place in the baseband device.

The RF2968 transmitter output is internally matched to 50Ω, and requires an AC-coupling capacitor. The receiver's low
noise amplifier (LNA) input (RXIN pin) is internally matched to present a 50Ω impedance to the front end filter. A single
front end filter may be shared by the transmitter and receiver by simply connecting the TXOUT coupling capacitor to
RXIN. Alternatively, the transmit path may be externally amplified to +20dBm, which, in conjunction with the RF2968’s
transmitgain control and receivedsignal strength indicator (RSSI), allows Bluetooth-compliant operation for Power Class

1. The RSSI data is accessed via the serial port and provides a 1dB resolution over the RX input power range of -20to­80 dBm. Transmit gain control is adjustable in 4dB steps and is also set via the serial port.

Baseband data is sent to the transmitter via the BDATA1 pin, which is a bidirectional pin, acting as an input in transmit
mode and an output in receivemode. The RF2968 performs the Gaussian filtering of the baseband data, FSK-modulates
the IF current controlled oscillator (ICO), and upconverts the IF to the RF channel frequency.

11

The on-chip voltage controlled oscillator (VCO) is frequency synthesized to one half of the required local oscillator (LO)
frequency and then doubled to produce the correct LO frequency. Two external tank inductors between RESNTR+ and
RESNTR- set the tuning range of the VCO. Voltageis supplied to the VCO from an on-chip regulator that is connected to
the midpoint of the two tank inductors through a filtering network. Due to the fast frequency hopping requirements of
Bluetooth, the loop filter components (connected to pins D0 and RSHUNT) are especially cr itical as they largely deter-
mine the hopping and settling time of the VCO. Use of the component values as given in the Application Schematic is
strongly recommended.

The RF2968 may use either a 10MHz, 11 MHz, 12MHz, 13MHz, or 20MHz reference clock frequency and can also sup­port a reference clock at double these frequencies to provide a migration path toward smaller end-product designs. This
clock may be supplied by an external reference applied directly to OSC I through a DC-blocking capacitor. If an external
reference is not available, then a crystal and two capacitors may be used to complete the reference oscillator circuitry
contained on-chip. For either an externally or internally generated referenced frequency, a resistor between OSC I and

OSC O is required for proper biasing. The frequency tolerance of the reference clock must be 20ppm or better to assure

TRANSCEIVERS

that the maximum allowed system frequency error remains within the demodulation bandwidth of the RF2968. A select­able 3.2kHz or 32kHz low power mode clock is available at the LPO pin to supply the baseband device with a low fre­quency clock in sleep mode. Where minimal sleep mode power consumption is a concern and reference clock frequency
selection is flexible,a 12MHz reference clock should be chosen.

The receiver uses a low-IF architecture to minimize external component count. The RF signal is downconverted to
1MHz, allowing IF filtering to be incorporated on chip. Demodulated data is output at the
cessing is performed by the data and clockrecovery circuitry,which utilizes a baseband PLL. Pin D1 istheloopfiltercon­nection for the baseband PLL. The synchronized data and clock are output at pins RECDATA and RECCLK.Ifthe
baseband device used with the RF2968 performs the clock recovery, then the D1 loop filter components may be omitted.

The interface between the RF2968 and baseband device is described in the 'Application Information' section of the full­length datasheet available from the RFMD web site (www.r fmd.com).

BDATA1

pin. Further data pro-

11-124

Rev A13 010912

Preliminary

RF2968

Detailed Functional Block Diagram

VCC7

1VCC1

2VCC2

32

Transmitter

Filter

Σ

3TXOUT

4RXIN

5VCC3

6VCC4

7LPO

8DVDDH

APPF LO

1MHzIF

Σ

APPF LO

9

IREF

IFDGND

VREG

31

30

BT = 0.5

TX
DATA
SYNC

4MHz

LOOP

/4

ICO

FILTER

Phase

Detector/

/4

Charge

Pump

1MHz

Receiver

FSK Demodulator

60 MHz

10

11

VCC5

TX DATA

D1

RESNTR+

Prescal er

16/17

LPF/

12

BPKTCTL

28

VCO

Clock / Data

Recovery

RESNTR-

RX DATA

29

LO

x2

Equalizer

Synthesizer

Address 7

Phase Detector/

Charge Pump

16

16

16

RX DATA

13

BDATA1

RSHUNT26DO

27

500 kHz

Address 4

Address 5

Address 6

TX DATA

14

RECCLK

500 kHz

1MHz

60 MHz

10 MHz
12 MHz

VCC6

25

24 PLLGND

BDATA1

10 MHz

BPKTCTL

BXTLEN

DBus

Address 30

Address 31

Address 3

5

25-Bit Latch

25

/2

Div R

/60

/6

Phase Detector/

/5

Charge Pump

15

RECDATA

Chip

Control

23 BnPWR

16-Bit Shift

Register

(Read Only)

25

25-Bit Shift

Register

(Write Only)

Ref. Osc.

Div R

16

BXTLEN

22 BDCLK

21 BDDATA

20 BnDEN

19 OSC I

18 OSC O

17 BRCLK

VCC1

VCC2

TX OUT

RX IN

VCC3

VCC4

LPO

DVDDH

Pin Out

VCC731IFDGND30VREG29RESNTR+28RESNTR-27RSHUNT26DO25VCC6

32

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

VCC5

D1

BDATA1

BPKTCTL

RECCLK

IREF

11

24

PLL GND

BnPWR

23

BDCLK

22

BDDATA

21

BnDEN

20

OSC I

19

OSC O

18

BRCLK

17

BXTLEN

RECDATA

TRANSCEIVERS

Rev A13 010912

11-125

RF2968

Preliminary

Application Schematic

for Typical GSM Handset

(Assumes Clock Recovery Performed by Baseband)

11

LPO

820 Ω

1 µF

V

CC

22 nF*

1

2

FL1

V

CC

22 nF

3

4

5

22 nF*

6

7

1 µF

3.9 nH

3.9 nH

43 kΩ

20 kΩ

330 pF

30 pF

V

CC

22 nF*

2526272829303132

24

23

22

21

20

19

18

470 kΩ

1nF

BnPWR

BDCLK

BDDATA

BnDEN

REF IN

8

9 10 11 12 13 14 15 16

TRANSCEIVERS

V

CC

20 kΩ

1%

*Note: Required supply filtering may vary depending on implementation.

22 nF*

11-126

17

BRCLK
BXTLEN
BDATA1
BPKTCTL

Rev A13 010912

Preliminary

VCC

Evaluation Board Schemati c

(Download Bill of Materials from www.rfmd.com.)

R5

43 kΩ

R4

20 kΩ

C11

330 pF

2526272829303132

24

C1*

22 nF

R6

820 Ω

C13

1 µF

1

C12
1 µF

3.9 nH

L2

L1

3.9 nH

C10

30 pF

BDCLK

BDDATA

BnDEN
BRCLK

BXTLEN

RECDATA

RECCLK

BPKTCTL

C9*

22 nF

RF2968

P1

10

9
8
7
6

VCC

5
4
3
2
1

CON20

20
19
18
17
16
15
14
13
12
11

VCC

BnPWR
BDATA1

VCC

LPO

RX IN/TX OUT

VCC

LPO

VCC

FL1

22 nF

C3*

C2

22 nF

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

R1

20 kΩ

1%

C4*

22 nF

C5

100 pF

*Note: Required supply filtering may vary depending on implementation.

C6

2.7 nF

23

22

21

20

BnPWR

BDCLK

BDDATA

BnDEN

11

19

R3

470 kΩ

18

17

Y1

13 MHz

C8

47 pF

C7

47 pF

BRCLK
BXTLEN
RECDATA
RECCLK
BDATA1
BPKTCTL

TRANSCEIVERS

Rev A13 010912

R2

22 kΩ

11-127

RF2968

.

Preliminary

Application Information

Baseband Interface

The RF2968 RF transceiverserves as the physical layer (PHY) in a Bluetooth system and suppor ts the BlueRF interface
between PHY and baseband devices. The RF2968 contains the data demodulation, DC compensation, and data and
clock extraction circuitry while the access code correlator function takes place in the baseband.

There are two interfaces between the RF2968 and the baseband. The serial interface provides the path for control data
exchange, and the bidirectional interface provides the path for modem, timing, and chip power control signals. Figure 1
shows bidirectional signals with arrowheads on both ends of the line.

BDATA1

BPKTCTL

BXTLEN

Bidirectional

Interface

BRCLK

BnPWR

Bidirectional

Interface

11

BDDATA

BASEBAND

SPI Master

Figure1. Baseband/RF2968 Interface

Serial Interface

Control data is exchanged between the RF2968 and the baseband by means of the DBus serial interface protocol.
BDCLK, BDDATA,andBnDEN are the signals comprising the serial interface. The baseband is the master device, initi-
ating all accesses to the RF2968 registers. The data registers of the RF2968 are programmed or recalled according to
the specified command format and address assignments. Data packets are transmitted M SB first.

Serial Data Packet Format

Field Number of Bits Comments

Device Address 3 [A7:A5] “101” for PHY
Read/Write 1 [R/W] “1”=Read, “0” =Write
RegisterAddress 5 [A4:A0] Maximumof 32 registers

TRANSCEIVERS

Data 16 [D15:D0] The RF2968 is programmed in Write mode and returns its register contents

During a wr ite, the baseband drives out each bit of the packet on the falling edge of BDCLK. The RF2968’s data register
is updated with the shift register contents on the first falling edge of BDCLK after BnDEN is driven high. See Figure 2.

BDCLK

in Read mode.

BDCLK
BnDEN

SPI Slave

..

RF2968

BDDATA

BnDEN

Figure 2. DBus Write Programming Diagram

11-128

R/W = write = 0

D15 D14A6 A5 A3 A2 A1 A0A7 A4 D1D2 D0 A6A7

...

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Preliminary

RF2968

In a read operation, the baseband sends the device address, READ bit (R/W = 1), and register address to the RF2968
followed by a “turn-around” bit which lasts half a clock cycle. This turn-around allows the RF2968 to drive its requested
data, via BDDATA, on the r ising edges of BDCLK. Following the transfer of the last data bit (D[0]), the baseband drives
BnDEN high and resumes control of BDDATA on the falling edge of the first BDCLK pulse after BnDEN is driven high.
SeeFigure3.

Floating

don't
care

BDCLK

BDDATA

BnDEN

Ma ster DrivingBDDATA

R/W= read = 1

Floating

Slave Driving BDDATA

...

D15A6 A5 A3 A2 A1 A0A7 A4 D1D2 D0 A6A7

D14

...

turn-around turn-aro und

Figure 3. DBus R ead Programming Diagram

Register Definition
The register address field allows up to 32 registers for various functions. The RF2968 implements only register

addresses 3-7 and 30-31.

Register 3 - IF Register 1 (Read-Only)

Bit Number Bit Name Comments

7 - 15 N/A Not Assigned

0 -6 RSSI[6:0] The RSSI value indicates the average power measured during the first 10µs

after a packet has been detected. The baseband reads this register to obtain
the current received s ignal strength indicator measurement. The RSSI value
may range from 0dBm to -127dBm in 1dB increments. (All 0’s indicates
0dBm; all 1’s indicates -127dBm.) The RSSI circuitry is designed to operate
from -20dBm to -80dBm with an accuracy of 4dB at -60dBm.
Example: RSSI[6:0]=[110101] indicates -53dBm.

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TRANSCEIVERS

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RF2968

Register 4 - IF Register 2 (Write-Only)

Bit Number Bit Name Comments

12-15 N/A Not Assigned

11 ChopENB Enables circuitry that significantly reduces the levels of RF PLL comparison

frequency spurious responses.
1: Spur cancellation disabled.
0: Normal mode. Spur cancel lation enabled.

10 Div2ENB Enables an additional divide-by-two operation in the reference d ivider cir-

cuitry to accommodate the use of a 20MHz-40MHz crystal or clock. This
allows a migration path to higher reference frequencies.
1: Normal mode. 10, 11, 12, 13, or 20MHz reference clock.
0: Expanded mode. Reference clock is double that allowed in normal mode.

8-9 LPO[1:0] Determines the function of the low power mode clock (output at pin 7) when

the device is in Sleep mode according to the table below. In non-Sleep
modes, the output is disabled.

5-7 Gain[2:0] Sets the gain o f the transmitter p ath. The gain is normally programmed

immediately after the register write to enter the WAIT DATA SYNC state in
Power Class 1 applications. Gain is adjustable from 0dBto-28dB in 4dB
steps. [All 0’s indicates high gain (0dB attenuation); all 1’s indicates low gain
(28dB attenuation).] Example: Gain[2:0]=[011 ] indicates 12dB attenuation.

4 ENSlowAGCB 1: Slow AGC disabled.

0: Normal mode. Slow AGC enabled.

3 N/A Not Assigned
2 TPL_AC Selects a path in the RX data DC estimation circuit.

1: Selects the DC estimation path that is AC coupled and which is normally

used for the payload part of packet.
0: Selects the fast DC estimation RX data path normally used for the access

code of packet.

0-1 TDet[1:0] Sets the receiver gain according to the table below.

Preliminary

11

TRANSCEIVERS

LPO [1:0]:

LPO[1:0] Output at LPO (Pin 7)

0X 32kHzclock
1 0 3.2kHz clock
1 1 Clock disabled

TDet [1:0]:

TDet[1:0] VGA Gain (dB) Filter Gain (dB) Total Gain (dB) Step Size (dB)

11 -11 1.5 -9.5
10 4.5 1.5 6.0 15.5
01 4.5 17 21.5 15.5
00 20 17 37.0 15.5

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RF2968

Register 5 - IF Register 3 (Write-Only)

Bit Number Bit Name Comments

15 BypassSM Selects or bypasses the state machine.

14 BBC Selects baseband control o r internal timer control for determi ning the time at which to perform DC

13 N/A Not assigned.
12 Test IF test mode enable. Used only in IC verification; not for use in end product.

11 CalRxVGA Calibration which compensates for the gain of the LNA, mixer, and VGA. See “Special Modes: Cal-

10 Cal_Tx_PLL Calibrates the K

9 Cal_Gauss_Cell Calibration which compensates for the o ffset and the amplitude of the Gaussian TX data that mod-

8 Loopback 1: Loopback mode. The TX IF output is looped back to the RX IF input.

7 PU_XTAL Powers up the crystal oscillator circuitry. See “BypassSM” bit.

6 PU_MULT Powers up the frequency multipl ier for the FM demodulator clock. See “Bypass SM” bit.

5 CalRxFil Calibrates the channel filter, demodulator low pass filter, and AC coupling filter in the DC estima-

4 CalRXPLL_Int Calibration which compensates for the offset of the RX data path in the RX PLL interface circuit.

3 PU_PA Powers up the transmit output amplifier. See “BypassSM” bit.

2 PU_RX Powers up all receiver and synthesizer circuits. See “BypassSM” bit.

1 PLL_BW Selects the loop bandwidth of the RF P LL by controlling the state of the RSHUNT pin. Under state

0 PU_TX Powers up all transmitter and synthesizer circuits except for the output amplifier. See “BypassSM”

1: Bypass mode. Internal power-up signals can be directly controlled by programming of the

respective bits in this register [0:3, 6:7].

0: Normal mode. All internally controlled power-up signals are derived from the state machine.

estimation on the trailer bits.
1: Baseband control. The baseband drives BPKTCTL high at the end of the sync word.
0: Internal timer control.

1: IF test mode
0: Normal mode

ibration”.

(gain of the current controlled oscillator) of the TX PLL and, by nature of the

design, calibrates the K

ulates the TX PLL ICO. See “Special Modes: Calibration”.

0: Normal mode

1: Power o n
0: Power off

1: Power o n
0: Power off

tion circuit in the receiver, as well as the Gaussian filter and GFSK harmonic filter in the transmit­ter. See “Special Modes: Calibration”.

See “Special Modes: Calibration”.

1: Power o n
0: Power off

1: Power o n
0: Power off

machine control, this switch is executed according to the setting of the PLLDel[1:0] bits.
1: Narrow bandwidth. RSHUNT is s hort-circuited to ground.
0: Wide bandwidth. RSHUNT is a high impedance.

bit.
1: Power o n
0: Power off

0

of the RX PLL. See “Spe cial Modes: Calibration”.

0

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RF2968

Register 6 - IF Register 4 (Write-Only)

Bit Number Bit Name Comments

0-15 N/A Not Assigned

Register 7 - PLL Control (Write-Only)

Bit Number Bit Name Comments

15 Set_Tx_PLL_LF_Ext Configures the LPO pin as a test pin when bits LPO[1:0] are set high.

1: Test mode. LPO is connected to the IF PLL loop filter of the transmitter.

(See “Special Modes: Transmitter Test Mode”.)

0: Normal mode. LPO is not connected to the IF PLL loop filter of the trans-

mitter.

13 - 14 PLL Del [1:0] Determin es the time in which the PLL remains in high bandwidth mode

before switching to low bandwidth mode. In high bandwidth mode, the PLL
loop bandwidth is optimized for fast frequency locking. In low bandwidth
mode, the loop bandwidth is optimized for low phase noise. See below. See
also pin descriptions of D0 and RSHUNT, and bit PLL_BW (Register 5, Bit

1).

12 RSSI_Test Configures the RSSI circuitry to operate continuously for test purposes.

1: Test mode. Continuous operation.
0: Normal mode. Packet-based operation.

9 - 11 DivR [2:0] Selects the external crystal frequency.See below.

8 TX_EN Powers up the TX voltage and current bias circuits and the TX PLL’s ICO

voltage threshold set circuit.

7 RX_EN Powers up the RX voltage and current bias circuits.

0 - 6 PLL [6:0] Sets the RF PLL frequency. See below.

Preliminary

11

PLLDel [1:0]:

DivR [2:0]:

TRANSCEIVERS

PLLDel [1:0] Delay (us)

00 0
01 50
10 100
11 150

DivR [2:0] Crystal Freq (MHz)

011 12
100 10
101 11
110 13
111 20

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RF2968

PLL[6:0]:

These bits determine the local oscillator (LO) frequency (i.e., the frequency at the doubler output) for both RX and TX
modes. The LO frequency is set 1MHz above the channel center frequency. The PLL [6:0] data bits represent the fre­quency offset (F

2402 MHz to 2480MHz, F
F

OFFSET

will range from 3 to 98 (high-side injection assumed in both cases).

) in MHz from a base frequency of 2400 MHz. For the normal Bluetooth frequency range of

OFFSET

OFFSET

will range from 3 to 81; for the optional extended Bluetooth range (up to 2497MHz),

Example:
Assume a channel frequency of 2448MHz.
The LO frequency is then: 2448+1=2449MHz,
and F

OFFSET

is: 2449-2400=49.

PLL [6:0] is then:0110001

Register 30 - M anufacturer’s ID Code LSB’s (Read-Only)

Bit Number Bit Name Comments

0 - 15 ID_Code [15:0] Lower 16 bits of ma nufacturer’s code. The fixed “1” LSB of the manufacturer

code is read at bit 0.

Register 31 - M anufacturer’s ID Code MSB’s (Read-Only)

Bit Number Bit Name Comments

0 - 15 ID_Code [31:16] Upper 16 bits of manufacturer’s code. The MSB o f the version number is

read at bit 15. The RF2968 code is hex10B9825D.

Bidirectional Interface

Data Exchange and Timing
All bidirectional timing may be derived from BRCLK, which is generated by the RF2968. The RF2968 uses the falling

edges of BRCLK, and the baseband uses the rising edges. Figure 4 shows the general timing for the case of data being
transferred from the RF2968 to the baseband.

BB Data

Sampling

Points

BRCLK

BDATA1

Figure 4. General Bidirectional Timing (RF2968 writing to baseband)

State Machine Control
The chip control circuitry of the RF2968 places the device into the required transmit, receive or power saving mode by

controlling the power down and reset states of all other circuits in the device. The chip control inputs come from the
baseband device (BnPWR, BXTLEN, BPKTCTL, BDATA1) via the bidirectional interface and from the registers at the
output of the DBus block(RXEN, TXE N). State machines in the baseband and the RF2968 maintain the state which con­trols the direction of the bidirectional lines. The baseband controls the state machine in the RF2968 and ensures that
data contentions do not occur during reset and normal operation. The control of individual sections of the RF2968 in
each state is as follows.

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11

RF2968

State Description

OFF All circuits are powered down and reset; configuration data is lost. (CLRB=0)
PWRON WAIT XTL Reset is released (CLRB=1) and the oscillator is turned on (PDXTAL=1).
HOLD XTL This mode is entered when the oscillator has settled. Configuration data can be read through the DBus inter-

face.

IDLE Thisis a standby mode. Data can be read into the control registers (through the DBus) and the oscillator

remains on. All other circuits are powered down.

SLEEP The device normally enters this mode fro m IDLE, in w hich case every circuit is powered down but not reset, so

that configuration data is retained. The device may also enter this mode from any other except PWRON WAIT
XTL or HOLD XTL, but the TXEN and RXE N functions are not overridden, so that TX and RX circuits may

remain on.
WAIT XTL The oscillator is turned on (PDXTAL=1) and allowed to settle before returning to IDLE mode.
WAIT DATA SYNC This is the start of the transmit sequence. This mode is entered by the baseband writing to the control registers

(through the DBus). When this happens, TXEN goes high, turn ing on the synthesizer and initializing a fixed

delay, after which all the transmit circuits (except for the PA) are turned on (PD_TX=1). The baseband waits

175µs before it starts sending transmit data to the RF2968 (to allow the synthesizer to settle). The device can-

not be in both transmit and receive modes at the same tim e, so RXEN must be low to enter this mode.
DATA SYNC A transition on BDATA1 (0 to 1) starts the synchronization of data between the RF2968 and the baseband

device.
ENABLE PA The PA is powered up (PDPA=1) and ready to begin transmitting.
TX DATA Data is transmitted in this mode. (The synthesizer has settled and the data path synchronized.)
DISABLE PA The PAis powered down (PDPA= 0). 1µs later, the synthesizer and the rest of the transmit circuits are powered

down (PD_TX=0). This delay prevents any “unwanted transmission” during power down. T he device then

returns to IDLE mode when the baseband writes to the control registers and drives TXEN low.
RX PLL WAIT Thisis th e start of the receive s equence and is entered from IDLE mode when a control register write from the

baseband forces RXEN high. This turns on the synthesizer and starts a timer which powers up the receive path

circuits after a fixed delay (PD_RX=1). The baseband device expects to receive data 175µs after the control

register write.
RX DATA Received data is s ent to the ba seband device via BDATA1 (unsynchronized) and RECDATA (synchronized with

RECCLK). Within this state, there are two DC estimation modes. In the “access code” mode, the RF2968 uses

a fast DC es timation to adjust for large frequency offsets. An inter nal timer (or alternatively BPKTCTL) signals

the end of the sync word , placing the DC estimation circuitry in the “payload” mode, in which compensation is

made for small frequency offsets. A control register write from the baseband drives RXEN low and returns the

device to IDLE mode. This turns off the receive path (PD_RX=0) and the synthesizer.

Preliminary

TRANSCEIVERS

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Preliminary

RF2968

State Machine
The RF2968 state machine is clocked with a 1MHz signal which is derived from the reference oscillator. (The mark -

space ratio of this 1MHz clock and its precise frequency are not important.) The inputs and outputs for all the states are
summarized in the table below.

Table 1. State Machine Inputs and Outputs

Inputs Outputs

Previous State

X OFF 0XXXXX00000

OFF PWRON WAIT 1 0 1 X X X 1 1 0 0 0

PWRONWAITHOLDXTL 1 1 1 X 00 1 1000

HOLD XTL IDLE 1 1 X X 0 0 1 1 0 0 0

IDLE SLEEP 1 0 X X 00 0 1000

SLEEP WAIT XTL 1 1 X X 0 0 1 1 0 0 0

WAIT XTL IDLE 1 1

IDLE WAIT DATA SYNC 1 1 X

WAIT DATA DAT A SYNC 1 1 X

DATA SYNC ENABLE PA 1 1 X 1 X 1 1 1 1 1 0
ENABLEPA TXDATA 1 1 X 1 X1 1 1110

TX DATA DISABLE PA 1 1 X 0 X 1 1 1

DISABLE PA IDLE 1 1 X X

IDLE RX PLL WAIT 1 1 X X 1 0 1 1 0 0

RX PLL WAIT RX DATA 1 1 X X 1 0 1 1 0 0 1

RXDATA IDLE 1 1 X X 0X 1 1000

Present State

a

BnPWR BXTLEN BDATA1BPKTCTL RXEN TXEN PDXTAL CLRB PDTX PDPA PDRX

X

X 00 1 1000

e

0
0

01 1 1

e

X1 1 1100

f

0 1 1000

X

b

1

c

0

00

00

d

1

Notes:
a. When the inputs try to force the controller into an undefined or illegal state, the state machine will remain in its

present state (e.g., if the present state is IDLE and the inputs tr y to force the device to TX DATA, the chip will stay in

IDLE mode).
b. PD_TX goes high after a fixed delay following TXEN going high.
c. 1µs delay from the PD_PA going low to PD_TX going low.
d. PD_RX goes high after a fixed delay following RXEN going high.
e. BPKTCTL must be low to distinguishDATA SYNC from ENABLE PA.
f. If RXEN=1 when entering IDLE from DISABLE PA, then IDLE is held for 1µs, after which the state transitions to RX

PLL WAIT.

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RF2968

Preliminary

Special Modes of Operation

Calibration
WhentheRF2968isReset (CLRB=0), all calibration values are cleared. Therefore, after the RF2968 is powered up

from the OFF state, it must be instructed to perform its self-calibration. Circuits requiring calibration include the RX vari­able gain amplifier (VGA), TX and RX PLL’s, RX channel filter, RX data paths, and TX Gaussian filter.

Calibration instructions are sent from the baseband to the RF2968 via the ser ial port (addressing Registers 5 and 7) and
must be performed in the order shown in the table below. After a calibration instruction is sent, the baseband must delay
for the length of time indicated before sending the next calibration instruction; this allows time for the RF2968 circuits to
settle and execute the instruction. At initialization, BypassSM, PU_XTAL, PU_MULT, and TX_EN are set high and
remain so for the duration of the calibration. Register 7 is only addressed during initializationto set TX_EN and configure
the reference frequency and RF PLL frequency.

.

Bit Settings for Calibration Sequence

Calibration Steps Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Required Time ( usec)

Initialization of PLL 7 0 0 0 0
Initialization of

Chip Control

CalibrateK

RX IF PLL’s

Calibrate Gaussian TX

and RX VGA

CalibrateIF Filters 5
CalibrateRX Offsets 5
Return Chip Control to

State Machine

of TX and

O

5 1000000011000000 2500

5 1 0 0 0 010 0 1 1 0 0 0 0 0 0 1024

1 0 0 01010 1 1 0 0 0101 285

5

1 0 0 00000 1 110 0 1 0 1608
1 0 0 0 0 0 0 0 1 1010 1 00 64

50

0 0 0 0 0 0 00000000 00

bxbxb

x

10

cxcxcxcxcxcxc

x

Total Calibration Time: 4481

a

d

0

11

Notes:
a) Shaded cells indicate no change from previous state.
b) Set according to reference frequency.
c) Set RF PLL frequency to a valid frequency (LO =2403 to 2481MHz).
d) Register 5 may be programmed immediately after Register 7.

TRANSCEIVERS

Transmitter Test Mode:
During normal TX mode, the transmitter's IF PLL is opened for modulation of the current controlled oscillator (ICO) for a

short period of time (0.4 to 3ms). For development purposes, open-loop m odulation may be performed for an indefinite
period of time by externally supplying the required ICO control voltage. This allows the ICO to maintain a locked condi­tion.

Transmitter Test Mode utilizes the LPO pin, which is switched to the output of the internal loop filter of the transmitter’s IF
ICO when Set_Tx_PLL_LF_Ext (Register 7, Bit 15) is set high and the 3.2kHz/32kHz low power oscillator is not in use.
This pin may be used either to monitor the control voltage during a packet transmission or to externally supply the control
voltage for an extended or continuous transmission. When monitoring the ICO control voltage, the voltage on the LPO
pin will dr ift from its initial voltage as the transmission time increases, but should remain in the range of 0.7V to 0.9V.
When supplying the ICO control voltage, the voltage to be applied to the LPO pin should be equal to the initial voltage
measured when monitoring.

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