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Product Description
Ordering Information
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro,NC 27409, USA
Tel (336)664 1233
Fax (336)664 0454
http://www.rfmd.com
Optimum Technology Matching® Applied
Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS
SiGe HBT
Si CMOS
25
RESNTR+
26
VCO OUT
29
DATA OUT
31
LVLADJ
32
RX ENABL
8MIX IN
6LNA OUT
4RX IN
2TX OUT
1TX ENABL 24 RESNTR-
23 MOD IN
22 DATA REF
21 DEMOD IN
19 IF2 BP-
18 IF2 BP+
17 IF2 IN
PA
LNA
Control
Logic
Gain
Control
Linear
RSSI
27
GND4
28
VCC1
30
VCC3
3GND2
5GND1
7GND3
9
GND5
10
MIX OUT+
11
VBG
12
RSSI
13
IF1 IN
14
IF1 BP+
15
IF1 BP-
16
IF1 OUT
20 GND6
RF2945
433/868/915 M HZ FSK/ASK/OOK TRANSCEIVER
• Wireless Meter Reading
• Keyless Entry Systems
• 433, 868 and 915MHz ISM Band Systems
• Wireless Data Transceiver
• Wireless Security S ystems
• Battery-Powered Portable Devices
The RF2945 is a monolithic integrated circuit intended for
use as a low cost FM transceiver. The device is provided
in 32-lead plastic LQFP packaging and is designed to be
used with a PLL IC to provide a fully functional FM transceiver. The chip is intended for digital (ASK, FSK, OOK)
applications in the North American 915MHz ISM band
and European 433/868MHz ISM bands. The integrated
VCO has a buffered output to feed the RF signal back to
the PLL IC to for m the frequency synthesizer. Internal
decoding of the RXENABL and TX ENABL lines allow for
half duplex operation as well as turning on the VCO to
give the synthesizer time to settle and complete power
downmode. The DATA REF line allows the use of an
external capacitor to control the DC level at the adaptive
Data Slicer input for setting the bit decisionthreshold.
• Fully Monolithic Integrated Transceiver
• 2.4V to 5.0V Supply Voltage
• Narrowband and Wideband FSK
• 300MHz to 1000MHz Frequency Range
• 10dB Cascaded Noise Figure
• 10mW Output Power With Power Control
RF2945 433/868/915MHz FSK/ASK/OOK Transceiver
RF2945 PCBA-L Fully Assembled Evaluation Board (433MHZ)
RF2945 PCBA-M Fully Assembled EvaluationBoard (868MHZ)
RF2945 PCBA-H FullyAssembled Evaluation Board (915MHz)
11
Rev A10 000919
7° MAX
0° MIN
+
0.15
0.10
0.60
0.127
7.00
+0.20sq.
5.00
+0.10sq.
0.22
+0.05
Dimensions in mm.
0.15
0.05
-A-
1.40
+0.05
0.50
Package Style: LQFP-32_5x5
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TRANSCEIVERS
Absolute Maximum Ratings
Parameter Ratings Unit
Supply Voltage -0.5 to +5.5 V
DC
Control Voltages -0.5 to +5.0 V
DC
Input RF Level +10 dBm
Output Load VSWR 50:1
Operating Ambient Temperature -40 to +85 °C
Storage Temperature -40 to +150 °C
Parameter
Specification
Unit Condition
Min. Typ. Max.
Overall
T=25°C, VCC=3.6V, Freq=915MHz
RF Frequency Range 300 to 1000 MHz
VCO and PLL Section
VCO Frequency Range 300 to 1000 MHz
VCO OUT Impedance 50 Ω
VCO OUT Level -20 dBm Freq=915MHz
VCO/PLL Phase Noise -72 dBc/Hz 10kHz offset, 5kHz loop BW
-98 dBc/Hz 100 kHz offset, 5kHz loop BW
Transmit Section
Max Modulation Frequency 2 MHz
Min Modulation Frequency Set by loop filter bandwidth
Maximum Power Level +7 +8.5 dBm Freq=433MHz
1 +3 5 dBm Freq=915MHz
Power Control Range 12 dB
Power Control Sensitivity 10 dB/V
Max FM Deviation 200 kHz Instantaneous frequency deviation is
inversely proportional with the modulation
voltage. Dependent on external circuitry.
Antenna Port Impe dance 50 Ω TX ENABL= “1”, R X ENABL=“0”
Antenna Port VSWR 1.5:1 TX Mode
Modulation Input Impedance 4 kΩ
Harmonics -38 dBc Freq=915MHz, with eval board filter
Spurious dBc Compliant to Part 15.249 and I-ETS 300 220
Overall Receive Section
Frequency Range 300 to 1000 MHz
Cascaded Voltage Gain 35 dB Freq=433MHz
23 dB Freq=915MHz
Cascaded Noise Figure 10 dB
Cascaded Input IP
3
-31 dBm Freq=433MHz
-26 dBm Freq=915MHz
RX Sensitivity -91.5 -96 dBm IF BW=400kHz, Freq=915MHz, S/N=8dB
LO Leakage -55 dBm Freq=915MHz
RSSI DC Output Range 0.5 to 2.5 V R
LOAD
=51kΩ
RSSI Sensitivity 22.5 mV/dB
RSSI Dynamic Range 70 80 dB
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
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TRANSCEIVERS
Parameter
Specification
Unit Condition
Min. Typ. Max.
LNA
VoltageGain 23 dB 433MHz
16 dB 915MHz
Noise Figure 4.8 dB 433MHz
5.5 dB 915MHz
Input IP
3
-27 dBm 433 MH z
-20 dBm 915 MH z
Input P
1dB
-37 dBm 433 MH z
-30 dBm 915 MH z
Antenna Port Impedance 50 Ω RX ENABL=“1”, TX ENABL=“0”
Antenna Port VSWR 1.5:1 RX Mode
Output Impedance Open Collector Ω 433MHz and 915MHz
Mixer
Single-ended configuration
Conversion Voltage Gain 8 dB 433MHz
7 dB 915MHz
Noise Figure (SSB) 10 dB 433MHz
17 dB 915MHz
Input IP
3
-21 dBm 433 MH z
-17 dBm 915 MH z
Input P
1dB
-31 dBm 433 MH z
-28 dBm 915 MH z
First IF Section
IF Frequency Range 0.1 10.7 25 MHz
VoltageGain 34 dB IF=10.7MHz, Z
L
=330Ω
Noise Figure 13 dB
IF1 Input Impedance 330 Ω
IF1 Output Impedance 330 Ω
Second IF Section
IF Frequency Range 0.1 10.7 25 MHz
VoltageGain 60 dB IF=10.7MHz
IF2 Input Impedance 330 Ω
IF2 Output Impedance 1 kΩ At IF2 OUT pin
Demod Input Impedance 10 kΩ
Data Output Bandwidth 1.4 MHz 3dB Bandwidth, Z
LOAD
=1MΩ || 3pF
Data Output Level 0.3 V
CC
-0.3 V Z
LOAD
=1MΩ || 3pF. Output voltage is pro-
portional with the instantaneous frequency
deviation.
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TRANSCEIVERS
Parameter
Specification
Unit Condition
Min. Typ. Max.
Power Down Control
Logical Controls “ON” 2.0 V Voltage supplied to the input
Logical Controls “OFF” 1.0 V Voltage supplied to the input
Control Input Impe dance 25k Ω
Turn On Time 1 ms Turn on/off times are dependent upon
Turn Off Time 1 ms PLL loop parameters
RX to TX and TX to RX Time 100 µs
Power Supply
Voltage 3.6 V Specifications
2.7 5.0 V Operating limits
Temperature range -40°C to +85°C
2.4 V Operating limits
Temperature range +10°C to +40°C
Current Consumption 17 22 27.4 mA TX ENABL, LVLADJ=3.6V,RX ENABL=0V
4.8 6.1 7.2 mA TX ENABL=3.6V, LVLADJ, RXENABL=0V
4.4 6.1 6.8 mA TX ENABL= 0V,RX ENABL=3.6V
1 µA TX ENABL, LVLADJ, RX ENABL=0V
3.6 mA PLL Only Mode, TX ENABL,
RX ENABL=3.6V, LVLADJ=0V
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TRANSCEIVERS
Pin Function Description Interface Schematic
1 TX ENABL
Enables the transmitter circuits. TX ENABL>2.0V powers up all transmitter functions. TX ENABL<1.0V turns off all transmitter functions
except the PLL functions.
2TXOUT
RF output pin for the transmitter electronics. TX OUT output impedance
is a low impedance when thetransmitter is enabled. TX OUT is a high
impedance when the transmitter is disabled.
3GND2
Ground connection for the 40 dB IF limiting amplifier and Tx PA functions. Keep traces physically short and connect immediately to ground
plane for best performance.
4RXIN
RF input pin for the receiver electronics. RX IN input impedance is a
low impedance when the transmitter is enabled. RX IN is a high impedance when the receiver is disabled.
5GND1
Ground connection for RF receiver functions. Keep traces physically
short and connect immediately to ground plane for best performance.
6LNAOUT
Output pin for the receiver RF low noise amplifier. This pin is an open
collector output and requires an exter n al pull up coil to provide bias and
tune the LNA output. A capacitor in series with this outputcan be used
to match the LNA to 50Ω impedance image filters.
7GND3
Same as pin 3.
8 MIX IN
RF input to the RF Mixer. An LC matching network b etween LNA OUT
and MIX IN can be us ed to connect the LNA output to the RF mixer
input in applications where an image filter is not needed or desired.
9GND5
GND5 is the ground connection shared by the input stage of the transmit power amplifier and the receiver RF mixer.
10 MIX OUT
IF output from the RF mixer. Interfaces directly to 10.7MHz ceramic IF
filters as shown in the application schematic . A pull-up inductor and
series matching capacitor s hould be used to present a 330Ω termination impedance to the ceramic filter.Alternately, an IF tank canbe used
to tailor the IF frequency and bandwi dth to meet the needs of a given
application.
11 VREF IF
DC voltage reference for the IF limiting amplifiers. A 10nF capacitor
from this pin to ground is required.
.
12 RSSI
A DC voltage proportional to the received signal strength is output from
this pin. The output voltage range is 0.5V to 2.3V an d increases w ith
increasing signal strength.
13 IF1 IN
IF input to the40dB limiting amplifier strip. A 10nF DC blocking capacitor is required on this input.
40 k
Ω
20 k
Ω
TX ENABL
TX OUT
20
V
CC
RX IN
500
LNA OUT
V
CC
GND5
MIX IN
MIX OUT
15 pF 15pF
GND5 GND5
V
CC
RSSI
IF1 IN
330 330
60 k
Ω
60 k
Ω
IF1 BP+ IF1 BP-
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TRANSCEIVERS
Pin Function Description Interface Schematic
14 IF1 BP+
DC feedback node for the 40dB limiting amplifier strip. A 10nF bypass
capacitor from this pin toground is required.
See pin 13.
15 IF1 BP-
Same as pin 14. See pin 13.
16 IF1 OUT
IF output from the 40dB limiting amplifier. The IF1 OUT output presents
a nominal 330 Ω output resistance and interfaces directly to 10.7MHz
ceramicfilters.
17 IF2 IN
IF input to the 60dB limiting amplifier s trip. A 10nF DC blocking capacitor is required on this input. The IF2 IN input presents a nominal 330 Ω
input resistance and interfaces directly to 10.7MHz ceramic filters.
18 IF2 BP+
DC feedback node for the 60dB limiting amplifier strip. A 10nF bypass
capacitor from this pin toground is required.
See pin 17.
19 IF2 BP-
Same as pin 18. See pin 17.
20 GND6
Ground connection for 60dB IF limiting amplifier. Keep traces physically
short and connect immediately to ground plane for best perfor m ance.
21 DEMOD IN
This pin is the input tothe FM demodulator.This pin is NOT AC coupled. Therefore, a DC blocking capacitor is required on this pin to avoid
shorting the demodulator input with the LC tank. A ceramic discriminator or DC blocked LC tank resonant at the IF should be connected to
this pin.
22 DATA REF
This pin is used for settingthe adaptive Data Slicer DC reference level.
A capacitor from this pin to ground can be u sed to set the reference
level at the average DC level of the data b it stream.The DC level determines the bit decision threshold.
23 MOD IN
FM analog or digital modulation can be imparted to the V CO through
this pin. The VCO varies in accordance to the voltage level presented
to this pin. To set the deviation to a desired level, a voltage divider referenced to Vcc is the recommended. This deviation is a lso dependent
upon the overall capacitance of the external resonant circuit.
See pin 24.
24 RESNTR+
This port is used to supply DC voltage to the VCO as well as t o tune the
center frequency of the VC O. Equal value inductors should be connected to this pin and pin 25 although a small imbalance can be used
to tune in the proper frequency range.
25 RESNTR-
See RESNTR+ description. See pin 24.
26 VCO OUT
This pin is used is s upply a buffered VCO output to go to the PLL chip.
This pin has a DC bias and needs to be AC coupled.
27 GND4
GND4 is the ground shared on chip bythe VCO, prescaler, and PLL
electronics.
IF1 OUT
IF2 IN
330 330
60 k
Ω
60 k
Ω
IF2 BP+ IF2 BP-
DEMOD IN
10 k
Ω
V
CC
50k
Ω
DATA REF
RESNTR-RESNTR+
4k
Ω
MOD IN
VCO OUT
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TRANSCEIVERS
* LVL ADJ pin must be low todisable transmitter.
Pin Function Description Interface Schematic
28 VCC1
This pin is used to supply DC bias to the LNA, Mixer, 1st IF Amp and
Bandgap reference. A RF bypass capacitor should be connected
directly to this pin and returned to ground. A 22pF capacitor isrecommended for 915MHz applications. A 68pF capacitor is recommended
for 433MHz applications.
29 DATA OUT
Demodulated data output from the demodulator. Output levels on this
are TTL/CMOS compatible. The magnitude of the load impedance is
intended to be 1MΩ or greater.
30 VCC3
This pin is used to supply DC bias and collector current tothe transmitter PA. It also supplies voltage to the 2
nd
IF Amplifier, Demod and data
slicer. A RF bypass capacitor should be connected directly to this pin
and returned to ground. A 22pF capacitor is recommended for 915MHz
applications. A 68pF capacitor is recommended for 433MHz applications.
31 LVL ADJ
This pin is used to vary the transmitter output power. An output level
adjustment range greater than 12dB is provided through analog voltage control of this pin. DC current ofthe transmitter power amp ia also
reduced with output power.
NOTE: This pin MUST be low when the transmitter is disabled.
32 RX ENABL
Enable pin for the receiver cir cuits. RX ENABL>2.0V powers up all
receiver functions. RX ENABL<1.0V turns off all receiver functions
except the PLL functions and the RF mixer.
Operation
Mode
TX ENABL RX ENABL Function
Sleep Mode
Low Low Entire chip is powered down. Total current consumption is <1µA. *
Transmit Mode
High Low Transmitter, VCO are on.
Receive Mode
Low High Receiver, VCO are on. *
PLL Lock
High High VCO is on. This mode allows time for a synthesizer loop to lock without
spending current on the transmitter or receiver.
DATA OUT
400 4k
Ω
LVL ADJ
40 k
Ω
50 k
Ω
RX ENABL
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RF2945 Theory of Operation and Application Information
The RF2945 is part of a family of low-power RF transceiver IC’s that was developed for wireless data communicationdevices operating in the European 433MHz
to 868 MHz ISM band, and 915MHz U.S. ISM band.
This IC has been implemented in a 15GHz silicon
bipolar process technology that allows low-power
transceiver operation in a variety of commercial wireless products.
In its basicform, the RF2945 can be implemented as a
two-way half-duplex FSK transceiver with the addition
of some crystals, filters, and passive components. The
RF2945 is designed to interface with common PLL IC’s
to form amulti-channel radio. The receiver IF section is
optimized to interface with low-cost 10.7MHz ceramic
filters and has a 3dB bandwidth of25MHz and can still
be used (with lower gain) at higher frequencies w ith
other types of filters. The PA output and LNA input are
available on separate pins andare designed to be connected together through a DCblocking capacitor. In the
transmit mode, the PA will have a 50Ω impedance and
the LNA will have a high impedance. In the receive
mode, the LNA will have a 50Ω impedance and the PA
will have a high impedance. This eliminates the need
for a TX/RX switch, and allows for a single RF filter to
be used in transmit and receive modes. Separate
access to the PA and LNA allows the RF2945 to interface with external components such as a high power
PA, lower NF LNA, upconverters, and downconverters,
for a variety of implementations.
FM/FSK SYSTEMS
The MOD IN pin dr ives an internal varactor for modulatingtheVCO.Thispincanbedrivenwithavoltage
level needed to generate the desired deviation. This
voltage can be carried on a DC bias to select desired
slope (deviation/volt) for FM systems. Or, a resistor
divider network referenced to VCC or ground can
divide down logic level signals to the appropriate level
for a desired deviation in FSK systems.
On the receiver demod, the DATA OUT pin is the output of an internal data slicer providing logic level outputs. The digital output is generated by a data slicer
that compares the demodulator with a DC reference
voltage recovered from the demodulator. The reference voltage is obtained by a filter capacitor on pin 22.
An on-chip 1.6MHz RC filter is provided at the demodulator output to filterthe undesirable 2xIF product. This
type data slicer has the ability to track out minor frequency errors in the system, but requires a longer
period of time for thepreamble for optimum results. For
best operation of the on-chip data slicer, FM deviation
needs to be larger than 40kHz
P-P
.
The data slicer itself is a transconductance amplifier,
and the DATA OUT pin is capable of driving rail-to-rail
output only into a very high impedance and a small
capacitance.The amount of capacitance will determine
the bandwidth of DATA OUT. In a 3pF load, the bandwidth is in excess of 500kHz. The rail-to-rail output of
the data slicer is alsolimited by the frequency deviation
and bandwidth of IF filters. With the 400kHz bandwidth
filters on the evaluation boards, the rail-to-rail output is
limited to less than 320kHz. Choosing the right IF
bandwidth and deviation versus data rate (mod index)
is important in evaluating the applicability of the
RF2945 for a given data rate.
The primary consideration when d irectly modulating
the VCO is the data rate versus PLL bandwidth. The
PLL will track out the modulation to the extent of its
bandwidth, which distorts the modulating data. Therefore, the lower frequency components of the modulating data should be five to 10 times the loop bandwidth
to minimize the distortion. The lower frequency components are generated by long strings of 1’s and 0’s in
data stream. By limiting the number of consecutive,
same bits, lower frequency components can be set. In
addition, the data stream should be balanced to minimize distortion. Using a coding pattern such as
Manchester is highlyrecommended to optimize system
performance.
The PLL loop bandwidth is important in several system
parameters. For example, switching from transmit to
receive requires the VCO to retune to another frequency. Theswitching speed is proportional to theloop
bandwidth: the higher the loop bandwidth, the faster
the switching times. Phase noise of the VCOis another
factor. Phase noise outside the bandwidth is because
of the VCO itself, rather than a crystal reference. The
design trade-offs must be made here in selecting a
PLL loop bandwidth with acceptable phase noise and
switching characteristics, as well as minimal distortion
of the modulation data.
ASK/OOK SYSTEMS
The transmitter of the RF2945 has an output power
level adjust (LVL ADJ) that can be used to provide
approximately 18dB of power control for amplitude
modulation. The RSSI output of the receiver section
can be used to recover the modulation. The RSSI output is from a currentsource, and needs to have a resis-
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11
TRANSCEIVERS
tor to convert to a voltage. A 51kΩ resistor load
typically produces an output of 0.7V to 2.5V. A parallel
capacitor is suggested to band limit the signal. For
ASK applications, the 18dB range of the LVL ADJ
does not produce enough voltage swing in theRSSI for
reliable communications. The on/off keying (OOK) is
suggested to provide reliable communications. To
achieve this, the LVL ADJ and TX ENABL need to be
controlled together (please note that LVL ADJ cannot
be left high when TX ENABL is low). This will provide
an on/off ratio of greater than 50dB. One of the unfortunate consequences of modulating in this manner is
VCO pulling by the PA. This results in a spurious output outside the desired transmit band, as the P LL
momentarily loses lock and reacquires. This may be
avoided by pulse-shaping TX data to slow the change
intheVCOloadtoapacewhichthePLLcantrackwith
its given loop bandwidth. The loop bandwidth may also
be increased to allow it to track faster changes brought
about by load pulling.
For the ASK/OOK receiver demodulator, an external
data slicer is required. The RSSI output is used to provide both the filter data and a very low pass filter (relative to the data rate) DC reference to the data slicer.
Because the very low pass filter has a slow time constant, a longer preamble may be required to allow for
the DC reference to acquire a stable state. Here, as in
the case of the FSK transmitter, the data pattern also
affects the DC reference and the reliability of the
receive data. Again, a coding scheme such as
Manchester should be used to improve data integrity.
APPLICATION AND LAYOUT CONSIDERATIONS
Both the RX IN and the TX OUT have a DC bias on
them. Therefore, a DC blocking cap is required. If the
RF filter has DC blocking characteristics (such as a
ceramic dielectric filter), then only one DC blockingcap
would be needed to separate the DC ofthe RX andTX.
These are RF signals and care should be taken to run
the signal keeping them physically short. Because of
the 50Ω/high impedance nature of these two signals,
they may be connected together into a single 50Ω
device (such as a filter). An external LNA orPAmay be
used, if desired, but an external RX/TX switch may be
required.
The VCO is a very sensitive block in the system. RF
signals feeding back into the VCO (either radiated or
coupled by traces) may cause the PLL to become
unlocked. The trace(s) for the anode of the tuning varactor should also be kept short. The layoutof the resonator and varactor are very important. The capacitor
and varactor should be c lose to the RF2945 pins, and
the trace length should be as short as possible. The
inductors may be placed further away, and reducing
the value of the inductors can compensate any trace
inductance. Printed inductors may also be used with
careful design. For best results, physical layout should
be as symmetrical as possible. Figure 1 is a recommended layoutpattern forthe VCO components. When
using the loop bandwidth lower than 5kHz shown on
the evaluation board, better filtering of the VCC at the
resonators (and lower VCC noise, as well) will help
reduce phase noise of the VCO. A series resistor of
100 Ω to 200Ω,anda1µF or larger capacitor may be
used.
For the interface between the LNA/mixer, the coupling
capacitor should be as close to the RF2945 pins as
possible, with the bias inductors further away. Once
again, the value of the inductor may be c hanged to
compensate for trace inductance. The output impedance of the LNA is in the order of several kΩ,which
makes matching to 50Ω very difficult. If image filtering
is desired, a high impedance filter is recommended.
The quad tank of the discriminator may be implemented with ceramic discriminator available from a
couple of sources. This design works well for wideband
applications where temperature range is limited. The
temperature coefficient of ceramic discriminators may
be in the order of +50ppm/°C. The alternative to the
ceramic discriminator is the LC tank, which provides a
broadband discriminator more useful for high data
rates.
Not to Scale
Representative of Size
24
23
Loop
Voltage
VCC
25
26
Figure 1. Recommended VCO Layout
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PLL Synthesizer
The RF2945 evaluation board uses an LMX2316 PLL
IC from National Semiconductor. This PLL IC may be
programmed from the software available from National
Semiconductor (codeloader at www.national.com/
appinfo/wireless/). An external reference oscillator is
required for the PLL IC allowing for the evaluation of
different reference frequencies or step sizes. The
National Semiconductor software also has a calculator
for determining the R and C component values for a
given loop bandwidth.
The RF2945 is controlled by RX ENABL and TX
ENABL which are decoded to put the RF2945 into one
of four states. It may be put into a PLL-only mode with
TX ENABL and RX ENABL both high. This condition is
used to provide time for the synthesizer to turn on and
obtain lock before turning on the receiver or transmitter. Note that LVL ADJ needs to be held low for PLLonlymode.Sometimes,itisdesirabletorampupthe
power amplifier to minimize load pulling on the VCO.
To do this with the RF2945, first put the RF2945 into
PLL mode by putting TX ENABL and RX ENABL high.
Then,rampupLVLADJtoturnonthetransmitterand
PA. The rate at which LVL ADJ is allowed to ramp up is
dependent on the PLL loop bandwidth. V CC pushing
also affects the VCO frequency. A good low pass filter
on VCC willminimize the VCC pushing effects.
For applications requiring fast switching speeds or
turn-on times, and low data rate loop filter bandwidths,
the LMX2316 may be configured to drive the loop filter
in a fast switching mode. Please refer to literature on
the LMX2316 for more information.
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TRANSCEIVERS
Pin Out
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32 293031 28 27 26 25
9121110 13 14 15 16
RESNTR+
MOD IN
DATA REF
DEMOD IN
GND6
IF2 BP-
IF2 BP+
IF2 IN
RESNTR-
VCO OUT
GND4
VCC1
DATA OUT
VCC3
LVL ADJ
RX ENABL
IF1 OUT
IF1 BP-
IF1 BP+
IF1 IN
RSSI
VREF IF
MIX OUT
GND5
MIX IN
GND3
LNA OUT
GND1
RX IN
GND2
TX OUT
TX ENABL
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Application Sche matic - 915 MHz
2526293132
8
6
4
2
1 24
23
22
21
19
18
17
PA
LNA
Control
Logic
Gain
Control
Linear
RSSI
272830
3
5
7
9 10 11 12 13 14 15 16
20
RX ENABL
TX ENABL
MOD IN
100 pF
100 pF
915 MHz SAW
10 nH
10 pF
22 pF10 nF
10
Ω
V
CC
Filter
10 nF10 nF
Filter
11 pF
8.2 uH
22 pF10 nF
10
Ω
V
CC
10 pF51 k
Ω
RSSI
10 nF
10 nF
FM Disc.
TBD
1.5 k
Ω
10 nF
D1
SMV1233-
011
2
pF
8.2
nH
8.2
nH
22 pF 10nF
100
Ω
V
CC
10 k
Ω
33 pF
PLL
IC
100
Ω
4.7
nF
30 k
Ω
330
pF
10 k
Ω
TBD
22 pF22 pF
10 nF10 nF
10
Ω
V
CC
10
Ω
V
CC
LVL ADJ
DATA OUT
Page 13
11-227
RF2945
Rev A10 000919
11
TRANSCEIVERS
Application Schematic - 915 MHz
IF=25MHz, BW=2MHz
2526293132
8
6
4
2
1
24
23
22
21
19
18
17
PA
LNA
Control
Logic
Gain
Control
Linear
RSSI
272830
3
5
7
9 10 11 12 13 14 15 16
20
TX ENABL
C6
22 pF
C7
22 pF
L4
10 nH
C21
10 pF
C22
22 pF
C23
0.1 uF
R7
10
Ω
C13
10 nF
C12
10 nF
C57
100 pF
L5
680 nH
C25
22 pF
C26
0.1 uF
R9
10
Ω
C10
10 nF
C11
10 pF
R3
51 k
Ω
RSS
I
C14
10 nF
C15
10 nF
C19
2.2 nF
C31
39 pF
50Ωµstrip
R80
0
Ω
C30*
4pF
C8
4pF
L1
8.2 nH
C9
4pF
J2
RF
R6*
N/C
L11
680 nH
C55
39 pF
C24
5pF
C5
4.7 uF
+
C27
39 pF
VCC
C54
10 pF
C53
47 pF
L10
680 nH
C56
3pF
C59
47 pFL9680 nH
C52
10 pF
C51*
4-22 pFL8680 nH
C20
10 nF
J4
MOD IN
50Ωµstrip
L3
8.2 nH
C16
2pF
D1
SMV1233-011
L2
8.2 nH
C17
22 pF
C18
0.1 uF
C81
4.7 uF
R4
100
Ω
VCC2
R14
10 k
Ω
C48
4.7 nF
R13
30 k
Ω
R12*
100
Ω
C47
330 pF
L7*
TBD
C50
22 pF
R60
0
Ω
C41
100 pF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VpFLo
VCC2CPo
Fo/LDGND
LEGND
DatafINb
ClockfIN
CEVCC1
GNDOSCin
C43
0.1 uF
C44
22 pF
VPLL
C34
1nF
VPLL
R24
27 k
Ω
R27
12 k
Ω
C32
22 pF
C33
0.1 uF
R11
10
Ω
VPLL
R25
27 k
Ω
R28
12 k
Ω
R26
27 k
Ω
R29
12 k
Ω
R30
51
Ω
50Ωµstrip
J5
REF OSC
RX ENABL
LVL ADJ
DATA OUT
C4
22 pF
C3
0.1 uF
R2
10
Ω
R1
10
Ω
C1
22 pF
C2
0.1 uF
C82
4.7 uF
+
C29
4.7 uF
+
VPLL/VCC2
1
2
P1
CON2
P1-1 VCC1
GND
P4
1
2
CON2
P4-1 RSSI
GND
N/C
GND
P2-1 LVLADJ
P2
1
2
3
CON3
P3
1
2
3
CON3
P3-1 TX ENABL
GND
P3-1 RX ENABL
P7
1
2
3
CON3
P7-1 VCC2
P7-3 VPLL
GND
P8
1
2
CON2
GND
P8-1 RX OUT
P6
DB9
4
957
6
183
2
LMX2316
Page 14
11-228
RF2945
Rev A10 000919
11
TRANSCEIVERS
Evaluation Board Schematic - 915MHz
(Download Bill of Materials from www.rfmd.com.)
C21
10 pF
L5
6.8 uH
C6
22 pF
C7
22 pF
C24
11 pF
C26
0.1 uF
R7
10
Ω
RX ENABL
P3-3
TX ENABL
P3-2
F1
SFE10.7MA21
R3
51 k
Ω
C11
10 pF
RSSI
F2
SFE10.7MA21
U4
CDF
107B-
A0-001
10.7MHz
C15
10 nF
C47
6.8nF
R87*
0
Ω
C50
22 pF
C17 22 pF
L3
8.2 nH
L2
8.2 nH
C16
2pF
C18 0.1 uF
R4
100
Ω
D1
SMV1233
-011
C1
22 pF
R1
10
Ω
P2-1
LVL ADJ
PLL LOOP BW ~5 kHz
R60
0
Ω
L7*
TBD
C58*
10 nF
R12
100
Ω
J5
REF OSC
R27
12 k
Ω
R28
12 k
Ω
R29
12 k
Ω
R24
27 k
Ω
R25
27 k
Ω
R26
27 k
Ω
P4-1
P4
RSSI
GND
1
2
P3-3
P3
1
2
3
4
5
TX ENABL
GND
RX ENABL
P3-2
NC
NC
P3-5
P3-4
V
PLL
(LMX2315)
VCC(RF2945)P1-1
P1-3
P1
GND
1
2
3
P2-1
P2-3
P2
GND
1
2
3
LVL ADJ
NC
C81 4.7 uF
C30*
5pF
C8
5pF
L1
8.2 nH
C9
5pF
J2
RF
C10
10nF
C12
10nF
C13
10nF
J1
RX OUT
J4
MOD IN
C27*
10 nF
J3
MIX OUT
* Denotes components that are normally depopulated.
16
17
232
10
8
Linear
RSSI
31
LNA
6
4
1
32 262425
13
19
18
11 1514
22
21
29
PA
Control
Logic
12
3
5
7
9
20
30 28 27
Gain
Control
C19
2.2 nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FLD
CPD
GND
GND
fNb
fIN
Vcc1
OSCin
Vp
Vcc2
FD/LD
LE
DATA
CLK
CE
GND
C33
0.1 uF
C32
22 pF
VPLL
R13
1.2k
Ω
C41
100 pF
C44
22 pF
C43
.01 uF
C34
1nF
R30
51
Ω
LMX2316
C49
TBD
L6*
2.2 uH
C28*
120 pF
R84
0
Ω
R83
0
Ω
C55*
100 pF
R8
8.2 k
Ω
C25
22 pF
R9
10
Ω
VCC1
C57*
100 pF
C56*
330 pF
L11*
680 nH
R82*
560
Ω
C54*
100 pF
C53*
330 pF
L10*
680 nH
R86
0
Ω
R85
0
Ω
C52*
100 pF
R81*
560
Ω
BW=400 kHz
10.7 MHz
VPLL
P6
DB9
4
957
6
1
2
3
8
R88
0
Ω
L8
4.7
uH
C51*
CAPVAR
C31
39
pF
R5*
4.3
k
Ω
C20
10 nF
2945400B
V
CC
50
Ω µ
strip
V
CC
C2
0.1 uF
C3
0.1 uFC422 pF
R2
10
Ω
C23
0.1
µ
f
L4
12 nH
R6*
N/C
V
CC
C22
22 pF
R80
0
Ω
C14
10 nF
C42 0.1 uF
R14
10 k
Ω
Page 15
11-229
RF2945
Rev A10 000919
11
TRANSCEIVERS
Evaluation Board Schematic - 433MHz
L
4
4
7
n
H
C21
33 pF
L5
6.8 uH
C6
100 pF
C7
100 pF
C24
12 pF
C26
0.1 uF
R7
10
Ω
RX ENABL
P3-3
TX ENABL
P3-2
F1
SFE10.7MA21
C12
10 nF
C13
10 nF
R3
51 k
Ω
C11
10 pF
RSSI
F2
SFE10.7MA21
U4
CDF
107BA0-001
10.7
MHz
C15
10 nF
C14
10 nF
C47
2.2 nF
C50
100 pF
C3
0.1
µ
F
R2
10
Ω
V
C
C
C18 0.1 uF
R4 100
Ω
D1
SMV1235
-011
C2
0.1
µ
F
R1
10
Ω
V
C
C
P2-1
LVL ADJ
PLLLOOPBW ~5kHz
R60
0
Ω
L7*
TBD
C42 33 nF
R12*
100
Ω
J5
REF O SC
R27
12 k
Ω
R28
12 k
Ω
R29
12 k
Ω
R24
27 k
Ω
R25
27 k
Ω
R26
27 k
Ω
P4-1
P4
RSSI
GND
1
2
P3-3
P3
1
2
3
4
5
TX ENABL
GND
RX ENABL
P3-2
NC
NC
P3-5
P3-4
V
PLL
(LMX2315)
V
CC
(RF2945)P1-1
P1-3
P1
GND
1
2
3
P2-1
P2-3
P2
GND
1
2
3
LVL ADJ
NC
C81 4.7 uF
C1
22 pFC422 pF
C30
8pF
C8
15 pF
L1
22 nH
C9
8pF
J2
RF
R6*
N/C
C10
10nF
J1
RX OUT
C27*
10 nF
J3
MIX OUT
* Denotes c omponents that are normally depopulated.
16
17
232
10
8
Linear
RSSI
LNA
6
4
1
32 262425
13
19
18
11 1514
22
21
29
PA
Control
Logic
12
3
5
7
9
20
30 28 27
Gain
Control
C19
2.2 nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FLD
CPD
GND
GND
fNb
fIN
Vcc1
OSCin
Vp
Vcc2
FD/LD
LE
DATA
CLK
CE
GND
C33
0.1 uF
C32
22 pF
VPLL
R13
4.7 k
Ω
C41
100pF
C44
22 pF
C43
.01 u F
R30
51
Ω
C34
1nF
LMX2316
R14
20 k
Ω
C49
220 pF
L6*
2.2 uH
C28*
120 pF
R84
0
Ω
R83
0
Ω
C55*
100 pF
R8
8.2 k
Ω
C25
100 pF
R9
10
Ω
VCC1
C57*
100 pF
C56*
330 pF
L11*
680 nH
R82*
560
Ω
C54*
100 pF
C53*
330 pF
L10*
680 nH
R86
0
Ω
R85
0
Ω
C52*
100 pF
R81*
560
Ω
BW=400 kHz
10.7 M Hz
VPLL
P6
DB9
4
957
6
123
8
L8
4.7
uH
C51*
3-10 pF
C31
39
pF
R5*
4.3
k
Ω
C20
10 nF
V
C
C
2945401-
V
C
C
C23
0.1
µ
F
C22
100 pF
L9
22 nH
R87*
0
Ω
C17 100 pF
L3
12 nH
L2
12 nH
C16
10 pF
C58*
10 nF
J4
MOD IN
R88
0
Ω
31
Page 16
11-230
RF2945
Rev A10 000919
11
TRANSCEIVERS
Evaluation Board Schematic - 868MHz
C21
9pF
L5
8.2 uH
C6
47 pF
C7
47 pF
C24
12 pF
C26
0.1 uF
R7
10
Ω
RX ENABL
P3-3
TX ENABL
P3-2
C10
10 nF
F1
SFE10.7MA21
C12
10 nF
C13
10 nF
R3
51 k
Ω
C11
10 pF
RSSI
F2
SFE10.7MA21
U4
CDF
107BA0-001
10.7MHz
C15
10 nF
C47
330 pF
R87*
0
Ω
C17 47 pF
L3
8.2 nH
L2
8.2 nH
C16
3pF
C18 0.1 uF
R4
100
Ω
D1
SMV1233
-011
C1
47 pF
R1
10
Ω
P2-1
LVL ADJ
PLL LOOP BW ~5 kHz
R60
0
Ω
L7*
TBD
C58*
10 nF
R12
100
Ω
J5
REF OSC
R27
12 k
Ω
R28
12 k
Ω
R29
12 k
Ω
R24
27 k
Ω
R25
27 k
Ω
R26
27 k
Ω
P4-1
P4
RSSI
GND
1
2
P3-3
P3
1
2
3
4
5
TX ENABL
GND
RX ENABL
P3-2
NC
NC
P3-5
P3-4
V
PLL
(LMX2315)
VCC(RF2945)P1-1
P1-3
P1
GND
1
2
3
P2-1
P2-3
P2
GND
1
2
3
LVL ADJ
NC
C81 4.7 uF
C30*
5pF
C8
5pF
L1
8.2 nH
C9
5pF
J2
RF
J1
RX OUT
J4
MOD IN
C27*
10 nF
J3
MIX OUT
* Denotes components that are normally depopulated.
16
17
232
10
8
Linear
RSSI
31
LNA
6
4
1
32 262425
13
19
18
11 1514
22
21
29
PA
Control
Logic
12
3
5
7
9
20
30 28 27
Gain
Control
C19
2.2 nF
C33
0.1 uF
C32
47 pF
R13
30 k
Ω
C41
47 pF
C44
47 pF
C43
.01 uF
C34
1nF
R30
51
Ω
C49*
TBD
L6*
2.2 uH
C28*
120 pF
R84
0
Ω
R83
0
Ω
C55*
100 pF
R8
8.2 k
Ω
C25
47 pF
R9
10
Ω
VCC1
C57*
100 pF
C56*
330 pF
L11*
680 nH
R82*
560
Ω
C54*
100 pF
C53*
330 pF
L10*
680 nH
R86
0
Ω
R85
0
Ω
C52*
100 pF
R81*
560
Ω
BW=400 kHz
10.7 MHz
VPLL
P6
DB9
4
957
6
1
2
3
8
R88
0
Ω
L8
4.7
uH
C51*
CAPVAR
C31
39
pF
R5*
4.3
k
Ω
C20
10 nF
2945402-
V
CC
50
Ω µ
strip
V
CC
C2
0.1 uF
C3
0.1 uFC447 pF
R2
10
Ω
C23
0.1
µ
f
L4
12 nH
R6*
N/C
V
CC
C22
47 pF
R80
0
Ω
C14
10 nF
C48 4.7 nF
R14
10 k
Ω
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FL
0
CP
0
GND
GND
fINb
fIN
VCC1
OSCin
Vp
VCC2
F0/LD
LE
DATA
CLK
CE
GND
LMX2316
C50
47 pF
R11
10
Ω
V
PLL
Page 17
11-231
RF2945
Rev A10 000919
11
TRANSCEIVERS
Evaluation Board Layout - 915MHz
Board Size 3.050” x 3.050”
Board Thickness 0.031”, Board Material FR-4
Page 18
11-232
RF2945
Rev A10 000919
11
TRANSCEIVERS
Page 19
11-233
RF2945
Rev A10 000919
11
TRANSCEIVERS
Evaluation Board Layout - 433MHz
Page 20
11-234
RF2945
Rev A10 000919
11
TRANSCEIVERS
Page 21
11-235
RF2945
Rev A10 000919
11
TRANSCEIVERS
Evaluation Board Layout - 868MHz
Page 22
11-236
RF2945
Rev A10 000919
11
TRANSCEIVERS
Page 23
11-237
RF2945
Rev A10 000919
11
TRANSCEIVERS
RSSI Output versus Temperature
V
CC
= 2.4 V, 915 MHz
0.0
0.5
1.0
1.5
2.0
2.5
-130.0 -110.0 -90.0 -70.0 -50.0 -30.0 -10.0 10.0
Received SignalStrength (dBm)
RSSI Output (V)
-40C
10C
25C
40C
85C
P
OUT
versus Level Controland V
CC
915 MHz and Temperature= 25°C
-30.0
-20.0
-10.0
0.0
10.0
0.0 1.0 2.0 3.0 4.0 5.0
Level Control(V)
P
OUT
(dBm)
Vcc=2.4V
Vcc=2.7V
Vcc=3.0V
Vcc=3.3V
Vcc=3.6V
Vcc=3.9V
Vcc=4.2V
Vcc=4.5V
Vcc=4.8V
TX Power Output and ICC versus Level Adjust
at 433MHz, 3.6V V
CC
-15.0
-10.0
-5.0
0.0
5.0
10.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
LVL ADJ (V)
RF P
0
(dBm)
5.0
10.0
15.0
20.0
25.0
30.0
ICC (mA)
Pout(433)
Icc(433)
TX Power Output and ICC versus Level Adjust
at 868MHz, 3.6V V
CC
-20.0
-15.0
-10.0
-5.0
0.0
5.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
LVL ADJ (V)
RF P
0
(dBm)
5.0
10.0
15.0
20.0
25.0
30.0
ICC (mA)
Pout(868)
Icc(868)
TX Power Output and ICC versus Level Adjust
at 905MHz, 3.6V V
CC
-20.0
-15.0
-10.0
-5.0
0.0
5.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
LVL ADJ (V)
RF P
0
(dBm)
5.0
10.0
15.0
20.0
25.0
30.0
ICC (mA)
Pout(905)
Icc(905)
Receive Currentversus V
CC
(Excluding PLL IC)
4.0
5.0
6.0
7.0
8.0
9.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage(V)
ICC (mA)
Icc (433)
Icc (868)
Icc (905)
Page 24
11-238
RF2945
Rev A10 000919
11
TRANSCEIVERS
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