Datasheet PIC12F1571, PIC12F1572, PIC12LF1571, PIC12LF1572 Datasheet

PIC12(L)F1571/2

8-Pin MCU with High-Precision 16-Bit PWMs

Description:

PIC12(L)F1571/2 microcontrollers combine the capabilities of 16-bit PWMs with Analog to suit a variety of applications. These devices deliver three 16-bit PWMs with independent timers for applications where high resolution is needed, such as LED lighting, stepper motors, power supplies and other general purpose applications. The core independent peripherals (16-bit PWMs, Complementary Waveform Generator), Enhanced Universal Synchronous Asynchronous Receiver Transceiver (EUSART) and Analog (ADCs, Comparator and DAC) enable closed-loop feedback and communication for use in multiple market segments. The EUSART peripheral enables the communication for applications such as LIN.

Core Features:

• C Compiler Optimized RISC Architecture

• Only 49 Instructions

• Operating Speed:

- DC – 32 MHz clock input

- 125 ns minimum instruction cycle

• Interrupt Capability

• 16-Level Deep Hardware Stack

• Two 8-Bit Timers

• One 16-Bit Timer

• Three Additional 16-Bit Timers available using the 16-Bit PWMs

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Low-Power Brown-out Reset (LPBOR)

• Programmable Watchdog Timer (WDT) up to 256s

• Programmable Code Protection

Memory:

• Up to 3.5 Kbytes Flash Program Memory

• Up to 256 Bytes Data SRAM Memory

• Direct, Indirect and Relative Addressing modes

• High-Endurance Flash Data Memory (HEF)

- 128 bytes if nonvolatile data storage

- 100k erase/write cycles

Operating Characteristics:

• Operating Voltage Range:

- 1.8V to 3.6V (PIC12LF1571/2)

- 2.3V to 5.5V (PIC12F1571/2)

• Temperature Range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

• Internal Voltage Reference module

• In-Circuit Serial Programming™ (ICSP™) via Two Pins

eXtreme Low-Power (XLP) Features:

• Sleep mode: 20 nA @ 1.8V, Typical

• Watchdog Timer: 260 nA @ 1.8V, Typical

• Operating Current:

-30 A/MHz @ 1.8V, typical

Digital Peripherals:

• 16-Bit PWM:

- Three 16-bit PWMs with independent timers

- Multiple Output modes (Edge-Aligned, Center-Aligned, Set and Toggle on Register Match)

- User settings for phase, duty cycle, period, offset and polarity

- 16-bit timer capability

- Interrupts generated based on timer matches with Offset, Duty Cycle, Period and Phase registers

• Complementary Waveform Generator (CWG):

- Rising and falling edge dead-band control

- Multiple signal sources

• Enhanced Universal Synchronous Asynchronous Receiver Transceiver (EUSART):

- Supports LIN applications

Device I/O Port Features:

• Six I/Os

• Individually Selectable Weak Pull-ups

• Interrupt-On-Change Pins Option with Edge-Selectable Option

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PIC12(L)F1571/2

Analog Peripherals:

• 10-Bit Analog-to-Digital Converter (ADC):

- Up to four external channels

- Conversion available during Sleep

• Comparator:

- Low-Power/High-Speed modes

- Fixed Voltage Reference at (non)inverting input(s)

- Comparator outputs externally accessible

- Synchronization with Timer1 clock source

- Software hysteresis enable

• 5-Bit Digital-to-Analog Converter (DAC):

- 5-bit resolution, rail-to-rail

- Positive reference selection

- Unbuffered I/O pin output

- Internal connections to ADCs and comparators

• Voltage Reference:

- Fixed voltage reference with 1.024V, 2.048V and 4.096V output levels

PIC12(L)F1571/2 FAMILY TYPES

Clocking Structure:

• Precision Internal Oscillator:

- Factory calibrated ±1%, typical

- Software-selectable clock speeds from 31 kHz to 32 MHz

• External Oscillator Block with:

- Resonator modes up to 20 MHz

- Two External Clock modes up to 32 MHz

• Fail-Safe Clock Monitor

• Digital Oscillator Input Available

Device

(K words)

Data Sheet Index

Program Memory Flash

PIC12(L)F1571 A 1 128 128 6 2/4 PIC12(L)F1572 A 2 256 128 6 2/4

Note 1: I – Debugging integrated on chip.

2: Three additional 16-bit timers available when not using the 16-bit PWM outputs.

Data Sheet Index: (Unshaded devices are described in this document.)

A DS40001723 PIC12(L)F1571/2 Data Sheet, 8-Pin Flash, 8-Bit MCU with High-Precision 16-Bit PWM.

High-Endurance

Data SRAM (bytes)

I/O Pins

Flash (bytes)

8-Bit/16-Bit Timers

(2)

134110 I Y

(2)

1 3 4 1 1 1 I Y

16-Bit PWM

Comparators

10-Bit ADC (ch)

CWG

5-Bit DAC

(1)

Debug

EUSART

XLP

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PIN DIAGRAMS

Note: See Ta bl e 1 for location of all peripheral functions.

VDD

RA5

RA3/MCLR

/VPP

VSS

RA0/ICSPDAT

RA1/ICSPCLK

RA2

RA4

PIC12(L)F1571

PIC12(L)F1572

Pin Diagram – 8-Pin PDIP, SOIC, DFN, MSOP, UDFN

PIC12(L)F1571/2

TABLE 1: 8-PIN ALLOCATION TABLE (PIC12(L)F1571/2)

(2)

I/O

RA0 7 AN0 DAC1OUT C1IN+ — PWM2 TX

RA1 6 AN1 VREF+ C1IN0- — PWM1 RX

RA2 5 AN2 — C1OUT T0CKI PWM3 — CWG1FLT

RA3 4 — — — T1G

RA4 3 AN3 — C1IN1- T1G PWM2

RA5 2 — — — T1CKI PWM1

VDD 1 — — — — — — — — — VDD

Vss 8 — — — — — — — — — VSS

Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

2: PIC12(L)F1572 only.

ADC

8-Pin PDIP/SOIC/MSOP/DFN/UDFN

Reference

Comparator

Timers

(1)

PWM

— — — IOC Y MCLR

(1)

TX CK

RX DT

(2) (2)

(1,2) (1,2)

EUSART

CWG

CWG1B IOC Y ICSPDAT

— IOC Y ICSPCLK

IOC

CWG1A

CWG1B

CWG1A

INT

(1)

IOC Y CLKOUT

(1)

IOC Y CLKIN

Interrupt

Pull-up

Y —

Basic

ICDDAT

ICDCLK

VPP

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1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13

3.0 Memory Organization ................................................................................................................................................................. 15

4.0 Device Configuration.................................................................................................................................................................. 41

5.0 Oscillator Module........................................................................................................................................................................ 47

6.0 Resets ........................................................................................................................................................................................ 59

7.0 Interrupts .................................................................................................................................................................................... 69

8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 83

9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 87

10.0 Flash Program Memory Control ................................................................................................................................................. 91

11.0 I/O Ports ................................................................................................................................................................................... 109

12.0 Interrupt-On-Change ................................................................................................................................................................ 119

13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 123

14.0 Temperature Indicator Module ................................................................................................................................................. 127

15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 129

16.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 143

17.0 Comparator Module.................................................................................................................................................................. 147

18.0 Timer0 Module ......................................................................................................................................................................... 155

19.0 Timer1 Module with Gate Control............................................................................................................................................. 159

20.0 Timer2 Module ......................................................................................................................................................................... 171

21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 175

22.0 16-Bit Pulse-Width Modulation (PWM) Module ........................................................................................................................ 203

23.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 231

24.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 243

25.0 Instruction Set Summary .......................................................................................................................................................... 245

26.0 Electrical Specifications............................................................................................................................................................ 259

27.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 283

28.0 Development Support............................................................................................................................................................... 305

29.0 Packaging Information.............................................................................................................................................................. 309

Appendix A: Data Sheet Revision History .......................................................................................................................................... 327

The Microchip Web Site..................................................................................................................................................................... 329

Customer Change Notification Service .............................................................................................................................................. 329

Customer Support .............................................................................................................................................................................. 329

Product Identification System............................................................................................................................................................. 331

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PIC12(L)F1571/2

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Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

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PIC12(L)F1571/2

NOTES:

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PIC12(L)F1571/2

1.0 DEVICE OVERVIEW

The PIC12(L)F1571/2 devices are described within this data sheet. The block diagram of these devices is shown in Figure 1-1, the available peripherals are shown in

Table 1-1 and the pinout descriptions are shown in Table 1-2.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC12(L)F1571

PIC12(L)F1572

Analog-to-Digital Converter (ADC) ●● Complementary Wave Generator

(CWG) Digital-to-Analog Converter (DAC) ●● Enhanced Universal

Synchronous/Asynchronous Receiver/Transmitter (EUSART)

Fixed Voltage Reference (FVR) ●● Temperature Indicator ●● Comparators

PWM Modules

PWM1 ●● PWM2 ●● PWM3 ●●

Timers

Timer0 ●● Timer1 ●● Timer2 ●●

●●

●

C1 ● ●

1.1 Register and Bit Naming

Conventions

1.1.1 REGISTER NAMES

When there are multiple instances of the same peripheral in a device, the peripheral control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance and control identifier. The control registers section will show just one instance of all the register names with an ‘x’ in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one.

1.1.2 BIT NAMES

There are two variants for bit names:

• Short name: Bit function abbreviation

• Long name: Peripheral abbreviation + short name

1.1.2.1 Short Bit Names

Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant.

Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the

short name is RegisterNamebits.ShortName. For

example, the enable bit, EN, in the COG1CON0 register can be set in C programs with the instruction, COG1CON0bits.EN = 1.

Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit name are appended with an underscore, plus the name of the register in which the bit resides, to avoid naming contentions.

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PIC12(L)F1571/2

1.1.2.2 Long Bit Names

Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral, thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN.

Long bit names are useful in both C and assembly programs. For example, in C, the COG1CON0 enable bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF COG1CON0,G1EN instruction.

1.1.2.3 Bit Fields

Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the COG1CON0 register contain the mode control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the COG1 to the Push-Pull mode:

COG1CON0bits.MD = 0x5;

Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name, MD2, and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for setting the COG1 to Push-Pull mode:

Example 1:

MOVLW ~(1<<G1MD1) ANDWF COG1CON0,F MOVLW 1<<G1MD2 | 1<<G1MD0 IORWF COG1CON0,F

Example 2:

BSF COG1CON0,G1MD2 BCF COG1CON0,G1MD1 BSF COG1CON0,G1MD0

1.1.3 REGISTER AND BIT NAMING EXCEPTIONS

1.1.3.1 Status, Interrupt and Mirror Bits

Status, interrupt enables, interrupt flags and mirror bits are contained in registers that span more than one peripheral. In these cases, the bit name shown is unique so there is no prefix or short name variant.

1.1.3.2 Legacy Peripherals

There are some peripherals that do not strictly adhere to these naming conventions. Peripherals that have existed for many years and are present in almost every device are the exceptions. These exceptions were necessary to limit the adverse impact of the new conventions on legacy code. Peripherals that do adhere to the new convention will include a table in the registers section indicating the long name prefix for each peripheral instance. Peripherals that fall into the exception category will not have this table. These peripherals include, but are not limited to, the following:

• EUSART

• MSSP

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FIGURE 1-1: PIC12(L)F1571/2 BLOCK DIAGRAM

Note 1: See applicable chapters for more information on peripherals.

2: See Table 1-1 for peripherals available on specific devices. 3: See Figure 2-1. 4: PIC12(L)F1572 only.

CLKOUT

CLKIN

RAM

CPU

(Note 3)

Timing

Generation

INTRC

Oscillator

MCLR

Program

Flash Memory

FVR

ADC

10-bit

Temp

Indicator

TMR0TMR1TMR2

PWM1PWM2PWM3CWG1

PORTA

Rev. 10-000039E

9/12/2013

DACC1

EUSART

(4)

PIC12(L)F1571/2

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TABLE 1-2: PIC12(L)F1571/2 PINOUT DESCRIPTION

Input

Name Function

RA0/AN0/C1IN+/DACOUT/

(2)

/CK

/CWG1B/PWM2/

ICSPDAT/ICDDAT

RA0

AN0 ADC channel input.

C1IN+ Comparator positive input.

Typ e

Output

Typ e

General purpose I/O.

DACOUT Digital-to-Analog Converter output.

TX USART asynchronous transmit.

(3) (4)

CK USART synchronous clock.

CWG1B CWG complementary output.

PWM2 PWM output.

ICSPDAT ICSP™ data I/O.

ICDDAT In-circuit debug data.

RA1/AN1/V DT

REF+/C1IN0-/RX

(2)

/PWM1/ICSPCLK/ICDCLK

(2)

RA1

General purpose I/O.

AN1 ADC channel input.

REF+ ADC Voltage Reference input.

C1IN0- Comparator negative input.

RX USART asynchronous input.

(3) (4)

DT USART synchronous data.

PWM1 PWM output.

ICSPCLK ICSP programming clock.

ICDCLK In-circuit debug clock.

RA2/AN2/C1OUT/T0CKI/ CWG1FLT

/CWG1A/PWM3/INT

RA2

AN2 ADC channel input.

General purpose I/O.

C1OUT Comparator output.

T0CKI Timer0 clock input.

(3) (4)

CWG1FLT Complementary Waveform Generator Fault input.

CWG1A CWG complementary output.

PWM3 PWM output.

INT External interrupt.

RA3/V

PP/T1G

/MCLR RA3

PP Programming voltage.

General purpose input with IOC and WPU.

(3) (4)

(1)

T1G Timer1 gate input.

Master Clear with internal pull-up.

General purpose I/O.

RA4/AN3/C1IN1-/T1G/TX CK

(1,2)

/CWG1B

(1)

/PWM2

CLKOUT

(1,2)

(1)

MCLR

RA4

AN3 ADC channel input.

C1IN1- Comparator negative input.

T1G Timer1 gate input.

TX USART asynchronous transmit.

(3) (4)

CK USART synchronous clock.

CWG1B CWG complementary output.

PWM2 PWM output.

CLKOUT F

OSC/4 output.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

2: PIC12(L)F1572 only. 3: Input type is selected by the port. 4: Output type is selected by the port.

Description

C = Schmitt Trigger input with I2C

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PIC12(L)F1571/2

TABLE 1-2: PIC12(L)F1571/2 PINOUT DESCRIPTION (CONTINUED)

Input

Name Function

(1,2)

RA5/T1CKI/RX

(1)

CWG1A

DD VDD Power — Positive supply.

SS VSS Power — Ground reference.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

/PWM1

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I HV = High Voltage XTAL = Crystal levels

2: PIC12(L)F1572 only. 3: Input type is selected by the port. 4: Output type is selected by the port.

/DT

(1)

/CLKIN

(1,2)

RA5

T1CKI Timer1 clock input.

RX USART asynchronous input.

DT USART synchronous data.

CWG1A CWG complementary output.

PWM1 PWM output.

CLKIN External Clock input (EC mode).

Typ e

(3) (4)

Output

Typ e

General purpose I/O.

Description

C = Schmitt Trigger input with I2C

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NOTES:

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PIC12(L)F1571/2

Program Counter

MUX

Addr MUX

16-Level Stack

(15-bit)

Program Memory

Read (PMR)

Instruction Reg

Configuration

FSR0 Reg

FSR1 Reg

BSR Reg

STATUS Reg

RAM

WReg

Power-up

Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Instruction

Decode and

Control

Timing

Generation

Internal

Oscillator

Block

ALU

Flash

Program

Memory

MUX

Data Bus

Program

Bus

Direct Addr

Indirect

Addr

RAM Addr

CLKIN

CLKOUT

DD VSS

Rev. 10-000055A

7/30/2013

2.0 ENHANCED MID-RANGE CPU

This family of devices contains an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.

FIGURE 2-1: CORE BLOCK DIAGRAM

• Automatic Interrupt Context Saving

• 16-Level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

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PIC12(L)F1571/2

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving”, for more information.

2.2 16-Level Stack with Overflow and Underflow

These devices have a hardware stack memory, 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled, will cause a Software Reset. See Section 3.5 “Stack” for more details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See

Section 3.6 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced midrange CPU to support the features of the CPU. See

Section 25.0 “Instruction Set Summary” for more

details.

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PIC12(L)F1571/2

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory:

- Configuration Words

- Device ID

-User ID

- Flash Program Memory

• Data Memory:

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

The following features are associated with access and control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit Program Counter (PC) capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented. Accessing a location above these boundaries will cause a wraparound within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 3-1).

3.2 High-Endurance Flash

This device has a 128-byte section of high-endurance Program Flash Memory (PFM) in lieu of data EEPROM. This area is especially well-suited for nonvolatile data storage that is expected to be updated frequently over the life of the end product. See

Section 10.2 “Flash Program Memory Overview”

for more information on writing data to PFM. See

Section 3.2.1.2 “Indirect Read with FSR” for more

information about using the FSR registers to read byte data stored in PFM.

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device

PIC12(L)F1571 1,024 03FFh 0380h-03FFh PIC12(L)F1572 2,048 07FFh 0780h-07FFh

Note 1: High-endurance Flash applies to the low byte of each address in the range.

Program Memory

Space (Words)

Last Program Memory

Address

High-Endurance Flash

Memory Address Range

(1)

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PIC12(L)F1571/2

Stack Level 0

Stack Level 15

Stack Level 1

Reset Vector

PC<14:0>

Interrupt Vector

Page 0

Rollover to Page 0

0000h

0004h 0005h

03FFh

0400h

7FFFh

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

On-chip

Program

Memory

Rev. 10-000040D

7/30/2013

Stack Level 0

Stack Level 15

Stack Level 1

Reset Vector

PC<14:0>

Interrupt Vector

Page 0

Rollover to Page 0

0000h

0004h 0005h

07FFh 0800h

7FFFh

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

On-chip Program Memory

Rev. 10-000040C

7/30/2013

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR PIC12(L)F1571

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR PIC12(L)F1572

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PIC12(L)F1571/2

constants

BRW ;Add Index in W to

;program counter to

;select data RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3

my_function

;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W

constants

DW DATA0 ;First constant DW DATA1 ;Second constant DW DATA2 DW DATA3

my_function

;… LOTS OF CODE… MOVLW DATA_INDEX ADDLW LOW constants MOVWF FSR1L MOVLW

HIGH constants

;MSb is set

automatically MOVWF FSR1H BTFSC STATUS,C ;carry from ADDLW? INCF FSR1H,f ;yes MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

3.2.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory.

3.2.1.1 RETLW Instruction

The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

3.2.1.2 Indirect Read with FSR

The program memory can be accessed as data by setting bit 7 of the FSRnH register and reading the matching INDFn register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDFn registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.

The HIGH operator will set bit<7> if a label points to a location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available, so the older table read method must be used.

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PIC12(L)F1571/2

Addresses BANKx

x00h or x80h INDF0 x01h or x81h INDF1 x02h or x82h PCL x03h or x83h STATUS x04h or x84h FSR0L x05h or x85h FSR0H x06h or x86h FSR1L x07h or x87h FSR1H x08h or x88h BSR

x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON

3.3 Data Memory Organization

The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3):

• 12 Core Registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of Common RAM

The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.6 “Indirect Addressing” for more information.

Data memory uses a 12-bit address. The upper five bits of the address define the bank address and the lower seven bits select the registers/RAM in that bank.

3.3.1 CORE REGISTERS

The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses: x00h/x08h through x0Bh/x8Bh). These registers are listed below in Ta b le 3 - 2 . For detailed information, see Tab le 3 -9 .

TABLE 3-2: CORE REGISTERS

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PIC12(L)F1571/2

3.3.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• The arithmetic status of the ALU

• The Reset status

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

and PD bits are not

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, refer to Section 25.0 “Instruction Set

Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in subtraction.

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — —TOPD ZDC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

(1)

bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow

bit 0 C: Carry/Borrow

Note 1: For Borrow

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

: Power-Down bit

1 = After power-down or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result

(1)

bit

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

(1)

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PIC12(L)F1571/2

Memory Region7-bit Bank Offset

00h

0Bh

0Ch

1Fh

20h

6Fh

7Fh

70h

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

General Purpose RAM

(80 bytes maximum)

Common RAM

(16 bytes)

Rev. 10-000041A

7/30/2013

3.3.2 SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses: x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet.

3.3.3 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses: x0Ch/x8Ch through x1Fh/x9Fh).

3.3.3.1 Linear Access to GPR

The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See

Section 3.6.2 “Linear Data Memory” for more

information.

3.3.4 COMMON RAM

There are 16 bytes of common RAM accessible from all banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

3.3.5 DEVICE MEMORY MAPS

The memory maps for PIC12(L)F1571/2 are as shown in Table 3-3 through Tab l e 3 - 8 .

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TABLE 3-3: PIC12(L)F1571 MEMORY MAP, BANK 0-7

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3 -2 )

00Bh

00Ch

00Dh

00Eh

00Fh

010h

011h 012h

013h

014h

015h

016h

017h 018h

019h

01Ah

01Bh

01Ch

01Dh 01Eh

01Fh

020h

06Fh

070h

07Fh

Legend: = Unimplemented data memory locations, read as ‘0’. Note 1: PIC12F1571 only.

PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA

—08Dh—10Dh—18Dh—20Dh—28Dh—30Dh—38Dh—

—08Eh—10Eh—18Eh—20Eh—28Eh—30Eh—38Eh—

—08Fh—10Fh—18Fh— 20Fh — 28Fh — 30Fh — 38Fh —

—090h—110h—190h— 210h — 290h — 310h — 390h —

PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h

PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h PIR3 093h PIE3 113h

—094h—114h— 194h PMDATH 214h — 294h — 314h — 394h —

TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h

TMR1L 096h PCON 116h BORCON 196h PMCON2 216h

TMR1H 097h WDTCON 117h FVRCON 197h VREGCON

T1CON 098h OSCTUN E 118h DACxCON0 198h

T1GCON 099h OSCCON 119h DACxCON1 199h

TMR2 09Ah OSCSTAT 11Ah

PR2 09Bh ADRESL 11Bh

T2CON 09Ch ADRESH 11Ch

— 09Dh ADCON0 11Dh APFCON 19Dh —21Dh—29Dh—31Dh—39Dh—

— 09Eh ADCON1 11Eh —19Eh—21Eh—29Eh—31Eh—39Eh— — 09Fh ADCON2 11Fh —19Fh— 21Fh — 29Fh — 31Fh — 39Fh —

General Purpose Register 80 Bytes

Common RAM

080h

Core Registers

(Ta bl e 3 -2 )

08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh

0A0h

General Purpose

0EFh

0F0h

0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

48 Bytes

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h-7Fh)

100h

Core Registers

(Ta bl e 3 -2 )

— 193h PMDATL 213h — 293h — 313h — 393h IOCAF

—19Ah—21Ah—29Ah—31Ah—39Ah—

—19Bh—21Bh—29Bh—31Bh—39Bh—

—19Ch—21Ch—29Ch—31Ch—39Ch—

120h

Unimplemented

Read as ‘0’

16Fh 1EFh 26Fh 2EFh 170h

Common RAM

(Accesses

70h-7Fh)

180h

1A0h

1F0h

200h

Core Registers

(Ta bl e 3 -2 )

(1)

— 218h — 298h — 318h — 398h — — 219h — 299h — 319h — 399h —

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h-7Fh)

Core Registers

(Ta bl e 3 -2 )

— 291h — 311h — 391h IOCAP

— 292h — 312h — 392h IOCAN

— 295h — 315h — 395h —

— 296h — 316h — 396h —

217h — 297h — 317h — 397h —

220h

Unimplemented

Read as ‘0’

270h

Common RAM

(Accesses

70h-7Fh)

280h

2A0h

2F0h

Core Registers

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h-7Fh)

300h

Core Registers

(Ta bl e 3 -2 )

320h

Unimplemented

Read as ‘0’

36Fh 3EFh

370h

Common RAM

(Accesses

70h-7Fh)

380h

3A0h

3F0h

Core Registers

(Ta bl e 3 -2 )

PIC12(L)F1571/2

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h-7Fh)

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TABLE 3-4: PIC12(L)F1572 MEMORY MAP, BANK 0-7

PIC12(L)F1571/2

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Ta bl e 3 -2 )

00Bh

00Ch

00Dh

00Eh

00Fh

010h

011h 012h

013h

014h

015h

016h

017h 018h

019h

01Ah

01Bh

01Ch

01Dh 01Eh

01Fh

020h

06Fh

070h

07Fh

Legend: = Unimplemented data memory locations, read as ‘0’. Note 1: PIC12F1572 only.

PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA

—08Dh—10Dh—18Dh—20Dh—28Dh—30Dh—38Dh—

—08Eh—10Eh—18Eh—20Eh—28Eh—30Eh—38Eh—

—08Fh—10Fh—18Fh— 20Fh — 28Fh — 30Fh — 38Fh —

—090h—110h—190h— 210h — 290h — 310h — 390h —

PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h

PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h PIR3 093h PIE3 113h

—094h—114h— 194h PMDATH 214h — 294h — 314h — 394h —

TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h

TMR1L 096h PCON 116h BORCON 196h PMCON2 216h

TMR1H 097h WDTCON 117h FVRCON 197h VREGCON

T1CON 098h OSCTUNE 118h DAC1CON0 198h

T1GCON 099h OSCCON 119h DAC1CON1 199h RCREG 219h

TMR2 09Ah OSCSTAT 11Ah

PR2 09Bh ADRESL 11Bh

T2CON 09Ch ADRESH 11Ch

— 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh —29Dh—31Dh—39Dh—

— 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh —29Eh—31Eh—39Eh— — 09Fh ADCON2 11Fh — 19Fh BAUDCON 21Fh — 29Fh — 31Fh — 39Fh —

General Purpose Register 80 Bytes

Common RAM

080h

Core Registers

(Ta bl e 3 -2 )

08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh

0A0h

General Purpose Register

80 Bytes

0EFh 0F0h

Accesses

70h-7Fh

0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

100h

Core Registers

(Ta bl e 3 -2 )

— 193h PMDATL 213h — 293h — 313h — 393h IOCAF

— 19Ah TXREG 21Ah —29Ah—31Ah—39Ah—

— 19Bh SPBRG 21Bh —29Bh—31Bh—39Bh—

— 19Ch SPBRGH 21Ch —29Ch—31Ch—39Ch—

120h

General Purpose Register

80 Bytes

16Fh 1EFh 26Fh 2EFh 170h

Accesses

70h-7Fh

180h

1A0h

1F0h

200h

Core Registers

(Ta bl e 3 -2 )

(1)

— 218h — 298h — 318h — 398h —

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

Core Registers

(Ta bl e 3 -2 )

— 291h — 311h — 391h IOCAP

— 292h — 312h — 392h IOCAN

— 295h — 315h — 395h —

— 296h — 316h — 396h —

217h — 297h — 317h — 397h —

— 299h — 319h — 399h —

220h

Unimplemented

Read as ‘0’

270h

Accesses

70h-7Fh

280h

2A0h

2F0h

Core Registers

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

300h

Core Registers

(Ta bl e 3 -2 )

320h

Unimplemented

Read as ‘0’

36Fh 3EFh

370h

Accesses

70h-7Fh

380h

3A0h

3F0h

Core Registers

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

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TABLE 3-5: PIC12(L)F1571/2 MEMORY MAP, BANK 8-23

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h

Core Registers

40Bh 40Ch 40Dh

40Eh

40Fh

410h

411h

412h

413h

414h

415h

416h

417h

418h —498h—518h—598h— 618h — 698h — 718h — 798h —

419h

41Ah

41Bh 41Ch 41Dh

41Eh

41Fh

420h

(Ta bl e 3 -2 )

—48Ch—50Ch—58Ch—60Ch—68Ch—70Ch—78Ch— —48Dh—50Dh—58Dh—60Dh—68Dh—70Dh—78Dh— —48Eh—50Eh—58Eh—60Eh—68Eh—70Eh—78Eh— —48Fh—50Fh—58Fh— 60Fh — 68Fh — 70Fh — 78Fh — —490h—510h—590h— 610h — 690h — 710h — 790h — —491h—511h—591h—611h— 691h CWG1DBR 711h — 791h — —492h—512h—592h— 612h — 692h CWG1DBF 712h — 792h — —493h—513h—593h— 613h — 693h CWG1CON0 713h — 793h — —494h—514h—594h— 614h — 694h CWG1CON1 714h — 794h — —495h—515h—595h— 615h — 695h CWG1CON2 715h — 795h — —496h—516h—596h— 616h — 696h — 716h — 796h — —497h—517h—597h— 617h — 697h — 717h — 797h —

—499h—519h—599h— 619h — 699h — 719h — 799h — —49Ah—51Ah—59Ah—61Ah—69Ah—71Ah—79Ah— —49Bh—51Bh—59Bh—61Bh—69Bh—71Bh—79Bh— —49Ch—51Ch—59Ch—61Ch—69Ch—71Ch—79Ch— —49Dh—51Dh—59Dh—61Dh—69Dh—71Dh—79Dh— —49Eh—51Eh—59Eh—61Eh—69Eh—71Eh—79Eh— —49Fh—51Fh—59Fh— 61Fh — 69Fh — 71Fh — 79Fh —

480h

48Bh

4A0h

Core Registers

(Ta bl e 3 -2 )

500h

50Bh

520h

Core Registers

(Ta bl e 3 -2 )

580h

58Bh

5A0h

Core Registers

(Ta bl e 3 -2 )

600h

60Bh

620h

Core Registers

(Ta bl e 3 -2 )

680h

68Bh

6A0h

Core Registers

(Ta bl e 3 -2 )

700h

70Bh

720h

Core Registers

(Ta bl e 3 -2 )

780h

78Bh

7A0h

Core Registers

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh

470h

Accesses

70h-7Fh

47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

4F0h

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

570h

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

5F0h

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

670h

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

6F0h

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

770h

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

7F0h

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h

Core Registers

80Bh 80Ch

86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh

870h

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

Legend: = Unimplemented data memory locations, read as ‘0’.

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

880h

88Bh 88Ch

8F0h

Core Registers

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

900h

90Bh 90Ch

970h

Core Registers

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

980h

98Bh

98Ch

9F0h

Core Registers

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

A00h

A0Bh

A0Ch

A70h

Core Registers

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

A80h

A8Bh A8Ch

AF0h

Core Registers

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

B00h

B0Bh B0Ch

B70h

Core Registers

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

B80h

B8Bh B8Ch

BF0h

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

Core Registers

(Ta bl e 3 -2 )

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

PIC12(L)F1571/2

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TABLE 3-6: PIC12(L)F1571/2 MEMORY MAP, BANK 24-31

PIC12(L)F1571/2

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31

C00h

Core Registers

C0Bh C0Ch C0Dh —C8Dh—D0Dh—E0Dh—E8Dh—F0Dh—

C0Eh

C0Fh

C10h

C11h

C12h

C13h

C14h

C15h

C16h

C17h

C18h

C19h

C1Ah

C1Bh C1Ch C1Dh

C1Eh

C1Fh

C20h

(Ta bl e 3 -2 )

—C8Ch—D0Ch—D8Ch

—C8Eh—D0Eh—E0Eh—E8Eh—F0Eh— —C8Fh—D0Fh—E0Fh—E8Fh—F0Fh— —C90h—D10h—E10h—E90h—F10h— —C91h—D11h—E11h—E91h—F11h— —C92h—D12h—E12h—E92h—F12h— —C93h—D13h—E13h—E93h—F13h— —C94h—D14h—E14h—E94h—F14h— —C95h—D15h—E15h—E95h—F15h— —C96h—D16h—E16h—E96h—F16h— —C97h—D17h—E17h—E97h—F17h— —C98h—D18h—E18h—E98h—F18h— —C99h—D19h—E19h—E99h—F19h— —C9Ah—D1Ah—E1Ah—E9Ah—F1Ah— —C9Bh—D1Bh—E1Bh—E9Bh—F1Bh— —C9Ch—D1Ch—E1Ch—E9Ch—F1Ch— —C9Dh—D1Dh—E1Dh—E9Dh—F1Dh— —C9Eh—D1Eh—E1Eh—E9Eh—F1Eh— —C9Fh—D1Fh—E1Fh—E9Fh—F1Fh—

C80h

C8Bh

CA0h

Core Registers

(Ta bl e 3 -2 )

D00h

D0Bh

D20h

Core Registers

(Ta bl e 3 -2 )

D80h

D8Bh

Core Registers

(Ta bl e 3 -2 )

See Tab l e 3- 7 for Register Mapping

Details

E00h

Core Registers

E0Bh E0Ch —E8Ch—F0Ch—F8Ch

E20h

(Ta bl e 3 -2 )

E80h

E8Bh

EA0h

Core Registers

(Ta bl e 3 -2 )

F00h

F0Bh

F20h

Core Registers

(Ta bl e 3 -2 )

F80h

F8Bh

Core Registers

(Ta bl e 3 -2 )

See Ta bl e 3 -7 for Register Mapping

Details

Unimplemented

Read as ‘0’

C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh

C70h

Accesses

70h-7Fh

CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

Legend: = Unimplemented data memory locations, read as ‘0’.

CF0h

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

D70h

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

DF0h

Accesses

70h-7Fh

E70h

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

EF0h

Unimplemented

Read as ‘0’

Accesses

70h-7Fh

F70h

Unimplemented

Read as ‘0’

FF0h

Accesses

70h-7Fh

Accesses

70h-7Fh

PIC12(L)F1571/2

Bank 31

D8Ch — D8Dh

— D8Eh PWMEN D8Fh PWMLD D90h PWMOUT D91h PWM1PHL D92h PWM1PHH D93h PWM1DCL D94h PWM1DCH D95h PWM1PRL D96h PWM1PRH D97h PWM1OFL D98h PWM1OFH D99h PWM1TMRL D9Ah PWM1TMRH D9Bh PWM1CON D9Ch PWM1INTE D9Dh PWM1INTF D9Eh PWM1CLKCON D9Fh PWM1LDCON DA0h PWM1OFCON DA1h PWM2PHL DA2h PWM2PHH DA3h PWM2DCL DA4h PWM2DCH DA5h PWM2PRL DA6h PWM2PRH DA7h PWM2OFL DA8h PWM2OFH DA9h PWM2TMRL DAAh PWM2TMRH DABh PWM2CON DACh PWM2INTE DADh PWM2INTF DAEh PWM2CLKCON DAFh PWM2LDCON DB0h PWM2OFCON DB1h PWM3PHL DB2h PWM3PHH DB3h PWM3DCL DB4h PWM3DCH DB5h PWM2PRL DB6h PWM3PRH DB7h PWM3OFL DB8h PWM3OFH DB9h PWM3TMRL DBAh PWM3TMRH DBBh PWM3CON DBCh PWM3INTE DBDh PWM3INTF DBEh PWM3CLKCON DBFh PWM3LDCON DC0h PWM3OFCON

DC1h

—

DEFh

Legend: = Unimplemented data memory locations,

read as ‘0’.

Bank 31

F8Ch

FE3h

Unimplemented

Read as ‘0’

FE4h STATUS_SHAD FE5h WREG_SHAD FE6h BSR_SHAD FE7h PCLATH_SHAD FE8h FSR0L_SHAD FE9h FSR0H_SHAD FEAh FSR1L_SHAD FEBh FSR1H_SHAD FECh

— FEDh STKPTR FEEh TOSL FEFh TOSH

Legend: = Unimplemented data memory locations,

read as ‘0’.

TABLE 3-7: PIC12(L)F1571/2 MEMORY

MAP, BANK 27

 2013-2015 Microchip Technology Inc. DS40001723D-page 25

TABLE 3-8: PIC12(L)F1571/2 MEMORY

MAP, BANK 31

PIC12(L)F1571/2

3.3.6 CORE FUNCTION REGISTERS SUMMARY

The Core Function registers listed in Ta bl e 3 -9 can be addressed from any bank.

TABLE 3-9: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0-31

x00h or

INDF0

x80h

x01h or

INDF1

x81h

x02h or

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x82h

x03h or

STATUS

x83h

x04h or

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x84h

x05h or

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x85h

x06h or

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x86h

x07h or

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x87h

x08h or

BSR

x88h

x09h or

WREG Working Register 0000 0000 uuuu uuuu

x89h

x0Ah or

PCLATH

x8Ah

x0Bh or

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

x8Bh Legend: x = unknown; u = unchanged; q = value depends on condition; — = unimplemented, read as ‘0’; r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register)

— — —TOPD ZDCC---1 1000 ---q quuu

— — —BSR<4:0>---0 0000 ---0 0000

— Write Buffer for the Upper 7 bits of the Program Counter -000 0000 -000 0000

Val ue o n

POR, BOR

xxxx xxxx uuuu uuuu

Value on All

Other Resets

DS40001723D-page 26  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00Ch PORTA — — RA<5:0>

00Dh — Unimplemented — —

00Eh

00Fh

010h

011h PIR1 TMR1GIF ADIF RCIF

012h PIR2 — —C1IF— — — — —

013h PIR3 — PWM3IF PWM2IF PWM1IF — — — —

014h — Unimplemented — —

015h TMR0 Holding Register for the 8-Bit Timer0 Count

016h TMR1L Holding Register for the Least Significant Byte of the 16-Bit TMR1 Count

017h TMR1H Holding Register for the Most Significant Byte of the 16-Bit TMR1 Count

018h T1CON TMR1CS<1:0> T1CKPS<1:0> —T1SYNC —TMR1ON

019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

01Ah TMR2 Timer2 Module Register

01Bh PR2 Timer2 Period Register

01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0>

01Dh — Unimplemented — —

01Eh

01Fh

Bank 1

08Ch TRISA — — TRISA<5:4> —

08Dh — Unimplemented — —

08Eh

08Fh

090h

091h PIE1 TMR1GIE ADIE RCIE

092h PIE2 — —C1IE — — — — —

093h PIE3 — PWM3IE PWM2IE PWM1IE — — — —

094h — Unimplemented — —

095h OPTION_REG WPUEN

096h PCON STKOVF STKUNF —RWDTRMCLR RI POR BOR

097h WDTCON — —WDTPS<4:0>SWDTEN

098h OSCTUNE — —TUN<5:0>

099h OSCCON SPLLEN IRCF<3:0> —SCS<1:0>

09Ah OSCSTAT — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS

09Bh ADRESL ADC Result Register Low

09Ch ADRESH ADC Result Register High

09Dh ADCON0 — CHS<4:0> GO/DONE ADON

09Eh ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0>

09Fh ADCON2 TRIGSEL<3:0> — — — —

Legend:x = unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1:

— Unimplemented — —

INTEDG TMR0CS TMR0SE PSA PS<2:0>

PIC12F1571/2 only.

PIC12(L)F1572 only.

Unimplemented, read as ‘1’.

(2)

TXIF

TXIE

(2)

— — TMR2IF TMR1IF

DONE

— — TMR2IE TMR1IE

T1GVAL T1GSS<1:0>

(2)

TRISA<2:0>

Val ue on

POR, BOR

--xx xxxx --xx xxxx

0000 --00 0000 --00

--0- ---- --0- ----

-000 ---- -000 ----

xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

0000 -0-0 uuuu -u-u 0000 0x00 uuuu uxuu

0000 0000 0000 0000 1111 1111 1111 1111

-000 0000 -000 0000

--11 1111 --11 1111

0000 --00 0000 --00

--0- ---- --0- ----

-000 ---- -000 ----

1111 1111 1111 1111 00-1 11qq qq-q qquu

--01 0110 --01 0110

--00 0000 --00 0000 0011 1-00 0011 1-00

-0q0 0q00 -qqq qqqq xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

-000 0000 -000 0000 0000 --00 0000 --00 0000 ---- 0000 ----

Val ue on All Other

Resets

 2013-2015 Microchip Technology Inc. DS40001723D-page 27

PIC12(L)F1571/2

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 2

10Ch LATA — — LATA<5:4> — LATA<2:0>

10Dh — Unimplemented — —

10Eh

10Fh

110h

111h CM1CON0 C1ON C1OUT C1OE C1POL

112h CM1CON1 C1INTP C1INTN C1PCH<1:0> —C1NCH<2:0>

113h — Unimplemented — —

114h

115h CMOUT

116h BORCON SBOREN BORFS — — — — — BORRDY

117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0>

118h DAC1CON0 DACEN —DACOE — DACPSS<1:0> — —

119h DAC1CON1 — — — DACR<4:0>

11A h

11C h

11Dh APFCON RXDTSEL CWGASEL CWGBSEL

11Eh — Unimplemented — —

11F h

Bank 3

18Ch ANSELA — — —ANSA4— ANSA<2:0>

18Dh — Unimplemented — —

18Eh

18Fh

190h

191h PMADRL Flash Program Memory Address Register Low Byte

192h PMADRH —

193h PMDATL Flash Program Memory Read Data Register Low Byte

194h PMDATH — — Flash Program Memory Read Data Register High Byte

195h PMCON1 —

196h PMCON2 Flash Program Memory Control Register 2

197h VREGCON

198h — Unimplemented — —

199h RCREG USART Receive Data Register

19Ah TXREG USART Transmit Data Register

19Bh SPBRGL Baud Rate Generator Data Register Low

19Ch SPBRGH Baud Rate Generator Data Register High

19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN

Legend: Note 1:

— Unimplemented — —

— C1SP C1HYS C1SYNC

— Unimplemented — —

— — — — — — —MC1OUT

— Unimplemented — —

— T1GSEL TXCKSEL P2SEL P1SEL

— Unimplemented — —

(3)

Flash Program Memory Address Register High Byte

(3)

CFGS LWLO FREE WRERR WREN WR RD

(1)

— — — — — —VREGPMReserved

= unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’.

PIC12F1571/2 only.

PIC12(L)F1572 only.

Unimplemented, read as ‘1’.

Val ue on

POR, BOR

--xx -xxx --uu -uuu

0000 -100 0000 -100 0000 -000 0000 -000

---- ---0 ---- ---0 10-- ---q uu-- ---u 0q00 0000 0q00 0000 0-0- 00-- 0-0- 00--

---0 0000 ---0 0000

000- 0000 000- 0000

---1 -111 ---1 -111

0000 0000 0000 0000 1000 0000 1000 0000 xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu 1000 x000 1000 q000 0000 0000 0000 0000

---- --01 ---- --01

0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 000x 0000 0010 0000 0010 01-0 0-00 01-0 0-00

Val ue on All Other

Resets

DS40001723D-page 28  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 4

20Ch WPUA — — WPUA<5:0>

20Dh — Unimplemented — —

20Eh

21Fh

Bank 5

28Ch ODCONA — —ODA<5:4> —ODA<2:0>

28Dh

29Fh

Bank 6

30Ch SLRCONA — — SLRA<5:4> — SLRA<2:0>

30Dh

31Fh

Bank 7

38Ch INLVLA — — INLVLA<5:0>

38Dh

390h

391h IOCAP

392h IOCAN — —IOCAN<5:0>

393h IOCAF — —IOCAF<5:0>

394h

39Fh

Bank 8

40Ch

41Fh

Bank 9

48Ch

49Fh

Legend: Note 1:

— Unimplemented — —

— —IOCAP<5:0>

— Unimplemented — —

= unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’.

PIC12F1571/2 only.

PIC12(L)F1572 only.

Unimplemented, read as ‘1’.

Val ue on

POR, BOR

--11 1111 --11 1111

--11 -111 --11 -111

--11 1111 --11 1111

--00 0000 --00 0000

Val ue on All Other

Resets

 2013-2015 Microchip Technology Inc. DS40001723D-page 29

PIC12(L)F1571/2

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 10

50Ch

51Fh

Bank 11

58Ch

59Fh

Bank 12

60Ch

61Fh

Bank 13

68Ch

690h

691h CWG1DBR

692h CWG1DBF — —CWG1DBF<5:0>

693h CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA — —G1CS0

694h CWG1CON1 G1ASDLB<1:0> G1ASDLA<1:0> — G1IS<2:0>

695h CWG1CON2 G1ASE G1ARSEN — — — G1ASDSC1 G1ASDSFLT —

696h

69Fh

Banks 14-26

x0Ch/ x8Ch — x1Fh/ x9Fh

Legend: Note 1:

— Unimplemented — —

— —CWG1DBR<5:0>

— Unimplemented — —

= unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’.

PIC12F1571/2 only.

PIC12(L)F1572 only.

Unimplemented, read as ‘1’.

Val ue on

POR, BOR

--00 0000 --00 0000

--xx xxxx --xx xxxx 0000 0--0 0000 0--0 0000 -000 0000 -000 00-- -00- 00-- -00-

Val ue on All Other

Resets

DS40001723D-page 30  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 27

D8Ch — Unimplemented — —

D8Dh

D8Eh PWMEN

D8Fh PWMLD — — — — — PWM3LDA_A PWM2LDA_A PWM1LDA_A

D90h PWMOUT — — — — — PWM3OUT_A PWM2OUT_A PWM1OUT_A

D91h PWM1PHL PH<7:0>

D92h PWM1PHH PH<15:8>

D93h PWM1DCL DC<7:0>

D94h PWM1DCH DC<15:8>

D95h PWM1PRL PR<7:0>

D96h PWM1PRH PR<15:8>

D97h PWM1OFL OF<7:0>

D98h PWM1OFH OF<15:8>

D99h PWM1TMRL TMR<7:0>

D9Ah PWM1TMRH TMR<15:8>

D9Bh PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL PWM1MODE<1:0> — —

D9Ch PWM1INTE — — — — PWM1OFIE PWM1PHIE PWM1DCIE PWM1PRIE

D9Dh PWM1INTF — — — — PWM1OFIF PWM1PHIF PWM1DCIF PWM1PRIF

D9Eh PWM1CLKCON — PWM1PS<2:0> — — PWM1CS<1:0>

D9Fh PWM1LDCON PWM1LDA PWM1LDT — — — —PWM1LDS<1:0>

DA0h PWM1OFCON — PWM1OFM<1:0> PWM1OFO — —PWM1OFS<1:0>

DA1h PWM2PHL PH<7:0>

DA2h PWM2PHH PH<15:8>

DA3h PWM2DCL DC<7:0>

DA4h PWM2DCH DC<15:8>

DA5h PWM2PRL PR<7:0>

DA6h PWM2PRH PR<15:8>

DA7h PWM2OFL OF<7:0>

DA8h PWM2OFH OF<15:8>

DA9h PWM2TMRL TMR<7:0>

DAAh PWM2TMRH TMR<15:8>

DABh PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL PWM2MODE<1:0> — —

DACh PWM2INTE — — — — PWM2OFIE PWM2PHIE PWM2DCIE PWM2PRIE

DADh PWM2INTF — — — — PWM2OFIF PWM2PHIF PWM2DCIF PWM2PRIF

DAEh PWM2CLKCON — PWM2PS<2:0> — — PWM2CS<1:0>

DAFh PWM2LDCON PWM2LDA PWM2LDT — — — —PWM2LDS<1:0>

Legend: Note 1:

— Unimplemented — —

— — — — — PWM3EN_A PWM2EN_A PWM1EN_A

= unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’.

PIC12F1571/2 only.

PIC12(L)F1572 only.

Unimplemented, read as ‘1’.

Val ue on

POR, BOR

---- -000 ---- -000

---- -000 ---- -000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 00-- 0000 00--

---- 000 ---- 000

-000 -000 -000 --00 00-- -000 00-- --00

-000 -000 -000 --00 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 00-- 0000 00--

---- 000 ---- 000

-000 -000 -000 --00 00-- -000 00-- --00

Val ue on All Other

Resets

 2013-2015 Microchip Technology Inc. DS40001723D-page 31

PIC12(L)F1571/2

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 27 (Continued)

DB0h PWM2OFCON — PWM2OFM<1:0> PWM2OFO — —PWM2OFS<1:0>

DB1h PWM3PHL PH<7:0>

DB2h PWM3PHH PH<15:8>

DB3h PWM3DCL DC<7:0>

DB4h PWM3DCH DC<15:8>

DB5h PWM3PRL PR<7:0>

DB6h PWM3PRH PR<15:8>

DB7h PWM3OFL OF<7:0>

DA8h PWM3OFH OF<15:8>

DA9h PWM3TMRL TMR<7:0>

DBAh PWM3TMRH TMR<15:8>

DBBh PWM3CON PWM3EN PWM3OE PWM3OUT PWM3POL PWM3MODE<1:0> — —

DBCh PWM3INTE — — — — PWM3OFIE PWM3PHIE PWM3DCIE PWM3PRIE

DBDh PWM3INTF — — — — PWM3OFIF PWM3PHIF PWM3DCIF PWM3PRIF

DBEh PWM3CLKCON — PWM3PS<2:0> — — PWM3CS<1:0>

DBFh PWM3LDCON PWM3LDA PWM3LDT — — — —PWM3LDS<1:0>

DC0h PWM3OFCON — PWM3OFM<1:0> PWM3OFO — —PWM3OFS<1:0>

Bank 28-30

58Ch

59Fh

Legend: Note 1:

— Unimplemented — —

= unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’.

PIC12F1571/2 only.

PIC12(L)F1572 only.

Unimplemented, read as ‘1’.

Val ue on

POR, BOR

---- 000 ---- 000

-000 -000 -000 --00 00-- -000 00-- --00

-000 -000 -000 --00

Val ue on All Other

Resets

DS40001723D-page 32  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 31

F8Ch — FE3h

FE4h STATUS_

FE5h WREG_

FE6h BSR_

FE7h PCLATH_

FE8h FSR0L_

FE9h FSR0H_

FEAh FSR1L_

FEBh FSR1H_

FECh — Unimplemented — —

FEDh STKPTR

FEEh TOSL Top-of-Stack Low Byte

FEFh TOSH — Top-of-Stack High Byte

Legend: Note 1:

— Unimplemented — —

SHAD

= unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’.

PIC12F1571/2 only.

PIC12(L)F1572 only.

Unimplemented, read as ‘1’.

— — — — — Z_SHAD DC_SHAD C_SHAD

Working Register Shadow

— — — Bank Select Register Shadow

— Program Counter Latch High Register Shadow

Indirect Data Memory Address 0 Low Pointer Shadow

Indirect Data Memory Address 0 High Pointer Shadow

Indirect Data Memory Address 1 Low Pointer Shadow

Indirect Data Memory Address 1 High Pointer Shadow

— — — Current Stack Pointer

Val ue on

POR, BOR

---- -xxx ---- -uuu

xxxx xxxx uuuu uuuu

---x xxxx ---u uuuu

-xxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

---1 1111 ---1 1111 xxxx xxxx uuuu uuuu

-xxx xxxx -uuu uuuu

Val ue on All Other

Resets

 2013-2015 Microchip Technology Inc. DS40001723D-page 33

PIC12(L)F1571/2

014

PCL

PCH

PCLATH

Instruction

with PCL as

Destination

GOTO,

CALL

CALLW

BRW

BRA

ALU result

OPCODE <10:0>

PC + W

PC + OPCODE <8:0>

Rev. 10-000042A

7/30/2013

3.4 PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC.

FIGURE 3-4: LOADING OF PC IN

DIFFERENT SITUATIONS

3.4.1 MODIFYING PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the Program Counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the Program Counter will change to the values contained in the PCLATH register and those being written to the PCL register.

3.4.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to the Program Counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556).

3.4.3 COMPUTED FUNCTION CALLs

A computed function CALL allows programs to maintain tables of functions and provides another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed CALLs by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH.

3.4.4 BRANCHING

The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed.

If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address, PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction.

DS40001723D-page 34  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2

STKPTR = 0x1F

Stack Reset Disabled (STVREN = 0)

Stack Reset Enabled (STVREN = 1)

Initial Stack Configuration:

After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL register will return ‘0’.Ifthe Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL register will return the contents of stack address 0x0F.

0x0000

STKPTR = 0x1F

TOSH:TOSL 0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x04

0x05

0x03

0x02

0x01

0x00

0x1F

TOSH:TOSL

Rev. 10-000043A

7/30/2013

3.5 Stack

All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-5 through 3-8). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN bit is programmed to ‘0’ (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an overflow/underflow, regardless of whether the Reset is enabled.

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the

CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to

an interrupt address.

3.5.1 ACCESSING THE STACK

The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. The TOSH:TOSL register pair points to the top of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. The STKPTR is 5 bits to allow detection of overflow and underflow.

Note: Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLW and interrupts will increment STKPTR while RETLW, RETURN and RETFIE will decrement STKPTR. At any time, the STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR.

Reference Figure 3-5 through Figure 3-8 for examples of accessing the stack.

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

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PIC12(L)F1571/2

STKPTR = 0x00

Return Address

This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x04

0x05

0x03

0x02

0x01

0x00

TOSH:TOSL

Rev. 10-000043B

7/30/2013

STKPTR = 0x06

After seven CALLsorsixCALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack.

Return Address

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x04

0x05

0x03

0x02

0x01

0x00

Return Address

TOSH:TOSL

Rev. 10-000043C

7/30/2013

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

DS40001723D-page 36  2013-2015 Microchip Technology Inc.

FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

STKPTR = 0x10

When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten.

Return Address0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x04

0x05

0x03

0x02

0x01

0x00

Return Address

TOSH:TOSL

Rev. 10-000043D

7/30/2013

PIC12(L)F1571/2

3.5.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in the Configuration Words is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register.

3.6 Indirect Addressing

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair, FSRnH and FSRnL.

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The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

PIC12(L)F1571/2

0x0000

0x0FFF

0x0000

0x7FFF0xFFFF

0x0000

0x0FFF

0x1000

0x1FFF

0x2000

0x29AF 0x29B0

0x7FFF

0x8000

Reserved

Traditional

Data Memory

Linear

Data Memory

Program

Flash Memory

FSR

Address

Range

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

Rev. 10-000044A

7/30/2013

FIGURE 3-9: INDIRECT ADDRESSING

DS40001723D-page 38  2013-2015 Microchip Technology Inc.

3.6.1 TRADITIONAL DATA MEMORY

Direct Addressing

40BSR 60

From Opcode

07FSRxH

000

07FSRxL

Indirect Addressing

00000 00001 00010 11111

Bank Select Location Select

0x00

0x7F

Bank Select Location Select

Bank 0 Bank 1 Bank 2

Bank 31

Rev. 10-000056A

7/31/2013

The traditional data memory is a region from FSR address, 0x000, to FSR address, 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

PIC12(L)F1571/2

 2013-2015 Microchip Technology Inc. DS40001723D-page 39

PIC12(L)F1571/2

0x020

Bank 0

0x06F

0x0A0

Bank 1

0x0EF

0x120

Bank 2

0x16F

0xF20

Bank 30

0xF6F

001

0077FSRnH FSRnL

Location Select

0x2000

0x29AF

Rev. 10-000057A

7/31/2013

0x0000

Program

Flash

Memory

(low 8 bits)

0x7FFF

0077FSRnH FSRnL

Location Select

0x8000

0xFFFF

Rev. 10-000058A

7/31/2013

3.6.2 LINEAR DATA MEMORY

The linear data memory is the region from FSR address, 0x2000, to FSR address, 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.

The 16 bytes of common memory are not included in the linear data memory region.

FIGURE 3-11: LINEAR DATA MEMORY

MAP

3.6.3 PROGRAM FLASH MEMORY

To make constant data access easier, the entire Program Flash Memory is mapped to the upper half of the FSR address space. When the MSb of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location are accessible via INDF. Writing to the Program Flash Memory cannot be accomplished via the FSR/INDF interface. All instructions that access Program Flash Memory via the FSR/INDF interface will require one additional instruction cycle to complete.

FIGURE 3-12: PROGRAM FLASH

MEMORY MAP

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PIC12(L)F1571/2

4.0 DEVICE CONFIGURATION

Device configuration consists of Configuration Words, code protection and Device ID.

4.1 Configuration Words

There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h.

Note: The DEBUG

is managed automatically by device development tools, including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.

bit in the Configuration Words

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PIC12(L)F1571/2

4.2 Register Definitions: Configuration Words

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

U-1 U-1 R/P-1 R/P-1 R/P-1 U-1

— —CLKOUTEN BOREN<1:0>

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1

(2)

MCLRE PWRTE

(1)

WDTE<1:0> —FOSC<1:0>

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after bulk erase

bit 13-12 Unimplemented: Read as ‘1’ bit 11 CLKOUTEN: Clock Out Enable bit

1 = Off – CLKOUT function is disabled; I/O or oscillator function on CLKOUT pin 0 =

– CLKOUT function is enabled on CLKOUT pin

bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits

11 =

– Brown-out Reset is enabled; the SBOREN bit is ignored

(1)

10 = Sleep – Brown-out Reset is enabled while running and disabled in Sleep; the SBOREN bit is ignored 01 =

SBODEN

– Brown-out Reset is controlled by the SBOREN bit in the BORCON register

00 = Off – Brown-out Reset is disabled; the SBOREN bit is ignored

bit 8 Unimplemented: Read as ‘1’ bit 7 CP

: Flash Program Memory Code Protection bit

(2)

1 = Off – Code protection is off; program memory can be read and written 0 = On– Code protection is on; program memory cannot be read or written externally

bit 6 MCLRE: MCLR

If LVP bit =

/VPP Pin Function Select bit

1 (On):

This bit is ignored. MCLR/VPP pin function is MCLR; weak pull-up is enabled. If LVP bit =

0 (Off): 1 = On – MCLR/VPP pin function is MCLR; weak pull-up is enabled 0 = Off – MCLR/VPP pin function is a digital input, MCLR is internally disabled; weak pull-up is under control

of pin’s WPU control bit

bit 5 PWRTE

: Power-up Timer Enable bit

(1)

1 = Off – PWRT is disabled 0 =

– PWRT is enabled

bit 4-3 WDTE<1:0>: Watchdog Timer Enable bits

11 =

– WDT is enabled; SWDTEN is ignored

10 = Sleep – WDT is enabled while running and disabled in Sleep; SWDTEN is ignored 01 =

SWDTEN

– WDT is controlled by the SWDTEN bit in the WDTCON register

00 = Off – WDT is disabled; SWDTEN is ignored

bit 2 Unimplemented: Read as ‘1’ bit 1-0 FOSC<1:0>: Oscillator Selection bits

11 = ECH – External Clock, High-Power mode: CLKI on CLKI 10 = ECM – External Clock, Medium Power mode: CLKI on CLKI 01 = 00 =

ECL INTOSC

– External Clock, Low-Power mode: CLKI on CLKI – I/O function on CLKI

(1)

—

Note 1: Enabling Brown-out Reset does not automatically enable the Power-up Timer.

2: Once enabled, code-protect can only be disabled by bulk erasing the device.

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PIC12(L)F1571/2

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

LVP

(1)

DEBUG

bit 13 bit 8

U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1

— — — — — —WRT<1:0>

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after bulk erase

(2)

LPBOREN BORV

(3)

STVREN PLLEN

bit 13 LVP: Low-Voltage Programming Enable bit

(1)

1 = On – Low-voltage programming is enabled, MCLR/VPP pin function is MCLR; MCLRE

Configuration bit is ignored

0 = Off – High voltage on MCLR

bit 12 DEBUG: Debugger Mode bit

/VPP must be used for programming

(2)

1 = Off – In-Circuit Debugger is disabled; ICSPCLK and ICSPDAT are general purpose I/O pins 0 = On – In-Circuit Debugger is enabled; ICSPCLK and ICSPDAT are dedicated to the debugger

bit 11 LPBOREN

: Low-Power Brown-out Reset Enable bit

1 = Off – Low-power Brown-out Reset is disabled 0 = On – Low-power Brown-out Reset is enabled

bit 10 BORV: Brown-out Reset Voltage Selection bit

(3)

1 = Low – Brown-out Reset voltage (VBOR), low trip point selected 0 = High – Brown-out Reset voltage (V

BOR), high trip point selected

bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit

1 = On – Stack overflow or underflow will cause a Reset 0 = Off – Stack overflow or underflow will not cause a Reset

bit 8 PLLEN: PLL Enable bit

1 = On – 4xPLL is enabled 0 = Off – 4xPLL is disabled

bit 7-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits

2 kW Flash Memory (

PIC12F1572):

11 = Off – Write protection is off 10 = Boot – 000h to 1FFh is write-protected, 200h to 7FFh may be modified by PMCON control 01 = Half – 000h to 3FFh is write-protected, 400h to 7FFh may be modified by PMCON control 00 = All – 000h to 7FFh is write-protected, no addresses may be modified by PMCON control

1 kW Flash Memory (

PIC12(L)F1571):

11 = Off – Write protection is off 10 = Boot – 000h to 0FFh is write-protected, 100h to 3FFh may be modified by PMCON control 01 = Half – 000h to 1FFh is write-protected, 200h to 3FFh may be modified by PMCON control 00 = All – 000h to 3FFh is write-protected, no addresses may be modified by PMCON control

Note 1: This bit cannot be programmed to ‘0’ when programming mode is entered via LVP.

2: The DEBUG

bit in Configuration Words is managed automatically by device development tools, including

debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.

3: See V

 2013-2015 Microchip Technology Inc. DS40001723D-page 43

BOR parameter for specific trip point voltages.

PIC12(L)F1571/2

4.3 Code Protection

Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting.

4.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from external reads and writes by the CP Configuration Words. When CP writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.4 “Write

Protection” for more information.

= 0, external reads and

bit in the

4.4 Write Protection

Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified.

The WRT<1:0> bits in the Configuration Words define the size of the program memory block that is protected.

4.5 User ID

Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See

Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing

these memory locations.

checksum calculation, see the “PIC12(L)F1571/2 Memory Programming Specification” (DS40001713).

For more information on

4.6 Device ID and Revision ID

The 14-bit Device ID word is located at 8006h and the 14-bit Revision ID is located at 8005h. These locations are read-only and cannot be erased or modified. See

Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.

DS40001723D-page 44  2013-2015 Microchip Technology Inc.

4.7 Register Definitions: Device ID

PIC12(L)F1571/2

RRRRRR

bit 13 bit 8

RRRRRRRR

DEV<7:0>

bit 7 bit 0

Legend:

R = Readable bit

‘0’ = Bit is cleared ‘1’ = Bit is set

bit 13-0 DEV<13:0>: Device ID bits

Refer to Tab le 4 -1 to determine what these bits will read on which device. A value of 3FFFh is invalid.

Note 1: This location cannot be written.

RRRRRR

bit 13 bit 8

(1)

DEV<13:8>

x = Bit is unknown

(1)

REV<13:8>

RRRRRRRR

REV<7:0>

bit 7 bit 0

Legend:

R = Readable bit

‘0’ = Bit is cleared ‘1’ = Bit is set

bit 13-0 REV<13:0>: Revision ID bits

These bits are used to identify the device revision.

Note 1: This location cannot be written.

x = Bit is unknown

TABLE 4-1: DEVICE ID VALUES

DEVICE Device ID Revision ID

PIC12F1571 3051h 2xxxh PIC12LF1571 3053h 2xxxh PIC12F1572 3050h 2xxxh PIC12LF1572 3052h 2xxxh

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PIC12(L)F1571/2

NOTES:

DS40001723D-page 46  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2

5.0 OSCILLATOR MODULE

5.1 Overview

The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications, while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include:

• Selectable system clock source between external or internal sources via software

• Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources

The oscillator module can be configured in one of the following clock modes:

1. ECL – External Clock Low-Power mode (0 MHz to 0.5 MHz)

2. ECM – External Clock Medium Power mode (0.5 MHz to 4 MHz)

3. ECH – External Clock High-Power mode (4 MHz to 32 MHz)

4. INTOSC – Internal Oscillator (31 kHz to 32 MHz)

Clock Source modes are selected by the FOSC<1:0> bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered.

The ECH, ECM, and ECL Clock modes rely on an external logic level signal as the device clock source.

The INTOSC internal oscillator block produces low, medium and high-frequency clock sources, designated as LFINTOSC, MFINTOSC and HFINTOSC (see Internal Oscillator Block, Figure 5-1). A wide selection of device clock frequencies may be derived from these three clock sources.

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PIC12(L)F1571/2

Rev. 10-000155A

10/11/2013

31 kHz

Oscillator

Prescaler

HFINTOSC

(1)

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

*500 kHz

*250 kHz

*125 kHz

62.5 kHz

*31.25 kHz

*31 kHz

IRCF<3:0>

INTOSC

to CPU and

Peripherals

Sleep

OSC

(1)

LFINTOSC

(1)

to WDT, PWRT, and other Peripherals

* Available with more than one IRCF selection

SCS<1:0>

600 kHz

Oscillator

FRC

(1)

to ADC and

other Peripherals

CLKIN

4x PLL

(2)

HFPLL

16 MHz

500 kHz

Oscillator

MFINTOSC

(1)

Internal Oscillator

Block

to Peripherals

PLLEN

SPLLEN

FOSC<1:0>

01Reserved

Note 1: See Section 5.2 “Clock Source Types”.

2: ST Buffer is high-speed type when using T1CKI. 3: If FOSC<1:0> = 00, 4x PLL can only be used if IRCF<3:0> = 1110.

FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

DS40001723D-page 48  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2

CLKIN

CLKOUT

Clock from Ext. System

PIC

MCU

FOSC/4 or

Note 1: Output depends upon CLKOUTEN

bit of

the Configuration Words.

I/O

(1)

5.2 Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the clock source to function.

Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated Phase-Locked Loop (HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHz Medium Frequency Internal Oscillator (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC).

The system clock can be selected between external or internal clock sources via the System Clock Select (SCS<1:0>) bits in the OSCCON register. See

Section 5.3 “Clock Switching” for additional

information.

5.2.1 EXTERNAL CLOCK SOURCES

An external clock source can be used as the device system clock by performing one of the following actions:

• Program the FOSC<1:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to:

- Timer1 oscillator during run time, or

- An external clock source determined by the

value of the FOSCx bits.

See Section 5.3 “Clock Switching” for more information.

5.2.1.1 EC Mode

The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the CLKIN input. CLKOUT is available for general purpose I/Os or CLKOUT.

Figure 5-2 shows the pin connections for EC mode.

EC mode has three power modes to select from through the FOSCx bits in the Configuration Words:

• ECH – High power, 4-20 MHz

• ECM – Medium power, 0.5-4 MHz

• ECL – Low power, 0-0.5 MHz

The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC

MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.

FIGURE 5-2: EXTERNAL CLOCK (EC)

MODE OPERATION

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PIC12(L)F1571/2

5.2.2 INTERNAL CLOCK SOURCES

The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions:

• Program the FOSC<1:0> bits in the Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run time. See

Section 5.3 “Clock Switching”for more

information.

In INTOSC mode, CLKIN is available for general purpose I/O. CLKOUT is available for general purpose I/O or CLKOUT.

The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN

The internal oscillator block has two independent oscillators and a dedicated Phase-Locked Loop, HFPLL, that can produce one of three internal system clock sources.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at 16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase-Locked Loop, HFPLL. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 5-3).

2. The MFINTOSC (Medium Frequency Internal

Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 5-3).

3. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at 31 kHz.

bit in the Configuration Words.

5.2.2.1 HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 5-3).

The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of multiple frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.8 “Internal

Oscillator Clock Switch Timing” for more information.

The HFINTOSC is enabled by:

• Configuring the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and

• Setting FOSC<1:0> = 00, or

• Setting the System Clock Source x (SCSx) bits of the OSCCON register to ‘1x’.

A fast start-up oscillator allows internal circuits to power up and stabilize before switching to HFINTOSC.

The High-Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running.

The High-Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value.

The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value.

5.2.2.2 MFINTOSC

The Medium Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 5-3).

The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.8 “Internal

Oscillator Clock Switch Timing” for more information.

The MFINTOSC is enabled by:

• Configuring the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and

• Setting FOSC<1:0> = 00, or

• Setting the System Clock Source x (SCSx) bits of the OSCCON register to ‘1x’

The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running.

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PIC12(L)F1571/2

5.2.2.3 Internal Oscillator Frequency Adjustment

The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 5-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator, a change in the OSCTUNE register value will apply to both.

The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency.

When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depends on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT) and peripherals, are

not affected by the change in frequency.

5.2.2.4 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a multiplexer (see Figure 5-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See

Section 5.2.2.8 “Internal Oscillator Clock Switch Timing” for more information. The LFINTOSC is also

the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> (OSCCON<6:3>) = 0000) as the system clock source (SCS<1:0> (OSCCON<1:0>) = 1x) or when any of the following are enabled:

• Configure the IRCF<3:0> bits of the OSCCON

• Set FOSC<1:0> = 00, or

• Set the System Clock Source x (SCSx) bits of the

OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running.

5.2.2.5 FRC

The FRC clock is an uncalibrated, nominal 600 kHz peripheral clock source.

The FRC is automatically turned on by the peripherals requesting the FRC clock.

The FRC clock will continue to run during Sleep.

5.2.2.6 Internal Oscillator Frequency Selection

The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register.

The postscaler outputs of the 16 MHz HFINTOSC, 500 kHz MFINTOSC and 31 kHz LFINTOSC output connect to a multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits, IRCF<3:0> of the OSCCON register, select the frequency output of the internal oscillators. One of the following frequencies can be selected via software:

• 32 MHz (requires 4x PLL)

•16 MHz

•8 MHz

•4 MHz

•2 MHz

•1 MHz

• 500 kHz (default after Reset)

•250 kHz

•125 kHz

•62.5 kHz

•31.25 kHz

• 31 kHz (LFINTOSC)

Note: Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCFx bits to select a different frequency.

The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source.

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PIC12(L)F1571/2

5.2.2.7 32 MHz Internal Oscillator Frequency Selection

The internal oscillator block can be used with the 4x PLL associated with the external oscillator block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source:

• The FOSCx bits in the Configuration Words must

be set to use the INTOSC source as the device system clock (FOSC<1:0> = 00).

• The SCSx bits in the OSCCON register must be

cleared to use the clock determined by FOSC<1:0> in the Configuration Words (SCS<1:0> = 00).

• The IRCFx bits in the OSCCON register must be

set to the 8 MHz HFINTOSC to use (IRCF<3:0> = 1110).

• The SPLLEN bit in the OSCCON register must be

set to enable the 4x PLL or the PLLEN bit of the Configuration Words must be programmed to a ‘1’.

Note: When using the PLLEN bit of the

Configuration Words, the 4x PLL cannot

be disabled by software and the 8 MHz HFINTOSC option will no longer be available.

The 4x PLL is not available for use with the internal oscillator when the SCSx bits of the OSCCON register are set to ‘1x’. The SCSx bits must be set to ‘00’ to use the 4x PLL with the internal oscillator.

5.2.2.8 Internal Oscillator Clock Switch Timing

When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-3). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows:

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new clock.

5. The new clock is now active.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

See Figure 5-3 for more details.

If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1.

Start-up delay specifications are located in the oscillator tables of Section 26.0 “Electrical

Specifications”.

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FIGURE 5-3: INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC/

LFINTOSC

IRCF<3:0>

System Clock

HFINTOSC/

LFINTOSC

IRCF <3:0>

System Clock

0 = 0

Oscillator Delay

(1)

2-Cycle Sync

Running

2-Cycle Sync Running

HFINTOSC/ LFINTOSC (WDT disabled)

HFINTOSC/

LFINTOSC (WDT enabled)

LFINTOSC

HFINTOSC/

IRCF <3:0>

System Clock

= 0  0

2-Cycle Sync

Running

LFINTOSC

HFINTOSC/MFINTOSC

LFINTOSC Turns Off unless WDT is Enabled

MFINTOSC

Oscillator

Note 1: See Ta bl e 5 -1 (Oscillator Switching Delays) for more information.

Delay

(1)

PIC12(L)F1571/2

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5.3 Clock Switching

The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCSx) bits of the OSCCON register. The following clock sources can be selected using the SCSx bits:

• Default system oscillator determined by FOSCx bits in the Configuration Words

• Timer1 32 kHz crystal oscillator

• Internal Oscillator Block (INTOSC)

5.3.1 SYSTEM CLOCK SELECT (SCSx)

BITS

The System Clock Select (SCSx) bits of the OSCCON register select the system clock source that is used for the CPU and peripherals.

• When the SCSx bits of the OSCCON register = 00, the system clock source is determined by the value of the FOSC<1:0> bits in the Configuration Words.

• When the SCSx bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator.

• When the SCSx bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCSx bits of the OSCCON register are always cleared.

Note: Any automatic clock switch does not

update the SCSx bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source.

5.4 Clock Switching Before Sleep

When clock switching from an old clock to a new clock is requested, just prior to entering Sleep mode, it is necessary to confirm that the switch is complete before the SLEEP instruction is executed. Failure to do so may result in an incomplete switch and consequential loss of the system clock altogether. Clock switching is confirmed by monitoring the clock status bits in the OSCSTAT register. Switch confirmation can be accomplished by sensing that the ready bit for the new clock is set or the ready bit for the old clock is cleared. For example, when switching between the internal oscillator with the PLL and the internal oscillator without the PLL, monitor the PLLR bit. When PLLR is set, the switch to 32 MHz operation is complete. Conversely, when PLLR is cleared, the switch from 32 MHz operation to the selected internal clock is complete.

When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 5-1.

TABLE 5-1: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Frequency Oscillator Delay

LFINTOSC

Sleep/POR

MFINTOSC

HFINTOSC Sleep/POR EC LFINTOSC EC

Any Clock Source

(1)

MFINTOSC

HFINTOSC Any Clock Source LFINTOSC

(1)

PLL Inactive PLL Active 16-32 MHz 2 ms (approx.)

Note 1: PLL inactive.

2: See Section 26.0 “Electrical Specifications”.

31 kHz

31.25 kHz-500 kHz

Oscillator Warm-up Delay (T

31.25kHz-16MHz DC – 32 MHz 2 cycles DC – 32 MHz 1 cycle of each

31.25 kHz-500 kHz

31.25kHz-16MHz

2 s (approx.)

31 kHz 1 cycle of each

WARM)

(2)

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5.5 Register Definitions: Oscillator Control

REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0

SPLLEN IRCF<3:0> —SCS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets

bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words = SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements).

If PLLEN in Configuration Words = 0:

1 = 4x PLL Is enabled 0 = 4x PLL is disabled

bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits

1111 = 16 MHz HF 1110 = 8 MHz or 32 MHz HF (see Section 5.2.2.1 “HFINTOSC”) 1101 = 4 MHz HF 1100 = 2 MHz HF 1011 = 1 MHz HF 1010 = 500 kHz HF 1001 = 250 kHz HF 1000 = 125 kHz HF 0111 = 500 kHz MF (default upon Reset) 0110 = 250 kHz MF 0101 = 125 kHz MF 0100 = 62.5 kHz MF 0011 = 31.25 kHz HF 0010 = 31.25 kHz MF 000x = 31 kHz LF

bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits

1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<1:0> in Configuration Words

(1)

Note 1: Duplicate frequency derived from HFINTOSC.

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REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER

U-0 R-0/q R-q/q R-0/q R-0/q R-q/q R-0/q R-0/q

— PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit q = Conditional bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets

bit 7 Unimplemented: Read as ‘0’ bit 6 PLLR 4x PLL Ready bit

1 = 4x PLL is ready 0 = 4x PLL is not ready

bit 5 OSTS: Oscillator Start-up Timer Status bit

1 = Running from the clock defined by the FOSC<1:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<1:0> = 00)

bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit

1 = HFINTOSC is ready 0 = HFINTOSC is not ready

bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit

1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate

bit 2 MFIOFR: Medium Frequency Internal Oscillator Ready bit

1 = MFINTOSC is ready 0 = MFINTOSC is not ready

bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit

1 = LFINTOSC is ready 0 = LFINTOSC is not ready

bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit

1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate

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REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — TUN<5:0>

bit 7 bit 0

Legend:

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits

100000 = Minimum frequency

•

111111 = 000000 = Oscillator module is running at the factory-calibrated frequency 000001 =

•

011110 = 011111 = Maximum frequency

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON SPLLEN IRCF<3:0> OSCSTAT OSCTUNE — — TUN<5:0> 57

T1CON Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

— PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 56

TMR1CS<1:0> T1CKPS<1:0> — T1SYNC — TMR1ON 167

—SCS<1:0>55

TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

13:8

7:0

— — — —CLKOUTENBOREN<1:0> —

CP MCLRE PWRTE WDTE<1:0> — FOSC<1:0>

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NOTES:

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Note 1: See Table 6-1 for BOR active conditions.

Device

Reset

Power-on

Reset

WDT

Time-out

Brown-out

Reset

LPBOR

Reset

RESET Instruction

MCLRE

Sleep

BOR

Active

(1)

PWRTE

LFINTOSC

VDD

ICSP™ Programming Mode Exit

Stack Underflow

Stack Overlfow

VPP/MCLR

Power-up

Timer

Rev. 10-000006A

8/14/2013

6.0 RESETS

To allow V

DD to stabilize, an optional Power-up Timer

can be enabled to extend the Reset time after a BOR

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

or POR event.

A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1.

• Low-Power Brown-out Reset (LPBOR)

•MCLR Reset

•WDT Reset

• RESET instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

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6.1 Power-on Reset (POR)

The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising V performance may require greater than minimum V The PWRT, BOR or MCLR extend the start-up period until all device operation conditions have been met.

6.1.1 POWER-UP TIMER (PWRT)

The Power-up Timer provides a nominal 64 ms time-out on a POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the V rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in the Configuration Words.

The Power-up Timer starts after the release of the POR and BOR.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00000607).

DD, fast operating speeds or analog

DD.

features can be used to

DD to

6.2 Brown-out Reset (BOR)

The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented.

The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in the Configuration Words. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Tab le 6 -1 for more information.

The Brown-out Reset voltage level is selectable by configuring the BORV bit in the Configuration Words.

DD noise rejection filter prevents the BOR from trig-

A V gering on small events. If V duration greater than parameter, T will reset. See Figure 6-2 for more information.

DD falls below VBOR for a

BORDC, the device

TABLE 6-1: BOR OPERATING MODES

BOREN<1:0> SBOREN Device Mode BOR Mode

11 X XActive

10 X

00 X X Disabled

Note 1: In these specific cases, “release of POR” and “wake-up from Sleep”, there is no delay in start-up. The BOR

ready flag (BORRDY = 1) will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits.

1 XActive

0 X Disabled Begins immediately

Awake Active Waits for BOR ready

Sleep Disabled

Instruction Execution upon:

Release of POR or Wake-up from Sleep

Waits for BOR ready

(BORRDY = 1)

Waits for BOR ready

(BORRDY = 1)

(BORRDY = x)

(1)

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TPWRT

(1)

VBOR

Internal

Reset

VBOR

Internal

Reset

TPWRT

(1)

< TPWRT

TPWRT

(1)

VBOR

Internal

Reset

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

6.2.1 BOR IS ALWAYS ON

When the BORENx bits of the Configuration Words are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.

6.2.2 BOR IS OFF IN SLEEP

When the BORENx bits of the Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and V

DD is higher than the BOR threshold.

FIGURE 6-2: BROWN-OUT SITUATIONS

BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.

6.2.3 BOR CONTROLLED BY SOFTWARE

When the BORENx bits of the Configuration Words are programmed to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or

DD level.

the V

BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

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6.3 Register Definitions: BOR Control

REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u

SBOREN BORFS

bit 7 bit 0

Legend:

bit 7 SBOREN: Software Brown-out Reset Enable bit

If BOREN<1:0> in Configuration Words =

1 = BOR is enabled 0 = BOR is disabled

If BOREN <1:0> in Configuration Words SBOREN is read/write, but has no effect on the BOR.

bit 6 BORFS: Brown-out Reset Fast Start bit

If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):

1 = Band gap is forced on always (covers Sleep/wake-up/operating cases) 0 = Band gap operates normally and may turn off

If BOREN<1:0> = BORFS is read/write, but has no effect on the BOR.

bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit

1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive

(1)

— — — — — BORRDY

01:

 01:

(1)

11 (Always On) or BOREN<1:0> = 00 (Always Off):

Note 1: BOREN<1:0> bits are located in the Configuration Words.

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6.4 Low-Power Brown-out Reset (LPBOR)

The Low-Power Brown-out Reset (LPBOR) operates like the BOR to detect low-voltage conditions on the VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The BOR bit in PCON is used for both BOR and the LPBOR. Refer to Register 6-2.

The LPBOR Voltage Threshold (V tolerance than the BOR (V less current (LPBOR current) to operate. The LPBOR is intended for use when the BOR is configured as disabled (BOREN<1:0> = 00) or disabled in Sleep mode (BOREN<1:0> = 10).

Refer to Figure 6-1 to see how the LPBOR interacts with other modules.

6.4.1 ENABLING LPBOR

The LPBOR is controlled by the LPBOR bit of the Configuration Words. When the device is erased, the LPBOR module defaults to disabled.

6.5 MCLR

The MCLR is an optional external input that can reset the device. The MCLR MCLRE and LVP bits of the Configuration Words (Table 6-2).

function is controlled by the

TABLE 6-2: MCLR CONFIGURATION

MCLRE LVP MCLR

00Disabled 10Enabled x1Enabled

6.5.1 MCLR ENABLED

When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR

DD through an internal weak pull-up.

The device has a noise filter in the MCLR The filter will detect and ignore small pulses.

Note: A Reset does not drive the MCLR

6.5.2 MCLR DISABLED

When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 11.3 “PORTA Registers” for more information.

LPBOR) has a wider

BOR), but requires much

pin is connected to

Reset path.

pin low.

6.6 Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See

Section 9.0 “Watchdog Timer (WDT)” for more

information.

6.7 RESET Instruction

A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Ta b le 6 - 4 for default conditions after a RESET instruction has occurred.

6.8 Stack Overflow/Underflow Reset

The device can reset when the Stack overflows or underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in the Configuration Words. See Section 3.5.2 “Overflow/Underflow

Reset” for more information.

6.9 Programming Mode Exit

Upon exit of Programming mode, the device will behave as if a POR had just occurred.

6.10 Power-up Timer

The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to

DD to stabilize before allowing the device to start

allow V running.

The Power-up Timer is controlled by the PWRTE bit of the Configuration Words.

6.11 Start-up Sequence

Upon the release of a POR or BOR, the following must occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled). CLR must be released (if enabled).

2. M

The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See

Section 5.0 “Oscillator Module” for more information.

The Power-up Timer runs independently of a MCLR Reset. If MCLR is kept low long enough, the Power-up Timer will expire. Upon bringing MCLR will begin execution after 10 F

Figure 6-3). This is useful for testing purposes or to

synchronize more than one device operating in parallel.

high, the device

OSC cycles (see

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Note 1: Code execution begins 10 FOSC cycles after the FOSC clock is released.

External Oscillators , PWRTEN = 1, IESO = 1

code execution

(1)

External Oscillators , PWRTEN = 0, IESO = 1

Ext. Oscillator

Osc Start-Up Timer

TOST

TPWRT

TOST

VDD

Internal POR

Internal RESET

MCLR

FOSC

Begin Execution

Power-up Timer

Int. Oscillator

code execution

(1)

External Oscillators , PWRTEN = 1, IESO = 0

code

execution

(1)

External Oscillators , PWRTEN = 0, IESO = 0

Ext. Oscillator

Osc Start-Up Timer

code

execution

(1)

TOST

TPWRT

TOST

VDD

Internal POR

Internal RESET

MCLR

FOSC

Begin Execution

Power-up Timer

Internal POR

External Clock (EC modes), PWRTEN = 0

Internal RESET

MCLR

FOSC

Begin Execution

Ext. Clock (EC)

Power-up Timer

External Clock (EC modes), PWRTEN = 1

code execution

(1)

code execution

(1)

TPWRT

Int. Oscillator

code execution

(1)

Internal Oscillator, PWRTEN = 0

Internal Oscillator, PWRTEN = 1

code execution

(1)

TPWRT

VDD

Internal POR

Internal RESET

MCLR

FOSC

Begin Execution

Power-up Timer

Rev. 10-000032A

7/30/2013

FIGURE 6-3: RESET START-UP SEQUENCE

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6.12 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Tab le 6 - 3 and Tab le 6 - 4 show the Reset conditions of these registers.

TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition

001110x11Power-on Reset 001110x0xIllegal, TO is Set on POR 001110xx0Illegal, PD is Set on POR

00u11u011Brown-out Reset uu0uuuu0uWDT Reset uuuuuuu00WDT Wake-up from Sleep uuuuuuu10Interrupt Wake-up from Sleep uuu0uuuuuMCLR uuu0uuu10MCLR u u u u 0 u u u u RESET Instruction Executed 1uuuuuuuuStack Overflow Reset (STVREN = 1) u1uuuuuuuStack Underflow Reset (STVREN = 1)

Reset during Normal Operation

Reset during Sleep

TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS

Condition

Power-on Reset 0000h ---1 1000 00-- 110x

Reset during normal operation 0000h ---u uuuu uu-- 0uuu

MCLR

Reset during Sleep 0000h ---1 0uuu uu-- 0uuu

MCLR WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 Interrupt Wake-up from Sleep PC + 1 RESET Instruction Executed 0000h ---u uuuu uu-- u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu

Legend: u = unchanged; x = unknown; - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and the Global Interrupt Enable bit (GIE) is set, the return address

is pushed on the stack and the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

Program Counter

(1)

STATUS

---1 0uuu uu-- uuuu

PCON

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6.13 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

• RESET Instruction Reset (RI

•MCLR Reset (RMCLR)

• Watchdog Timer Reset (RWDT

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

The PCON register bits are shown in Register 6-2.

6.14 Register Definitions: Power Control

REGISTER 6-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF STKUNF

bit 7 bit 0

)

—RWDTRMCLR RI POR BOR

Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 STKOVF: Stack Overflow Reset Flag bit

1 = A Stack Overflow Reset occurred 0 = A Stack Overflow Reset has not occurred or is cleared by firmware

bit 6 STKUNF: Stack Underflow Reset Flag bit

1 = A Stack Underflow Reset occurred 0 = A Stack Underflow Reset has not occurred or is cleared by firmware

bit 5 Unimplemented: Read as ‘0’ bit 4 RWDT

bit 3 RMCLR

bit 2 RI

bit 1 POR

bit 0 BOR

: Watchdog Timer Reset Flag bit

1 = A Watchdog Timer Reset has not occurred or is set by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware)

: MCLR Reset Flag bit

1 = A MCLR 0 = A MCLR

: RESET Instruction Flag bit

1 = A RESET instruction has not been executed or set by firmware 0 = A RESET instruction has been executed (cleared by hardware)

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)

Reset has not occurred or is set by firmware Reset has occurred (cleared by hardware)

: Power-on Reset Status bit

: Brown-out Reset Status bit

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TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BORCON SBOREN BORFS

PCON STKOVF STKUNF

STATUS WDTCON — — WDTPS<4:0> SWDTEN 89

Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR

— — —TOPD Z DC C 19

— — — — — BORRDY 62

—RWDTRMCLR RI POR BOR 66

Reset and Watchdog Timer Reset during normal operation.

TABLE 6-6: SUMMARY OF CONFIGURATION WORD WITH RESETS

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

on Page

CONFIG1

CONFIG2

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

13:8

7:0

13:8

7:0 — — — — — — WRT<1:0>

— — — — CLKOUTEN BOREN<1:0> —

CP MCLRE PWRTE WDTE<1:0> — FOSC<1:0>

— — LV P DEBUG LPBOR BORV STVREN PLLEN

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TMR0IF

TMR0IE

INTF INTE

IOCIF IOCIE

Interrupt to CPU

Wake-up (If in Sleep mode)

GIE

(TMR1IF) PIR1<0>

PIRn<7>

PEIE

(TMR1IE) PIE1<0>

Peripheral Interrupts

PIEn<7>

Rev. 10-000010A

1/13/2014

7.0 INTERRUPTS

The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.

This chapter contains the following information for interrupts:

• Operation

• Interrupt Latency

• Interrupts during Sleep

•INT Pin

• Automatic Context Saving

FIGURE 7-1: INTERRUPT LOGIC

Many peripherals produce interrupts. Refer to the corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 7-1.

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7.1 Operation

Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt enable bit(s) for the specific interrupt event(s)

• PEIE bit of the INTCON register (if the interrupt enable bit of the interrupt event is contained in the PIE1, PIE2 and PIE3 registers)

The INTCON, PIR1, PIR2 and PIR3 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits.

The following events happen when an interrupt event occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the stack

• Critical registers are automatically saved to the shadow registers (See “Section 7.5 “Automatic

Context Saving”.”)

• PC is loaded with the interrupt vector, 0004h

The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit.

For additional information on a specific interrupt’s operation, refer to its peripheral chapter.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.

7.2 Interrupt Latency

Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 7-2 and Figure 7-3 for more details.

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Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Fosc

CLKR

PC 0004h 0005h

Inst(0004h)NOP

GIE

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4

1-Cycle Instruction at PC

Inst(0004h)NOP

2-Cycle Instruction at PC

FSR ADDR PC+1 PC+2 0004h 0005h

Inst(0004h)NOP

GIE

PCPC-1

3-Cycle Instruction at PC

Execute

Interrupt

Inst(PC)

Interrupt Sampled during Q1

Inst(PC)

PC-1 PC+1

NOP

New PC/

PC+1

0005hPC-1

PC+1/FSR

ADDR

0004h

NOP

Interrupt

GIE

Interrupt

INST(PC) NOPNOP

FSR ADDR PC+1 PC+2 0004h 0005h

Inst(0004h)NOP

GIE

PCPC-1

3-Cycle Instruction at PC

Interrupt

INST(PC) NOPNOP

NOP

Inst(0005h)

Execute

PIC12(L)F1571/2

FIGURE 7-2: INTERRUPT LATENCY

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Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

FOSC

CLKOUT

INT Pin

INTF

GIE

Instruction Fetched

Instruction Executed

Interrupt Latency

(2)

PC + 1

PC + 1 0004h 0005h

Inst (0004h)

Inst (0005h)

Forced NOP

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Forced NOP

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 T

CY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: For minimum width of INT pulse, refer to AC specifications in Section 26.0 “Electrical Specifications”. 4: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1)

(3)

(4)

(1)

INSTRUCTION FLOW

FIGURE 7-3: INT PIN INTERRUPT TIMING

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7.3 Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section 8.0 “Power-Down Mode

(Sleep)” for more details.

7.4 INT Pin

The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector.

7.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers:

• W register

• STATUS register (except for TO

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved.

and PD)

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7.6 Register Definitions: Interrupt Control

REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0

(1)

GIE

bit 7 bit 0

Legend:

PEIE

(2)

TMR0IE INTE IOCIE TMR0IF INTF IOCIF

(3)

bit 7 GIE: Global Interrupt Enable bit

(1)

1 = Enables all active interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

(2)

1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt 0 = Disables the INT external interrupt

bit 3 IOCIE: Interrupt-On-Change Enable bit

1 = Enables the Interrupt-On-Change 0 = Disables the Interrupt-On-Change

bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed 0 = TMR0 register has not overflow

bit 1 INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur

bit 0 IOCIF: Interrupt-On-Change Interrupt Flag bit

1 = When at least one of the Interrupt-On-Change pins changed state 0 = None of the Interrupt-On-Change pins have changed state

(3)

Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 3: The IOCIF Flag bit is read-only and cleared when all the Interrupt-On-Change flags in the IOCxF registers

have been cleared by software.

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REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0

TMR1GIE ADIE RCIE

bit 7 bit 0

Legend:

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt

bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt 0 = Disables the ADC interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt

bit 3-2 Unimplemented: Read as ‘0’ bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt

(1)

TXIE

(1)

— — TMR2IE TMR1IE

(1)

Note 1: PIC12(L)F1572 only.

2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

U-0 U-0 R/W-0/0 U-0 U-0 U-0 U-0 U-0

— —C1IE— — — — —

bit 7 bit 0

Legend:

bit 7-6 Unimplemented: Read as ‘0’ bit 5 C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt

bit 4-0 Unimplemented: Read as ‘0’

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0

— PWM3IE PWM2IE PWM1IE — — — —

bit 7 bit 0

Legend:

bit 7 Unimplemented: Read as ‘0’ bit 6 PWM3IE: PWM3 Interrupt Enable bit

1 = Enables the PWM3 interrupt 0 = Disables the PWM3 interrupt

bit 5 PWM2IE: PWM2 Interrupt Enable bit

1 = Enables the PWM2 interrupt 0 = Disables the PWM2 interrupt

bit 4 PWM1IE: PWM1 Interrupt Enable bit

1 = Enables the PWM1 interrupt 0 = Disables the PWM1 interrupt

bit 3-0 Unimplemented: Read as ‘0’

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0

TMR1GIF ADIF RCIF

bit 7 bit 0

Legend:

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 6 ADIF: ADC Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 3-2 Unimplemented: Read as ‘0’ bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

(1)

TXIF

(1)

— — TMR2IF TMR1IF

(1)

Note 1: PIC12(L)F1572 only.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

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REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

U-0 U-0 R/W-0/0 U-0 U-0 U-0 U-0 U-0

— —C1IF— — — — —

bit 7 bit 0

Legend:

bit 7-6 Unimplemented: Read as ‘0’ bit 5 C1IF: Numerically Controlled Oscillator Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 4-0 Unimplemented: Read as ‘0’

Note: Interrupt flag bits are set when an interrupt

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REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

U-0 R-0/0 R-0/0 R-0/0 U-0 U-0 U-0 U-0

—PWM3IF

(1)

PWM2IF

bit 7 bit 0

Legend:

bit 7 Unimplemented: Read as ‘0’ bit 6 PWM3IF: PWM3 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 5 PWM2IF: PWM2 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 4 PWM1IF: PWM1 Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 3-0 Unimplemented: Read as ‘0’

(1)

PWM1IF

(1)

— — — —

Note 1: These bits are read-only. They must be cleared by addressing the Flag registers inside the module.

2: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

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TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74

OPTION_REG PIE1 TMR1GIE ADIE RCIE PIE2 PIE3 PIR1 TMR1GIF ADIF RCIF PIR2 PIR3

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts. Note 1: PIC12(L)F1572 only.

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 157

(1)

— —C1IE— — — — — 76 — PWM3IE PWM2IE PWM1IE — — — — 77

(1)

— —C1IF— — — — — 79 — PWM3IF PWM2IF PWM1IF — — — — 80

TXIE

TXIF

(1)

— — TMR2IE TMR1IE 75

— — TMR2IF TMR1IF 78

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8.0 POWER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing a SLEEP instruction.

Upon entering Sleep mode, the following conditions exist:

1. WDT will be cleared but keeps running if enabled for operation during Sleep.

2. PD

3. TO

4. CPU clock is disabled.

5. 31 kHz LFINTOSC is unaffected and peripherals

6. Timer1 and peripherals that operate from

7. ADC is unaffected if the dedicated FRC oscillator

8. I/O ports maintain the status they had before

9. Resets other than WDT are not affected by

Refer to individual chapters for more details on peripheral operation during Sleep.

To minimize current consumption, the following conditions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• CWG module using HFINTOSC

I/O pins that are high-impedance inputs should be pulled to V currents caused by floating inputs.

Examples of internal circuitry that might be sourcing current include the FVR module. See

Section 13.0 “Fixed Voltage Reference (FVR)”

for more information on this module.

8.1 Wake-up from Sleep

The device can wake-up from Sleep through one of the following events:

1. External Reset input on MCLR

2. BOR Reset if enabled.

3. POR Reset.

4. Watchdog Timer if enabled.

5. Any external interrupt.

6. Interrupts by peripherals capable of running

bit of the STATUS register is cleared. bit of the STATUS register is set.

that operate from it may continue operation in Sleep.

Timer1 continue operation in Sleep when the Timer1 clock source selected is:

•LFINTOSC

•T1CKI

• Timer1 oscillator

is selected.

SLEEP was executed (driving high, low or high-impedance).

Sleep mode.

DD or VSS externally to avoid switching

pin if enabled.

during Sleep (see individual peripheral for more information)

The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wakeup event occurred, refer to Section 6.12 “Determining

the Cause of a Reset”.

When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.

8.1.1 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP instruction:

- SLEEP instruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared bit of the STATUS register will not be set

-TO

-PD bit of the STATUS register will not be

cleared.

• If the interrupt occurs during or after the

execution of a SLEEP instruction:

- SLEEP instruction will be completely

executed

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared bit of the STATUS register will be set

-TO

-PD bit of the STATUS register will be cleared

Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test

bit. If the PD bit is set, the SLEEP instruction

the PD was executed as a NOP.

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PIC12(L)F1571/2

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN

(1)

CLKOUT

(2)

Interrupt Flag

GIE bit

(INTCON reg.)

Instruction Flow

Instruction Fetched

Instruction Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC – 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Forced NOP

PC + 2 0004h 0005h

Forced NOP

OST

(3)

PC + 2

Note 1: External Clock. High, Medium, Low mode assumed.

2: CLKOUT is shown here for timing reference. 3: TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (if available). 4: GIE = 1 assumed. In this case, after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

8.2 Low-Power Sleep Mode

This device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode.

Low-Power Sleep mode allows the user to optimize the operating current in Sleep. Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register, which puts the LDO and reference circuitry in a low-power state whenever the device is in Sleep.

8.2.1 SLEEP CURRENT VS. WAKE-UP TIME

In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize.

The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The normal mode is beneficial for applications that need to wake from Sleep quickly and frequently.

8.2.2 PERIPHERAL USAGE IN SLEEP

Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The LDO will remain in the normal power mode when those peripherals are enabled. The LowPower Sleep mode is intended for use with these peripherals:

• Brown-out Reset (BOR)

• Watchdog Timer (WDT)

• External interrupt pin/Interrupt-On-Change pins

• Timer1 (with external clock source)

The Complementary Waveform Generator (CWG) module can utilize the HFINTOSC oscillator as either a clock source or as an input source. Under certain conditions, when the HFINTOSC is selected for use with the CWG module, the HFINTOSC will remain active during Sleep. This will have a direct effect on the Sleep mode current.

Please refer to section Section 23.10 “Operation

During Sleep” for more information.

Note: The PIC12LF1571/2 does not have a

configurable Low-Power Sleep mode. PIC12LF1571/2 is an unregulated device and is always in the lowest power state when in Sleep with no wake-up time penalty. This device has a lower maximum V I/O voltage than the PIC12F1571/2. See

Section 26.0 “Electrical Specifications”

for more information.

DD and

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8.3 Register Definitions: Voltage Regulator Control

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1

— — — — — —VREGPMReserved

bit 7 bit 0

Legend:

bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit

1 = Low-Power Sleep mode enabled in Sleep

Draws lowest current in Sleep, slower wake-up.

0 = Normal power mode enabled in Sleep

Draws higher current in Sleep, faster wake-up.

bit 0 Reserved: Read as ‘1’, maintain this bit set

(2)

(1)

Note 1: PIC12F1571/2 only.

2: See Section 26.0 “Electrical Specifications”

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 IOCAF IOCAN IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 121 PIE1 TMR1GIE ADIE RCIE PIE2 PIE3 PIR1 TMR1GIF ADIF RCIF PIR2 PIR3

STATUS WDTCON

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode. Note 1: PIC12(L)F1572 only.

— — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 122 — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 121

(1)

— —C1IE— — — — — 76 — PWM3IE PWM2IE PWM1IE — — — — 77

(1)

— —C1IF— — — — — 79 — PWM3IF PWM2IF PWM1IF — — — — 80

— — —TOPD Z DC C 19 — — WDTPS<4:0> SWDTEN 89

TXIE

TXIF

(1)

— — TMR2IE TMR1IE 75

— — TMR2IF TMR1IF 78

Page

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WDTE<1:0> = 01

SWDTEN

WDTE<1:0> = 11

WDTE<1:0> = 10

23-%it Programmable

Prescaler WDT

LFINTOSC

WDTPS<4:0>

WDT

Time-out

Sleep

Rev. 10-000141A

7/30/2013

9.0 WATCHDOG TIMER (WDT)

The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes:

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256 seconds (nominal)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM

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9.1 Independent Clock Source

The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See

Section 26.0 “Electrical Specifications” for the

LFINTOSC tolerances.

9.2 WDT Operating Modes

The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in the Configuration Words. See Ta bl e 9 - 1 .

9.2.1 WDT IS ALWAYS ON

When the WDTEx bits of the Configuration Words are set to ‘11’, the WDT is always on. WDT protection is active during Sleep.

9.2.2 WDT IS OFF IN SLEEP

When the WDTEx bits of the Configuration Words are set to ‘10’, the WDT is on, except in Sleep. WDT protection is not active during Sleep.

9.2.3 WDT CONTROLLED BY SOFTWARE

When the WDTEx bits of the Configuration Words are set to ‘01’, the WDT is controlled by the SWDTEN bit of the WDTCON register.

WDT protection is unchanged by Sleep. See Table 9-1 for more details.

TABLE 9-1: WDT OPERATING MODES

WDTE<1:0> SWDTEN

11 X XActive

10 X

00 X XDisabled

Device

Mode

Awake Active

Sleep Disabled

1 XActive 0 XDisabled

WDT

Mode

9.3 Time-out Period

The WDTPS<4:0> bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is two seconds.

9.4 Clearing the WDT

The WDT is cleared when any of the following conditions occur:

•Any Reset

• CLRWDT instruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• Oscillator fails

• WDT is disabled

• Oscillator Start-up Timer (OST) is running

See Table 9-2 for more information.

9.5 Operation During Sleep

When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the device exits Sleep, the WDT is cleared again.

The WDT remains clear until the OST, if enabled, completes. See Section 5.0 “Oscillator Module” for more information on the OST.

When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO in the STATUS register are changed to indicate the event. The RWDT bit in the PCON register can also be used. See Section 3.0 “Memory Organization” for more information.

and PD bits

TABLE 9-2: WDT CLEARING CONDITIONS

Conditions WDT

WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF<3:0> bits) Unaffected

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PIC12(L)F1571/2

9.6 Register Definitions: Watchdog Control

REGISTER 9-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0

— — WDTPS<4:0> SWDTEN

bit 7 bit 0

Legend:

bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate 11111 = Reserved; results in minimum interval (1:32)

•

10011 = Reserved; results in minimum interval (1:32) 10010 = 1:8388608 (2 10001 = 1:4194304 (2 10000 = 1:2097152 (2 01111 = 1:1048576 (2 01110 = 1:524288 (2 01101 = 1:262144 (2 01100 = 1:131072 (2

) (Interval 256s nominal)

) (Interval 128s nominal)

) (Interval 64s nominal)

) (Interval 32s nominal)

) (Interval 16s nominal)

) (Interval 8s nominal)

) (Interval 4s nominal)

01011 = 1:65536 (Interval 2s nominal) (Reset value) 01010 = 1:32768 (Interval 1s nominal) 01001 = 1:16384 (Interval 512 ms nominal) 01000 = 1:8192 (Interval 256 ms nominal) 00111 = 1:4096 (Interval 128 ms nominal) 00110 = 1:2048 (Interval 64 ms nominal) 00101 = 1:1024 (Interval 32 ms nominal) 00100 = 1:512 (Interval 16 ms nominal) 00011 = 1:256 (Interval 8 ms nominal) 00010 = 1:128 (Interval 4 ms nominal) 00001 = 1:64 (Interval 2 ms nominal) 00000 = 1:32 (Interval 1 ms nominal)

bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> =

1x:

This bit is ignored. If WDTE<1:0> =

01: 1 = WDT is turned on 0 = WDT is turned off

If WDTE<1:0> =

00: This bit is ignored.

(1)

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

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TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON SPLLEN IRCF<3:0>

PCON

STATUS WDTCON — — WDTPS<4:0> SWDTEN 89 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Watchdog Timer.

STKOVF STKUNF —RWDTRMCLR RI POR BOR 66

— — —TOPD Z DC C 19

—SCS<1:0>55

TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1 13:8

7:0

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Watchdog Timer.

— — — — CLKOUTEN BOREN<1:0> — 42

CP MCLRE PWRTE WDTE<1:0> — FOSC<1:0>

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10.0 FLASH PROGRAM MEMORY CONTROL

The Flash program memory is readable and writable during normal operation over the full V Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are:

•PMCON1

•PMCON2

•PMDATL

•PMDATH

• PMADRL

•PMADRH

When accessing the program memory, the PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the PMADRH:PMADRL register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read.

The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump.

The Flash program memory can be protected in two ways; by code protection (CP Words) and write protection (WRT<1:0> bits in the Configuration Words).

Code protection (CP writing, to the Flash program memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a bulk erase to the device, clearing all Flash program memory, Configuration bits and User IDs.

Write protection prohibits self-write and erase to a portion or all of the Flash program memory as defined by the bits WRT<1:0>. Write protection does not affect a device programmers ability to read, write or erase the device.

Note 1: Code protection of the entire Flash

program memory array is enabled by clearing the CP Words.

= 0) disables access, reading and

bit in the Configuration

bit of the Configuration

DD range.

(1)

10.1 PMADRL and PMADRH Registers

The PMADRH:PMADRL register pair can address up to a maximum of 16K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register.

10.1.1 PMCON1 AND PMCON2 REGISTERS

PMCON1 is the control register for Flash program memory accesses.

Control bits, RD and WR, initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared by hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation.

The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine.

The PMCON2 register is a write-only register. Attempting to read the PMCON2 register will return all ‘0’s.

To enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the PMCON2 register. The required unlock sequence prevents inadvertent writes to the program memory write latches and Flash program memory.

10.2 Flash Program Memory Overview

It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum size that can be erased by user software.

After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the PMDATH:PMDATL register pair.

Note: If the user wants to modify only a portion of

a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. Then, new data and retained data can be written into the write latches to reprogram the row of Flash program memory. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations.

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Start

Read Operation

Select

Program or Configuration Memory

(CFGS)

Select

Word Address

(PMADRH:PMADRL)

Initiate Read operation

(RD = 1)

Instruction fetched ignored

NOP execution forced

Data read now in

PMDATH:PMDATL

Instruction fetched ignored

NOP execution forced

End

Read Operation

Rev. 10-000046A

7/30/2013

See Table 10-1 for erase row size and the number of write latches for Flash program memory.

TABLE 10-1: FLASH MEMORY

ORGANIZATION BY DEVICE

Write

Latches

(words)

Device

PIC12(L)F1571 PIC12(L)F1572

Row Erase

(words)

16 16

10.2.1 READING THE FLASH PROGRAM MEMORY

To read a program memory location, the user must:

1. Write the desired address to the

PMADRH:PMADRL register pair.

2. Clear the CFGS bit of the PMCON1 register.

3. Then, set control bit, RD, of the PMCON1 register.

Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction to be ignored. The data is available in the very next cycle in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions.

The PMDATH:PMDATL register pair will hold this value until another read or until it is written to by the user.

Note: The two instructions following a program

memory read are required to be NOPs. This prevents the user from executing a 2-cycle instruction on the next instruction after the RD bit is set.

FIGURE 10-1: FLASH PROGRAM

MEMORY READ FLOWCHART

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Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

BSF PMCON1,RD

Executed Here

INSTR(PC + 1)

Executed Here

PC + 1 PMADRH,PMADRL

PC+3

PC + 5

Flash ADDR

RD bit

PMDATH,PMDATL

PC + 3 PC + 4

INSTR (PC + 1)

INSTR(PC – 1) Executed Here

INSTR(PC + 3)

Executed Here

INSTR(PC + 4) Executed Here

Flash Data

PMDATH

PMDATL

INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)

Instruction Ignored,

Forced NOP

INSTR(PC + 2)

Executed Here

Instruction Ignored,

Forced NOP

* This code block will read 1 word of program * memory at the memory address:

PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL ; Select Bank for PMCON registers

MOVLW PROG_ADDR_LO ;

MOVWF PMADRL ; Store LSB of address

MOVLW PROG_ADDR_HI ;

MOVWF PMADRH ; Store MSB of address

BCF PMCON1,CFGS ; Do not select Configuration Space

BSF PMCON1,RD ; Initiate read

NOP ; Ignored (Figure 10-2)

MOVF PMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location

MOVF PMDATH,W ; Get MSB of word

MOVWF PROG_DATA_HI ; Store in user location

FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

EXAMPLE 10-1: FLASH PROGRAM MEMORY READ

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Start

Unlock Sequence

End

Unlock Sequence

Write 0x55 to

PMCON2

Write 0xAA to

PMCON2

Initiate

Write or Erase operation

(WR = 1)

Instruction fetched ignored

NOP execution forced

Instruction fetched ignored

NOP execution forced

Rev. 10-000047A

7/30/2013

10.2.2 FLASH MEMORY UNLOCK SEQUENCE

The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations:

• Row erase

• Load program memory write latches

• Write of program memory write latches to

program memory

• Write of program memory write latches to User

IDs

The unlock sequence consists of the following steps:

1. Write 55h to PMCON2

2. Write AAh to PMCON2

3. Set the WR bit in PMCON1

4. NOP instruction

5. NOP instruction

Once the WR bit is set, the processor will always force two NOP instructions. When an erase row or program row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. When the operation is loading the program memory write latches, the processor will always force the two NOP instructions and continue uninterrupted with the next instruction.

Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed.

FIGURE 10-3: FLASH PROGRAM

MEMORY UNLOCK SEQUENCE FLOWCHART

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Note 1: See Figure 10-3.

Start

Erase Operation

End

Erase Operation

Disable Interrupts

(GIE = 0)

Select

Program or Configuration Memory

(CFGS)

Select Erase Operation

(FREE = 1)

Select Row Address

(PMADRH:PMADRL)

Enable Write/Erase Operation

(WREN = 1)

Unlock Sequence

(See Note 1)

Re-enable Interrupts

(GIE = 1)

Disable Write/Erase Operation

(WREN = 0)

CPU stalls while

Erase operation completes

(2 ms typical)

Rev. 10-000048A

7/30/2013

10.2.3 ERASING FLASH PROGRAM MEMORY

While executing code, program memory can only be erased by rows. To erase a row:

1. Load the PMADRH:PMADRL register pair with

any address within the row to be erased.

2. Clear the CFGS bit of the PMCON1 register.

3. Set the FREE and WREN bits of the PMCON1

4. Write 55h, then AAh, to PMCON2 (Flash

programming unlock sequence).

5. Set control bit, WR, of the PMCON1 register to

begin the erase operation.

See Example 10-2. After the “BSF PMCON1,WR” instruction, the processor

requires two cycles to set up the erase operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction.

FIGURE 10-4: FLASH PROGRAM

MEMORY ERASE FLOWCHART

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; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL PMADRL MOVF ADDRL,W ; Load lower 8 bits of erase address boundary MOVWF PMADRL MOVF ADDRH,W ; Load upper 6 bits of erase address boundary MOVWF PMADRH BCF PMCON1,CFGS ; Not configuration space BSF PMCON1,FREE ; Specify an erase operation BSF PMCON1,WREN ; Enable writes

MOVLW 55h ; Start of required sequence to initiate erase MOVWF PMCON2 ; Write 55h MOVLW 0AAh ; MOVWF PMCON2 ; Write AAh BSF PMCON1,WR ; Set WR bit to begin erase NOP ; NOP instructions are forced as processor starts NOP ; row erase of program memory.

; ; The processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction

BCF PMCON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts

Required

Sequence

EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY

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10.2.4 WRITING TO FLASH PROGRAM MEMORY

Program memory is programmed using the following steps:

1. Load the address in PMADRH:PMADRL of the

row to be programmed.

2. Load each write latch with data.

3. Initiate a programming operation.

4. Repeat Steps 1 through 3 until all data is written.

Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write.

Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See

Figure 10-5 (row writes to program memory with

16 write latches) for more details.

The write latches are aligned to the Flash row address boundary defined by the upper 11 bits of PMADRH:PMADRL (PMADRH<6:0>:PMADRL<7:4>), with the lower 4 bits of PMADRL (PMADRL<3:0>) determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF.

The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO = 1. When the last word to be loaded into the write latch is ready, the LWLO bit is cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash program memory.

Note: The special unlock sequence is required

to load a write latch with data or initiate a Flash programming operation. If the unlock sequence is interrupted, writing to the latches or program memory will not be initiated.

1. Set the WREN bit of the PMCON1 register.

2. Clear the CFGS bit of the PMCON1 register.

3. Set the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is ‘1’, the write sequence will only load the write latches and will not initiate the write to Flash program memory.

4. Load the PMADRH:PMADRL register pair with the address of the location to be written.

5. Load the PMDATH:PMDATL register pair with the program memory data to be written.

6. Execute the unlock sequence (Section 10.2.2 “Flash Memory Unlock

Sequence”). The write latch is now loaded.

7. Increment the PMADRH:PMADRL register pair to point to the next location.

8. Repeat Steps 5 through 7 until all but the last write latch has been loaded.

9. Clear the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is ‘0’, the write sequence will initiate the write to Flash program memory.

10. Load the PMDATH:PMDATL register pair with the program memory data to be written.

11. Execute the unlock sequence (Section 10.2.2 “Flash Memory Unlock

Sequence”). The entire program memory latch

content is now written to Flash program memory.

Note: The program memory write latches are

reset to the blank state (0x3FFF) at the completion of every write or erase operation. As a result, it is not necessary to load all the program memory write latches. Unloaded latches will remain in the blank state.

An example of the complete write sequence is shown in

Example 10-3. The initial address is loaded into the

PMADRH:PMADRL register pair; the data is loaded using Indirect Addressing.

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6 8

1414

Write Latch #15

0Fh

1414

Program Memory Write Latches

14 14 14

PMADRH<6:0>:

PMADRL<7:4>

Flash Program Memory

Row

Row Address Decode

Addr

Write Latch #14

0Eh

Write Latch #1

01h

Write Latch #0

00h

Addr

Addr Addr

000h

000Fh

000Eh

0000h 0001h

001h 001Fh

001Eh

0010h 0011h

002h 002Fh002Eh0020h 0021h

7FEh

7FEFh7FEEh

7FE0h 7FE1h

7FFh 7FFFh7FFEh7FF0h 7FF1h

PMADRL<3:0>

800h 8009h - 801Fh8000h - 8003h

Configuration

Words

USERID0-3

8007h – 8008h8006h

DEVICE ID

Dev / Rev

reserved reserved

Configuration Memory

CFGS = 0

CFGS = 1

PMADRH PMADRL

76 07 43 0

c3 c2 c1 c0r9 r8 r7 r6 r5 r4 r3- r1 r0r2

PMDATH PMDATL

75 07 0

8004h – 8005h

411

Rev. 10-000004B

7/25/2013

FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES

PIC12(L)F1571/2

Disable Interrupts

(GIE = 0)

Start

Write Operation

Select

Program or Config. Memory

(CFGS)

Select Row Address

(PMADRH:PMADRL)

Select Write Operation

(FREE = 0)

Enable Write/Erase

Operation (WREN = 1)

Unlock Sequence

(Figure x-x)

Disable

Write/Erase Operation

(WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Write Operation

No delay when writing to

Program Memory Latches

Determine number of words

to be written into Program or

Configuration Memory. The number of words cannot exceed the number of words

per row.

(word_cnt)

Load the value to write

(PMDATH:PMDATL)

Update the word counter

(word_cnt--)

Last word to

write ?

Increment Address

(PMADRH:PMADRL++)

Unlock Sequence

(Figure x-x)

CPU stalls while Write

operation completes

(2ms typical)

Load Write Latches Only

(LWLO = 1)

Write Latches to Flash

(LWLO = 0)

Yes

Figure 10-3

FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART

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; This write routine assumes the following: ; 1. 32 bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the Least Significant bits = 00000) is loaded in ADDRH:ADDRL ; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) ;

BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL PMADRH ; Bank 3 MOVF ADDRH,W ; Load initial address MOVWF PMADRH ; MOVF ADDRL,W ; MOVWF PMADRL ; MOVLW LOW DATA_ADDR ; Load initial data address MOVWF FSR0L ; MOVLW HIGH DATA_ADDR ; Load initial data address MOVWF FSR0H ; BCF PMCON1,CFGS ; Not configuration space BSF PMCON1,WREN ; Enable writes BSF PMCON1,LWLO ; Only Load Write Latches

LOOP

MOVIW FSR0++ ; Load first data byte into lower MOVWF PMDATL ; MOVIW FSR0++ ; Load second data byte into upper MOVWF PMDATH ;

MOVF PMADRL,W ; Check if lower bits of address are '00000' XORLW 0x1F ; Check if we're on the last of 16 addresses ANDLW 0x1F ; BTFSC STATUS,Z ; Exit if last of 16 words, GOTO START_WRITE ;

MOVLW 55h ; Start of required write sequence: MOVWF PMCON2 ; Write 55h MOVLW 0AAh ; MOVWF PMCON2 ; Write AAh BSF PMCON1,WR ; Set WR bit to begin write NOP ; NOP instructions are forced as processor

; loads program memory write latches

NOP ;

INCF PMADRL,F ; Still loading latches Increment address GOTO LOOP ; Write next latches

START_WRITE

BCF PMCON1,LWLO ; No more loading latches - Actually start Flash program

; memory write

MOVLW 55h ; Start of required write sequence: MOVWF PMCON2 ; Write 55h MOVLW 0AAh ; MOVWF PMCON2 ; Write AAh BSF PMCON1,WR ; Set WR bit to begin write NOP ; NOP instructions are forced as processor writes

; all the program memory write latches simultaneously

NOP ; to program memory.

; After NOPs, the processor ; stalls until the self-write process in complete

; after write processor continues with 3rd instruction BCF PMCON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts

Required

Sequence

Required

Sequence

EXAMPLE 10-3: WRITING TO FLASH PROGRAM MEMORY

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Datasheet PIC12F1571, PIC12F1572, PIC12LF1571, PIC12LF1572 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Description:

Core Features:

Memory:

Operating Characteristics:

eXtreme Low-Power (XLP) Features:

Digital Peripherals:

Device I/O Port Features:

Analog Peripherals:

PIC12(L)F1571/2 FAMILY TYPES

Clocking Structure:

Pin Diagram – 8-Pin PDIP, SOIC, DFN, MSOP, UDFN

TABLE 1: 8-PIN ALLOCATION TABLE (PIC12(L)F1571/2)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

1.1.1 REGISTER NAMES

1.1.2 BIT NAMES

1.1.3 REGISTER AND BIT NAMING EXCEPTIONS

FIGURE 1-1: PIC12(L)F1571/2 BLOCK DIAGRAM

TABLE 1-2: PIC12(L)F1571/2 PINOUT DESCRIPTION

2.0 ENHANCED MID-RANGE CPU

FIGURE 2-1: CORE BLOCK DIAGRAM

2.1 Automatic Interrupt Context Saving

2.2 16-Level Stack with Overflow and Underflow

2.3 File Select Registers

2.4 Instruction Set

3.0 MEMORY ORGANIZATION

3.1 Program Memory Organization

3.2 High-Endurance Flash

TABLE 3-1: DEVICE SIZES AND ADDRESSES

3.2.1 READING PROGRAM MEMORY AS DATA

EXAMPLE 3-1: RETLW INSTRUCTION

3.3 Data Memory Organization

3.3.1 CORE REGISTERS

TABLE 3-2: CORE REGISTERS

REGISTER 3-1: STATUS: STATUS REGISTER

3.3.2 SPECIAL FUNCTION REGISTER

3.3.3 GENERAL PURPOSE RAM

3.3.4 COMMON RAM

3.3.5 DEVICE MEMORY MAPS

TABLE 3-3: PIC12(L)F1571 MEMORY MAP, BANK 0-7

TABLE 3-4: PIC12(L)F1572 MEMORY MAP, BANK 0-7

TABLE 3-5: PIC12(L)F1571/2 MEMORY MAP, BANK 8-23

TABLE 3-6: PIC12(L)F1571/2 MEMORY MAP, BANK 24-31

3.3.6 CORE FUNCTION REGISTERS SUMMARY

TABLE 3-9: CORE FUNCTION REGISTERS SUMMARY

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY

3.4 PCL and PCLATH

3.4.1 MODIFYING PCL

3.4.2 COMPUTED GOTO

3.4.3 COMPUTED FUNCTION CALLs

3.4.4 BRANCHING

3.5 Stack

3.5.1 ACCESSING THE STACK

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

3.5.2 OVERFLOW/UNDERFLOW RESET

3.6 Indirect Addressing

FIGURE 3-9: INDIRECT ADDRESSING

3.6.1 TRADITIONAL DATA MEMORY

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

3.6.2 LINEAR DATA MEMORY

3.6.3 PROGRAM FLASH MEMORY

4.0 DEVICE CONFIGURATION

4.1 Configuration Words

4.2 Register Definitions: Configuration Words

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

4.3 Code Protection

4.3.1 PROGRAM MEMORY PROTECTION

4.4 Write Protection

4.5 User ID