Datasheet OZ6912T, OZ6912B Datasheet (O2Micro)

Single-Slot ACPI CardBus Controller

FEATURES

• ACPI-PCI Bus Power Management Interface

Specification Rev 1.1 Compliant

• Supports OnNow LAN wakeup, OnNow Ring Indicate,

PCI CLKRUN#, PME#, and CardBus CCLKRUN#

• Compliant with PCI specification v2.2, 2000 PC Card

Standard 7.1

• Yenta™ PCI to PCMCIA CardBus Bridge register

compatible

• ExCA (Exchangeable Card Architecture) compatible

registers mappable in memory and I/O space

• Intel

• Supports PCMCIA_ATA Specification

• Supports 5V/3.3V PC Cards and 3.3V CardBus cards

• Supports single PC Card or CardBus slot with hot

• Supports multiple FIFOs for PCI/CardBus data transfer

• Supports Direct Memory Access for PC/PCI and

• Programmable interrupt protocol: PCI, PCI+ISA,

• Win’98 IRQ and PC-98/99 compliant

• Supports parallel or serial interface for socket power

• Zoomed Video Support; Zoomed video buffer enable

• D3

• 3.3Vaux Power Support

• Integrated PC 98/99 -Subsystem Vendor ID support,

• LED Activity Pins

ORDERING INFORMATION

OZ6912T - 144pin LQFP
OZ6912B - 144pin Mini-BGA

GENERAL DESCRIPTION

The OZ6912 is an ACPI and PC98/99 Logo Certified, high
performance, single slot PC Card controller with a
synchronous 32-bit bus master/target PCI interface. This
PC Card to PCI bridge host controller is compliant with the
2000 PC Card Standard. This standard incorporates the
new 32-bit CardBus while retaining the 16-bit PC Card

TM

82365SL PCIC Register Compatible

insertion and removal

PCI/Way on PC Card socket
PCI/Way, or PC/PCI interrupt signaling modes

control including devices from Micrel and TI
pins

state PME# wakeup support

cold

with auto lock bit

OZ6912

specification as defined by PCMCIA release 2.1. CardBus
is intended to support “temporal” add-in functions on PC
Cards, such as Memory cards, Network interfaces,
FAX/Modems and other wireless communication cards, etc.
The high performance and capability of the CardBus
interface will enable the new development of many new
functions and applications.

The OZ6912 CardBus controller is compliant with the latest
ACPI-PCI Bus Power Management Interface Specification.
It supports all four power states and the PME# function for
maximum power savings and ACPI compliance. Additional
compliance to OnNow Power Management includes D3
state support, paving the way for low sleep state power
consumption and minimized resume times. To allow host
software to reduce power consumption further, the OZ6912
provides a power-down mode in which internal clock
distribution and the PC Card socket clocks are stopped. An
advanced CMOS process is also used to minimize system
power consumption.

The OZ6912 single PCMCIA socket supports a mix and
match 3.3V/5V 8/16-bit PC Card R2 card or 32-bit CardBus
R3 card. The R2 card support is compatible with the Intel
82365SL PCIC controller, and the R3 card support is fully
compliant with the 2000 PC Card Standard CardBus
specification. The OZ6912 is a stand alone device, which
means that it does not require an additional buffer chip for
the PC Card socket interface. In addition, the OZ6912
supports dynamic PC Card hot insertion and removal, with
auto configuration capabilities.

The OZ6912 is fully compliant with the 33Mhz PCI Bus
specification, v2.2. It supports a master device with internal
CardBus direct data transfer. The OZ6912 implements a
FIFO data buffer architecture between the PCI bus and
CardBus socket interface to enhance data transfers to
CardBus devices. The bi-directional FIFO buffer permits the
OZ6912 to accept data from a target bus (PCI or CardBus
interface) while simultaneously transferring data. This
architecture not only speeds up data transfers but also
prevents system deadlocks.

The OZ6912 is a PCMCIA R2/CardBus controller, providing
the most advanced design flexibility for PC Cards that
interface with advanced notebook designs.

cold

06/28/00 OZ6912-SF-1.5 Page 1

Copyright 2000 by O

Micro All Rights Reserved Patent Pending

2

Functional Block Diagram

OZ6912

PCI Interface

PCI Configuration/

Function Control Registers

Power Switch

Control

PCI

Function Control

Configuration/

Registers

Power
Contro

Switch

l

PC Card
Machine

8/16-Bit

16-

PC

Bit

Machin

Card

e

PCI

PCI

Arbite

Arbiter

r

CardBu

CardBus FIFO
Data Buffering

Data

s

Buffering

CardBus
PC Card
Machine

and

Arbiter

FIFO

ACPI/ OnNow

Power Management

for PC99

Interrupt

Interrup

Subsystem

Subsyste

t

m

Powe

Power

Switc

r

Switch

h

Interface

Single PC Card Interface

PC Card
Interface

OZ6912-SF-1.5 Page 2

OZ6912

SYSTEM BLOCK DIAGRAM

The following diagram is a typical system block diagram utilizing the OZ6912 ACPI CardBus controller with other related
chipsets.

CPU

PCI Bus

VGA

AGP

OZ6912

CardBus

Controller

PC

Card

Memory

North Bridge

South Bridge

ISA

OZ6912-SF-1.5 Page 3

PIN DIAGRAM - 144 Pin LQFP

D10/CAD31

D1/CAD29

D9/CAD30

D8/CAD28

D2/RFU

WP/IOIS16/CCLKRUN#

CD2/CCD2#

CORE_VCC

D0/CAD27

OZ6912

BVD1/STSCHG#/RI#/CSTSCHG

BVD2/SPKR#/LED/CAUDIO

RDY/IREQ#/CINT#

WAIT#/CSERR#

A2/CAD24

A0/CAD26

A1/CAD25

VS1/CVS1

GND

INPACK#/CREQ#

REG#/CCBE3#

SOCKET_VCC

A3/CAD23

CORE_VCC

RESET/CRST#

A25/CAD18

A4/CAD22

VS2/CVS2

A6/CAD20

A5/CAD21

A7/CAD18

A23/CFRAME#

A22/CTRDY#

A15/CIRDY#

A12/CCBE2#

A24/CAD17

GND

REQ#
GNT#

AD31
AD30
AD29

GND

AD28

AD27
AD26
AD25
AD24

C/BE3#

IDSEL

CORE_VCC

AD23
AD22
AD21

PCI_VCC

AD20

RST#

PCI_CLK

GND
AD19
AD18
AD17
AD16

C/BE2#

FRAME#

IRDY#

PCI_VCC

TRDY#

DEVSEL#

STOP#

PERR#

SERR#

PAR

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

4

4

4

4

4

3

3

3

3

3

3

3

3

3

3

2

2

2

2

2

2

2

2

2

2

1

1
2

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3
3
4

5
6
7
8
9
10

11
12
13
14
15
16

17
18
19
20
21
22
23
24
25
26
27
28

29
30
31
32
33
34
35
36

37383940414243444546474849505152535455565758596061626364656667686970717

O2Micro, Inc.

OZ6912

2

1

1

0

9

8

1

1

1

1

1

7

6

5

4

1

1

1

1

1

1

1
3

108

1

1

0

107

0

2

1

9

106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

2

A16/CCLK
A21/CDEVSEL#
WE#/CGNT#
A20/CSTOP#
A14/CPERR#
A19/CBLOCK#

CORE_VCC
A13/CPAR
A18/RFU
A8/CCBE1#
A17/CAD16
A9/CAD14

IOW#/CAD15
A11/CAD12
GND

IORD#/CAD13
OE#/CAD11
CE2#/CAD10
SOCKET_VCC

A10/CAD9

CE1#/CCBE0#
D15/CAD8
CORE_VCC

D7/CAD7
D14/RFU
D6/CAD5
D13/CAD6
D5/CAD3
D12/CAD4
D4/CAD1

GND

D11/CAD2
D3/CAD0

CD1/CCD1#

VCCD1#/SCLK

VCCD0#/SDATA

VPPD1

MF0

C/BE1#

AD15

AD14

AD13

PCI_VCC

GND

AD12

AD11

C/BE0#

AD10

AD9

PCI_VCC

AD8

AD7

AD6

AD5

AD4

AD2

AD0

AD3

AD1

MF1

GND

RI_OUT/PME#

MF3

MF2

SPKR_OUT#

MF4

GLOBAL_RST#

AUX_VCC

VPPD0/SLATCH

MF5

MF6

SUSPEND#

OZ6912-SF-1.5 Page 4

Pin List

Bold Text = Normal Default Pin Name

PCI Bus Interface Pins

Pin Name Description

AD[31:0]

C/BE[3:0]#

FRAME#

IRDY#

TRDY#

STOP#

IDSEL

DEVSEL#

PERR#

SERR#

PCI Bus Address/Data: These pins connect to
PCI bus signals AD[31:0]. A Bus transaction
consists of an address phase followed by one or
more data phases.

PCI Bus Command / Byte Enable: The
command signaling and byte enables are
multiplexed on the same pins. During the address
phase of a transaction, C/BE [3:0] # are interpreted
as the bus commands. During the data phase,
C/BE[3:0]# are interpreted as byte enables. The
byte enables are to be valid for the entirety of
each data phase, and they indicat e which bytes in
the 32-bit data path are to carry m eaningful data
for the current data phase.
Cycle Frame: This signal indicates to the OZ6912
that a bus transaction is beginning. While
FRAME# is asserted, data transfers continue.
When FRAME# is de-asserted, the trans action is
in its final phase.
Initiator Ready: This signal indicates the initiat i ng

agent’s ability to com plete the current data phas e
of the transaction. I RDY# is used in conjunction
with TRDY#.

Target Ready: This signal indicates target
Agent's the OZ6912’s ability to complete the
current data phase of the t ransaction. TRDY# is
used in conjunction with IRDY#.

Stop: This signal indicates the current target is
requesting the master to stop the current
transaction.

Initialization Device Sele c t : This input is used as
chip select during configuration read and write
transactions. This is a point-to-point signal.
IDSEL can be used as a chip select during
configuration read and write transacti ons.

Device Select: This signal i s driven active LOW
when the PCI address is recognized as
supported, thereby acting as the target for the
current PCI cycle. The Target must respond
before timeout occurs or t he cycle will terminate.

Parity Error: The output is driven active LOW
when a data parity error is detected during a write
phase.

System Error: This output is driven active LOW
to indicate an address parit y error.

OZ6912

Pin Number

LQFP BGA

3-5, 7-11, 15­17, 19, 23-26,
38-41, 43, 45­47, 49, 51-57

12, 27, 37, 48 E1, J3, N1, N5 TTL I/O PCI_Vcc PCI

28 J4 TTL I/O PCI_Vcc PCI

29 K1 TTL I/O PCI_Vcc PCI

31 K3 TTL I/O PCI_Vcc PCI

33 L2 TTL I/O PCI_Vcc PCI

13 F4 TTL I PCI_Vcc PCI

32 L1 TTL I/O PCI_Vcc PCI

34 L3 - TO PCI_Vcc PCI

35 M1 - TO PCI_Vcc PCI

C2, C1, D4, D2,
D1, E4, E3, E2,
F2, F1, G2, G3,
H3, H4, J1, J2,
N2, M3, N3,
K4, M4, K5, L5,
M5, K6, M6,
N6, M7, N7, L7,
K7, N8

Input Type

TTL I/O PCI_Vcc PCI

Power

Rail

Drive

Spec

Spec

Spec

Spec

Spec

Spec

Spec

Spec

Spec

Spec

OZ6912-SF-1.5 Page 5

Pin Name Description

PAR

PCI_CLK

RST#

GNT#

REQ#

Parity: This pin generates PCI parity and ensures
even parity across AD[31:0] and C/BE[3:0]#.
During the address phase, PAR is valid after one
clock. W ith data phases , PAR is s table one clock
after a write or read transaction.

PCI Clock: This input provides timing for all
transactions on the PCI bus to and from the
OZ6912. All PCI bus signals, except RST#, are
sampled and driven on the rising edge of
PCI_CLK. This input can be operated at
frequencies from 0 to 33 MHz.

Device Reset: This input is used t o initialize all
registers and internal logic to their reset states
and place most OZ6912 pins in a HIGH­impedance state.

Grant: This signal indicates that access to the bus
has been granted.

Request: This signal indicates to the arbiter that
the OZ6912 requests use of the bus.

Power Control and General Interface Pins

Pin Name Description

RI_OUT/
PME#

SPKR_OUT#

MF[6:0]

SUSPEND#

G_RST#

Ring Indicate Out: This pin is Ring Indicate
when the following occurs while O
B Register (index 2Eh) bit 7 is set to 1:

1) Power Control (Index+02h) bit 7 set to 1

2) Interrupt and General Control (Index+03h)
bit 7 set to 1

3) PCI O

Power Management Event: A power
management event is t he process by which the
OZ6912 can request a change of its power
consumption state. Usually, a PME occurs
during a request to change from a power saving
state to the fully operational state.
Speaker Output: This output can be used to
support PC Card audio output. See O2 Mode E
Register (Index + 3Eh), bit 1.
Multifunction Terminal [6:0]: See PCI
Multifunction MUX Register (Offset : 08h).

Suspend: This signal is used to protect the
internal registers from clearing when the PCI
RST# signal is asserted. When low, this s i gnal i s
used to mask t he PCI RESET during suspend.
This pin can be used during suspend to prevent
controller reset.
Global_Reset#: This signal can be connected to
either PCI reset or ACPI reset depending on
system implementation. If the D3 cold state is
implemented, this s ignal shoul d be connected t o
the ACPI reset, otherwise, connect to P CI reset.
This signal can reset the P ME content under the
D3 cold state if AUX_VCC is provi ded.

Micro Control 2 (Offset: D4h) bit X =

2

0

Mode Control

2

OZ6912

Pin Number

LQFP BGA

36 M2 TTL I/O PCI_Vcc PCI

21 H1 - I PCI_Vcc -

20 G4 - I AUX_Vcc -

2 B1 TTL I PCI_Vcc PCI

1 A1 - TO PCI_Vcc PCI

Pin Number

LQFP BGA

59 L8 - TO Aux_Vcc 4mA

62 M9 TTL I/O Aux_Vcc 6mA

60-61, 64-65,

67-69

70 L11 TTL I Aux_Vcc -

66 M10 TTL I Aux_Vcc -

K8, N9, K9,

N10, L10,
N11, M11

Input Type

Input Type

TTL I/O Aux_Vcc 6mA

Power

Rail

Power

Rail

Drive

Spec

Spec

Spec

Drive

OZ6912-SF-1.5 Page 6

Pin Name Description

VPPD0/
SLATCH

VPPD1
VCCD0#/

SDATA

VCCD1#/
SCLK

VPPD0: This power input is used with parallel
power control chip

SLATCH: This output controls a serial interface
power control chip.
VPPD1: This power input is used a parallel
power interface chip.
VCCD0#: Rail power inputs for use with a
parallel power control chip.

Serial Data: This pin serves as output DATA pin
when used with a serial interface of serial power
control chip.
VCCD1#: Rail power inputs for use with a
parallel power control chip.

Serial Clock: The input is us ed as a reference
clock (10-100kHz, usually 32kHz) to control a
serial power control chips. By setting PCI

Micro Control 2 register (Offset : D4h) bit 13 t o

O

2

1, SCLK is an output. Defaul t is input mode.

OZ6912

Pin Number

LQFP BGA

71 N12 TTL I/O Aux_Vcc 6mA

72 M12 - TO Aux_Vcc 6mA
73 N13 TTL I/O Aux_Vcc 6mA

74 M13 TTL I/O Aux_Vcc 6mA

Input Type

Power

Rail

Drive

OZ6912-SF-1.5 Page 7

PC Card Socket Interface Pins

Refer to PCI Bus Interface pin descriptions for details on CardBus function.

EXCEPTIONS: CCD[2:1]#, CAUDIO, CSTSCHG, CVS[2:1]

Pin Name Description

REG#/
CCBE3#

A[25:24]/
CAD[19, 17]

A23/
CFRAME#

A22/
CTRDY#

A21/
CDEVSEL#

A20/
CSTOP#

A19/
CBLOCK#

A18/
RFU

A17/
CAD16

A16/
CCLK#

Register Access: During PC Card memory cycles,
this output c hooses between Attri bute and Comm on
Memory. During I/O cycles for non-DMA transfers,
this signal is active (low). During ATA mode, this
signal is always inactive. For DMA cycles on the
OZ6912 to a DMA-capable card, REG# becomes
DACK to the PCMCIA card.

CardBus Command Byte Enable: In CardBus
mode, this pin is the CCBE3#.

Address: PC Card socket address 25:24 outputs.
CardBus Address/Data: CardBus mode, these pins

are the CAD bits 19 and 17.

Address: PC Card socket address 23 output.
CardBus Frame: In CardBus mode, this pin is the

CFRAME# signal.

Address: PC Card socket address 22 output.
CardBus Target Ready: In CardBus mode, this pin

is the CTRDY# signal.

Address: PC Card socket address 21 output.
CardBus Device Select: In CardBus mode, t his pin

is the CDEVSEL# signal.

Address: PC Card socket address 20 output.
CardBus Stop: In CardBus mode, this pin is the

CSTOP# signal.

Address: PC Card socket address 19 output.
CardBus Lock: In CardBus mode, this si gnal is the

CBLOCK# signal used for locked transactions.

Address: PC Card socket address 18 output.
Reserved: In CardBus mode, this pin is res erved for

future use.

Address: PC Card socket address 17 output.
CardBus Address/Data: In CardBus mode, this pi n

is the CAD bit 16.

Address: PC Card socket address 16 output.
CardBus Clock: In CardBus mode, t h i s pin supplies

the clock to the ins erted card.

Pin Number

LQFP BGA

125 B7 TTL I/O Socket

116, 113 A10, D10 TTL I/O Socket

111 B11 TTL I/O Socket

109 A13 TTL I/O-

107 B13 TTL I/O-

105 C12 TTL I/O-

103 D11 TTL I/O-

100 E10 TTL TO Socket

98 E12 TTL I/O Socket

108 B12 TTL I/O Socket

OZ6912

Input Type

PU

PU

PU

PU

Power

Rail

_Vcc

_Vcc

_Vcc

Socket
_Vcc

Socket
_Vcc

Socket
_Vcc

Socket
_Vcc

_Vcc

_Vcc

_Vcc

Drive

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

OZ6912-SF-1.5 Page 8

Pin Name Description

A15/
CIRDY#

A14/
CPERR#

A13/
CPAR

A12/
CCBE2#

A[11:9]/
CAD
[12,9,14]

A8/
CCBE1#

A[7:0]/
CAD[18]
[20:26]

D15/
CAD8

D14/
RFU

D[13:3]/
CAD[6, 4, 2,
31, 30, 28, 7,
5, 3, 1, 0]

D2/
RFU

D[1:0]/
CAD[29,27]

OE#/
CAD11

WE#/
CGNT#

Address: PC Card socket address 15 output.
CardBus Initiator Ready: In CardBus mode, this

pin is the CIRDY# signal.

Address: PC Card socket address 14 output.
CardBus Parity Error: CardBus mode, this pin is

the CPERR# signal.

Address: PC Card socket address 13 output.
CardBus Parity: In CardBus mode, this pin is the

CPAR signal.

Address: PC Card socket address 12 output.
CardBus Command/Byte Enable: In CardBus

mode, this pin is the CCBE2# signal.

Address: PC Card socket address 11:9 output.
CardBus Address/Data: In CardBus mode, these

pins are the CAD bits 12, 9 and 14.

Address: PC Card socket address 8 output.
CardBus Command/Byte Enable: In CardBus

mode, this pin is the CCBE1# signal.

Address: PC Card socket address 7:0 outputs .
CardBus Address/Data: In CardBus mode, these

pins are the CAD bits 18 and 20:26.

Data: PC Card socket I/O data bit 15.
CardBus Address/Data: In CardBus mode, this pin

is the CAD bit 8.

Data: PC Card socket I/O data bit 14.
Reserved: In CardBus mode, this pin is res erved for

future use.

Data: PC Card socket I /O data bits 13:3.
CardBus Address/Data: In CardBus mode, this pin

is the CAD bit 6 4, 2, 31, 30, 28, 7, 5, 3, 1, and 0,
respectively.

Data: PC Card socket I/O data bit 2.
Reserved: In CardBus mode, this pin is res erved for

future use.

Data: PC Card socket I/O data bits 1:0.
CardBus Address/Data: In CardBus mode, these

pins are the CAD bits 29 and 27, res pectively.
Output Enable: This output goes active (low) to
indicate a memory read from the OZ6912 to PC
Card.

CardBus Address/Data: In CardBus mode, this pin
is the CAD bit 11.
Write Enable: This output goes active (low) to
indicate a memory write from the OZ6912 to the P C
Card socket.

CardBus Grant: In CardBus mode, this pin is the
CGNT# signal.

OZ6912

PU

PU

Power

Rail

Socket
_Vcc

Socket
_Vcc

_Vcc

_Vcc

_Vcc

_Vcc

_Vcc

_Vcc

_Vcc

_Vcc

_Vcc

_Vcc

_Vcc

_Vcc

Pin Number

LQFP BGA

110 A12 TTL I/O-

104 C13 TTL I/O-

101 D13 TTL I/O Socket

112 A11 TTL I/O Socket

95, 89, 97 F11, G12,

99 E11 TTL I/O Socket

115, 118,
120, 121,
124, 127,
128, 129

87 H12 TTL I/O Socket

84 J13 TTL I/O Socket

82, 80, 77,

144, 142,

140, 85, 83,

81, 79, 76

143 A2 TTL I/O Socket

141, 139 B3, C4 TTL I/O Socket

92 G10 TTL I/O Socket

106 C11 TTL TO Socket

E13

B10, C9,

A9, D8, A8,

C7, D7, A6

J11, K13,

K10, B2,

C3, A3,
H10, J12,
J10, K12,

L13

Input Type

TTL I/O Socket

TTL I/O Socket

TTL I/O Socket

Drive

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

OZ6912-SF-1.5 Page 9

Pin Name Description

IORD#/
CAD13

IOW#/
CAD15

WP/
IOIS16#/
CCLKRUN#

INPACK#/
CREQ#

RDY/IREQ#/
CINT#

WAIT#/
CSERR#

CD[2:1]/
CCD[2:1]#

CE2#/
CAD10

CE1#/
CCBE0#

I/O Read: This output goes active (low) for I/O
reads from the OZ6912 to the socket.

CardBus Address/Data: In CardBus mode, this
pin is the CAD bit 13.
I/O Write: This output goes active (low) for I/O
writes from the OZ6912 to the soc ket.

CardBus Address/Data: In CardBus mode, this
pin is the CAD bit 15.
Write Protect / I/O is 16-Bit: In Memory mode,
this input is indicates the status of the write
protect switch on the PC Card. I n I/O mode, this
input indicates the si ze of current dat a transf er on
the PC Card.

CardBus Clock Run: In CardBus m ode, this pin
is the CCLKRUN# signal, which starts and stops
the CardBus CCLK. To enable the CLKRUN#
signal, ExCA register 3Bh bit[3:2] must be
enabled.
Input Acknowledge: The INPACK# function is
not applicable in PCI bus environm ents. This pin
is provided for Legacy card compatibility.

CardBus Request: In CardBus m ode, this pin is
the CREQ# signal.
Ready / Interrupt Request: In Memory mode,
this input indi cates that the card i s ready or busy.
In I/O mode, t his input indicates a card interrupt
request.

CardBus Interrupt: In CardBus mode, this pi n is
the CINT# signal. This signal is active-low and
level-sensitive.
Wait: This pin is driven by the PC Card to delay
completion of the c urrent cycle.

CardBus System Error: In CardBus mode, thi s
pin is the CSERR# signal.
Card Detect: These inputs indicate a card is
present in the socket. They are internally pulled
high to AUX_VCC.

CardBus Card Detect: In CardBus mode, these
inputs are used with CV S[2:1] to detec t presence
and type of card.
Card Enable 2: This pin is driven low to control
byte/word card access. CE2# enables odd­numbered address bytes.

CardBus Address/Data: In CardBus mode, this
pin is the CAD bit 10.
Card Enable 1: This pin is driven low to control
byte/word card access. CE1# enables even­numbered address bytes. W hen configured for 8­bit cards, CE1# is active and A0 is used to
indicate access of odd- or even-numbered bytes.

CardBus Command/Byte Enable: In CardBus
mode, this pin is the CCBEO# signal.

OZ6912

Pin Number

LQFP BGA

93 F13 TTL I/O Socket

96 F10 TTL I/O Socket

136 D5 TTL I/O-PU Socket

123 B8 - I-PU Socket

132 D6 - I-PU Socket

133 A5 TTL I-PU Socket

137, 75 A4, L12 TTL I-PU-

91 G11 TTL I/O Socket

88 H13 TTL I/O Socket

Input Type

Schmitt

Power

Rail

_Vcc

_Vcc

_Vcc

_Vcc

_Vcc

_Vcc

Aux_Vcc CardBus

_Vcc

_Vcc

Drive

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

CardBus
spec.

spec.

CardBus
spec.

CardBus
spec.

OZ6912-SF-1.5 Page 10

Pin Name Description

RESET/
CRST#

BVD2/SPKR#/
LED/CAUDIO

BVD1/
STSCHG#/RI#
/CSTSCHG

VS[2:1]/
CVS[2:1]

SOCKET_VCC

Reset: This active high output res ets the card.
To prevent reset glitches, this signal is high­impedance unless a card is seated in the
socket, card power is applied, and the card’s
interface signals are enabled.

CardBus Reset: In CardBus mode, t his pin is
the CRST# output.
Battery Voltage Detect 2 / Speaker / LED: In
Memory mode, this input serves as the BVD2
(battery warning status) input. In I/ O mode, this
input can be configured as the card’s SPKR#
audio input or drive-active LED input.

CardBus Audio: In CardBus mode, this pin is
the CAUDIO input.

Battery Voltage Detect 1 / Status Change /
Ring Indicate: In Memory mode, this is the

BVD1 (battery-dead st atus) input. In I /O mode,
this is the STSCHG# input indicating that the
card’s internal status has changed, or the ring
indicates input for wakeup-on-ring system
power management support. See bit 7 of the
Interrupt and General Control register (03h).

CardBus Status Change: In CardBus mode,
this pin is the CSTSCHG. Thi s pin can be used
to generate PME#.
Voltage Sense: These pins are used in
conjunction with CD[2:1] to determ ine the type
and voltage of a card. Thes e pins are int ernally
pulled high to AUX_VCC. See Table 1.

CardBus Voltage Sense: In CardBus mode,
these pins are the CVS[2: 1] pi ns.
Socket Power: These pins are the power rail
input for the socket interface control logic.
These pins can be 0, 3. 3, or 5 V,. The socket
interface outputs will operate at the voltage
applied to these pins.

OZ6912

Pin Number

LQFP BGA

119 B9 TTL TO Socket

134 B5 - I-PU Socket

135 C5 - I-PU Socket

117, 131 D9, C6 TTL I/O-PU Aux_Vcc CardBus

90, 126 G13, A7 - PWR - -

Input Type

Power

Rail

_Vcc

_Vcc

_Vcc

Drive

CardBus
spec.

-

-

spec.

OZ6912-SF-1.5 Page 11

OZ6912

Power, Ground, and Reserved Pins

Pin Name Description

AUX_VCC

CORE_VCC

PCI_VCC

GND

Auxiliary VCC: This pin is connected to the
system’s 3.3/5V power supply. For the device
to 5V tolerant, connect t o +5V power.
CORE_VCC: This pin provides power to the
core circuitry of the OZ6912. It must be
connected to a 3.3V power supply.

PCI Bus VCC: These pins can be connected to
either a 3.3V or5V power supply. The P CI bus
interface will operate at the voltage applied to
these pins, i ndependent of the voltage applied
to other OZ6912 pin groups.

System Ground

Pin Number

LQFP BGA

63 L9 - PWR - -

14, 86, 102,

122, 138

18, 30, 44,

50

6, 22, 42,

58, 78, 94,

114, 130

F3, H11,

D12, C8

B4

G1, K2,

N4, L6

D3, H2,
L4, M8,

K11, F12,

C10, B6

Input Type

- PWR - -

- PWR - -

- GND - -

Legend

I/O Type Description Power Rail Source of Output’s Power

I Input Pin 1 AUX_VCC: outputs powered from AUX_VCC
I-PU Input pin with internal pull-up 2 SOCKET_VCC: outputs powered from the socket
I-PU Schmitt Input pin with internal pull-up and S chmitt trigger
O Output 4 CORE_VCC: outputs powered from the CORE_VCC
OD Open-drain
TO Tri-state output
TO-PU Tri-state output with internal pull-up
OD-PU Open-drain output with internal pull-up
PWR Power pin

3 PCI_VCC: outputs powered from PCI bus power supply

Power

Rail

Drive

OZ6912-SF-1.5 Page 12

Package Information - 144 Pin LQFP

Hd

D

He

E

A2A

OZ6912

1

Y

GAGE

PLANE

eb

0.25

L

0.08(0.003)

1

L

M

SYMBOL

A1
A2

b

c
D
E

e

Hd
He

L

L1

Y

c

MILLIMETER INCH

MIN. NOM. MAX. MIN. NOM. MAX.

0.05 0.10 0.15 0.002 0.004 0.006

1.35 1.40 1.45 0.053 0.055 0.057

0.17 0.22 0.27 0.007 0.009 0.011

0.090 0.200 0.004 0.008

20.00 0.787

20.00 0.787

0.50 0.020

22.00 0.866

22.00 0.866

0.45 0.60 0.75 0.018 0.024 0.030

1.00 0.039

0.08 0.003

0707

OZ6912-SF-1.5 Page 13

144 Pin Mini - BGA

OZ6912

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. "e" REPRESENTS THE SOLDER BALL GRID PITCH.

3. "N" REPRESENTS THE MAXIMUM NUMBER OF SOLDER BALLS FOR MATRIX SIZE
M1 AND M2.

4. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER AFTER

REFLOW AND PARALLEL TO PRIMARY DATUM Z, THE ORIGINAL SOLDER BALL
DIAMETER IS 0.45 mm.

5. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.

6. A1 CORNER MUST BE IDENTIFIED BY INK MARK, METALLIZED MARKINGS,

IDENTATION OR OTHER FEATURE OF PACKAGE BODY, LID OR INTEGRAL
HEATSLUG, ON THE TOP SURFACE OF THE PACKAGE.

7. SOLDER BALL DEPOPULATION IS ALLOWED. DEPOPULATION IS THE OMISSION OF
BALLS FROM A FULL MATRIX (M1 OR M2).

8. BALL PAD A1 CORNER INDICATOR (NC) SOLDER BALL

OZ6912-SF-1.5 Page 14