Datasheet OZ6833T, OZ6833B Datasheet (O2Micro)

FEATURES

• Single-chip CardBus host adapter

• Supports 2 PCMCIA 1.0 and JEIDA 4.2 R2 cards or 2

CardBus cards

• ACPI-PCI Bus Power Management Interface
Specification Rev1.0 Compliant

• Supports OnNow LAN wakeup, OnNow Ring Indicate,
PCI CLKRUN#, PME#, and CardBus CCLKRUN#

• Compliant with PCI specification v2.1S, 1998 PC Card
Standard 7.0

• Yenta PCI to PCMCIA CardBus Bridge register
compatible

• ExCA (Exchangeable Card Architecture) compatible
registers map-able in memory and I/O space

• Intel 82365SL PCIC Register Compatible

• Supports PCMCIA_ATA Specification

• Supports 5V/3.3V PC Cards and 3.3V CardBus cards

• Supports two PC Card or CardBus slots with hot

insertion and removal

• Supports multiple FIFOs for PCI/CardBus data transfer

• Supports Direct Memory Access for PC/PCI and

PC/Way on PC Card socket

• Programmable interrupt protocol: PCI, PCI+ISA,
PCI/Way, or PC/PCI interrupt signaling modes

• Win’98 IRQ and PC-97/98 compliant

• Parallel or Serial interface for socket power control

devices (TI or Micrel)

• Zoomed Video Support

• Integrated PC 98 – Subsystem Vendor ID support, with

auto lock bit

• LED Activity Pins

ORDERING INFORMATION

OZ6833T – 208 pin TQFP
OZ6833B – 208 pin Mini-BGA

GENERAL DESCRIPTION

The OZ6833 ACPI CardBus controller provides a high
performance, synchronous, 32-bit, bus master/target
interface between computers and plug in PC Cards.
CardBus is the new 32-bit interface standard of Personal
Computer Memory Card International Association,
PCMCIA. The CardBus provides 32-bit interface with
multiplexed address and data lines. This will allow the
addition of high performance computer system
enhancements and new functions in a user-friendly way.
Further, the expansion capability of the CardBus will
provide benefits to the end user. CardBus is intended to

OZ6833

ACPI CardBus Controller

support “temporal” add-in functions on PC Cards, such as
Memory cards, Network interfaces, FAX/Modems and other
wireless communication cards, etc. The high performance
and capability of the CardBus interface will enable further
development of many new functions and applications.

The OZ6833 CardBus controller is a 33MHz PCI compliant
master/target device that attaches to the PCI bus and
manages two PC Card sockets. The PC Card sockets
support both 3.3V / 5V versions of 8/16-bit PCMCIA R2
card or 32-bit CardBus card. R2 card support is compatible
with the Intel 82365SL PCIC controller. CardBus card
support is fully compatible with the 1998 PC Card Standard
V7.0. The OZ6833 is a stand alone device. It does not
require an additional buffer chip for the two PC Card socket
interface. The OZ6833 is implemented with a complex
multiple FIFO data buffer for the PCI and CardBus interface
to provide better PCI/CardBus access.

The FIFO buffers allow the bridge to accept data from a
target bus while moving data to it, facilitating deadlock
prevention. In addition, the OZ6833 is designed with
dynamic PC Card hot insertion and removal and auto
configuration capabilities.

The OZ6833 ACPI CardBus Controller provides the power
saving mixed 5V / 3.3V capability. An advance CMOS
process minimizes system power consumption. The dev ice
also provides a power-down mode, allowing host software
to reduce power consumption further while stopping
internal clock distribution and the clocks on PC Card
sockets. The OZ6833 is not only a CardBus bridge, but
also a socket controller. The OZ6833 supports two master
devices and arbitrates the priority of each. Further, it
supports inter CardBus direct data transfer. The register set
in the OZ6833 is the superset of the OZ67xx register set,
assuring full compatibility with existing socket/card-services
software and PC-card applications. The OZ6833 provides
the most advanced design flexibility for the PC Card
interface in notebook computer design.

To enhance the performance between the PCI bus and any
CardBus card, two buffers (each composed of 16 double
words) are added on both sides going from PCI to CardBus
or the other way around. By implementing these buffers,
the OZ6833 will not refuse data from a target bus while
moving data and preventing deadlock situations.

In order to allow maximum flexibility for system designers,
the CINT# of the PC card 32-bit may be programmed to
steer to either INTA# or INTB# of the PCI bus. Further, the
interrupts may be programmed to route through the bridge
to either PCI INT lines or IRQ interrupts on the ISA bus.

04/25/00 OZ6833-DS-1.55 Page 1
Copyright 1999 by O2Micro All Rights Reserved

FUNCTIONAL BLOCK DIAGRAM

PCI Interface

OZ6833

PCI Configuration/

Function Control Registers

Power Switch

Control

PCI

Function Control

Configuration/

Registers

Power
Contro

Switch

l

PC Card
Machine

EXCA

8/16-Bit

16-

PC

Bit

Machin

Card

State

e

PCI

PCI

Arbite

Arbiter

r

CardBus FIFO

CardBu

Data Buffering

s

CardBus
PC Card

State

Machine

and

Arbiter

FIFO

ACPI/ OnNow

Power Management

for PC99

Interrupt

Subsystem

Interrup

t

EXCA

8/16 Bit

PC Card

State

Machine

CardBus
PC Card

State

Machine

and

Arbiter

Powe

Power

Switc

r

Switch

h

Interface

Socket A PC Card Interface

PC Card
Interface

Socket B PC Card Interface

OZ6833-DS-1.55 Page 2

OZ6833

SYSTEM BLOCK DIAGRAM

The following diagram is a typical system block diagram utilizing the OZ6833 ACPI CardBus controller with other related
chipsets.

CPU

PCI Bus

VGA

AGP

OZ6833

CardBus

Controller

PC

Card

PC

Card

Memory

North Bridge

South Bridge

ISA

OZ6833-DS-1.55 Page 3

PIN DIAGRAM - 208 PIN TQFP

OZ6833

IRQ7/SIN#/B_VPP_PGM

B_RESET/CRESET#

B_WP/CCLKRUN#

IRQ14/CLKRUN#

IRQ5/SERIRQ

RST#

2

2

2

2

0

0

0

P

C

K

C

I

L

_

N

P

C

G

I

_

#

T

P

C

I

_

R

#

E

Q

A

D

3

1

A

0

D

3

P

C

I

_

V

C

C

A

D

2

9

A

8

D

2

A

7

D

2

A

D

2

6

A

5

D

2

4

A

D

2

C

#

/

B

E

3

R

C

E

_

O

N

D

G

I

D

S

E

L

A

D

3

2

A

2

D

2

A

1

D

2

A

D

0

2

A

9

D

1

P

C

I

V

C

C

_

A

D

8

1

7

A

D

1

6

A

D

1

C

#

/

B

E

2

R

C

E

O

N

G

D

_

R

F

A

E

#

M
G

R

C

E

_

O

N

D

I

R

D

Y

#

R

T

D

Y

#

D

E

V

S

E

L

#

P

O

S

T

#

P

E

R

R

#

S

E

R

R

#

P

A

R

C

/

B

#

E

1

P

C

V

C

I

C

_

5

A

D

1

A

D

1

4

A

3

D

1

2

A

D

1

A

D

1

1

A

0

D

1

R

C

O

N

D

G

E

_

A

D

9

A

D

8

C

/

B

E

#

0

A

D

7

A

D

6

P

C

I

_

V

C

C

A

D

5

A

D

4

0

1

7

6

5

8

2
3
4
5
6
7
8
9

0

1
1

1
2

1

3

1
1

4
5

1

6

1

7

1

8

1

9

1

0

2

1

2

2

2

3

2

4

2

5

2

6

2

7

2

8

2

9

2

0

3

1

3

2

3

3

3

4

3

5

3

6

3

7

3

8

3

9

3

0

4

1

4

2

4
4

3
4

4

5

4
4

6
7

4

8

4
4

9

0

5

1

5
5

2

5

5

5

5

3

6

5

4

B_SOCKET_VCC

B_CD2#/CCD2#

IRQ4/INTB#

2
0
4

5

5

7

8

B_D10/CAD31

B_D2/RFU

INTA#

2

2

2

2

1
0
3

5
9

1

0

0

0

9

9

2

1

0

9

8

6

6

6

6

6

0

1

2

3

4

IRQ11/SKTB_ACTV

B_BVD1/CSTCHG

B_D0/CAD27

B_D8/CAD28

B_D1/CAD29

B_D9/CAD30

1

1

9

9

7

6

6

6

6

5

B_A0/CAD26

1

1

1

1

1

9

9

9

9

9

5

4

3

2

1

6

6

6

7

7

8

9

0

B_INPACK#/CREQ#

B_REG#/CC_BE3#

B_BVD2/CAUDIO

B_A1/CAD25

1

1
9

8

0

9

7

7
2

1

B_WAIT#/CSERR#

B_A2/CAD224

B_A3/CAD23

1

1

1

1

1

8

8

8

8

8

8

7

6

5

4

O

M

i

2

O

Z

7

7

7

7

7

3

4

6

5

7

8

B_VS2/CVS2

B_A6/CAD20

B_A5/CAD21

B_A4/CAD22

CORE_VCC

GND

1

1

1

1

1

1
8
3

r

c

6

7

7
9

1

8

8

8

7

7

2

o

8

8
0

7

1

0

9

8

7

,

I

.

c

n

3

3

8

8

8

8

8

1

2

3

4

5

B_A23/CFRAME#

B_A12/CCBE2#

B_A24/CAD17

B_A25/CAD19

B_A7/CAD18

1

1

1

1

1

7

7

7

7

7

6

5

4

3

2

8

8

8

8

9

6

7

8

9

0

B_RDY_IREQ#/CINT#

B_A21/CDEVSEL#

B_A20/CSTOP#

B_A22/CTRDY#

B_A15/CIRDY#

1

1

7

7

0

1

9
1

B_WE#/CGNT#

B_A16/CCLK

1

1

1

1

1

6

6

6

6

6

9

8

7

6

5

9

9

9

9

9

4

2

3

6

5

B_SOCKET_VCC

B_A19/CBLOCK#

B_A14/CPERR#

IRQ12/PME#

1

1

1

6

6

6

4

3

2

1

9

9

9

0

8

7

9

0

B_A8/CCBE1#

B_A17/CAD16

B_A13/CPAR

B_A18/RFU

1

1

1

1

1

6

6

5

5

5

6

5

1

1

0

9

8

7

5

1

5

1

5

1

5

1

5

1

5

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

3

1

3

1

3

1
1

3
3

1

3

1
1

3
3

1

3

1
1

3
2

1

2

1
1

2
2

1

2

1
1

2
2

1

2

1

2

1

2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

0

1

0

1

0

1

1

1

1

1

0

1

0

0

0

0

4

1

2

3

I

O

B

_

W

/

R

C

#

A

5

D

5

B

A

_

4

I

O

B

_

3

A

B

_

2

B

V

_

1

O

B

_

0

C

B

_

9

B

A

_

8

D

B

_

7

C

B

_

6

B

V

_

5

D

B

_

4

D

B

_

3

B

S

_

2

D

B

_

1

D

B

_

0

D

B

_

9

D

B

_

8

B

_

D

7

D

B

_

6

C

B

_

5

B

_

D

4

R

C

O

3

E

D

L

2

S

C

L

1

S

D

A

0

A

S

L

9

C

O

R

8

S

P

K

7

A

U

X

6

A

_

C

5

W

A

_

4

D

A

_

3

A

D

_

2

D

A

_

1

D

A

_

0

A

D

_

9

D

A

_

8

B

A

_

7

A

S

_

6

A

A

_

5

V

A

_

4

A

B

_

3

A

A

_

2

R

A

_

1

A

A

_

0

I

N

A

_

9

A

A

_

3

8

A

W

_

7

A

4

A

_

6

R

A

_

5

A

A

5

_

1

/

C

9

A

D

4

1

R

D

/

C

#

A

D

1

3

/

C

1

A

D

1

1

2

/

S

C

1

V

S

1

E

#

/

C

1

A

D

1

/

C

#

A

D

E

2

0

1

/

C

0

A

1

D

9

5

1

/

C

A

D

8

/

C

#

C

E

1

#

B

E

0

V

P

P

_

C

C

4

1

/

R

U

F

/

C

7

A

D

7

C

O

K

E

V

C

C

_

T

3

1

/

C

A

D

6

/

C

6

A

D

5

/

C

2

1

A

D

4

/

5

C

A

D

3

/

C

1

A

D

1

2

/

C

4

A

D

1

D

/

C

#

C

1

D

1

#

/

C

3

A

D

0

V

E

_

C

C

_

U

/

T

S

O

K

T

A

C

I

_

T

V

I

Y

V

K

C

/

A

_

A

/

T

B

V

_

T

C

H

/

B

_

N

G

E

_

D

O

R

_

U

T

_

V

C

C

/

C

#

D

C

2

P

/

C

K

C

L

1

/

C

0

A

D

/

R

U

2

F

/

C

9

A

D

3

/

C

1

A

D

2

/

C

8

A

D

2

/

C

0

A

D

2

V

/

D

S

S

T

1

C

K

O

E

_

T

/

C

0

A

6

D

2

V

C

P

P

C

_

/

V

D

C

2

A

/

C

1

5

A

D

2

/

C

#

C

E

G

/

C

2

A

D

4

2

P

A

C

K

#

/

C

3

A

D

2

A

I

#

T

/

C

S

/

C

A

2

D

2

E

/

S

E

T

C

/

C

A

D

1

2

T

#

C

5

C

#

C

3

V

C

#

5

C

_

#

#

D

2

R

U

N

#

1

3
0

9
8
7

C

H

G

V

C

C

U

D

I

O

B

#

E

3

/

C

R

#

E

Q

E

R

R

#

R

E

#

S

E

T

AD0

AD3

AD2

AD1

CORE_GND

LOCK#

A_D3/CAD0

A_SOCKET_VCC

A_CD1#/CCD1#

A_D4/CAD1

A_D11/CAD2

A_D5/CAD3

A_D12/CAD4

A_D6/CAD5

A_D13/CAD6

A_D7/CAD7

A_D14/RFU

A_CE1#/CCBE0#

A_D15/CAD8

IRQ15/RING_OUT

A_A10/CAD9

A_CE2#/CAD10

A_OE#/CAD11

A_VS1/CVS1

A_A11/CAD12

A_IORD#/CAD13

CORE_VCC

A_A9/CAD14

A_IOWR/CAD15

A_A8/CCBE1#

A_A17/CAD16

A_A13/CPAR

A_A18/RFU

A_A14/CPERR#

IRQ3/VCC3#

A_A19/CBLOCK#

A_WE#/CGNT#

A_A20/CSTOP#

A_RDY_IREQ#/CINT#

A_A21/CDEVSEL#

A_A16/CCLK

A_A22/CTRDY#

A_A15/CIRDY#

A_A23/CFRAME#

A_A12/CCBE2#

SOCKET_VCC

A_A24/CAD17

A_A7/CAD18

GND

A_A25/CAD19

A_A6/CAD20

A_VS2/CVS2

OZ6833-DS-1.55 Page 4

PIN LIST

Bold Text = Normal Default Pin Name

PCI Bus Interface Pins

Pin Name Description

AD[31:0]

C/BE[3:0]#

FRAME#

IRDY#

TRDY#

STOP#

IDSEL

DEVSEL#

PERR#

PCI Bus Address Input/Data: These
pins connect to PCI bus signals AD[31:0].
A Bus transaction c onsists of an address
phase followed by one or more data
phases.

PCI Bus Command/Byte Enable: The
command signali ng and byte enables are
multiplexed on the same pins . During the
address phase of a transaction,
C/BE[3:0]# are interpreted as the bus
commands. During the data phase,
C/BE[3:0]# are interpreted as byte
enables. The byte enables are to be val id
for the entirety of each data phase, and
they indicate which bytes in t he 32-bit data
path are to carry meaningful dat a for the
current data phase.

Cycle Frame: This input indicates to the
OZ6833 that a bus transaction is
beginning. While FRAME# is asserted,
data transfers continue. When FRAME#
is de-asserted, the transaction is in its final
phases.

Initiator Ready: This input indicates the

initiating agent’s ability to complete the
current data phase of the transaction.
IRDY# is used in conjunction with TRDY#.

Target Ready: This output indicates
target Agent’s the OZ6833’s ability to
complete the current data phase of the
transaction. TRDY# is used in conjunction
with IRDY#.

Stop: This output indicates the current
target is requesting the m aster to s top the
current transaction.

Initialization Device Select: This input is
used as a chip sel ect during configurat ion
read and write transactions. This is a
point-to-point signal. IDS EL can be used
as a chip selec t during configuration read
and write transactions.

Device Select: This output is driven
active LOW when the PCI address is
recognized as supported, thereby acting
as the target for the current PCI cycle.
The Target must respond before timeout
occurs or the cycle will terminate.

Parity Error: The output is driven active
LOW when a dat a parity error is detected
during a write phase.

OZ6833

Pin Number

TQFP BGA

4-5, 7-12, 16­20, 22-24, 38­43, 45-46, 48-

49, 51-56

13, 25, 36, 47 F4, H1, M4, R1 TTL I/O 4 -

27 J3 TTL I/O 4

29 J1 TTL I/O 4 -

30 K2 TTL I/O 4 PCI Spec

32 L4 TTL I/O 4 PCI Spec

15 F3 TTL I 4 -

31 K3 TTL I/O 4 PCI Spec

33 K1 - TO 4 PCI Spec

B1, C1, D2, D1,
E4, E3, E2, E1,

G4, F1, G2,
G3, H4, H2,

H3, J4, M2, M3,

N4, M1, N2,
N1, P2, P1, P3,
R2, R3, T2, U1,

T3, U2, P4

Input Type

TTL I/O 4 PCI Spec

Power

Rail

Drive

-

OZ6833-DS-1.55 Page 5

Pin Name Description

SERR#

PAR

PCI_CLK

RST#

RI_OUT

CLKRUN#

PME#

SKTB_ACTV

INTA#

System Error: This output is driven
active LOW t o indicate an address parity
error.

Parity: This pin generates PCI parity and
ensures even parity across A D[31:0] and
C/BE[3:0]#. During the address phase,
PAR is valid after one clock. W ith data
phases, PAR is stable one clock after a
write or read transaction.

PCI Clock: This input provides timing for
all transactions on the PCI bus to and from
the OZ6833. All PCI bus signal s, except
RST#, are sampled and driven on the
rising edge of PCI_CLK. This input can be
operated at frequencies from 0 to 33MHz.

Device Reset: This input is used to
initialize all registers and internal logic to
their reset states and plac e most OZ6833
pins in a HIGH-impedance s t ate.

Ring Indicate Out: This pin is Ring
Indicate when the following occurs while

Mode Control B Register (index 2Eh)

O

2

bit 7 is set to 1:

1) Power Control (Index+02h) bit 7 set
to 1

2) Interrupt and General Control
(Index+03h) bit 7 set to 1

3) PCI O

PCI Clock Run Request: This signal is
used by the central resource to request
permission to stop the PCI clock or to slow
it down, and the OZ6833 responds
accordingly. To enable the CLKRUN#
signal, you need to enable ExCA register
3B bit[3:2].

Power Management Event: A power
management event is the process by
which the OZ6833 can request a change
of its power consumption state. Usuall y, a
PME occurs during a request to change
from a power saving state to the fully
operational state.

Socket B Activity: This signal indicates
that there is any activit y on the socket B
read/write access. Refer to PCI
Configuration Register 90h.

PCI Bus Interrupt A: This output
indicates a programmable interrupt
request generated from any of a number
of card actions. Although there is no
specific mapping requirement for
connecting interrupt lines from the
OZ6833 to the system , a common use is
to connect this pin to t he system PCI bus
INTA# signal.

Micro Control 2 (Offset: D4h)

2

bit X = 0

OZ6833

Pin Number

TQFP BGA

34 L2 - TO 4 PCI Spec

35 L3 TTL I/O 4 PCI Spec

1 A1 TTL I 4 -

207 C3 TTL I 1 -

72 P8 - TO 1 4mA

208 B2 TTL I/O 4 PCI Spec

163 D13 - TO 5 4mA

193 A7 - TO 1 4mA

203 A3 - TO 4 PCI Spec

Input Type

Power

Rail

Drive

OZ6833-DS-1.55 Page 6

Pin Name Description

INTB#

SOUT#/
IRQSER

SIN#

GNT#

REQ#

LOCK#

PCI_VCC

PCI Bus Interrupt B: This output
indicates a programmable interrupt
request generated from any of a number
of card actions. Although there is no
specific mapping requirement for
connecting interrupt lines from the
OZ6833 to the system , a common use is
to connect this pin to t he system PCI bus
INTB# signal.

SOUT#/IRQSER: In PC/PCI Serial
Interrupt Signaling mode, this pin is the
serial interrupt output, SOUT#. In PC/Way
mode, this pin is t he IRQ serializer pin to
the interrupt controller.

SIN#: In PC/PCI Serial Input Signaling
mode, this pin is t he serial interrupt input,
SIN#.

Grant: This signal indicates that access
to the bus has been granted.

Request: This signal indicates to the
arbiter that the OZ6833 requests use of
the bus.

PCI LOCK#: This signal is used by a PCI
master to perf orm a locked transact ion to
a target memory. LOCK# is used to
prevent more than one mast er from using
a particular system resource.

PCI Bus VCC: These pins can be
connected to either a 3.3- or 5-volt power
supply. The PCI bus interfac e pin outputs
listed in this table (Table 2-1) will operate
at the voltage applied to these pins,
independent of the voltage applied to
other OZ6833 pin groups.

PCMCIA Sockets Interface Pins

Socket A pin number --- Socket B pin number

Name1 Description2

-REG#/
CCBE3#

A[25:24]/
CAD[19, 17]

A23/
CFRAME#

Register Access: During PCMCIA
memory cycles, this output chooses
between attribute and common
memory. During I/O cycles for non-DMA
transfers, this signal is active (low).
During ATA mode, t his signal is al ways
inactive. For DMA cycles on the
OZ6833 to a DMA-capable card, -REG
is inactive during I/O c ycles to indicate
DACK to the PCMCIA card.
CardBus Command Byte Enable: In
CardBus mode, this pi n i s the CCBE3#.

PCMCIA socket address 25:24 outputs.
CardBus Address/Data: CardBus
mode, these pins are the CA D bits 19
and 17.
PCMCIA socket address 23 output.
CardBus Frame: In CardBus mode,
this pin is the CFRAME# si gnal .

OZ6833

Pin Number

TQFP BGA

204 C4 - TO 4 PCI Spec

205 B3 TTL I/O 4 PCI Spec

206 A2 TTL I/O 4 PCI Spec

2 D4 TTL I 4 PCI Spec

3 C2 N/A TO 4 PCI Spec

58 U3 TTL I/O 4 PCI Spec

6, 21, 37, 50 D3, G1, L1, T1 - P WR -

Pin Number

Socket A Socket B

TQFP B GA TQ FP BGA

112 P15 188 D7 1 I/O 2 or 3 CardBus

102,

R15,

99

U15

96 U14 172 D11 1 I/O 2 or 3 CardBus

176,

174

D10,

B11

Input Type

Qty I/O Pwr Drive

2 I/O 2 or 3 CardBus

Power

Rail

Drive

spec.

spec.

spec.

OZ6833-DS-1.55 Page 7

OZ6833

Name1 Description2

A22/
CTRDY#

A21/
CDEVSEL#

A20/
CSTOP#

A19/
CBLOCK#

A18/
RFU

A17/
CAD16

A16/
CCLK#

A15/
CIRDY#

A14/
CPERR#

A13/
CPAR

A12/
CCBE2#

A[11:9]/
CAD[12, 9,
14]

A8/
CCBE1#

A[7:0]/
CAD[18, 20­26]

D15/
CAD8

D14/
RFU

PCMCIA socket address 22 output.
CardBus Target Ready: In CardBus
mode, this pin is the CTRDY# signal.
PCMCIA socket address 21 output.
CardBus Device Select: In CardBus
mode, this pin is the CDEVSEL# signal.
PCMCIA socket address 20 output.
CardBus Stop: In CardBus mode, this
pin is the CSTOP# signal.
PCMCIA socket address 19 output.
CardBus Lock: In CardBus mode, t his
signal is the CB LOCK# signal used for
locked transactions .
PCMCIA socket address 18 output.
Reserved: In CardBus mode, this pin is
reserved for future use.
PCMCIA socket address 17 output.
CardBus Address/Data: In CardBus
mode, this pin is t he CAD bit 16.
PCMCIA socket address 16 output.
CardBus Clock: In CardBus mode, this
pin supplies the clock to the inserted
card.
PCMCIA socket address 15 output.
CardBus Initiator Ready: In CardBus
mode, this pin is t he CIRDY# signal.
PCMCIA socket address 14 output.
CardBus Parity Error: CardBus mode,
this pin is the CPERR# signal.
PCMCIA socket address 13 output.
CardBus Parity:b In CardBus mode,
this pin is the CPAR s i gnal .
PCMCIA socket address 12 output.
CardBus Command/Byte Enable: In
CardBus mode, this pi n is the CCBE2#
signal.
PCMCIA socket address 11:9 output.
CardBus Address/Data: In CardBus
mode, these pin are the CAD bits 12, 9
and 14.
PCMCIA socket address 8 output.
CardBus Command/Byte Enable: In
CardBus mode, this pi n is the CCBE1#
signal.
PCMCIA socket address 7:0 outputs.
CardBus Address/Data: In CardBus
mode, these pins are the CA D bits 18
and 20:26.

PCMCIA socket data/0 bit 15.
CardBus Address/Data: In CardBus
mode, this pin is t he CAD bit 8.
PCMCIA socket data I/0 bit 14.
Reserved: In CardBus mode, this pin is
reserved for future use.

Pin Number

Socket A Socket B

TQFP B GA TQ FP BGA

94 R13 170 A13 1 I/O-PU 2 or 3 CardBus

92 U12 168 C13 1 I/O-PU 2 or 3 CardBus

90 T12 166 A14 1 I/O-PU 2 or 3 CardBus

88 P12 164 C14 1 I/O-PU 2 or 3 CardBus

85 U10 161 B14 1 TO 2 or 3 CardBus

83 R10 158 D14 1 I/O 2 or 3 CardBus

93 P13 169 B12 1 I/O 2 or 3 CardBus

95 T13 171 C12 1 I/O-PU 2 or 3 CardBus

86 T11 162 A15 1 I/O-PU 2 or 3 CardBus

84 P11 159 B15 1 I/O 2 or 3 CardBus

97 U13 173 A12 1 I/O 2 or 3 CardBus

77, 73,

80

82 T10 157 A17 1 I/O 2 or 3 CardBus

100,
103,
105,
107,
109,
111,
113,

116

71 R7 148 D17 1 I/O 2 or 3 CardBus

69 U6 145 E14 1 I/O 2 or 3 2 mA

U8,
U7,

P10

R14,
T15,
U17,
T17,
P16,
N14,
N16,

N15

153,
149,

155

175,
178,
181,
183,
185,
187,
189,

191

C17,
E17,

C16

C11,
B10,
A10,

C9,
A9,
C8,

A8, C7

Qty I/O Pwr Drive

spec.

spec.

spec.

spec.

spec.

spec.

spec.

spec.

spec.

spec.

spec.

3 I/O 2 or 3 CardBus

spec.

spec.

8 I/O 2 or 3 CardBus

spec.

spec.

OZ6833-DS-1.55 Page 8

OZ6833

Name1 Description2

D[13:3]/
CAD[6, 4, 2,
31, 30, 28, 7,
5, 3, 1, 0]

D2/
RFU

D[1:0]/
CAD[29,27]

-OE/
CAD11

-WE/
CGNT#

-IORD/
CAD13

-IOWR/
CAD15

WP/

-IOIS16/
CCLKRUN#

PCMCIA socket data I/0 bits 13:3.
CardBus Address/Data: In CardBus
mode, this pin is t he CAD bit 6 4, 2, 31,
30, 28, 7, 5, 3, 1, and 0, respectively.

PCMCIA socket data I/O bit 2.
Reserved: In CardBus mode, this pin is
reserved for future use.
PCMCIA socket data I/O bits 1:0.
CardBus Address/Data: In CardBus
mode, these pins are the CA D bits 29
and 27, respectively.
Output Enable: This output goes active
(low) to indicate a memory read from
the PCMCIA socket to the OZ6833.
CardBus Address/Data: In CardBus
mode, this pin is t he CAD bit 11.
Write Enable: This out put goes active
(low) to indicate a memory write from
the OZ6833 to the PCMCIA socket.
CardBus Grant: In CardBus mode, this
pin is the CGNT# signal.
I/O Read: This output goes active (low)
for I/O reads from the socket to the
OZ6833.
CardBus Address/Data: In CardBus
mode, this pin is t he CAD bit 13.
I/O Write: This output goes active (low)
for I/O writes from the OZ6833 to the
socket.
CardBus Address/Data: In CardBus
mode, this pin is t he CAD bit 15.
Write Protect/ I/O Is 16-Bit: In Memory
Card Interface mode, this inputs is
interpreted as the status of the write
protect switch on the PCMCIA c ard. In
I/O Card Interface mode, this input
indicates the size of t he I/O data at the
current address on the PCMCIA card.
CardBus Clock Run: In CardBus
mode, this pin is the CCLKRUN# signal,
which starts and stops the CardBus
CCLK. To enable the CLKRUN# s ignal,
ExCA register 3Bh/7Bh bi t[3:2] m ust be
enabled.

Pin Number

Socket A Socket B

TQFP B GA TQ FP BGA

67, 65,

63,
124,
122,
120,

68, 66,
64, 62,

59

123 L15 198 A6 1 I/O 2 or 3 CardBus

121,

119

75 R8 151 D16 1 I/O 2 or 3 CardBus

89 U11 165 B13 1 TO 2 or 3 CardBus

78 T9 154 C15 1 I/O 2 or 3 CardBus

81 U9 156 B16 1 I/O 2 or 3 CardBus

125 L17 201 B4 1 I/O-PU 2 or 3 CardBus

R6,
P6,
T5,

K14,

L16,
L14,

P7,
T6,
U5,

R5, R4

M17,

M15

142,
140,
138,
199,
197,
195,
144,
141,
139,
137,

135

196,

194

F16,
F14,

G16,

A5,
B5,
D5,

F17,
G17,
G15,

H17,

H15

C6, B6 2 I/O 2 or 3 CardBus

Qty I/O Pwr Drive

11 I/O 2 or 3 CardB us

spec.

spec.

spec.

spec.

spec.

spec.

spec.

spec.

OZ6833-DS-1.55 Page 9

OZ6833

Name1 Description2

-INPACK/
CREQ#

RDY/

-IREQ/
CINT#

-WAIT/
CSERR#

CD[2:1]/
CCD[2:1]#

-CE2/
CAD10

-CE1/
CCBE0#

RESET/
CRST#

Input Acknowledge: The -INPACK
function is not applicable in PCI bus
environments. However, for
compatibility with other Cirrus Logic
products, this pin s hould be connected
to the PCMCIA socket’s -INPACK pin.
CardBus Request: In CardBus m ode,
this pin is the CREQ# si gnal .
Ready/Interrupt Request: In Memory
Card Interface mode, this input
indicates to the OZ6833 that t he card is
either ready or busy. In I/O Card
Interface mode, this input indicates a
card interrupt request.
CardBus Interrupt: In CardBus mode,
this pin is the CINT# signal . This signal
is active-low and level-sensit ive.
Wait: This input indicates a request by
the card to the OZ6833 to halt the c ycle
in progress until this signal is
deactivated.
CardBus System Error: In CardBus
mode, this pin is the CSERR# signal.
Card Detect: These inputs indicate to
the OZ6833 that a card is in the socket.
They are internally pulled high to the
voltage of the AuxVCC power pin.
CardBus Card Detect: In CardBus
mode, these inputs are used with
CVS[2:1] to detect presence and type of
card.
Card Enable pin is driven low by the
OZ6833 during card access cycles to
control byte/word card access. -CE1
enables even-numbered address byt es,
and -CE2 enables odd-numbered
address bytes. When configured for 8­bit cards, only -CE1 is active and A0 is
used to indicate access of odd- or even­numbered bytes.
CardBus Address/Data: In CardBus
mode, this pin is t he CAD bit 10.

Card Enable pin is driven low by the
OZ6833 during card access cycles to
control byte/word card access. -CE1
enables even-numbered address byt es,
and -CE2 enables odd-numbered
address bytes. When configured for 8­bit cards, only -CE1 is active and A0 is
used to indicate access of odd- or even­numbered bytes.
CardBus Command/Byte Enable: In
CardBus mode, thi s pin is t he CCBEO#
signal.

Card Reset: This output is low for
normal operation and goes high t o reset
the card. To prevent reset glitc hes to a
card, this signal is high-impedance
unless a card is seated in the socket,
card power is applied, and the card’s
interface signals are enabled.
CardBus Reset: In CardBus mode, t hi s
pin is the CRST# output.

Pin Number

Socket A Socket B

TQFP B GA TQ FP BGA

110 R17 186 B8 1 I-PU 2 or 3 CardBus

91 R12 167 D12 1 I-PU 2 or 3 CardBus

108 P14 184 D8 1 I-PU 2 or 3 CardBus

126,

61

74 T8 150 D15 1 I/O 2 or 3 CardBus

70 T7 147 E16 1 I/O 2 or 3 CardBus

106 R16 182 B9 1 TO 2 or 3 CardBus

K16,

P5

202,

136

A4,

G14

Qty I/O Pwr Drive

spec.

spec.

spec.

2 I-PU-

Schmitt

1 CardBus

spec.

spec.

spec.

spec.

OZ6833-DS-1.55 Page 10

OZ6833

Pin Number

Name1 Description2

BVD2/

-SPKR/

-LED/
CAUDIO

BVD1/

-STSCHG/

-RI/

-CSTSCHG

VS2/
CVS2

VS1/
CVS1

SOCKET_VCC Connect thes e pins to the Vcc supply

1

To differentiate the sockets in the pin diagram, all socket- specific pins have either A_ or B_ prefixes to the pin names indicated.

For example, A_A[25:0] and B_A[25:0] are the independent address buses to the sockets.

2

When a socket is configured as an ATA drive interface, socket interface pin functions change.

Battery Voltage Detect 2/Speaker/
LED: In Memory Card Interface m ode,

this input serves as the BVD2 (battery
warning status) input. In I/O Card
Interface mode, this input can be
configured as a card’s -SPKR binary
audio input. For ATA or non-ATA
(SFF-68) disk-drive support, this input
can also be configured as a drive­status LED input.
CardBus Audio: In CardBus mode,
this pin is the CAUDIO i nput.

Battery Voltage Detect 1/Status
Change/Ring Indicate: In Memory

Card Interface mode, t his input serves
as the BVD1 (battery-dead status)
input. In I/ O Card Interface m ode, this
input is the -STSCHG input, which
indicates to the OZ6833 that the card’s
internal status has changed. If bi t 7 of
the Interrupt and General Control
register is set to `1`, this pi n serves as
the ring indicate i nput for wakeup-on­ring system power management
support.
CardBus Status Change: In CardBus
mode, this pin is the CSTSCHG. This
pin can be used to generate PME#.
Voltage Sense 2: This pin is used in
conjunction with VS1 to det ermine the
operating voltage of the c ard. This pin
is internally pulled high t o the voltage
of the AuxVCC power pin under the
combined control of t he external data
write bits and the CD pull up control
bits. This pin connects to PCMCIA
socket pin 57.
CardBus Voltage Sense: In CardBus
mode, these pins are the CV S2 pin.
Voltage Sense 1: This pin is used in
conjunction with VS2 to det ermine the
operating voltage of the c ard. This pin
is internally pulled high t o the voltage
of the AuxVCC power pin under the
combined control of t he external data
write bits and the CD pull up control
bits. This pin connects to PCMCIA
socket pin 43.
CardBus Voltage Sense: In CardBus
mode, these pins are the CV S1 pin.

of the socket (pins 17 and 51 of the
respective PCMCIA socket). These
pins can be 0, 3. 3, or 5 V, depending
on card presence, card type, and
system configuration. The socket
interface outputs (listed in this table,
Table 2-2) will operate at the voltage
applied to these pins , independent of
the voltage applied to other OZ6833
pin groups.

Socket A Socket B

TQFP BGA TQFP BGA

114 P17 190 B7 1 I-PU 2 or 3 -

118 M16 192 D6 1 I-PU 2 or 3 -

104 T16 179 C10 1 I/O-PU 1 CB-spec

76 P9 152 B17 1 I/O-PU 1 CB-spec

117,

98, 60

N17,
T14,

U4

200,
160,

143

C5,

A16,

F15

Qty I/O Pwr Drive

3 PWR - -

OZ6833-DS-1.55 Page 11

Power Control and General Interface Pins

Pin Name Description

SPKR_OUT

LED_OUT/
SKTA_ACTV

CPWRCLK/
A_VCC5#

CPWRDATA/

B_VCC3#

CPWRLATC/

B_VCC5#

Speaker Output: This output can be
used as a digital output to a speaker to
allow a system to support PC Card
fax/modem/voice and audio sound
output. This output is enabled by sett ing
the socket’s Misc. Control 1 regis ter bit
4 to “1” (for the socket whose speaker
signal is to be directed from BVD2/­SPKR/-Led to this pin).
LED Output/SKTA_ACTV: This output
can be used as an LED driver to indicate
disk activity when a socket’s BVD2/­SPKR/-LED pin has been programmed
for LED support.
In the O2 Mode(Index 3B/7B bit 5) , this
pin indicates the socket A activity. The
socket B activity refers to PCI
Configuration Register offset 90h (Mux
Control register)
Card Power Clock: This input is used as
a reference clock (10-100 kHz, usually
32 kHz) to control the serial i nterface of
the socket power control chips.
A_VCC5#: This active-LOW output
controls the 5 -volt supply to the A
socket’s VCC pins. The active-LOW
level of this output is mut ually exclusive
with that of -VCC_3.
Card Power Serial Data: This pin
serves as output DATA pin when used
with the serial interface of Texas
Instruments’ TPS2202IDF socket power
control chip.
B_VCC3#: This active-LOW output
controls the 3.3-volt supply to the A
socket’s VCC pins. The active-LOW
level of this output is mut ually exclusive
with that of -VCC_5.
Card Power Serial Latch: This pin
serves as output LATCH pi n when used
with the serial interface of Texas
Instruments’ TPS2202IDF socket power
control chip.
B_VCC5#: This active-LOW output
controls the 5 -volt supply to the A
socket’s VCC pins. The active-LOW
level of this output is mut ually exclusive
with that of -VCC_3.

OZ6833

Pin Number

TQFP BGA

128 J14 TTL I/O 1 12mA

133 J17 TTL I/O 1 12mA

132 H14 TTL I/O 1 12mA

131

130 J16 N/A I/O 1 12mA

J15

Input Type

TTL I/O 1 12mA

Power

Rail

Drive

OZ6833-DS-1.55 Page 12

Pin Name Description

A_VCC3# This active-LOW output controls of the

A_VPP_VCC

B_VPP_VCC

3.3-volt supply to the socket ’s VCC pins.
The active-LOW level of this output is
mutually exclusive with of V CC_5#. This

mode active only in SktPwr Parallel
mode enabled
VPP_VCC: This active-HIGH output

controls the s ocket A VCC s upply to the
socket’s VPP1 and VPP2 pins. The
active-HIGH level of this output is
mutually exclusive with that of
VPP_PGM. This mode active only in

SktPwr Parallel mode enabled
VPP_VCC: This active-HIGH output

controls the s ocket B VCC s upply to the
socket’s VPP1 and VPP2 pins. The
active-HIGH level of this output is
mutually exclusive with that of
VPP_PGM. This mode active only in

SktPwr Parallel mode enabled

Power, Ground, and Reserved Pins

Pin Name Description

AUX_VCC This pin is connected t o the system’s 5-

CORE_VCC This pin provides power to the core

CORE_GND All OZ6833 ground pins should be

volt power supply. In sys tems where 5
volts is not available, this pin can be
connected to the system’s 3.3-volt supply
if your PCI_VCC and CORE_VCC
connected to 3.3V

circuitry of the OZ6833. It could be
connected to a 3.3 power supply.

connected to system ground.

OZ6833

Pin Number

TQFP BGA

87 R11 N/A TO 1 4mA

115 M14 N/A TO 1 4mA

146 E15 N/A TO 1 4mA

Pin Number

TQFP BGA

127 K15 N/A PWR - -

134, 79, 180 H16, R9, D9 N/A PWR - -

26, 14, 28, 44,

57, 101, 129,

177

A11, J2, K4,

K17, N3, T4,

F2, U16

Input Type

Input Type

N/A GND -

Power

Rail

Power

Rail

Drive

Drive

-

Legend

I/O Type Description

I Input Pin 1 AUX_VCC: outputs powered from AUX_VCC

I-PU Input pin with internal pull-up 2 A_SLOT_VCC: outputs powered from the socket A

O Output 3 B_SLOT_VCC: outputs powered from the socket B

OD Open-drain 4 PCI_VCC: outputs powered from PCI bus power supply

TO Tri-state output
TO-PU Tri-state output with int ernal pul l -up
OD-PU Open-drain output with internal pull-up

PW Power pin

OZ6833-DS-1.55 Page 13

Power

Rail

5 CORE_VCC: outputs powered from the CORE_VCC

Source of Output’s Power

PACKAGE SPECIFICATIONS

D

D

1

156 105

OZ6833

157

208

1 52

INCHES MILLIMETERSSymbol

MIN NOM MAX MIN NOM MAX

A - - 0.063 - - 1.60

A

0.002 - 0.006 0.05 - 0.15

1

0.053 0.055 0.057 1.35 1.40 1.45

A

2

b 0.007 0.009 0.011 0.17 0.22 0.27
c 0.004 - 0.008 0.09 - 0.20
D 1.181 30.00 BSC.

D

1

E 1.181 30.00 BSC.

E

1

e 0.020 BSC. 0.50 BSC.
L 0.018 0.024 0.030 0.45 0.60 0.75

L

1

θ

1.102 28.00 BSC.

1.102 28.00 BSC.

0.039 REF 1.00 REF

0° 3.5° 7° 0° 3.5° 7°

104

OZ6833 208-PIN TQFP

1

E

E

O2MICRO, INC.

F F

53

be

A

A2

A1

SEATING PLANE

GAGE PLANE

SEC: F-F

0.25

B

B

L

L1

θ

OZ6833-DS-1.55 Page 14

208 PIN – BGA

m
m

5

1

15mm

OZ6833

1.10mm

1.10mm

(Top View)

U T R P N M L K J H G F E D C B A

17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

Index A1

0.48mm
± 0.05

0.8mm

1.10mm

(Bottom View)

OZ6833-DS-1.55 Page 15