The OZ6812 is a PCMCIA R2/CardBus controller, providing
the most advanced design flexibility for PC Cards that
interface with advanced notebook designs.
• ACPI-PCI Bus Power Management Interface
Specification Rev 1.1 Compliant
• Supports OnNow LAN wakeup, OnNow Ring Indicate,
PCI CLKRUN#, PME#, and CardBus CCLKRUN#
• Compliant with PCI specification V2.2, 1998 PC Card
• Supports 5V/3.3V PC Cards and 3.3V CardBus cards
• Supports single PC Card or CardBus slot with hot
• Supports multiple FIFOs for PCI/CardBus data transfer
• Supports Direct Memory Access for PC/PCI and
• Programmable interrupt protocol: PCI, PCI+ISA,
• Win’98 IRQ and PC-98/99 compliant
• Parallel or Serial interface for socket power control
• Zoomed Video Support
• Integrated PC 98/99 -Subsystem Vendor ID support,
• LED Activity Pins
ORDERING INFORMATION
OZ6812T - 144pin LQFP
OZ6812B - 144pin Mini-BGA
TM
82365SL PCIC Register Compatible
insertion and removal
PCI/Way on PC Card socket
PCI/Way, or PC/PCI interrupt signaling modes
devices including Micrel and TI
with auto lock bit
GENERAL DESCRIPTION
The OZ6812 is an ACPI and PC98/99 logo certified, high
performance, single slot PC Card controller with a
synchronous 32-bit bus master/target PCI interface. This
PC Card to PCI bridge host controller is compliant with the
OZ6812
ACPI CardBus Controller
1998 PC Card Standard. This standard incorporates the
new 32-bit CardBus while retaining the 16-bit PC Card
specification as defined by PCMCIA release 2.1. CardBus
is intended to support “temporal” add-in functions on PC
Cards, such as Memory cards, Network interfaces,
FAX/Modems and other wireless communication cards, etc.
The high performance and capability of the CardBus
interface will enable the development of many new
functions and applications.
The OZ6812 CardBus controller is compliant with the latest
ACPI-PCI Bus Power Management Interface Specification.
It supports all four power states and the PME# function for
maximum power savings and ACPI compliance. The device
also provides a power-down mode to allow host software to
reduce power consumption further by stopping internal
clock distribution as well as the PC Card socket clock. In
addition, an advanced CMOS process is utilized to
minimize system power consumption.
The OZ6812 single PCMCIA socket supports 3.3V/5V 8/16bit PC Card R2 card or 32-bit CardBus R3 card. The R2
card support is compatible with the Intel 82365SL PCIC
controller, and the R3 card support is fully compliant with
the 1998 PC Card Standard CardBus specification. The
OZ6812 is a stand alone device, which means that it does
not require an additional buffer chip for the PC Card socket
interface. In addition, the OZ6812 supports dynamic PC
Card hot insertion and removal, with auto configuration
capabilities.
The OZ6812 is fully compliant with the 33Mhz PCI Bus
specification, V2.2. It supports a master device with
internal CardBus direct data transfer. The OZ6812
implements a FIFO data buffer architecture between the
PCI bus and CardBus socket interface to enhance data
transfers to CardBus devices. The bi-directional FIFO
buffer (composed of 16 double words) permits the OZ6812
to accept data from a target bus (PCI or CardBus interface)
while simultaneously transferring data. This architecture
not only speeds up data transfers but also prevents system
deadlocks.
PCI Bus Address Input / Data: These pins
connect to PCI bus signals AD[31:0]. A Bus
transaction consis ts of an addres s phas e followed
by one or more data phases.
PCI Bus Command / Byte Enable: The
command signaling and byte enables are
multiplexed on the same pins. During the address
phase of a transaction, C/BE [3:0] # are interpreted
as the bus commands. During the data phase,
C/BE[3:0]# are interpreted as byte enables. The
byte enables are to be valid for the entirety of
each data phase, and they indicat e which bytes in
the 32-bit data path are to carry m eaningful data
for the current data phase.
Cycle Frame: This input indicates to the OZ6812
that a bus transaction is beginning. While
FRAME# is asserted, data transfers continue.
When FRAME# is de-asserted, the trans action is
in its final phase.
Initiator Ready: This i nput indicates the initiat ing
agent’s ability to com plete the current data phas e
of the transaction. I RDY# is used in conjunction
with TRDY#.
Target Ready: This output indicates target
Agent's the OZ6812’s ability to complete the
current data phase of the t ransaction. TRDY# is
used in conjunction with IRDY#.
Stop: This output indicates the current target is
requesting the master to stop the current
transaction.
Initialization Device Sele c t : This input is used as
a chip select during c onfiguration read and write
transactions. This is a point-to-point signal.
IDSEL can be used as a chip select during
configuration read and write transacti ons.
Device Select: This output i s driven active LOW
when the PCI address is recognized as
supported, thereby acting as the target for the
current PCI cycle. The Target must respond
before timeout occurs or t he cycle will terminate.
Parity Error: The output is driven active LOW
when a data parity error is detected during a write
phase.
System Error: This output is driven active LOW
to indicate an address parit y error.
Parity: This pin generates PCI parity and ensures
even parity across AD[31:0] and C/BE[3:0]#.
During the address phase, PAR is valid after one
clock. W ith data phases , PAR is s table one clock
after a write or read transaction.
PCI Clock: This input provides timing for all
transactions on the PCI bus to and from the
OZ6812. All PCI bus signals, except RST#, are
sampled and driven on the rising edge of
PCI_CLK. This input can be operated at
frequencies from 0 to 33 MHz.
Device Reset: This input is used t o initialize all
registers and internal logic to their reset states
and place most OZ6812 pins in a HIGHimpedance state.
Grant: This signal indicates that access to the bus
has been granted.
Request: This signal indicates to the arbiter that
the OZ6812 requests use of the bus.
Power Control and General Interface Pins
Pin Name Description
RI_OUT/
PME#
SPKR_OUT#
MF[6:0]
SUSPEND#
Ring Indicate Out: This pin is Ring Indicate
when the following occurs while O
B Register (index 2Eh) bit 7 is set to 1:
1) Power Control (Index+02h) bit 7 set to 1
2) Interrupt and General Control (Index+03h)
bit 7 set to 1
3) PCI O2Micro Control 2 (Off set : D4h) bit X =
0
Power Management Event: A power
management event is t he process by which the
OZ6812 can request a change of its power
consumption state. Usually, a PME occurs
during a request to change from a power saving
state to the fully operational state.
Speaker Output: This output can be used to
support PC Card audio output. See O2 Mode E
Register (Index + 3Eh), bit 1.
Multifunction Terminal [6:0]: See PCI
Multifunction MUX Register (Offset : 08h).
Suspend: This signal is used to protect the
internal registers from clearing when the PCI
RST# signal is asserted. When low, this s i gnal i s
used to mask t he PCI RESET during suspend.
This pin can be used during suspend to prevent
controller reset.
Mode Control
2
OZ6812
Pin Number
LQFP BGA
36 L3 TTL I/O PCI_Vcc PCI
21 G4 - I PCI_Vcc -
20 G2 - I AUX_Vcc -
2 B2 TTL I PCI_Vcc PCI
1 A1 - TO PCI_Vcc PCI
Pin Number
LQFP BGA
59 M8 - TO Aux_Vcc 4mA
62 K8 TTL I/O Aux_Vcc 12mA
69-67, 65-64,
61-60
70 N12 TTL I Aux_Vcc -
L10, K9, N11,
L9, N10-9, L8
Input Type
Input Type
TTL I/O Aux_Vcc 12mA
Power
Rail
Power
Rail
Drive
Spec
Spec
Spec
Drive
OZ6812-SF-1.5 Page 5
Page 6
Pin Name Description
VPPD0/
SLATCH
VPPD1
VCCD0#/
SDATA
VCCD1#/
SCLK
VPPD0: This power input is used with parallel
power control chip
SLATCH: This output controls a serial interface
power control chip.
VPPD1: This power input is used a parallel
power interface chip.
VCCD0#: Rail power inputs for use with a
parallel power control chip.
Serial Data: This pin serves as output DATA pin
when used with a serial interface of serial power
control chip.
VCCD1#: Rail power inputs for use with a
parallel power control chip.
Serial Clock: The input is us ed as a reference
clock (10-100kHz, usually 32kHz) to control a
serial power control chips. By setting PCI
O2Micro Control 2 register (Offset :D4h) bit 13 to
1, SCLK is an output. Defaul t is input mode.
Refer to PCI Bus Interface pin descriptions for details on CardBus function.
EXCEPTIONS: CCD[2:1]#, CAUDIO, CSTSCHG, CVS[2:1]
Pin Name Description
REG#/
CCBE3#
A[25:24]/
CAD[19, 17]
A23/
CFRAME#
A22/
CTRDY#
A21/
CDEVSEL#
A20/
CSTOP#
A19/
CBLOCK#
A18/
RFU
A17/
CAD16
A16/
CCLK#
Register Access: During PC Card memory cycles,
this output c hooses between Attri bute and Comm on
Memory. During I/O cycles for non-DMA transfers,
this signal is active (low). During ATA mode, this
signal is always inactive. For DMA cycles on the
OZ6812 to a DMA-capable card, REG# becomes
DACK to the PCMCIA card.
CardBus Command Byte Enable: In CardBus
mode, this pin is the CCBE3#.
Address: PC Card socket address 25:24 outputs.
CardBus Address/Data: CardBus mode, these pins
are the CAD bits 19 and 17.
Address: PC Card socket address 23 output.
CardBus Frame: In CardBus mode, this pin is the
CFRAME# signal.
Address: PC Card socket address 22 output.
CardBus Target Ready: In CardBus mode, this pin
is the CTRDY# signal.
Address: PC Card socket address 21 output.
CardBus Device Select: In CardBus mode, t his pin
is the CDEVSEL# signal.
Address: PC Card socket address 20 output.
CardBus Stop: In CardBus mode, this pin is the
CSTOP# signal.
Address: PC Card socket address 19 output.
CardBus Lock: In CardBus mode, this si gnal is the
CBLOCK# signal used for locked transactions.
Address: PC Card socket address 18 output.
Reserved: In CardBus mode, this pin is res erved for
future use.
Address: PC Card socket address 17 output.
CardBus Address/Data: In CardBus mode, this pi n
is the CAD bit 16.
Address: PC Card socket address 16 output.
CardBus Clock: In CardBus mode, t h i s pin supplies
the clock to the ins erted card.
Pin Number
LQFP BGA
125 B8 TTL I/O Socket
116, 113 B10, B11 TTL I/O Socket
111 D10 TTL I/O Socket
109 A13 TTL I/O-
107 C12 TTL I/O-
105 D11 TTL I/O-
103 C13 TTL I/O-
100 D13 TTL TO Socket
98 F10 TTL I/O Socket
108 C11 TTL I/O Socket
OZ6812
Input Type
PU
PU
PU
PU
Power
Rail
_Vcc
_Vcc
_Vcc
Socket
_Vcc
Socket
_Vcc
Socket
_Vcc
Socket
_Vcc
_Vcc
_Vcc
_Vcc
Drive
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
OZ6812-SF-1.5 Page 7
Page 8
Pin Name Description
A15/
CIRDY#
A14/
CPERR#
A13/
CPAR
A12/
CCBE2#
A[11:9]/
CAD
[12,9,14]
A8/
CCBE1#
A[7:0]/
CAD[18]
[20:26]
D15/
CAD8
D14/
RFU
D[13:3]/
CAD[6, 4, 2,
31, 30, 28, 7,
5, 3, 1, 0]
D2/
RFU
D[1:0]/
CAD[29,27]
OE#/
CAD11
WE#/
CGNT#
Address: PC Card socket address 15 output.
CardBus Initiator Ready: In CardBus mode, this
pin is the CIRDY# signal.
Address: PC Card socket address 14 output.
CardBus Parity Error: CardBus mode, this pin is
the CPERR# signal.
Address: PC Card socket address 13 output.
CardBus Parity: In CardBus mode, this pin is the
CPAR signal.
Address: PC Card socket address 12 output.
CardBus Command/Byte Enable: In CardBus
mode, this pin is the CCBE2# signal.
Address: PC Card socket address 11:9 output.
CardBus Address/Data: In CardBus mode, these
pins are the CAD bits 12, 9 and 14.
Address: PC Card socket address 8 output.
CardBus Command/Byte Enable: In CardBus
mode, this pin is the CCBE1# signal.
Address: PC Card socket address 7:0 outputs .
CardBus Address/Data: In CardBus mode, these
pins are the CAD bits 18 and 20:26.
Data: PC Card socket I/O data bit 15.
CardBus Address/Data: In CardBus mode, this pin
is the CAD bit 8.
Data: PC Card socket I/O data bit 14.
Reserved: In CardBus mode, this pin is res erved for
future use.
Data: PC Card socket I /O data bits 13:3.
CardBus Address/Data: In CardBus mode, this pin
is the CAD bit 6 4, 2, 31, 30, 28, 7, 5, 3, 1, and 0,
respectively.
Data: PC Card socket I/O data bit 2.
Reserved: In CardBus mode, this pin is res erved for
future use.
Data: PC Card socket I/O data bits 1:0.
CardBus Address/Data: In CardBus mode, these
pins are the CAD bits 29 and 27, res pectively.
Output Enable: This output goes active (low) to
indicate a memory read from the OZ6812 to PC
Card.
CardBus Address/Data: In CardBus mode, this pin
is the CAD bit 11.
Write Enable: This output goes active (low) to
indicate a memory write from the OZ6812 to the P C
Card socket.
CardBus Grant: In CardBus mode, this pin is the
CGNT# signal.
OZ6812
Pin Number
LQFP BGA
110 B12 TTL I/O-
104 E10 TTL I/O-
101 E11 TTL I/O Socket
112 A12 TTL I/O Socket
95, 89, 97 F12, H12,
99 E12 TTL I/O Socket
115, 118,
120, 121,
124, 127,
128, 129
87 H11 TTL I/O Socket
84 J12 TTL I/O Socket
82, 80, 77,
144, 142,
140, 85, 83,
81, 79, 76
143 B3 TTL I/O Socket
141, 139 C4, A3 TTL I/O Socket
92 G12 TTL I/O Socket
106 B13 TTL TO Socket
E13
A11-10, B9,
A9-7, B7,
D7
K13-12,
L12, C3,
A2, D5,
J13, J11,
J10, L13,
M13
Input Type
PU
PU
TTL I/O Socket
TTL I/O Socket
TTL I/O Socket
Power
Rail
Socket
_Vcc
Socket
_Vcc
_Vcc
_Vcc
_Vcc
_Vcc
_Vcc
_Vcc
_Vcc
_Vcc
_Vcc
_Vcc
_Vcc
_Vcc
Drive
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
OZ6812-SF-1.5 Page 8
Page 9
Pin Name Description
IORD#/
CAD13
IOW#/
CAD15
WP/
IOIS16#/
CCLKRUN#
INPACK#/
CREQ#
RDY/IREQ#/
CINT#
WAIT#/
CSERR#
CD[2:1]/
CCD[2:1]#
CE2#/
CAD10
CE1#/
CCBE0#
I/O Read: This output goes active (low) for I/O
reads from the OZ6812 to the socket.
CardBus Address/Data: In CardBus mode, this
pin is the CAD bit 13.
I/O Write: This output goes active (low) for I/O
writes from the OZ6812 to the soc ket.
CardBus Address/Data: In CardBus mode, this
pin is the CAD bit 15.
Write Protect / I/O is 16-Bit: In Memory mode,
this input is indicates the status of the write
protect switch on the PC Card. I n I/O mode, this
input indicates the si ze of current dat a transf er on
the PC Card.
CardBus Clock Run: In CardBus m ode, this pin
is the CCLKRUN# signal, which starts and stops
the CardBus CCLK. To enable the CLKRUN#
signal, ExCA register 3Bh bit[3:2] must be
enabled.
Input Acknowledge: The INPACK# function is
not applicable in PCI bus environm ents. This pin
is provided for Legacy card compatibility.
CardBus Request: In CardBus m ode, this pin is
the CREQ# signal.
Ready / Interrupt Request: In Memory mode,
this input indi cates that the card i s ready or busy.
In I/O mode, t his input indicates a card interrupt
request.
CardBus Interrupt: In CardBus mode, this pi n is
the CINT# signal. This signal is active-low and
level-sensitive.
Wait: This pin is driven by the PC Card to delay
completion of the c urrent cycle.
CardBus System Error: In CardBus mode, thi s
pin is the CSERR# signal.
Card Detect: These inputs indicate a card is
present in the socket. They are internally pulled
high to AUX_VCC.
CardBus Card Detect: In CardBus mode, these
inputs are used with CV S[2:1] to detec t presence
and type of card.
Card Enable 2: This pin is driven low to control
byte/word card access. CE2# enables oddnumbered address bytes.
CardBus Address/Data: In CardBus mode, this
pin is the CAD bit 10.
Card Enable 1: This pin is driven low to control
byte/word card access. CE1# enables evennumbered address bytes. W hen configured for 8bit cards, CE1# is active and A0 is used to
indicate access of odd- or even-numbered bytes.
CardBus Command/Byte Enable:In CardBus
mode, this pin is the CCBEO# signal.
OZ6812
Pin Number
LQFP BGA
93 G10 TTL I/O Socket
96 F11 TTL I/O Socket
136 A4 TTL I/O-PU Socket
123 C8 - I-PU Socket
132 C6 - I-PU Socket
133 A5 TTL I-PU Socket
137, 75 C5, K10 TTL I-PU-
91 G13 TTL I/O Socket
88 H13 TTL I/O Socket
Input Type
Schmitt
Power
Rail
_Vcc
_Vcc
_Vcc
_Vcc
_Vcc
_Vcc
Aux_Vcc CardBus
_Vcc
_Vcc
Drive
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
CardBus
spec.
spec.
CardBus
spec.
CardBus
spec.
OZ6812-SF-1.5 Page 9
Page 10
Pin Name Description
RESET/
CRST#
BVD2/SPKR#/
LED / CAUDIO
BVD1/
STSCHG#/RI#/
CSTSCHG
VS[2:1]/
CVS[2:1]
SOCKET_VCC
Reset: This active high output res ets the card.
To prevent reset glitches, this signal is highimpedance unless a card is seated in the
socket, card power is applied, and the card’s
interface signals are enabled.
CardBus Reset: In CardBus mode, t his pin is
the CRST# output.
Battery Voltage Detect 2 / Speaker / LED: In
Memory mode, this input serves as the BVD2
(battery warning status) input. In I/ O mode, this
input can be configured as the card’s SPKR#
audio input or drive-active LED input.
CardBus Audio: In CardBus mode, this pin is
the CAUDIO input.
Battery Voltage Detect 1 / Status Change /
Ring Indicate: In Memory mode, this is the
BVD1 (battery-dead st atus) input. In I /O mode,
this is the STSCHG# input indicating that the
card’s internal status has changed, or the ring
indicates input for wakeup-on-ring system
power management support. See bit 7 of the
Interrupt and General Control register (03h).
CardBus Status Change: In CardBus mode,
this pin is the CSTSCHG. Thi s pin can be used
to generate PME#.
Voltage Sense: These pins are used in
conjunction with CD[2:1] to determ ine the type
and voltage of a card. Thes e pins are int ernally
pulled high to AUX_VCC. See Table 1.
CardBus Voltage Sense: In CardBus mode,
these pins are the CVS[2: 1] pi ns.
Socket Power: These pins are the power rail
input for the socket interface control logic.
These pins can be 0, 3. 3, or 5 V,. The socket
interface outputs will operate at the voltage
applied to these pins.
OZ6812
Pin Number
LQFP BGA
119 C9 TTL TO Socket
134 D6 - I-PU Socket
135 B5 - I-PU Socket
117, 131 D9, B6 TTL I/O-PU Aux_Vcc CardBus
90, 126 G11, C7 - PWR - -
Input Type
Power
Rail
_Vcc
_Vcc
_Vcc
Drive
CardBus
spec.
-
-
spec.
OZ6812-SF-1.5 Page 10
Page 11
OZ6812
Power, Ground, and Reserved Pins
Pin Name Description
Aux_VCC
CORE_VCC
PCI_VCC
GND
Auxiliary VCC: This pin is connected to the
system’s 3.3/5V power supply. For the device
to 5V tolerant, connect t o +5V power.
CORE_VCC: This pin provides power to the
core circuitry of the OZ6812. It must be
connected to a 3.3V power supply.
PCI Bus VCC: These pins can be connected to
either a 3.3V or5V power supply. The P CI bus
interface will operate at the voltage applied to
these pins, i ndependent of the voltage applied
to other OZ6812 pin groups.
System Ground
Pin Number
LQFP BGA
63 M9 - PWR - -
14, 66, 86,
102, 122,
138
18, 30, 44,
50
6, 22, 42,
58, 78, 94,
114, 130
F4, M10,
H10, D12,
D8, B4
G3, K2,
M4, K6
D3, H1,
L4, N8,
K11, F13,
C10, A6
Input Type
- PWR - -
- PWR - -
- GND - -
Legend
I/O Type Description Power Rail Source of Output’s Power
I Input Pin 1 AUX_VCC: outputs powered from AUX_VCC
I-PU Input pin with internal pull-up 2 SOCKET_VCC: outputs powered from the socket
I-PU Schmitt Input pin with internal pull-up and Schmitt
trigger
O Output
OD Open-drain 4 CORE_VCC: outputs powered from t he CORE _VCC
TO Tri-state output
TO-PU Tri -state output with internal pull-up
OD-PU Open-drain output with internal pull-up
PWR Power pin
3 PCI_VCC: outputs powered from PCI bus power
supply
Power
Rail
Drive
OZ6812-SF-1.5 Page 11
Page 12
Package Information - 144 Pin LQFP
Hd
D
He
E
A2A
OZ6812
1
Y
GAGE
PLANE
eb
0.25
L
0.08(0.003)
1
L
M
SYMBOL
A1
A2
b
c
D
E
e
Hd
He
L
L1
Y
c
MILLIMETERINCH
MIN. NOM. MAX. MIN. NOM. MAX.
0.05 0.10 0.15 0.002 0.004 0.006
1.35 1.40 1.45 0.053 0.055 0.057
0.17 0.22 0.27 0.007 0.009 0.011
0.0900.200 0.0040.008
20.000.787
20.000.787
0.500.020
22.000.866
22.000.866
0.45 0.60 0.75 0.018 0.024 0.030
1.000.039
0.080.003
0707
OZ6812-SF-1.5 Page 12
Page 13
144 Pin Mini - BGA
OZ6812
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
3. "N" REPRESENTS THE MAXIMUM NUMBER OF SOLDER BALLS FOR MATRIX SIZE
M1 AND M2.
4. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER AFTER
REFLOW AND PARALLEL TO PRIMARY DATUM Z, THE ORIGINAL SOLDER BALL
DIAMETER IS 0.45 mm.
5. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
6. A1 CORNER MUST BE IDENTIFIED BY INK MARK, METALLIZED MARKINGS,
IDENTATION OR OTHER FEATURE OF PACKAGE BODY, LID OR INTEGRAL
HEATSLUG, ON THE TOP SURFACE OF THE PACKAGE.
7. SOLDER BALL DEPOPULATION IS ALLOWED. DEPOPULATION IS THE OMISSION OF
BALLS FROM A FULL MATRIX (M1 OR M2).
8. BALL PAD A1 CORNER INDICATOR (NC) SOLDER BALL
OZ6812-SF-1.5 Page 13
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