Datasheet OQ8844 Datasheet (Philips)

Page 1
INTEGRATED CIRCUITS
DATA SH EET
OQ8844
Digital Servo Driver (DSD-2)
Product specification File under Integrated Circuits, IC01
1995 Nov 27
Page 2
Digital Servo Driver (DSD-2) OQ8844
FEATURES Servo functions
• 1-bit class-D focus actuator driver (3.3 Ω)
• 1-bit class-D radial actuator driver (3.7 Ω)
• 1-bit class-D sledge motor driver (2.5 Ω).

GENERAL DESCRIPTION

The OQ8844 or Digital Servo Driver 2 (DSD2) consists of 1-bit class-D power drivers, which are specially designed for digital servo applications. Three such amplifiers are integrated in one chip, to drive the focus and radial actuators and the sledge motor of a compact disc optical system.

Other features

• Supply voltage 5 V only
• Small package (SOT163-1)
• Higher efficiency, compared with conventional drivers,
due to the class-D principle
• Built-in digital notch filters for higher efficiency
The main benefits of using this principle are its higher efficiency grade compared to conventional analog power amplifiers, its higher integration level, its differential output and the fact that only a few external components are needed. When using these digital power drivers in a digital servo application, the statement ‘complete digital servo loop’ becomes more realistic.
• Enable input for focus and radial driver
• Enable input for sledge driver
• Differential outputs for all drivers
• Separate power supply pins for all drivers.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
DDD
V
DD(F)
V
DD(R)
V
DD(S)
I
DDDq
I
DD(F)
I
DD(R)
I
DD(S)
f
i(clk)
P
tot
T
amb
digital supply voltage 4.5 − 5.5 V supply voltage focus actuator 4.5 − 5.5 V supply voltage radial actuator 4.5 − 5.5 V supply voltage sledge actuator 4.5 − 5.5 V quiescent supply current digital part −−10 µA supply current focus − 126 250 mA supply current radial − 20 250 mA supply current sledge − 150 560 mA input clock frequency − 4.2336 5 MHz total power dissipation − 110 − mW operating ambient temperature −40 − +85 °C

ORDERING INFORMATION

TYPE
NUMBER
NAME DESCRIPTION VERSION
PACKAGE
OQ8844 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
1995 Nov 27 2
Page 3
Digital Servo Driver (DSD-2) OQ8844

BLOCK DIAGRAM

RAC
FOC
SLC
CLI
EN1 EN2
4
3
2
7 8
9
OQ8844
CONTROL
V
V
V
DD(R)
DDD
613141
DIGITAL
NOTCH FILTER
DIGITAL
NOTCH FILTER
DIGITAL
NOTCH FILTER
5101718
V
SS(R)
SSD
V
DD(F)
V
SS(F)
V
DD(S)
ENDSTAGE
H−BRIDGE
ENDSTAGE
H−BRIDGE
ENDSTAGE
H−BRIDGE
V
SSS
11 12
15 16
19 20
MBG785
RA+ RA−
FO+ FO−
SL+ SL−
Fig.1 Block diagram.
1995 Nov 27 3
Page 4
Digital Servo Driver (DSD-2) OQ8844

PINNING

SYMBOL PIN DESCRIPTION
V
DD(S)
SLC 2 PDM input for sledge driver FOC 3 PDM input for focus driver RAC 4 PDM input for radial driver V
SSD
V
DDD
CLI 7 clock input EN1 8 enable input 1 EN2 9 enable input 2 V
SS(R)
RA+ 11 radial driver (positive output) RA− 12 radial driver (negative output) V
DD(R)
V
DD(F)
FO+ 15 focus driver (positive output) FO− 16 focus driver (negative output) V
SS(F)
V
SSS
SL+ 19 sledge driver (positive output) SL− 20 sledge driver (negative output)
supply voltage for sledge motor
1
driver
5 digital ground 6 digital supply voltage
10 radial driver ground
13 radial supply voltage 14 focus supply voltage
17 focus ground 18 sledge driver ground
handbook, halfpage
V
V
1
DD(S)
2
SLC
FOC
3
RAC
4
V
5
SSD
V
DDD
CLI EN1 EN2 RA−
SS(R)
6 7 8 9
10
OQ8844
MBG784
Fig.2 Pin configuration.
20
SL− SL+
19
V
18
SSS
V
17
SS(F)
16
FO−
15
FO+ V
14
DD(F)
V
13
DD(R)
12 11
RA+
1995 Nov 27 4
Page 5
Digital Servo Driver (DSD-2) OQ8844
FUNCTIONAL DESCRIPTION Principle of a class-D digital power driver
Figure 3 shows the block diagram of one of the digital drivers integrated in the DSD2. It consists of a timing block and four CMOS switches. The input signal is a 1-bit Pulse Density Modulated (PDM) signal, the output of the digital servo ICs.
The maximum operating clock frequency of the device is 5 MHz. With the mentioned digital servo ICs, the operating frequency of the digital drivers is 4.2336 MHz (96 × 44.1 kHz). The sampling frequency of the 1-bit code however is 1.0584 MHz, so internally in the DSD2 the clock speed of the switches will be 1.0584 MHz. The higher input clock frequency is used to make non-overlapping pulses to prevent short-circuits between the supply voltages. For the control of the switches, two states can be distinguished. If the 1-bit code contains a logic 1, switches A and D are closed and current will flow in the direction as shown in Fig.4.
If the 1-bit code contains a logic 0, switches B and C are closed and current will flow in the opposite direction, as shown in Fig.5.
This indicates that the difference between the mean number of ones and zeros in the PDM signal determines the direction in which the actuator or motor will rotate.
half the sample frequency of 1.0584 MHz. This results in a high dissipation and the motor does not move.
To improve the efficiency, a digital notch filter is added at the input of the digital drivers. This filters the Idle mode pattern (1010101010 etc.) see Fig.6.
The amplitude transfer as a function of frequency is given in Fig.7.
Figure 7 shows that the filter has a zero on consequentially filtering out the idle pattern (101010). The output of this filter is a three-level code (1.5-bit). For the control of the switches three states (1.5-bit) can be distinguished: the two states as described earlier and a third one. This state is used when an idling pattern is supplied.
Switches C and D are closed (see Fig.8). In this idle mode, no current will flow and thus the efficiency will be improved. This mode is also used to short-circuit the inductive actuator/motor. In this way, high induction voltages are prevented because the current can commutate via the filter and the short-circuit in the switches. All three drivers (radial, focus and sledge) contain a digital notch filter as described. Each driver has its own power supply pins to reduce crosstalk because of the relative high current flowing through the pins.
1
⁄2fs,
If the mean number of ones and zeros is equal (Idle mode) the current through the motor or actuator is alternated between the positive and negative direction at a speed of
1995 Nov 27 5
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Digital Servo Driver (DSD-2) OQ8844
1-bit
code
TIMING
clock
MBG786
(1) Sledge motor; focus/radial motor.
Fig.3 One of the digital drivers.
V
DD
1-bit
code
(1)
M
V
SS
'1'
TIMING
clock
MBG787
(1) Sledge motor; focus/radial motor.
V
DD
I
pos
AB
(1)
M
CD
V
SS
Fig.4 1-bit code is logic 1.
V
DD
I
neg
1-bit
code
'0'
TIMING
clock
MBG788
(1) Sledge motor; focus/radial motor.
AB
(1)
M
CD
V
SS
Fig.5 1-bit code is logic 0.
1995 Nov 27 6
1-bit 1.5-bit
The filter consists of a simple delay element (flip-flop) and an adder. The transfer from input-to-output is: H(z) =1 + z
1/Z
MBG789
−1
.
Fig.6 Notch filter at input of digital drivers.
Page 7
Digital Servo Driver (DSD-2) OQ8844
|H|
MBG790
1/2f
s
Fig.7 Amplitude transfer.

Switches

The digital part of the power drivers consists of standard cells. The power switches are specifically designed for CD applications. The most important feature is their on-resistance. In the applications, they have to drive very low-ohmic actuators and/or motors. The switches are designed to have an on-resistance of 2 Ω for the actuator drivers and 1 Ω for the sledge motor driver. In any mode, there are always two switches in series with the actuator/motor. The total loss due to the switches is 4 Ω for the actuators and 2 Ω for the sledge motor.

Timing of input and output signals

All internal timing signals are derived from the externally supplied CLI signal.
V
DD
1-bit
code
'idle'
TIMING
clock
MBG791
(1) Sledge motor; focus/radial motor.
AB
(1)
M
CD
I
idle
V
SS
Fig.8 Idling pattern.
The switching of the outputs occurs in a similar way, except that in this event the negative edge of CLI is used. In this way, the input signals are immune to the noise radiated by the switching of the outputs. It is possible that an output transition will have a noticeable effect on the power supply voltage or the ground voltage. To avoid simultaneous transitions of all outputs, the outputs of each bridge are also clocked at a different phase of CLI. Consequentially there are only 3 out of 4 negative edges effective.
To reset the circuit, both the reset condition and the clock should be present, because all flip-flops are reset synchronously. The clock signal is also required to obtain one of the possible modes of operation indicated in Table 1.
Sampling of the data inputs (SLC, FOC and RAC) occurs at a frequency of
1
⁄4CL. For each channel, the clocking-in
occurs at a different positive edge of CLI. Because there are only 3 channels, and the clock frequency CLI is divided-by-4, only 3 out of 4 positive edges are effective for sampling one of the inputs.
1995 Nov 27 7
Page 8
Digital Servo Driver (DSD-2) OQ8844
Table 1 Possible modes of operation
EN1 EN2 SLEDGE DRIVER
FOCUS/RADIAL
DRIVER
0 0 off off standby 0 1 off on partly operating 1 0 off off reset 1 1 on on operating
The timing diagram as shown in Fig.9 gives the relation between the different clocks. The negative edge of the signals called nc10 to nc12 is used to process the incoming data (see Table 2). The negative edge of all signals called c10s to c12s is used to trigger the outputs (see Table 2).
Table 2 Signals nc10 to nc12 and c10s to c12s
SIGNAL DESCRIPTION
ncl0 sledge input sampling clock ncl1 focus input sampling clock ncl2 radial input sampling clock
cl0s sledge output trigger clock cl1s focus output trigger clock cl2s radial output trigger clock
MODE

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER MIN. MAX. UNIT
V
DDD
V
DDA
V
− V
SSD
P
tot
T
stg
T
amb
SSA
digital supply voltage −0.5 +6.5 V analog supply voltage −0.5 +6.5 V ground supply voltage difference −5+5mV total power dissipation − 730 mW storage temperature −55 +150 °C operating ambient temperature −40 +85 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT
R
th j-a
thermal resistance from junction to ambient in free air 75 K/W
1995 Nov 27 8
Page 9
Digital Servo Driver (DSD-2) OQ8844

CHARACTERISTICS

V
DDD=VDDA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DDD
V
DDA
I
DDDq
I
DD(F)max
I
DD(R)max
I
DD(S)max
f
i(clk)
P
tot
T
amb
Digital inputs; SLC, FOC, RAC, CLI, EN1 and EN2
V
IL
V
IH
I
LI
Clock input; CLI
f
clk
Analog outputs; FO+ and FO−
I
O
R
O
Analog outputs; RA+ and RA−
I
O
R
O
Analog outputs; SL+ and SL−
I
O
R
O
=5V; V
SSD=VSSA
=0V; T
=25°C; unless otherwise specified.
amb
supply voltage digital part 4.5 − 5.5 V supply voltage analog part 4.5 − 5.5 V quiescent supply current digital
−−10 µA
part maximum supply current focus note 1 − 126 250 mA maximum supply current radial note 1 − 20 250 mA maximum supply current sledge note 1 − 150 560 mA input clock frequency − 4.2336 5 MHz totalpower dissipation − 110 − mW operating ambient temperature −40 − +85 °C
LOW level input voltage T HIGH level input voltage T
= −40 to 85 °C −−0.2V
amb
= −40 to 85 °C 0.8V
amb
DDD
−− V
DDD
V
input leakage current −−1µA
clock frequency − 4.2336 5 MHz
output current −−250 mA output resistance note 2 − 3.3 4.1 Ω
output current −−250 mA output resistance note 2 − 3.7 4.6 Ω
output current −−560 mA output resistance note 2 − 2.5 3.1 Ω
Notes
V
DDA max
1. Maximum supply current depends on the value of R
L
=
:
I
max
---------------------------­RORL+()
2. Output resistance is defined as the series resistance of the complete bridge.
1995 Nov 27 9
Page 10
1995 Nov 27 10
inputs
outputs
full pagewidth
MBG792
CLI
SLC
FOC
RAC
ncI0
ncI1
ncI2
cI0s
cI1s
cI2s
SL+
SL−
FO+
FO−
RA+
RA−

Timing diagram

Digital Servo Driver (DSD-2) OQ8844
Philips Semiconductors Product specification
Sampling of the incoming data is marked by a ‘∗’.
Fig.9 Timing diagram.
Page 11
Digital Servo Driver (DSD-2) OQ8844

PACKAGE OUTLINE

SO20: plastic small outline package; 20 leads; body width 7.5 mm
D
c
y
Z
20
pin 1 index
1
e
11
A
2
10
w M
b
p

SOT163-1

E
H
E
Q
A
1
L
p
L
detail X
(A )
A
X
v M
A
A
3
θ
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
mm
OUTLINE VERSION
SOT163-1
A
max.
2.65
0.10
A
1
0.30
0.10
0.012
0.004
A2A
2.45
2.25
0.096
0.089
IEC JEDEC EIAJ
075E04 MS-013AC
0.25
0.01
b
3
p
0.49
0.32
0.36
0.23
0.019
0.013
0.014
0.009
UNIT
inches
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
(1)E(1) (1)
cD
13.0
7.6
7.4
0.30
0.29
1.27
0.050
12.6
0.51
0.49
REFERENCES
1995 Nov 27 11
eHELLpQ
10.65
10.00
0.419
0.394
1.4
0.055
1.1
0.4
0.043
0.016
1.1
1.0
0.043
0.039
PROJECTION
0.25
0.25 0.1
0.01
0.01
EUROPEAN
ywv θ
Z
0.9
0.4
0.035
0.004
0.016
ISSUE DATE
95-01-24 97-05-22
o
8
o
0
Page 12
Digital Servo Driver (DSD-2) OQ8844
SOLDERING Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“IC Package Databook”
Reflow soldering
Reflow soldering techniques are suitable for all SO packages.
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.
(order code 9398 652 90011).
Wave soldering
Wave soldering techniques can be used for all SO packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
• The longitudinal axis of the package footprint must be parallel to the solder flow.
• The package footprint must incorporate solder thieves at the downstream end.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
1995 Nov 27 12
Page 13
Digital Servo Driver (DSD-2) OQ8844

DEFINITIONS

Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1995 Nov 27 13
Page 14
Digital Servo Driver (DSD-2) OQ8844
NOTES
1995 Nov 27 14
Page 15
Digital Servo Driver (DSD-2) OQ8844
NOTES
1995 Nov 27 15
Page 16
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SCD45 © Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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Printed in The Netherlands
513061/50/01/pp16 Date of release: 1995 Nov 27 Document order number: 9397 750 00471
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