Datasheet OQ2541HP Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

OQ2541HP

SDH/SONET data and clock
recovery unit STM1/4/16
OC3/12/48

Preliminary specification
Supersedes data of 1998 Feb 09
File under Integrated Circuits, IC19

1999 Mar 19

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit

OQ2541HP

STM1/4/16 OC3/12/48

FEATURES

• Data and clock recovery up to 2.5 Gbits/s (STM1/OC3,
STM4/OC12 and STM16/OC48)

• Differential data input with 2.5 mV peak-to-peak typical
sensitivity

• Differential CML (Current-Mode Logic) data and clock
outputs with 50 Ω driving capability

• Adjustable CML output level

• Loop mode for system testing

• BER related LOS detection

• Few external components needed

• LQFP48 plastic package

• Power dissipation typical 350 mW

• Single supply voltage.

ORDERING INFORMATION

TYPE

NUMBER

OQ2541HP LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

NAME DESCRIPTION VERSION

DESCRIPTION

The OQ2541HP is a data and clock recovery IC intended
for use in SDH (Synchronous Digital Hierarchy) and
SONET (Synchronous Optical Network) systems.
The circuit recovers data and extracts the clock signal from
an incoming bitstream up to 2.5 Gbits/s. It can be
configured for use in STM1/OC3, STM4/OC12 and
STM16/OC48 systems.

APPLICATIONS

• Data and clock recovery in STM1/OC3, STM4/OC12
and STM16/OC48 transmission systems (up to

2.5 Gbits/s).

PACKAGE

1999 Mar 19 2

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

BLOCK DIAGRAM

handbook, full pagewidth

DCSQ

DIN

DINQ

36

33

34

LOS

39

ALEXANDER

PHASE

DETECTOR

enable

DOUT_622

DOUT_1250

27

FREQUENCY

DIVIDER 1

1/2/4/16

OQ2541HP

DOUT_155

28

30

AREF

DATA

CLOCK

OUTPUT

48

AND

ENL

OQ2541HP

1

42
43
45
46

6
7
3
4

DOUT
DOUTQ
COUT
COUTQ
DLOOP
DLOOPQ
CLOOP
CLOOPQ

CREF

CREFQ

21
22

17 2

2, 5, 8, 10, 11, 14, 17,
20, 23, 26, 29, 32, 35,
38, 41, 44, 47

GND

FREQUENCY

WINDOW

DETECTOR

(1000 ppm)

FREQUENCY

12 24 25, 31

DREF_19LOCK

+

DIVIDER 2

64/128

9

CAPDOQDREF_39

∫ dt

CAPUPQ

proportional

path

integrating

path

130 pF130 pF

1516

VCRO

2.5 GHz

POWER

CONTROL

V

EE

37

MBH972

PC

Fig.1 Block diagram.

1999 Mar 19 3

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

PINNING

SYMBOL PIN DESCRIPTION

ENL 1 loop mode enable input (active low)
GND 2 ground
CLOOP 3 clock output in loop mode (differential)
CLOOPQ 4 inverted clock output in loop mode (differential)
GND 5 ground
DLOOP 6 data output in loop mode (differential)
DLOOPQ 7 inverted data output in loop mode (differential)
GND 8 ground
DREF_19 9 reference frequency select input (see Table 1)
GND 10 ground
GND 11 ground
LOCK 12 phase lock detection output
i.c. 13 internally connected (leave open)
GND 14 ground
CAPUPQ 15 external loop filter capacitor
CAPDOQ 16 external loop filter capacitor return
GND 17 ground
i.c. 18 internally connected (leave open)
i.c. 19 internally connected (leave open)
GND 20 ground
CREF 21 reference clock input (differential)
CREFQ 22 inverting reference clock input (differential)
GND 23 ground
DREF_39 24 reference frequency select input (see Table 1)
V

EE

GND 26 ground
DOUT_1250 27 STM mode select input (see Table 2)
DOUT_622 28 STM mode select input (see Table 2)
GND 29 ground
DOUT_155 30 STM mode select input (see Table 2)
V

EE

GND 32 ground
DIN 33 data input (differential)
DINQ 34 inverting data input (differential)
GND 35 ground
i.c. 36 internally connected (leave open)
PC 37 negative power supply control signal output
GND 38 ground
LOS 39 loss-of-signal detection output
i.c. 40 internally connected (leave open)

25 negative supply voltage

31 negative supply voltage

OQ2541HP

1999 Mar 19 4

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit

OQ2541HP

STM1/4/16 OC3/12/48

SYMBOL PIN DESCRIPTION

GND 41 ground
DOUT 42 data output in normal mode (differential)
DOUTQ 43 inverted data output in normal mode (differential)
GND 44 ground
COUT 45 clock output in normal mode (differential)
COUTQ 46 inverted clock output in normal mode (differential)
GND 47 ground
AREF 48 reference voltage input for controlling voltage swing on data and clock outputs

handbook, full pagewidth

ENL

GND

CLOOP

CLOOPQ

GND

DLOOP

DLOOPQ

GND

DREF_19

GND
GND

LOCK

COUTQ

GND
47

14

GND

COUT

46

45

15

16

CAPUPQ

CAPDOQ

GND
44

OQ2541HP

17

GND

AREF
48

1
2
3
4
5
6
7
8

9
10
11
12

13

i.c.

DOUT

DOUTQ
43

42

18

19

i.c.

i.c.

GND
41

20

GND

i.c.
40

21

CREF

GND

LOS
39

38

22

23

GND

CREFQ

PC

36
35
34
33
32
31
30
29
28
27
26
25

24 37

MBH971

DREF_39

i.c.

i.c.
GND
DINQ
DIN
GND

V

EE
DOUT_155
GND
DOUT_622
DOUT_1250
GND
V

EE

Fig.2 Pin configuration.

1999 Mar 19 5

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

FUNCTIONAL DESCRIPTION

The OQ2541HP recovers data and clock signals from an
incoming high speed bitstream. The input signal on DIN,
DINQ is buffered and amplified by the input circuitry.

The signal is then fed to the Alexander phase detector
where the phase of the incoming data is compared with
that of the internal clock. If the signals are out of phase, the
phase detector generates (UP or DOWN) correction
pulses that shift the phase of the VCRO (Voltage
Controlled Ring Oscillator) output in discrete amounts, ∆ϕ,
until the clock and data signals are in phase.
The technique used is based on principles first proposed
by J.D.H. Alexander, hence the phase detector’s name.

The eye pattern of the incoming data is sampled at three
instants A, T and B (see Fig.3). When clock and data
signals are synchronized (locked), A is in the centre of the
data bit, T is in the vicinity of the next transition, and B is in
the centre of the bit following the transition. If the same
level is recorded at both A and B, a transition has not
occurred and no action is taken regardless of the value
at T. If A and B are different, however, a transition has
occurred and the phase detector uses the value at T to
determine whether the clock was too early or too late with
respect to the data transition. If A and T are the same, but
different from B, the clock was too early and needs to be
slowed down a little. The Alexander phase detector then
generates a DOWN pulse which stretches a single output
pulse from the ring oscillator by approximately 0.25% (or
1 ps in STM16 mode; 1 ps is 0.25% of the 400 ps bit
period). This forces the VCRO to run at a slightly lower
frequency for one bit period. The phase of the clock is thus
shifted fractionally with respect to the data.

OQ2541HP

of the clock signal, while the integrating path adjusts the
centre frequency.

The frequency window detector checks that the VCRO
frequency is within a 1000 ppm (parts per million) window
around the required frequency. It compares the output of
frequency divider 2 with the reference frequency at CREF,
CREFQ (19.44 MHz or 38.88 MHz as available; see
Table 1). If the VCRO frequency is found to be outside this
window, the frequency window detector disables the
Alexander phase detector and forces the VCRO output to
a frequency within the window. The phase detector then
starts acquiring lock again. Because of the loose coupling
(1000 ppm), the reference frequency doesn’t need to be
highly accurate or stable. Any crystal based oscillator that
generates a reasonably accurate frequency (e.g. 100ppm)
will do.

Since sampling point A is always in the centre of the eye
pattern when the data and clock signals are in phase
(locked), the values recorded at this point are taken as the
retrieved data. The data and clock signals are available at
the CML output buffers, which are capable of driving a
50 Ω load.

handbook, halfpage

DATADATA

ATB

CLOCK

MGK143

Fig.3 Data sampling.

If, on the other hand, B and T are the same but different
from A, the clock was too late and needs to be speeded up
for synchronization. The phase detector generates an UP
pulse forcing the VCRO to run at a slightly higher
frequency (+0.25%) for one bit period. The phase of the
clock is shifted with respect to the data (as above, but in
the opposite direction). Only the proportional path is active
while these phase adjustments are being made. Because
the instantaneous frequency of the VCRO can be changed
only in one of two discrete steps (±0.25%), this type of loop
is also known as a Bang/Bang PLL.

If not only the phase but also the frequency of the VCRO
is incorrect, a long train of UP or DOWN pulses will be
generated. This pulse train is integrated to generate a
control voltage that is used to shift the centre frequency of
the VCRO. Once the correct frequency has been
established, the phase will need to be adjusted for
synchronization. The proportional path adjusts the phase

1999 Mar 19 6

Power Control (PC)

The OQ2541HP contains an on-board voltage regulator.
An external power transistor is needed to deliver supply
current, IEE, to this circuit. The required external circuit is
straightforward, and can be built using a few components.
A suitable circuit is depicted in Fig.21. A different
configuration could be used, as long as the power supply
rejection ratio is greater than 60 dB for all frequencies.
The inductor is a (lossy) 1 µH RF-choke (EMI) with an
impedance greater than 50 Ω at frequencies higher than
2 MHz. Any transistor with a β > 100 and enough current
sink capability can be used.

The OQ2541HP can also be used with a -5V or -5.2V
supply voltage. The only adaption that has to be made to
the Power Control circuit is resistor R of 2Ω. This should
be 6.8Ω with a -5V supply and 8.2Ω with a -5.2V supply.

Philips Semiconductors Preliminary specification



SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

handbook, full pagewidth

BAND GAP
REFERENCE

V

100 nF

2 Ω

1 kΩ

EE

β > 100

R1

2 Ω

kΩ

OQ2541HP

OQ2541

PC

3.3

1

nF

1 µF

L1

MGK141

−4.5 V

Fig.4 Schematic diagram of OQ2541HP power control loop.

Output amplitude reference (AREF)

The voltage swing at the CML compatible output stages
DOUT, DOUTQ; COUT, COUTQ; DLOOP, DLOOPQ and
CLOOP, CLOOPQ can be controlled by adjusting the
voltage at the AREF pin. An internal voltage divider of
500 Ω and16 kΩ between GND and VEE initially fixes this
level.

In most applications the outputs will be DC coupled to a
load, which can be as low as 50 Ω (±0.20%). The output
level regulation circuit will maintain a 200 mV
peak-to-peak single-ended swing across this load.
The voltage at AREF is half the single-ended peak-to-peak
value of the output signal (or −100 mV in this case).
No adjustments are necessary with DC coupling.

If the outputs are AC coupled, however, the voltage at
AREF is half the single-ended peak-to-peak value of the

+

R

output signal multiplied by a factor

where R

is the external load and Ro is the output

L

LRo

-------------------­R

L

impedance of the OQ2541HP.

This can be achieved by connecting a 7.3 kΩ resistor
between AREF and V

EE

.

The formulae for calculating the required voltage at AREF
and the external resistance needed between AREF and
V

when the outputs are AC coupled are:

EE

V

AREF

RLRo+

-------------------­R

1

V

×–=

-- -

swing

2

L

(1)

and:

V

EE



R1

×

---------------- ­V



R

AREF

=

----------------------------------------------------------------




–

1



AREF



R1



×

------- ­R2



where R1 = 500 Ω, R2 = 16 kΩ and V

V

EE

---------------- ­V

AREF

1–

(2)

1–

= −3.3 V. R

EE

AREF

is connected between AREF and VEE.

To maintain a 200 mV peak-to-peak single-ended swing
across a 50 Ω AC coupled load, the voltage at AREF must

100 mV– 50 Ω 100 Ω+()×

be .

-------------------------------------------------------------------------

1999 Mar 19 7

50 Ω

300 mV–=

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

Loop mode enable (ENL)

Loop mode is provided for system testing. Loop mode is
enabled by applying a voltage lower than 0.8 V (TTL LOW)
to the ENL pin. This selects loop mode outputs DLOOP,
DLOOPQ and CLOOP, CLOOPQ. If a voltage greater than

2.0 V (TTL HIGH) is applied to ENL, then DOUT, DOUTQ
and COUT, COUTQ are switched in while DLOOP,
DLOOPQ and CLOOP, CLOOPQ are disabled to minimize
power consumption. If ENL is connected to VEE(−3.3 V),
all outputs are enabled.

External capacitor for loop filter (CAPUPQ; CAPDOQ)

The loop filter is an integrator with a built in capacitance of
2 × 130 pF. An external 200 nF capacitance must be
connected between CAPUPQ and CAPDOQ to ensure
loop stability while the frequency window detector is
active.

Lock detection (LOCK)

The LOCK pin should be interpreted as an indication if the
reference clock (CREF) is present and if the acquisition aid
(frequency window detector) is working properly.
The LOCK pin is an open collector TTL output and should
be pulled up with a 10kΩ resistor to the positive supply.
If the VCO frequency is within a 1000 ppm window around
the desired frequency the LOCK pin will go HIGH. If no
reference clock is present, or the VCO is outside the 1000
ppm window, the LOCK pin will be LOW. The logic level of
LOCK does not indicate if the PLL is locked onto the
incoming data; this is indicated by the LOS signal.

OQ2541HP

Loss-of-signal detection (LOS)

The Loss of Signal (LOS) function is closely related to the
Alexander Phase Detector functionality. Refer to Fig.3 for
the meaning of A,B and T in this section.

In the functional description it is described that the phase
detector doesn’t take any action if the value at sample
points A and B is the same, because there hasn’t been any
transition. However, if the values at A and B are the same,
but different from T, this still means there hasn’t been any
transition, but somehow T got the wrong value. This is
probably due to noise or bad signal integrity, which will
lead to a Bit Error. Hence the occurrence of this particular
situation is an indication for Bit Errors. If too many of these
Bit Errors occur per time and the PLL is gradually losing
lock, the LOS alarm is asserted. The LOS assert level is
around a Bit Error Rate (BER) of 5⋅10
level is around BER of 1⋅10-3.

The LOS detection is BER related, but neither dependent
of datastream content, nor protocol. Therefore, a
SDH/SONET datastream is no prerequisite for a proper
LOS function. Since the LOS function of the OQ2541HP is
derived from digital signals, it is a good supplement to an
analog, amplitude based, LOS indication.

The LOS alarm is an open collector TTL compatible
output. A pull-up resistor should be connected to a positive
supply. LOS will be HIGH (TTL) if the data signal is absent
at DIN, DINQ or BER is > 5⋅10-2, otherwise it will be LOW
(BER < 1⋅10-3).

-2

and the de-assert

Reference frequency select (DREF_19, DREF_39)

A reference clock signal (either 19.44 MHz or 38.88 MHz, whichever is available) must be connected to CREF and
CREFQ. Pins DREF_19 and DREF_39 are used to select the appropriate output frequency at frequency divider 2. Since
the reference clock is only used as acquisition aid for the PLL (Frequency Window Detector), the quality of the reference
clock is not important. There is no phase noise specification imposed on the reference clock generator and even
frequency stability may be in the order of 100 ppm. In general most inexpensive crystal based oscillators are suitable.

Table 1 Reference Frequency Select

FREQUENCY

MHz

19.44 128 V

38.88 64 GND V

1999 Mar 19 8

DIV # DREF_19 DREF_39

EE

V

EE
EE

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit

OQ2541HP

STM1/4/16 OC3/12/48

STM mode select (DOUT_155, DOUT_622, DOUT_1250)

All three mode select pins should be connected to GND for STM16 (2488.32 Mbits/s) operation. The dividers are daisy
chained, so both DOUT_1250 and DOUT_622 must be connected to VEE in STM4 (622.08 Mbits/s) mode. All three pins
must be connected to VEE in STM1 mode (see Table 2). The connections to VEE and GND should have low resistance
and inductance; short PCB tracks are recommended.

Table 2 STM Mode Select

MODE

STM1 155.52 16 V
STM4 622.08 4 GND V
STM16 2488.32 1 GND GND GND

BIT RATE

Mbits/s

DIV # DOUT_155 DOUT_622 DOUT_1250

EE

V

EE
EE

V

EE

V

EE

1999 Mar 19 9

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit

OQ2541HP

STM1/4/16 OC3/12/48

POSITIVE SUPPLY APPLICATION

Due to the versatile design of the OQ2541HP, the device can also operate in a positive supply application, although some
pins have a different mode of operation. This section deals with these differences and supports the user with successful
application of the OQ2541HP in a +5V environment. A sample application diagram can be found in figure 21. Note that
all GND pins are now connected to VCC. All VEE pins are not connected to ground, but to pin 25, the regulated voltage
from the power controller.

Loop mode and normal mode output select (

In a positive supply application, the default RF output will be the LOOP MODE outputs. Due to the decoding logic at the
ENL pin, it is only possible to select the pins DLOOP(Q) and CLOOP(Q) as outputs or enable all outputs. If ENL is
connected to VCC (+5V), the LOOP MODE outputs are active. All outputs become active If ENL is connected to pin VEE
(the voltage on pin 25 is approximately 3.3V below VCC). Beware not to connect ENL to ground, this would destroy the
IC. In the positive supply application the NORMAL MODE outputs can not be selected anymore.

Loss of signal detect and Lock detect (LOS & LOCK)

In the negative supply application, LOS and LOCK are open collector outputs, that require pull-up resistors to a positive
supply. In the positive supply application, the pull-up voltage would be higher then the positive supply and the LOS and
LOCK signals would not be TTL compatible. The internal circuit at pins LOS and LOCK can however be used in a current
mirror configuration. It requires only an external PNP transistor, BC857 or equivalent, to mirror the current. A 10kΩ
pull-down resistor to ground yields a TTL compatible signal again, albeit inverted. The table below shows the meaning
of the LOS and LOCK flag, when used according to the application schematic of figure 21.

ENL)

Table 3 LOS and LOCK indication for positive supply

SIGNAL DESCRIPTION LEVEL TTL

LOS active Loss-of-signal; BER >5 10
LOS inactive No loss-of-signal; BER < 1 10
LOCK active Reference clock present and VCO in 1000 ppm window 0V (ground) LOW
LOCK inactive No reference clock present or VCO outside 1000 ppm window +5V (VCC) HIGH

Divider settings

The reference frequency dividers and the STM mode selectors still operate the same in a positive supply application.
The only difference is that pins formerly connected to GND (ground) should now be connected to VCC (+5V), whereas
pins connected to VEE still should be connected to pin VEE (pin 25). Connection to ground (0V) will damage the IC.

RF input/outputs

All RF inputs, outputs and internal signals of the OQ2541HP are referenced to the most positive supply, pins GND.
In the positive supply application, this means all RF signals are referenced to VCC. Therefore a clean VCC rail is of
ultimate importance for proper RF performance. The best performance is obtained when the transmission line reference
plane is also decoupled to the VCC. Careful design of VCC and good decoupling schemes should be taken into account.
While designing the printed circuit board, bear in mind that the VCC has become what was formerly ground.

-2

-3

0V (ground) LOW

+5V (VCC) HIGH

1999 Mar 19 10

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit

OQ2541HP

STM1/4/16 OC3/12/48

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

EE

V

n

I

n

P

tot

T

amb

T

j

T

stg

negative supply voltage −6 +0.5 V
DC voltages

pins 3, 4, 6, 7, 21, 22, 33, 34, 42, 43, 45, 46
pins 1, 12, 39
pins 9, 24, 27, 28, 30, 37, 48
pins 15, 16

−1
VEE− 0.5
VEE− 0.5
VEE+ 0.5

+0.5
+5.5
+0.5

−0.5

V
V

V
V

input current

pin 1 − 1mA

pins 21, 22, 33, 34 −20 +10 mA
total power dissipation − 700 mW
ambient temperature −40 +85 °C
junction temperature −40 +110 °C
storage temperature −65 +150 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R
R

th(j-s)
th(j-a)

thermal resistance from junction to solder point 46 K/W
thermal resistance from junction to ambient in free air 67 K/W

Note

1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single sided
57x57x1.6mm FR4 epoxy PCB with 35µm thick copper traces. The measurements are performed in still air.

1999 Mar 19 11

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit

OQ2541HP

STM1/4/16 OC3/12/48

CHARACTERISTICS

External supply voltage = −4.5 V; T

= -40°C to +85°C; Typical values at T

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

EE

I

EE

negative supply voltage note 1 −3.50 −3.30 −3.10 V
negative supply current open outputs − 105 155 mA

P power dissipation − 350 550 mW

Data and Clock inputs: DIN, DINQ and CREF, CREFQ

V

i(p-p)

V

sens(p-p)

input voltage (peak-to-peak)
input sensitivity (peak-to-peak)

(2)(3)

50 Ω measurement system 7 200 450 mV

(2)(4)

VIO input offset voltage −3 0 +3 mV
VI, V
Z

i

IQ

input voltages −600 −200 +250 mV
single ended input impedance

(5)

Data and Clock outputs: DOUT, DOUTQ; DLOOP, DLOOPQ; COUT, COUTQ and CLOOP, CLOOPQ

V

o(p-p)

voltage swing (single ended)
voltage swing (single ended)

(6)

50 Ω measurement system 170 200 210 mV

(7)

=25°C; all voltages referenced to GND.

amb

− 2.5 7 mV

− 50 −Ω

50 − 400 mV

VO, V
Z

o

t

, t

r

f

output voltages −600 − 0mV

OQ

single ended output impedance − 100 −Ω
rise/fall time differential

data outputs − 116 − ps
clock outputs − 54 − ps

t

d

data to clock delay note 8 50 80 110 ps

Output amplitude adjustment: AREF

V

AREF

output amplitude reference voltage floating pin −110 −100 −90 mV

Power Control output: PC

g

m

I

O

Loop mode enable input:

V

IL

V

IH

transconductance −84 −60 −42 mA/V
output current 1 − 3.5 mA

ENL

LOW-level input voltage −− 0.8 V
HIGH-level input voltage 2.0 −−V

Phase lock and loss-of-signal indicators: LOCK and LOS

V

OL

V

OH

t

a

t

d

BER

LOS

HIGH-level output voltage note 9 −0.6 −−V
LOW-level output voltage note 9 −− 3.3 V
LOS assert time note 10 − 0.1 − µs
LOS de-assert time −10 −µs
LOS assert Bit Error Rate − 5 ⋅10
LOS de-assert Bit Error Rate − 1 ⋅10

−2

−3

− BER

− BER

1999 Mar 19 12

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit

OQ2541HP

STM1/4/16 OC3/12/48

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

PLL Characteristics

t

acq

J

tol(p-p)

TDR transitionless data run note 12 − 2000 − bits

acquisition time CREF = 19.44 MHz − 100 200 µs

CREF = 38.88 MHz − 50 200 µs

(11)

jitter tolerance (peak-to-peak) STM1/OC3 mode

f = 6.5 kHz 1.5 >5 − UI
f = 65 kHz 0.15 1.3 − UI
f = 1 MHz 0.15 0.8 − UI

STM4/OC12 mode

f = 25 kHz 1.5 >5 − UI
f = 100 kHz 0.7 3 − UI
f = 250 kHz 0.15 1.3 − UI
f = 1 MHz 0.15 0.50 − UI
f = 5 MHz 0.15 0.35 − UI

STM16/OC48 mode

f = 100 kHz 1.5 11 − UI
f = 1 MHz 0.15 1.1 − UI
f = 10 MHz 0.15 0.23 − UI

Notes

1. Typical supply voltage for the voltage regulator is −4.5 V (see Fig.21).

2. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value. (true
differential excitation)

3. The specified input voltage range is the guaranteed and tested range for proper operation; BER <10

4. An input sensitivity for BER <10

-10

of 7 mVpp is guaranteed. Typical input sensitivity for BER <10

-10

.

-10

is 2.5mVpp.

5. CML inputs are terminated internally using 50 Ω on-chip resistors to ground (GND).

6. Output voltage range with default reference voltage on AREF (floating pin).

7. Output voltage range with adjustment of voltage on AREF (see section “Output amplitude reference (AREF)”).

8. Data to clock delay according to figure 5. Measured with 1010 data pattern, single ended output signals and rising
edge of COUT to DOUT or CLOOP to DLOOP. Note that small deviations from specified value are possible if
differentially measured.

9. External 10 kΩ pull-up resistor to +3.3 V.

10. LOS assert/de-assert timing and BER level are for indication only. The values are neither production tested nor
guaranteed.

11. Measured according ITU specification G.958 on the OM5801 STM16 demoboard. See application note AN96051.

12. TDR is bitrate independent.

1999 Mar 19 13

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

handbook, full pagewidth

V

I(max)

V

IQH

V

IH

V

IQL

V

IL

V

I(min)

COUT or
CLOOP

CML INPUT

V

IO

GND

V

i(p-p)

Fig.5 Logic level symbol definitions for CML.

V

O(max)

V

V

V

O(min)

OQH

V

OH

OQL

V

OL

CML OUTPUT

V

OO

GND

-200mV

OQ2541HP

GND

V

o(p-p)

MGK144

DOUT or
DLOOP

t

d

GND

-200mV

Fig.6 Data to clock delay for CML outputs; COUT to DOUT or CLOOP to DLOOP.

1999 Mar 19 14

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

TYPICAL PERFORMANCE CHARACTERISTICS

140

120

100

80

IEE (mA)

60

40

20

0

-40 -20 0 20 40 60 80
T (deg C)

OQ2541HP

-3.30

-3.35

-3.40

VEE (V)

-3.45

-3.50

-40 -20 0 20 40 60 80
T (deg C)

Fig.7 IEE versus Temperature.

100

90
80
70
60
50

td (ps)

40
30
20
10

0

-40 -20 0 20 40 60 80
T (deg C)

Fig.8 VEE versus Temperature. Note that the

voltage on pin VEE is regulated by the
power controller

Fig.9 DATA to CLOCK delay versus

Temperature. (see figure 5 for definition)

1999 Mar 19 15

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

TYPICAL PERFORMANCE CHARACTERISTICS

70
68
66
64
62
60

tf (ps)

58
56
54
52
50

-40 -20 0 20 40 60 80
T (deg C)

OQ2541HP

(CONTINUED)

80
78
76
74
72
70

tr (ps)

68
66
64
62
60

-40 -20 0 20 40 60 80
T (deg C)

Fig.10 Clock output fall time versus Temperature.

Measured on single ended output.

110

105

100

95

90

tf (ps)

85

80

75

70

-40 -20 0 20 40 60 80
T (deg C)

Fig.12 Data output fall time versus Temperature.

Measured on single ended output

Fig.11 Clock output rise time versus Temperature.

Measured on single ended output.

170

165

160

155

tr (ps)

150

145

140

-40 -20 0 20 40 60 80
T (deg C)

Fig.13 Data output rise time versus Temperature.

Measured on single ended output.

1999 Mar 19 16

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)

1.0E+0

1.0E-1

1.0E-2

1.0E-3

1.0E-4

OQ2541HP

1.0E-5

BER

1.0E-6

1.0E-7

1.0E-8

1.0E-9

1.0E-10

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Vin(p-p) in mV

Fig.14 Bit Error Rate versus input signal on DI/DIQ in STM1 mode(155.52 Mbits/s).

(A complementary input signal of the indicated value is applied to DI and DIQ).

1999 Mar 19 17

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)

1.0E+0

1.0E-1

1.0E-2

1.0E-3

OQ2541HP

1.0E-4

1.0E-5

BER

1.0E-6

1.0E-7

1.0E-8

1.0E-9

1.0E-10

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Vin (p-p) in mV

Fig.15 Bit Error Rate versus input signal on DI/DIQ in STM4 mode (622.08 Mbits/s).

(A complementary input signal of the indicated value is applied to DI and DIQ..

1999 Mar 19 18

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)

1.0E+0

1.0E-1

1.0E-2

1.0E-3

1.0E-4

OQ2541HP

BER

1.0E-10

1.0E-11

1.0E-5

1.0E-6

1.0E-7

1.0E-8

1.0E-9

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Vin (p-p) in mV

Fig.16 Bit Error Rate versus input signal on DI/DIQ in STM16 mode (2488.32 Mbits/s).

(A complementary input signal of the indicated value is applied to DI and DIQ)

1999 Mar 19 19

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)

1000

100

10

1

0.1
10 100 1000 10000 100000

OQ2541HP

Fig.17 Jitter Tolerance in STM16 mode (2488.32 Mbits/s). Measured on OM5801 demoboard

100

10

1

0.1
10 100 1000 10000

Fig.18 Jitter Tolerance in STM4 mode (622.08 Mbits/s). Measured on OM5800 demoboard

1999 Mar 19 20

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)

OQ2541HP

Fig.19 Output waveforms on Data and Clock outputs in STM16 mode (2488.32 Mbits/s). (single ended).

Fig.20 Output waveforms on Data and Clock outputs in STM4 mode (622.08 Mbits/s). (single ended)

1999 Mar 19 21

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

APPLICATION INFORMATION

handbook, full pagewidth

CAPUPQ

100 nF 100 nF

CAPDOQ

PRE­AMP

(OQ2539)

39 MHz

system clock

DREF_19
DREF_39

V

EE

CREFQ

DIN

DINQ

DCSQ

CREF

15

16

33
34

36

21
22

9
24

GND

17

OQ2541

(1)

OQ2541HP

+3.3 V

+3.3 V

10 kΩ

10 kΩ

normal

output

loop

output

output
select

LOS

39

LOCK

12

DOUT

42

DOUTQ

43

COUT

45

COUTQ

46

DLOOP

6

DLOOPQ

7

CLOOP

3

CLOOPQ

4

ENL

1

AREF

48

DOUT_1250

27

DOUT_622

28

DOUT_155

30

3725, 31

V

EE

PC

(1) All GND pins must be connected directly

to the PCB ground plane (pins 2, 5, 8, 10,
11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41,
44 and 47).

100

nF

2 Ω

kΩ

β > 100

2 Ω

kΩ

1

3.3

1 µF

nF

L1

−4.5 V

MBH973

1

Fig.21 Application diagram showing the OQ2541HP configured for 2488.32 Mbits/s mode (STM16/OC48).

1999 Mar 19 22

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

APPLICATION INFORMATION (CONTINUED)

handbook, full pagewidth

CAPUPQ

100 nF 100 nF

CAPDOQ

PRE­AMP

(OQ2539)

39 MHz

system clock

DREF_19
DREF_39

V

EE

CREFQ

DIN

DINQ

DCSQ

CREF

15

16

33
34

36

21
22

9
24

GND

17

OQ2541

(1)

OQ2541HP

+3.3 V

+3.3 V

10 kΩ

10 kΩ

normal

output

loop

output

output
select

V

EE

LOS

39

LOCK

12

DOUT

42

DOUTQ

43

COUT

45

COUTQ

46

DLOOP

6

DLOOPQ

7

CLOOP

3

CLOOPQ

4

ENL

1

AREF

48

DOUT_1250

27

DOUT_622

28

DOUT_155

30

3725, 31

V

EE

PC

100

nF

2 Ω

1

kΩ

(1) All GND pins must be connected directly

to the PCB ground plane (pins 2, 5, 8, 10,
11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41,
44 and 47).

Fig.22 Application diagram showing the OQ2541HP configured for 622.08 Mbits/s mode (STM4/OC12).

1999 Mar 19 23

β > 100

2 Ω

kΩ

1

3.3

1 µF

nF

L1

−4.5 V

MBH973

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

APPLICATION INFORMATION (POSITIVE SUPPLY)

handbook, full pagewidth

CAPUPQ

100 nF 100 nF

CAPDOQ

PRE-

AMP

(OQ2539)

39 MHz

system clock

DREF_19

V

CC

DREF_39

V

EE

CREFQ

DIN

DINQ

DCSQ

CREF

15

16

33
34

36

21
22

9
24

GND

17

OQ2541

(1)

OQ2541HP

+3.3 V

V

CC

+3.3 V

10kΩ

10 kΩ

10 kΩ

V

CC

normal

output

loop

output

output
select

LOS

V

10kΩ

CC

=

=

unused
output

main

output

LOCK

LOS

39

LOCK

12

DOUT

42

DOUTQ

43

COUT

45

COUTQ

46

DLOOP

6

DLOOPQ

7

CLOOP

3

CLOOPQ

4

ENL

1

AREF

48

DOUT_1250

27

DOUT_622

28

DOUT_155

30

3725, 31

V

EE

PC

(1) All GND pins must be connected directly

to the PCB +5V (VCC) plane (pins 2, 5, 8,
10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38,
41, 44 and 47).

VCCV

CC

100

2 Ω

nF

kΩ

β > 100

V

CC

2 Ω

kΩ

1

3.3

1 µF

nF

L1

−4.5 V

MBH973

1

Fig.23 Application diagram showing the OQ2541HP configured for 2488.32 Mbits/s positive supply application.

Note that loopmode outputs are used as outputs. ENL=HIGH selects these outputs. ENL=LOW selects
loopmode and normal mode outputs simultaneously.

1999 Mar 19 24

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

PACKAGE OUTLINE

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

c

y

X

36

37

25

Z

24

E

A

OQ2541HP

SOT313-2

e

w M

pin 1 index

48

1

e

DIMENSIONS (mm are the original dimensions)

mm

A

A1A2A3bpcE

max.

0.20

0.05

1.45

1.35

1.60

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

b

p

0.25

w M

D

H

D

0.27

0.17

12

Z

D

(1) (1)(1)

D

0.18

7.1

0.12

6.9

b

p

13

v M

B

v M

0 2.5 5 mm

scale

(1)

eH

H

D

7.1

6.9

0.5

9.15

8.85

E

A

B

9.15

8.85

H

E

LL

E

0.75

0.45

A

p

A

2

A

1

L

detail X

Z

D

0.12 0.10.21.0

0.95

0.55

(A )

3

L

p

Zywv θ

E

0.95

0.55

θ

o

7

o

0

OUTLINE
VERSION

SOT313-2

IEC JEDEC EIAJ

REFERENCES

1999 Mar 19 25

EUROPEAN

PROJECTION

ISSUE DATE

94-12-19
97-08-01

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“Data Handbook IC26; Integrated Circuit Packages”

our
(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

OQ2541HP

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Mar 19 26

Philips Semiconductors Preliminary specification

SDH/SONET data and clock recovery unit

OQ2541HP

STM1/4/16 OC3/12/48

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

(3)(4)
(5)

SOLDERING METHOD

(1)

suitable

suitable
suitable

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Mar 19 27

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
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Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1999 SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 465012/00/02/pp28 Date of release: 1999Mar 19 Document order number: 9397 750 05448