Datasheet OQ2536HP Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

OQ2536HP

SDH/SONET STM16/OC48
demultiplexer

Product specification
File under Integrated Circuits, IC19

1998 Mar 10

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

FEATURES

• Normal and loop (test) modes

• 1.2 V GTL (Gunning Transceiver Logic) level compatible

data and clock outputs (low speed interface)

• Differential CML (Current-Mode Logic) data and clock
inputs

DESCRIPTION

The OQ2536HP is a 32-channel demultiplexer intended
for use in STM16/OC48 applications. It demultiplexes a
single 2.5 Gbits/s input channel to 32 × 78 Mbits/s output
channels. The data and clock outputs on the low speed
interface are GTL compatible, while the high speed data
and clock inputs are CML compatible.

• High input sensitivity (100 mV for the high speed inputs)

• Boundary Scan Test (BST) at low speed interface, in

accordance with

“IEEE Std 1149.1-1990”

• Low power dissipation (typically 1.45 W).

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

OQ2536HP HLQFP100 plastic heat-dissipating low profile quad flat package; 100 leads; body

14 × 14 × 1.4 mm

BLOCK DIAGRAM

handbook, full pagewidth

DIN

DINQ

CIN

CINQ

DLOOP

DLOOPQ

CLOOP

CLOOPQ

DIOA
DIOC

54
53

56
57

65
66

60
59

32
31

(2)

GND

2.5 Gbits/s

2.5 GHz

13, 14, 36,
26, 27, 28,
76, 77

29 5 7 5

V

DD

37, 63, 85,

86

V

CC2

1 : 4 DMUX

OQ2536HP

DIVIDE BY 4

11, 38, 39,
62, 88

V

EE

622

Mbits/s

4

622 MHz

BAND GAP

REFERENCE 2

74 51

BGCAP2

V

CC1

4 ×

1 : 8 DMUX

DIVIDE BY 8

34 73

BST LOGIC

78 MHz

BAND GAP

REFERENCE 1

BGCAP1

REFC

Mbits/s

(1)

75
68

69
70
72
71

12

78

ENL

TRST
TMS
TCK
TDI
TDO

CDIV

MGK346

SOT470-1

D0

to

D31

(1) See Chapter “Pinning” for D0 to D31 pin numbers.
(2) Pins 1, 8, 17, 22, 25, 29, 33, 35, 40 to 50, 52, 55, 58, 61, 64, 67, 78, 82, 91 and 96.

Fig.1 Block diagram.

1998 Mar 10 2

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

PINNING

SYMBOL PIN TYPE

(1)

DESCRIPTION

GND 1 S ground
D29 2 O 78 Mbits/s data output channel for D29
D25 3 O 78 Mbits/s data output channel for D25
D21 4 O 78 Mbits/s data output channel for D21
D17 5 O 78 Mbits/s data output channel for D17
D13 6 O 78 Mbits/s data output channel for D13
D9 7 O 78 Mbits/s data output channel for D9
GND 8 S ground
D5 9 O 78 Mbits/s data output channel for D5
D1 10 O 78 Mbits/s data output channel for D1
V

EE

11 S supply voltage (−4.5 V)
CDIV 12 O 78 MHz clock output
V
V

CC2
CC2

13 S supply voltage (+1.5 V)

14 S supply voltage (+1.5 V)
D28 15 O 78 Mbits/s data output channel for D28
D24 16 O 78 Mbits/s data output channel for D24
GND 17 S ground
D20 18 O 78 Mbits/s data output channel for D20
D16 19 O 78 Mbits/s data output channel for D16
D12 20 O 78 Mbits/s data output channel for D12
D8 21 O 78 Mbits/s data output channel for D8
GND 22 S ground
D4 23 O 78 Mbits/s data output channel for D4
D0 24 O 78 Mbits/s data output channel for D0
GND 25 S ground
V

DD

V

DD

V

DD

26 I supply voltage (+3.3 V)

27 I supply voltage (+3.3 V)

28 I supply voltage (+3.3 V)
GND 29 S ground
i.c. 30 − internally connected, to be left open-circuit
DIOC 31 A cathode of temperature diode array
DIOA 32 A anode of temperature diode array
GND 33 S ground
BGCAP2 34 A pin for connecting external band gap decoupling capacitor (4 × 1 : 8 DMUX)
GND 35 S ground
V
V
V
V

CC2
CC2
EE
EE

36 S supply voltage (+1.5 V)

37 S supply voltage (+1.5 V)

38 S supply voltage (−4.5 V)

39 S supply voltage (−4.5 V)
GND 40 S ground

1998 Mar 10 3

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

SYMBOL PIN TYPE

(1)

DESCRIPTION

GND 41 S ground
GND 42 S ground
GND 43 S ground
GND 44 S ground
GND 45 S ground
GND 46 S ground
GND 47 S ground
GND 48 S ground
GND 49 S ground
GND 50 S ground
BGCAP1 51 A pin for connecting external band gap decoupling capacitor (1 : 4 DMUX)
GND 52 S ground
DINQ 53 I inverted data input in normal mode
DIN 54 I data input in normal mode
GND 55 S ground
CIN 56 I clock input in normal mode
CINQ 57 I inverted clock input in normal mode
GND 58 S ground
CLOOPQ 59 I inverted clock input from multiplexer IC OQ2535 (loop mode)
CLOOP 60 I clock input from multiplexer IC OQ2535 (loop mode)
GND 61 S ground
V
V

EE
CC2

62 S supply voltage (−4.5 V)

63 S supply voltage (+1.5 V)
GND 64 S ground
DLOOP 65 I data input from multiplexer IC OQ2535 (loop mode)
DLOOPQ 66 I inverted data input from multiplexer IC OQ2535 (loop mode)
GND 67 S ground
TRST 68 I test RESET input for BST mode (active LOW)
TMS 69 I test mode select input for BST
TCK 70 I test clock input for BST mode
TDO 71 O serial test data output for BST mode
TDI 72 I serial test data input for BST mode
REFC 73 A pin for connecting external reference decoupling capacitor (for standard TTL

reference)

V

CC1

74 S supply voltage (+5.0 V)
ENL 75 I loop mode enable input (active LOW)
V

DD

V

DD

76 I supply voltage (+3.3 V)

77 I supply voltage (+3.3 V)
GND 78 S ground
D31 79 O 78 Mbits/s data output channel for D31
D27 80 O 78 Mbits/s data output channel for D27

1998 Mar 10 4

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

SYMBOL PIN TYPE

(1)

DESCRIPTION

D23 81 O 78 Mbits/s data output channel for D23
GND 82 S ground
D19 83 O 78 Mbits/s data output channel for D19
D15 84 O 78 Mbits/s data output channel for D15
V
V

CC2
CC2

85 S supply voltage (+1.5 V)

86 S supply voltage (+1.5 V)
D11 87 O 78 Mbits/s data output channel for D11
V

EE

88 S supply voltage (−4.5 V)
D7 89 O 78 Mbits/s data output channel for D7
D3 90 O 78 Mbits/s data output channel for D3
GND 91 S ground
D30 92 O 78 Mbits/s data output channel for D30
D26 93 O 78 Mbits/s data output channel for D26
D22 94 O 78 Mbits/s data output channel for D22
D18 95 O 78 Mbits/s data output channel for D18
GND 96 S ground
D14 97 O 78 Mbits/s data output channel for D14
D10 98 O 78 Mbits/s data output channel for D10
D6 99 O 78 Mbits/s data output channel for D6
D2 100 O 78 Mbits/s data output channel for D2

Note

1. Pin type abbreviations: O = Output, I = Input, S = power Supply, A = Analog function.

1998 Mar 10 5

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

handbook, full pagewidth

GND

D29
D25
D21
D17
D13

D9

GND

D5
D1

V

EE

CDIV

V

CC2

V

CC2

D28
D24

GND

D20
D16
D12

D8

GND

D4
D0

GND

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

D2D6D10

100

D14

GND

D18

D22

D26

D30

GNDD3D7

99989796959493929190898887868584838281

VEED11

CC2VCC2

V

D15

OQ2536HP

D19

D27

GND

D23

8079787776

D31

GND

VDDV

DD

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52

51

ENL
V

CC1

REFC
TDI
TDO
TCK
TMS

TRST
GND

DLOOPQ
DLOOP
GND
V

CC2

V

EE

GND
CLOOP
CLOOPQ
GND
CINQ
CIN
GND
DIN
DINQ
GND
BGCAP1

26

VDDVDDV

DD

31323334353637383940414243444546474849

GND

i.c.

DIOC

DIOA

GND

GND

BGCAP2

CC2VCC2

V

30

29

28

27

Fig.2 Pin configuration.

1998 Mar 10 6

VEEV

EE

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

50

GND

MGK345

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

FUNCTIONAL DESCRIPTION

The OQ2536HP is a 32-channel demultiplexer, intended
for use in STM16/OC48 applications. It demultiplexes a
single 2.5 Gbits/s input channel to 32 × 78 Mbits/s output
channels.

The demultiplexing is performed in two stages.
The 2.5 Gbits/s data channel is first demultiplexed to four
622 Mbits/s data channels. Each of these channels is then
fed to a 1 : 8 demultiplexer to generate 32 × 78 Mbits/s
output channels.

ENL control input is used for switching between

The
normal and loop modes. When loop mode is enabled
(ENL = LOW), inputs DLOOP, DLOOPQ, CLOOP and
CLOOPQ are selected. In normal mode (ENL = HIGH),
inputs DIN, DINQ, CIN and CINQ are selected.

The signal applied to CIN and CINQ is a 2.5 GHz
recovered clock signal, e.g. coming from the OQ2541 data
and clock recovery IC. The clock is divided down to
78 MHz, which is used for receive logic timing and is
available as a GTL compatible output at pin CDIV.

High bit rate stage: 1 : 4 DMUX

The 2.5 Gbits/s data stream is fed into a 1 : 4
demultiplexer to generate four 622 Mbits/s channels.

IC. If multiple decoupling capacitors are used for a single
supply node, large distance between the capacitances
should be avoided in order to avoid resonance.

To minimize low frequency switching noise in the vicinity of
the OQ2536HP, all power supply lines should be filtered
once by an LC-circuit with a low cutoff frequency
(as shown in the application diagram, Fig.7).

Ground connection

The ground connection on the PCB needs to be a large
copper area fill connected to a common ground plane with
low inductance.

RF connections

A coupled stripline or microstrip with an odd mode
characteristic impedance of 50 Ω (nominal value) should
be used for the RF connections on the PCB.
The connections should be kept as short as possible. This
applies to the CML differential line pairs CIN and CINQ,
DIN and DINQ, CLOOP and CLOOPQ, and DLOOP and
DLOOPQ. In addition, the following lines should not vary in
length by more than 5 mm:

• CIN, CINQ, DIN and DINQ

• DLOOP, DLOOPQ, CLOOP and CLOOPQ.

The input pins DIN, DINQ, DLOOP, DLOOPQ, CIN, CINQ,
CLOOP and CLOOPQ are terminated internally with 50 Ω
resistors to GND.

Low bit rate part: 4 × 1 : 8 DMUX

The four 622 Mbits/s output channels coming from the
high bit rate stage are loaded into four 8-bit shift registers.
The 622 MHz clock for these shift registers comes from the
preceding stage.

The 32 bits contained in the shift registers are loaded into
latches and made available on outputs D0 to D31. These
outputs are 1.2 V GTL compatible and have internal 100 Ω
pull up resistors. The 78 MHz clock output, CDIV, has an
internal 50 Ω pull up resistor.

The first serial data bit coming in at DIN or DLOOP is given
out at pin D31 (MSB) and so on.

The data outputs may not always represent four STM
bytes. This is because the internal load pulse for the output
latches is not synchronized to the STM16 frame.

Power supply connections

The power supply pins need to be individually decoupled
using chip capacitors mounted as close as possible to the

Interface to receive logic

The 78 Mbits/s interface lines, CDIV and D0 to D31,
should not exceed 50 mm in length. The parasitic
capacitance of these lines should be as small as possible
(less than 3 pF is desirable).

ESD protection

All pads are protected by ESD protection diodes, with the
exception of the high frequency inputs DIN, DINQ,
DLOOP, DLOOPQ, CIN, CINQ, CLOOP and CLOOPQ.

Cooling

In many cases it is necessary to mount a special cooling
device on the package. The thermal resistance from
junction to case, R

and from junction to ambient, R

th j-c

th j-a

are given in Chapter “Thermal characteristics”. Since the
heat-slug in the package is connected to the die, the
cooling device should be electrically isolated.

To calculate if a heatsink is necessary, the maximum
allowed total thermal resistance R is calculated as:

TjT

–

th

=

----------------------- -

amb

P

tot

(1)R

,

1998 Mar 10 7

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

where:

Rth= total thermal resistance from junction to ambient

in the application
Tj= junction temperature
T

= ambient temperature.

amb

As long as Rth is greater than R

of the OQ2536HP

th j-a

including environmental conditions like air flow and board
layout, no heatsink is necessary. For example if
Tj= 120 °C, T

R

th

which is more than the worst case R

=70°C and P

amb

120 70–()

-----------------------------

1.45

= 1.45 W, then:

tot

34.4==KW⁄[]

= 33 K/W, so no

th j-a

(2)

heatsink is necessary.
Another example; if for safety reasons Tj should stay as

low as 110 °C, while T

R

110 85–()

-----------------------------

th

2.0

=85°C and P

amb

12.5==KW⁄[]

= 2 W, then:

tot

(3)

In this case extra cooling is needed. The thermal
resistance of the heatsink is calculated as follows:

R

thh a–

1



–

--------

---------------- -



R

R

th

1

thj a–

1–

R

– R

thj c–

–≤

thc h–

(4)

where:

= thermal resistance from heatsink to ambient

R

th h-a

R

= thermal resistance from case to heatsink

th c-h

R

= thermal resistance from junction to case,

th j-c

see Chapter “Thermal characteristics”.

If for instance R

R

thh a–



-----------



12.5

= 0.5 K/W and R

th c-h

1

1

–

-----­33

1–

3.1– 17.0≤≤KW⁄[]

= 33 K/W then:

th j -a

(5)

Built in temperature sensor

Three series-connected diodes have been integrated for
measuring junction temperature. The diode array,
accessed by means of the DIOA (anode) and DIOC
(cathode) pins, has a temperature dependency of
approximately −6 mV/°C. With a diode current of 1 mA,
the voltage will be somewhere in the range 1.7 to 2.5 V,
depending on temperature.

Boundary Scan Test (BST) interface

Boundary scan test logic has been implemented for all
digital inputs and outputs on the low frequency interface, in
accordance with

“IEEE Std 1149.1-1990”

. All scan tests
other than SAMPLE mode are available. The boundary
scan test logic consists of a TAP controller, a BYPASS
register, a 2-bit instruction register, a 32-bit identification
register and a 36-bit boundary scan register (the last two
are combined). The architecture of the TAP controller and
the BYPASS register is in accordance with IEEE
recommendations.
The four command modes, selected be means of the
instruction register, are: EXTEST (00), PRELOAD (01),
IDCODE (10) and BYPASS (11).
All boundary scan test inputs, TDI, TMS, TCK and TRST,
have internal pull up resistors. The maximum test clock
frequency at TCK is 12 MHz.

Table 1 BST identifier code

VERSION OQ 2536 (BINARY) PHILIPS SEMICONDUCTORS LSB

0001 01 00 1001 11101000 0000 0011 101

(2)

Notes

1. LSB is shifted out first on the TDO pin.

2. The manufacturer’s code was implemented incorrectly. It should have been 0000 0010 101.

1998 Mar 10 8

(1)

1

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

Table 2 BST bit order

BIT NUMBER SYMBOL PIN

33 (MSB) D31 79
32 D27 80
31 D23 81
30 D19 83
29 D15 84
28 D11 87
27 D7 89
26 D3 90
25 D30 92
24 D26 93
23 D22 94
22 D18 95
21 D14 97
20 D10 98
19 D6 99
18 D2 100
17 D29 2
16 D25 3
15 D21 4
14 D17 5
13 D13 6
12 D9 7
11 D5 9
10 D1 10
9 CDIV 12
8 D28 15
7 D24 16
6 D20 18
5 D16 19
4 D12 20
3D8 21
2D4 23
1D0 24
0 (LSB)

(1)

ENL 75

Note

1. LSB is shifted out first on the TDO pin.

1998 Mar 10 9

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V
V
V
V
V

I

P
T
T

CC1
EE
DD
CC2
n

n

tot
j
stg

supply voltage −0.5 +6.0 V
supply voltage −6.0 +0.5 V
supply voltage −0.5 +5.0 V
supply voltage −0.5 +2.0 V
DC voltage

pins 2 to 7, 9, 10, 15, 16, 18 to 21, 23, 24, 79, 80, 81, 83, 84, 87, 89,

0.0 2.0 V

90, 92 to 95 and 97 to 100
pins 53, 54, 56, 57, 59, 60, 65 and 66 −1.0 +0.5 V
pins 68, 69, 70, 72, 73 and 75 −0.5 V
pins 30, 34 and 51 V
pins 31and 32 V

− 0.5 0.5 V

EE

− 0.5 V

EE

CC1

CC1

+ 0.5 V

+ 0.5 V

DC current

pins 2 to 7, 9, 10, 15, 16, 18 to 21, 23, 24, 79, 80, 81, 83, 84, 87, 89,

− 15 mA

90, 92 to 95, and 97 to 100
pin 12 − 30 mA
pins 31 and 32 − 10 mA

pin 71 − 50 mA
total power dissipation − 2.6 W
junction temperature − 120 °C
storage temperature −65 +150 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R
R

th j-c
th j-a

thermal resistance from junction to case 2.6 K/W
thermal resistance from junction to

ambient

see note 1

airflow = 0 ft/min 33 K/W
airflow = 100 ft/min 28 K/W
airflow = 200 ft/min 25 K/W
airflow = 400 ft/min 22 K/W
airflow = 600 ft/min 20 K/W

Note

1. The thermal resistance from junction to ambient is strongly depending on the board design and airflow. The values
given in the table are typical values and are measured on a single sided test board with dimensions of
76 × 114 × 1.6 mm. Better values can be obtained when mounted on multilayer boards with large ground planes.

1998 Mar 10 10

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

DC CHARACTERISTICS

Typical values at T
ambient temperature range and supply voltage range.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

General

V

CC1

V

EE

V

DD

V

CC2

I

CC1

I

EE

I

DD

I

CC2

P

tot

T

j

T

amb

TTL input:

V

IL

V

IH

I

IL

I

IH

supply voltage 4.75 5.0 5.25 V
supply voltage −4.75 −4.5 −4.25 V
supply voltage 3.14 3.3 3.47 V
supply voltage 1.1 1.5 1.6 V
supply current − 14 22 mA
supply current − 170 215 mA
supply current − 100 185 mA
supply current note 1 − 190 525 mA
total power dissipation note 1 − 1.45 2.6 W
junction temperature −−+120 °C
ambient temperature −40 − +85 °C

ENL

LOW-level input voltage −−0.8 V
HIGH-level input voltage 2.0 −−V
LOW-level input current −90 − - µA
HIGH-level input current - − 210 µA

TTL inputs: TDI, TCK, TMS and

V

IL

V

IH

LOW-level input voltage −−0.4 V
HIGH-level input voltage 2.0 −−V

CML inputs: CIN, CINQ, DIN, DINQ, CLOOP, CLOOPQ, DLOOP and DLOOPQ; note 3
V

V
V
Z

i(p-p)
IO
I,IQ
i

input voltage (peak-to-peak value) 50 Ω measurement
permitted input offset voltage −25 − +25 mV
input voltages −600 − +250 mV

single ended input impedance for DC signal − 50 −Ω
TTL output: TDO; note 4
V

OL

LOW-level output voltage IOL=4mA − 0.3 0.5 V

=25°C and at typical supply voltages; minimum and maximum values are valid over the entire

amb

TRST; note 2

100 250 500 mV

system

1998 Mar 10 11

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

OH

I

OZ

Outputs: CDIV and D0 to D31; notes 5 and 6
V

OL

V

OH

Temperature diode array

∆V

DIOA-DIOC

Notes

1. Maximum current I
in LOW state.

2. TDI, TCK, TMS and TRST are connected via 90 kΩ to VDD.

3. See Fig.3 for symbol definitions.

4. TDO is switched to high impedance state if BST is inactive.

5. Output CDIV has an internal pull-up resistor of 50 Ω to V
100 Ω to V

6. The first serial data bit coming in at DIN or DLOOP is given out at D31 (MSB) and so on.

7. The HIGH-level output voltage depends on the supply voltage V

8. The temperature diode array can be used to measure the temperature of the die. The temperature dependency of
this voltage is approximately −6 mV/K.

HIGH-level output voltage IOH= −400 µA 2.4 4.0 − V
output current in high impedance state −−1µA

LOW-level output voltage Open outputs - 0.3 0.4 V
HIGH-level output voltage; note 7 1.1 1.5 1.6 V

diode voltage range

and maximum power dissipation P

CC2

.

CC2

(8)

I

=1mA − 2.1 − V

I(d)

are worst case figures i.e. data outputs D0 to D31 remain

tot

. Outputs D0 to D31 have internal pull-up resistors of

CC2

.

CC2

handbook, full pagewidth

V

I(max)

V

IQH

V

IH

V

IQL

V

IL

V

I(min)

CML INPUT

V

IO

GND

V

i (p-p)

Fig.3 Logic level symbol definitions for CML.

1998 Mar 10 12

V

O(max)

V

V

V

O(min)

OQH

V

OH

OQL

V

OL

CML OUTPUT

V

OO

GND

V

o (p-p)

MGK144

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

TIMING

Typical values at T
ambient temperature range and supply voltage range.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

CML input timing; note 1; Fig.5

f

clk(CIN)

t

su

t

h

SR

CIN

input clock frequency 2.488 −−GHz
input data set-up time 140 −−ps
input data hold time 80 −−ps

clock slew rate 1 −−V/ns
TTL output timing; note 2; Fig.6
f

clk(CDIV)

δ

CDIV

t

r(CDIV)

t

f(CDIV)

t

r(D0 to D31)

t

f(D0 to D31)

t

CDV

t

DI

output clock frequency f

output clock duty factor - 50 - %

output clock rise time Measured between

output clock fall time −−1000 ps

data out rise time −−5100 ps

data out fall time −−1000 ps

clock edge to data valid time −−2700 ps

data invalid time −−2850 ps

=25°C and at typical supply voltages; minimum and maximum values are valid over the entire

amb

clk(CDIV)

= 2.488 GHz − 77.76 − MHz

−−2700 ps
10% and 90% levels
of full output swing

Notes

1. The specified timing characteristics are applicable in both normal and loop modes.

2. A capacitive load of 15 pF was connected at all outputs. An input reference level of 1 V was used.

handbook, halfpage

MBK756

100 Ω

V

CC2

D0 to D31

GND

handbook, halfpage

50 Ω

MBK757

V

CC2

CDIV

GND

Fig.4 GTL output circuits.

1998 Mar 10 13

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

handbook, full pagewidth

CIN

DIN

T

cy(CIN)

t

su

t

h

valid data

Fig.5 CML input timing.

50%

100 mV

MGK347

handbook, full pagewidth

D0 to D31

T

cy(CDIV)

t

CDV

t

DI

Fig.6 Output timing.

1998 Mar 10 14

1.0 VCDIV

1.1 V

0.9 V

MGK348

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

APPLICATION INFORMATION

handbook, full pagewidth

micro-

controller

BOUNDARY SCAN
TEST EQUIPMENT

DLOOP

OQ2535

MUX

DLOOPQ

CLOOP

CLOOPQ

ENL

TDI

TCK

TMS

TRST

TDO

DLOOP

DLOOPQ

CLOOP

CLOOPQ

DATA AND CLOCK RECOVERY

OQ2541

D

DIN DINQ

54

75

72
70
69

68

71

65
66
60
59

D0 to D31

DQ

53

OQ2536

CL

56

CLQ

CIN

57

51

34
73

32

(1)

74

(4)

12

CDIV

CINQ

31

(2)

(3)

BGCAP1

BGCAP2
REFC

DIOA

DIOC

V

CC2

V

CC1

V

DD

V

EE

GND

100

nF

100

nF

100

nF

100

nF

V

EE

10 nF

V

EE

10 nF

33 nF

ferrite

bead

ferrite

bead

ferrite

bead

ferrite

bead

1 µF

1 µF

1 µF

1 µF

D0 to D31 C78

RECEIVE LOGIC

MGK349

(1) V

pins 13, 14, 36, 37, 63, 85 and 86 should be connected together, and to the filter network.

CC2

(2) VDD pins 26, 27, 28, 76 and 77 should be connected together, and to the filter network.
(3) VEE pins 11, 38, 39, 62 and 8 should be connected together, and to the filter network.
(4) All GND pins (pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36, 40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89, 92 to 98 and 100) must be connected directly

to the PCB ground plane.

Fig.7 Application diagram.

1998 Mar 10 15

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

PACKAGE OUTLINE

HLQFP100: plastic heat-dissipating low profile quad flat package;
100 leads; body 14 x 14 x 1.4 mm

c

y

X

A

SOT470-1

100

75

76

pin 1 index

1

e

w M

b

p

D

H

D

51

50

Z

E

e

E

J

w M

b

p

26

25

Z

D

0 5 10 mm

v M

A

B

v M

B

scale

H

E

A

2

A

A

1

detail X

(A )

3

L

p

L

θ

DIMENSIONS (mm are the original dimensions)

mm

OUTLINE
VERSION

SOT470-1

A

A1A2A3b

max.

0.20

1.6

0.05

cE

p

1.5

1.3

0.28

0.16

0.18

0.12

0.25

IEC JEDEC EIAJ

UNIT

Notes

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

2. Heatsink intrusion 0.0127 maximum.

(1)

(1) (1)(1)

D

14.1

13.9

REFERENCES

eH

14.1

13.9

0.5

16.25

15.75

1998 Mar 10 16

(2)

E

16.25

15.75

J

10.15

9.15

p

0.75

0.45

0.12 0.10.21.0

EUROPEAN

PROJECTION

H

D

LL

Zywv θ

Z

D

1.15

1.15

0.85

0.85

ISSUE DATE

97-01-13

E

o

7

o

0

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Reflow soldering

Reflow soldering techniques are suitable for all LQFP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

(order code 9398 652 90011).

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1998 Mar 10 17

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1998 Mar 10 18

Philips Semiconductors Product specification

SDH/SONET STM16/OC48 demultiplexer OQ2536HP

NOTES

1998 Mar 10 19

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 425102/200/01/pp20 Date of release: 1998 Mar 10 Document order number: 9397 750 01623