Page 1
1
®
OPA688
Unity Gain Stable, Wideband
VOLTAGE LIMITING AMPLIFIER
OPA688
®
FEATURES
● HIGH LINEARITY NEAR LIMITING
● FAST RECOVERY FROM OVERDRIVE: 2.4ns
● LIMITING VOLTAGE ACCURACY: ±15mV
● –3dB BANDWIDTH (G = +1): 530MHz
● SLEW RATE: 1000V/µs
● ±5V AND 5V SUPPLY OPERATION
● HIGH GAIN VERSION: OPA689
APPLICATIONS
● FAST LIMITING ADC INPUT BUFFER
● CCD PIXEL CLOCK STRIPPING
● VIDEO SYNC STRIPPING
● HF MIXER
● IF LIMITING AMPLIFIER
● AM SIGNAL GENERATION
● NON-LINEAR ANALOG SIGNAL PROCESSING
● COMPARATOR
DESCRIPTION
The OPA688 is a wideband, unity gain stable voltage
feedback op amp that offers bipolar output voltage limiting. Two buffered limiting voltages take control of the
output when it attempts to drive beyond these limits.
This new output limiting architecture holds the limiter
offset error to ±15mV. The op amp operates linearly to
within 30mV of the output limit voltages.
The combination of narrow nonlinear range and low
limiting offset allows the limiting voltages to be set
within 100mV of the desired linear output range. A fast
2.4ns recovery from limiting ensures that overdrive signals will be transparent to the signal channel. Implementing the limiting function at the output, as opposed to
the input, gives the specified limiting accuracy for any
gain, and allows the OPA688 to be used in all standard
op amp applications.
Non-linear analog signal processing will benefit from
the OPA688’s sharp transition from linear operation to
output limiting. The quick recovery time supports high
speed applications.
The OPA688 is available in an industry standard pinout
in PDIP-8 and SO-8 packages. For higher gain, or
transimpedance applications requiring output limiting
with fast recovery, consider the OPA689.
©
1997 Burr-Brown Corporation PDS-1424D Printed in U.S.A. January, 2000
TM
OPA688
OPA688
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
LIMITED OUTPUT RESPONSE
V
INVO
Time (200ns/div)
Input and Output Voltage (V)
VH = –VL = 2.0V
G = +2
2.10
2.05
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
DETAIL OF LIMITED OUTPUT VOLTAGE
Time (50ns/div)
V
O
Output Voltage (V)
For most current data sheet and other product
information, visit www.burr-brown.com
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
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®
OPA688
AC PERFORMANCE (see Figure 1)
Small Signal Bandwidth V
O
< 0.2Vp-p
G = +1, R
F
= 25Ω 530 — — — MHz Typ C
G = +2 260 150 140 135 MHz Min B
G = –1 230 — — — MHz Typ C
Gain-Bandwidth Product (G ≥ +5) V
O
< 0.2Vp-p 290 175 170 160 MHz Min B
Gain Peaking G = +1, R
F
= 25Ω, VO < 0.2Vp-p 11 — —
—
dB Typ C
0.1dB Gain Flatness Bandwidth V
O
< 0.2Vp-p 50 — — — MHz Typ C
Large Signal Bandwidth V
O
= 4Vp-p, VH = –VL = 2.5V 145 100 95 90 MHz Min B
Step Response:
Slew Rate 4V Step, V
H
= –VL = 2.5V 1000 800 770 650 V/µs Min B
Rise/Fall Time 0.2V Step 1.2 2.6 2.7 3 ns Max B
Settling Time: 0.05% 2V Step 7 ———nsTypC
Spurious Free Dynamic Range f = 5MHz, V
O
= 2Vp-p 66 62 58 53 dB Min B
Differential Gain NTSC, PAL, R
L
= 500Ω 0.02 — — — % Typ C
Differential Phase NTSC, PAL, R
L
= 500Ω 0.01 — — — ° Typ C
Input Noise:
Voltage Noise Density f ≥ 1MHz 6.3 7.2 7.8 8 nV/√Hz Max B
Current Noise Density f ≥ 1MHz 2.0 2.5 2.9 3.6 pA/√Hz Max B
DC PERFORMANCE (V
CM
= 0)
Open Loop Voltage Gain (A
OL
)V
O
= ±0.5V 52 46 44 43 dB Min A
Input Offset Voltage ±2
±6 ±7 ±9 mV Max A
Average Drift ——±14 ±14 µV/°C Max B
Input Bias Current
(3)
+6 ±12 ±13 ±20 µA Max A
Average Drift — — –60 –90 nA/°C Max B
Input Offset Current ±0.3
±2 ±3 ±4 µA Max A
Average Drift ——±10 ±10 nA/°C Max B
INPUT
Common-Mode Rejection Input Referred, V
CM
= ±0.5V 57 50 49 47 dB Min A
Common-Mode Input Range
(4)
±3.3 ±3.2 ±3.2 ±3.1 V Min A
Input Impedance
Differential-Mode 0.4 || 1 — — — MΩ || pF Typ C
Common-Mode 1 || 1 — — — MΩ || pF Typ C
OUTPUT V
H
= –VL = 4.3V
Output Voltage Range R
L
≥ 500Ω±4.1 ±3.9 ±3.9 ±3.8 V Min A
Current Output, Sourcing V
O
= 0 105 90 85 80 mA Min A
Sinking V
O
= 0 –85 –70 –65 –60 mA Min A
Closed-Loop Output Impedance G = +1, R
F
= 25Ω, f < 100kHz 0.2 — — — Ω Typ C
POWER SUPPLY
Operating Voltage, Specified ±5———VTypC
Maximum — ±6 ±6 ±6 V Max A
Quiescent Current, Maximum 15.8 17 19 20 mA Max A
Minimum 15.8 14 12.8 11 mA Min A
Power Supply Rejection Ratio +V
S
= 4.5V to 5.5V
+PSR (Input Referred) 65 58 57 55 dB Min A
OUTPUT VOLTAGE LIMITERS Pins 5 and 8
Default Limit Voltage Limiter Pins Open ±3.3
±3.0 ±3.0 ±2.9 V Min A
Minimum Limiter Separation (V
H
– VL) 200 200 200 200 mV Min B
Maximum Limit Voltage — ±4.3 ±4.3 ±4.3 V Max B
Limiter Input Bias Current Magnitude
(5)
VO = 0
Maximum 54 65 68 70 µA Max A
Minimum 54 35 34 31 µA Min A
Average Drift — — 40 45 nA/°C Max B
Limiter Input Impedance 2 || 1 — — — MΩ || pF Typ C
Limiter Feedthrough
(6)
f = 5MHz –60 — — — dB Typ C
DC Performance in Limit Mode V
IN
= ±2V
Limiter Offset (V
O
– VH) or (VO – VL) ±15 ±35 ±40 ±40 mV Max A
Op Amp Input Bias Current Shift
(3)
3———µA Typ C
AC Performance in Limit Mode
Limiter Small Signal Bandwidth V
IN
= ±2V, VO < 0.02Vp-p 450 — — — MHz Typ C
Limiter Slew Rate
(7)
100 — — — V/µs Typ C
Limited Step Response 2x Overdrive
Overshoot V
IN
= 0 to ±2V Step 250 — — — mV Typ C
Recovery Time V
IN
= ±2V to 0V Step 2.4 2.8 3.0 3.2 ns Max B
Linearity Guardband
(8)
f = 5MHz, VO = 2Vp-p 30 — — — mV Typ C
SPECIFICATIONS—VS = ±5V
G = +2, RL = 500Ω, RF = 402Ω, VH = –VL = 2V (Figure 1 for AC performance only), unless otherwise noted.
OPA688U, P
TYP GUARANTEED
(1)
0°C to –40°C to
MIN/
TEST
PARAMETER CONDITIONS +25°C +25°C +70°C +85°C UNITS MAX
LEVEL
(2)
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®
OPA688
THERMAL CHARACTERISTICS
Temperature Range Specification: P, U
–40 to +85
———°C Typ C
Thermal Resistance Junction-to-Ambient
P 8-Pin DIP 100 — — — °C/W Typ C
U 8-Pin SO-8 125 — — — °C/W Typ C
NOTES: (1) Junction Temperature = Ambient Temperature for low temperature limit and 25°C guaranteed specifications. Junction Temperature = Ambient Temperature
+ 23°C at high temperature limit guaranteed specifications. (2) TEST LEVELS: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation. (C) Typical value for information only. (3) Current is considered positive out of node. (4) CMIR tested as < 3dB
degradation from minimum CMRR at specified limits. (5) I
VH
(VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3,
Figure 1 and Figure 8 . (6) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V
H
(or VL) when VIN = 0. (7) VH slew rate conditions are:
V
IN
= +2V, G = +2, VL = –2V, VH = step between 2V and 0V. VL slew rate conditions are similar. (8) Linearity Guardband is defined for an output sinusoid (f = 5MHz,
V
O
= 0VDC ±1Vp-p) centered between the limiter levels (VH and VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases
by 3dB (see Figure 9).
SPECIFICATIONS—VS = ±5V (CONT)
G = +2, RL = 500Ω, RF = 402Ω, VH = –VL = 2V (Figure 1 for AC performance only), unless otherwise noted.
OPA688U, P
TYP GUARANTEED
(1)
0°C to –40°C to
MIN/
TEST
PARAMETER CONDITIONS +25°C +25°C +70°C +85°C UNITS MAX
LEVEL
(2)
AC PERFORMANCE (see Figure 2)
Small Signal Bandwidth V
O
< 0.2Vp-p
G = +1, R
F
= 25Ω 515 — — — MHz Typ C
G = +2 240 110 105 100 MHz Min B
G = –1 190 — — — MHz Typ C
Gain-Bandwidth Product (G ≥ +5) V
O
< 0.2Vp-p 275 130 125 120 MHz Min B
Gain Peaking G = +1, R
F
= 25Ω, VO < 0.2Vp-p 10 — — — dB Typ C
0.1dB Gain Flatness Bandwidth V
O
< 0.2Vp-p 50 — — — MHz Typ C
Large Signal Bandwidth V
O
= 2Vp-p 240 110 105 100 MHz Min B
Step Response:
Slew Rate 2V Step 1000 800 770 650 V/µs Min B
Rise/Fall Time 0.2V Step 2.3 2.6 2.7 3 ns Max B
Settling Time: 0.05% 1V Step 12 ———nsTypC
Spurious Free Dynamic Range f = 5MHz, V
O
= 2Vp-p 64 60 56 51 dB Min B
Input Noise:
Voltage Noise Density f ≥ 1MHz 6.3 7.2 7.8 8 nV/√Hz Max B
Current Noise Density f ≥ 1MHz 2.0 2.5 2.9 3.6 pA/√Hz Max B
DC PERFORMANCE V
CM
= 2.5V
Open Loop Voltage Gain (A
OL
)V
O
= ±0.5V 52 46 44 43 dB Min A
Input Offset Voltage ±2
±6 ±7 ±9 mV Max A
Average Drift ——±14 ±14 µV/°C Max B
Input Bias Current
(3)
+6 ±12 ±13 ±20 µA Max A
Average Drift — — –60 –90 nA/°C Max B
Input Offset Current ±0.3
±2 ±3 ±4 µA Max A
Average Drift ——±10 ±10 nA/°C Max B
SPECIFICATIONS—VS = +5V
G = +2, RL = 500Ω tied to VCM = 2.5V, RF = 402Ω, VL = V
CM
–1.2V, VH = V
CM
+1.2V (Figure 2 for AC performance only), unless otherwise noted.
OPA688U, P
TYP GUARANTEED
(1)
0°C to –40°C to
MIN/
TEST
PARAMETER CONDITIONS +25°C +25°C +70°C +85°C UNITS MAX
LEVEL
(2)
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®
OPA688
INPUT
Common-Mode Rejection Input Referred, V
CM
= ±0.5V 55 48 47 45 dB Min A
Common-Mode Input Range
(4)
VCM ±0.8 VCM ±0.7 VCM ±0.7 VCM ±0.6 V Min A
Input Impedance
Differential-Mode 0.4 || 1 — — — MΩ || pF Typ C
Common-Mode 1 || 1 — — — MΩ || pF Typ C
OUTPUT V
H
= VCM +1.8V, VL = = VCM –1.8V
Output Voltage Range R
L
≥ 500Ω VCM ±1.6 VCM ±1.4 VCM ±1.4 VCM ±1.3 V Min A
Current Output, Sourcing V
O
= 2.5V 70 60 55 50 mA Min A
Sinking V
O
= 2.5V –60 –50 –45 –40 mA Min A
Closed-Loop Output Impedance G = +1, R
F
= 25Ω, f < 100kHz 0.2 — — — Ω Typ C
POWER SUPPLY Single Supply Operation
Operating Voltage, Specified +5 — — — V Typ C
Maximum — +12 +12 +12 V Max A
Quiescent Current, Maximum 13 15 15 16 mA Max A
Minimum 13 11 10 9 mA Min A
Power Supply Rejection Ratio V
S
= 4.5V to 5.5V
+PSR (Input Referred) 65 — — — dB Typ C
OUTPUT VOLTAGE LIMITERS Pins 5 and 8
Default Limiter Voltage Limiter Pins Open V
CM
±0.9 VCM ±0.6 VCM ±0.6 VCM ±0.6 V Min A
Minimum Limiter Separation (V
H
– VL) 200 200 200 200 mV Min B
Maximum Limit Voltage — V
CM
±1.8 VCM ±1.8 VCM ±1.8 V Max B
Limiter Input Bias Current Magnitude
(5)
VO = 2.5V
Maximum 35 65 75 85 µA Max A
Minimum 35 0 00µA Min A
Average Drift — — 30 50 nA/°C Max B
Limiter Input Impedance 2 || 1 — — — MΩ || pF Typ C
Limiter Feedthrough
(6)
f = 5MHz –60 — — — dB Typ C
DC Performance in Limit Mode V
IN
= VCM ±1.2V
Limiter Voltage Accuracy (V
O
– VH) or (VO – VL) ±15 ±35 ±40 ±40 mV Max A
Op Amp Bias Current Shift
(3)
5———µA Typ C
AC Performance in Limit Mode
Limiter Small Signal Bandwidth V
IN
= VCM ±1.2V, VO < 0.02Vp-p 300 — — — MHz Typ C
Limiter Slew Rate
(7)
20———V/µs Typ C
Limited Step Response 2x Overdrive
Overshoot V
IN
= VCM to V
CM
±1.2V Step 55 — — — mV Typ C
Recovery Time V
IN
= VCM ±1.2V to VCM Step 15 ———nsMaxC
Linearity Guardband
(8)
f = 5MHz, VO = 2Vp-p 30 — — — mV Max C
THERMAL CHARACTERISTICS
Temperature Range Specification: P, U
–40 to +85
———°C Typ C
Thermal Resistance Junction-to-Ambient
P 8-Pin DIP 100 — — — °C/W Typ C
U 8-Pin SO-8 125 — — — °C/W Typ C
NOTES: (1) Junction Temperature = Ambient Temperature for low temperature limit and 25°C guaranteed specifications. Junction Temperature = Ambient
Temperature + 23°C at high temperature limit guaranteed specifications. (2) TEST LEVELS: (A) 100% tested at 25 °C. Over temperature limits by characterization
and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (3) Current is considered positive out of node. (4) CMIR
tested as < 3dB degradation from minimum CMRR at specified limits. (5) I
VH
(VH bias current) is negative, and IVL (VL bias current) is positive, under these conditions.
See Note 3, Figures 2, and Figure 8. (6) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V
H
(or VL) when VIN = 0. (7) VH slew
rate conditions are: V
IN
= V
CM
+0.4V, G = +2, VL = V
CM
–1.2V, VH = step between VCM + 1.2V and VCM. VL slew rate conditions are similar. (8) Linearity Guardband
is defined for an output sinusoid (f = 5MHz, V
O
= V
CM
±1Vp-p) centered between the limiter levels (VH and VL). It is the difference between the limiter level and the
peak output voltage where SFDR decreases by 3dB (see Figure 9).
SPECIFICATIONS—VS = +5V (CONT)
G = +2, RL = 500Ω tied to VCM = 2.5V, RF = 402Ω, VL = –1.2V, VH = +1.2V (Figure 2 for AC performance only), unless otherwise noted.
OPA688U, P
TYP GUARANTEED
(1)
0°C to –40°C to
MIN/
TEST
PARAMETER CONDITIONS +25°C +25°C +70°C +85°C UNITS MAX
LEVEL
(2)
Page 5
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®
OPA688
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................................................. ±6.5V
Internal Power Dissipation .......................... See Thermal Characteristics
Common-Mode Input Voltage ............................................................. ±V
S
Differential Input Voltage ..................................................................... ±V
S
Limiter Voltage Range........................................................... ±(VS – 0.7V)
Storage Temperature Range: P, U ................................–40°C to +125°C
Lead Temperature (DIP, soldering, 10s) ..................................... +300°C
(SO-8, soldering, 3s) ...................................... +260°C
Junction Temperature .................................................................... +175°C
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
PIN CONFIGURATION
Top View DIP-8, SO-8
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.
1
2
3
4
8
7
6
5
NC
Inverting Input
Non-Inverting Input
–V
S
V
H
+V
S
Output
V
L
PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER
(1)
MEDIA
OPA688P DIP-8 Plastic DIP 006 –40°C to +85°C OPA688P OPA688P Rails
OPA688U SO-8 Surface Mount 182 –40°C to +85°C OPA688U OPA688U Rails
"""""OPA688U/2K5 Tape and Reel
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of OPA688U/2K5” will get a single 2500-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
Page 6
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®
OPA688
TYPICAL PERFORMANCE CURVES —VS = ±5V
G = +2, RL = 500Ω, RF = 402Ω, VH = –VL = 2V (Figure 1 for AC performance only), unless otherwise noted.
VL—LIMITED PULSE RESPONSE
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
Time (20ns/div)
Input and Output Voltages (V)
V
O
V
IN
G = +2
V
L
= –2V
12
9
6
3
0
–3
–6
–9
–12
–15
–18
NON-INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (Hz)
Normalized Gain (dB)
1M 10M 100M 1G
VO = 0.2Vp-p
G = +1, RC = ∞, RF = 25Ω
G = +1, RC = 175Ω, RF = 25Ω
G = +2, RC = ∞
R
F
R
S
150Ω
R
G
R
C
V
O
V
IN
G = +5, RC = ∞
6
3
0
–3
–6
–9
–12
–15
–18
–21
–24
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (Hz)
Normalized Gain (dB)
1M 10M 100M 1G
VO = 0.2Vp-p
G = –2
G = –5
G = –1
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (V)
VO = 0.2Vp-p
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
VH—LIMITED PULSE RESPONSE
V
O
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
Time (20ns/div)
Input and Output Voltages (V)
V
IN
G = +2
V
H
= +2V
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (V)
VO = 4Vp-p
VH = –VL = 2.5V
2.5
2.0
1.5
0.10
0.05
0
–0.5
–1.0
–1.5
–2.0
–2.5
Page 7
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®
OPA688
TYPICAL PERFORMANCE CURVES —VS = ±5V (cont.)
G = +2, RL = 500Ω, RF = 402Ω, VH = –VL = 2V (Figure 1 for AC performance only), unless otherwise noted.
HARMONIC DISTORTION vs FREQUENCY
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
2nd and 3rd Harmonic Distortion (dBc)
HD2
HD3
VO = 2Vp-p
R
L
= 500Ω
Frequency (Hz)
1M 10M 20M
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
± Limit Voltage (V)
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
2nd and 3rd Harmonic Distortion (dBc)
VO = 0V
DC
±1Vp
f
1
= 5MHz
R
L
= 500Ω
HD2
HD3
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
3RD HARMONIC DISTORTION vs OUTPUT SWING
Output Swing (Vp-p)
3rd Harmonic Distortion (dBc)
0.1 1.0 5.0
RL = 500Ω
f1 = 20MHz
f1 = 10MHz
f1 = 5MHz
f1 = 2MHz
f1 = 1MHz
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
HARMONIC DISTORTION vs LOAD RESISTANCE
Load Resistance (Ω)
2nd and 3rd Harmonic Distortion (dBc)
50 100 1000
VO = 2Vp-p
f
1
= 5MHz
HD2
HD3
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
2ND HARMONIC DISTORTION vs OUTPUT SWING
Output Swing (Vp-p)
2nd Harmonic Distortion (dBc)
0.1 1.0 5.0
RL = 500Ω
f1 = 20MHz
f1 = 10MHz
f1 = 1MHz
f1 = 5MHz
f1 = 2MHz
12
9
6
3
0
–3
–6
–9
–12
–15
–18
LARGE-SIGNAL FREQUENCY RESPONSE
Frequency (Hz)
1M 10M 100M 1G
Gain (dB)
G = +2
≤ 0.2Vp-p
2Vp-p
Page 8
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®
OPA688
TYPICAL PERFORMANCE CURVES —VS = ±5V (cont.)
G = +2, RL = 500Ω, RF = 402Ω, VH = –VL = 2V (Figure 1 for AC performance only), unless otherwise noted.
60
50
40
30
20
10
0
–10
–20
OPEN-LOOP FREQUENCY RESPONSE
Frequency (Hz)
10k 100k 1M 10M 100M 1G
Open-Loop Gain (dB)
0
–30
–60
–90
–120
–150
–180
–210
–240
Open-Loop Phase (deg)
Gain
Phase
VO = 0.2Vp-p
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
LIMITER FEEDTHROUGH
Frequency (Hz)
Feedthrough (dB)
1M 10M 50M
402Ω
200Ω
402Ω
V
O
8
V
H
= 0.02Vp-p + 2V
DC
6
3
0
–3
–6
–9
–12
–15
–18
–21
–24
LIMITER SMALL-SIGNAL FREQUENCY RESPONSE
Frequency (Hz)
1M 10M 100M 1G
Limiter Gain (dB)
VO = 0.02Vp-p
402Ω
200Ω
402Ω
V
O
8
V
H
= 0.02Vp-p + 2.0V
DC
2V
DC
12
9
6
3
0
–3
–6
–9
–12
–15
–18
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (Hz)
1M 10M 100M 1G
Gain to Capacitive Load (dB)
VO = 0.2Vp-p
CL = 100pF
CL = 0
CL = 10pF
OPA688
R
S
200Ω
1kΩ is optional
V
IN
V
O
C
L
1kΩ
402Ω
402Ω
80
70
60
50
40
30
20
10
0
R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
1 10 100 300
R
S
(Ω)
100
10
1
INPUT NOISE DENSITY
Frequency (Hz)
100 1k 10k 100k 1M 10M
Input Voltage Noise Density (nV/√Hz)
Input Current Noise Density (pA/√Hz)
Voltage Noise
6.3nV/√Hz
Current Noise
2.0pA/√Hz
Page 9
9
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OPA688
TYPICAL PERFORMANCE CURVES —VS = ±5V (cont.)
G = +2, RL = 500Ω, RF = 402Ω, VH = –VL = 2V (Figure 1 for AC performance only), unless otherwise noted.
100
10
1
0.1
CLOSED-LOOP OUTPUT IMPEDANCE
Frequency (Hz)
1M 1G10M 100M
Output Impedance (Ω)
G = +1
R
F
= 25Ω
V
O
= 0.2Vp-p
100
95
90
85
80
75
70
65
60
55
50
PSR AND CMR vs TEMPERATURE
Ambient Temperature (°C)
–50 –25 0 25 50 75 100
PSR and CMR, Input Referred (dB)
PSR–
PSRR
PSR+
CMRR
5.0
4.5
4.0
3.5
3.0
VOLTAGE RANGES vs TEMPERATURE
Ambient Temperature (°C)
–50 –25 0 25 50 75 100
±Voltage Range (V)
Output Voltage Range
VH = –VL = 4.3V
Common-Mode Input Range
20
18
16
14
12
10
SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE
Ambient Temperature (°C)
–50 –25 0 25 50 75 100
Supply Current (mA)
120
110
100
90
80
70
Output Current (mA)
Output Current, Sourcing
Supply Current
|Output Current, Sinking|
100
75
50
25
0
–25
–50
–75
–100
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE
Limiter Headroom (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Limter Input Bias Current (µA)
Maximum Over Temperature
Minimum Over Temperature
Limiter Headroom = +VS – V
H
Current = IVH or –I
VL
= VL – (–VS)
Page 10
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OPA688
TYPICAL PERFORMANCE CURVES —VS = +5V
G = +2, RF = 402Ω, RL = 500Ω tied to V
CM
= 2.5V, VL = V
CM
–1.2V, VH = V
CM
+1.2V, (Figure 2 for AC performance only), unless otherwise noted.
6
3
0
–3
–6
–9
–12
–15
–18
–21
–24
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (Hz)
Normalized Gain (dB)
1M 10M 100M 1G
VO = 0.2Vp-p
G = –5
G = –2
G = –1
12.0
9.0
6.0
3.0
0
–3.0
–6.0
–9.0
–12.0
–15.0
–18.0
LARGE-SIGNAL FREQUENCY RESPONSE
Frequency (Hz)
1M 10M 100M 1G
Gain (dB)
2.0Vp-p
≤ 0.2Vp-p
G = +2
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
HARMONIC DISTORTION vs FREQUENCY
Frequency (Hz)
1M 10M 20M
2nd and 3rd Harmonic Distortion (dBc)
VO = 2Vp-p
R
L
= 500Ω
HD2
HD3
12
9
6
3
0
–3
–6
–9
–12
–15
–18
NON-INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (Hz)
1M 10M 100M 1G
VO = 0.2Vp-p
G = +1, RC = ∞, RF = 25Ω
G = +1, RC = 175Ω, RF = 25Ω
G = +2, RC = ∞
G = +5, RC = ∞
Normalized Gain (dB)
R
F
R
S
150Ω
R
G
R
C
V
O
V
IN
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
|
Limit Voltages – 2.5VDC
|
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
2nd and 3rd Harmonic Distortion (dBc)
VO = 2.5V ±1Vp
f
1
= 5MHz
R
L
= 500Ω
HD2
HD3
VH AND VL—LIMITED PULSE RESPONSE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Time (20ns/div)
Input and Output Voltages (V)
VH = VCM +1.2V
V
L
= VCM –1.2V
V
O
V
O
V
IN
V
IN
V
CM
= 2.5V
Page 11
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®
OPA688
TYPICAL APPLICATIONS
DUAL SUPPLY, NON-INVERTING AMPLIFIER
Figure 1 shows a non-inverting gain amplifier for dual
supply operation. This circuit was used for AC characterization of the OPA688, with a 50Ω source, which it matches,
and a 500Ω load. The power supply bypass capacitors are
shown explicitly in Figures 1 and 2, but will be assumed in
the other figures. The limiter voltages (VH and VL) and their
bias currents (IVH and IVL) have the polarities shown.
SINGLE SUPPLY, NON-INVERTING AMPLIFIER
Figure 2 shows an AC coupled, non-inverting gain amplifier
for single supply operation. This circuit was used for AC
characterization of the OPA688, with a 50Ω source, which
it matches, and a 500Ω load. The power supply bypass
capacitors are shown explicitly in Figures 1 and 2, but will
be assumed in the other figures. The limiter voltages (V
H
and VL) and their bias currents (IVH and IVL) have the
polarities shown. Notice that the single supply circuit can
use 3 resistors to set VH and VL, where the dual supply
circuit usually uses 4 to reference the limit voltages to
ground.
LIMITED OUTPUT, ADC INPUT DRIVER
Figure 3 shows a simple ADC driver that operates on single
supply, and gives excellent distortion performance. The
limit voltages track the input range of the converter, completely protecting against input overdrive.
FIGURE 1. DC-Coupled, Dual Supply Amplifier. FIGURE 2. AC-Coupled, Single Supply Amplifier.
FIGURE 3. Single Supply, Limiting ADC Input Driver.
OPA688
49.9Ω
6
I
VH
V
O
V
IN
I
VL
–VS = –5V
3
2
4
7
8
5
R
F
402Ω
R
G
402Ω
500Ω
0.1µF
0.1µF0.1µF
174Ω
3.01kΩ 1.91kΩ
3.01kΩ 1.91kΩ
0.1µF
VH = +2V
V
L
= –2V
+
2.2µF
+
2.2µF
+VS = +5V
OPA688
57.6Ω
6
I
VH
VH = 3.7V
V
O
VL = 1.3V
V
IN
I
VL
806Ω
3
2
4
7
8
5
806Ω
523Ω
976Ω
523Ω
R
G
402Ω
R
F
402Ω
500Ω
0.1µF
0.1µF
0.1µF
+
2.2µF
0.1µF
VS = +5V
0.1µF
0.1µF
OPA688
VS = +5V
4
2
3
7
5
8
6
VS = +5V
+3.5V
+1.5V
V
IN
REFB
REFT
IN
0.1µF
100pF
V
H
= +3.6V
V
L
= +1.4V
0.1µF
0.1µF
0.1µF
402Ω
24.9Ω
562Ω
102Ω
402Ω
715Ω
715Ω
102Ω
562Ω
ADS822
10-Bit
40MSPS
10-Bit
Data
VS = +5V
INT/EXT
RSEL +V
S
GND
Page 12
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OPA688
PRECISION HALF WAVE RECTIFIER
Figure 4 shows a half wave rectifier with outstanding precision and speed. VH (pin 8) will default to a voltage between
3.1 and 3.8V if left open, while the negative limit is set to
ground.
When VO tries to go below ground, CCII charges C1 through
D1, which restores the output back to ground. D1 adds a
propagation delay to the restoration process, which then has
an exponential decay with time constant R1C1/G (G = +2 =
the OPA688 gain). When the signal is above ground, it
decays to ground with a time constant of R2C1. The OPA688
output recovers very quickly from overdrive.
FIGURE 6. Unity-Gain Buffer.
FIGURE 4. Precision Half Wave Rectifier.
OPA688
6
V
O
–VS = –5V
+VS = +5V
V
IN
2
3
4
7
8
5
402Ω402Ω
200Ω
NC
VERY HIGH SPEED SCHMITT TRIGGER
Figure 5 shows a very high speed Schmitt trigger. The
output levels are precisely defined, and the switching time
is exceptional. The output voltage swings between ±2V.
UNITY-GAIN BUFFER
Figure 6 shows a unity-gain voltage buffer using the OPA688.
The feedback resistor (RF) isolates the output from any board
inductance between pins 2 and 6. We recommend that RF ≥
24.9Ω for unity-gain buffer applications. RC is an optional
compensation resistor that reduces the peaking typically seen
at G = +1. Choosing RC = RS + RF gives a unity gain buffer
with approximately the G = +2 frequency response.
DC RESTORER
Figure 7 shows a DC restorer using the OPA688 and
OPA660. The OPA660’s OTA amplifier is used as a current
conveyor (CCII) in this circuit, with a current gain of 1.0.
OPA688
V
O
8
5
V
L
= –1V
V
H
= +3V
R
1
40.2Ω
402Ω
R
2
100kΩ
D
1
402Ω
20Ω
20Ω
V
IN
200Ω
R
Q
1kΩ
D
2
C
1
100pF
6
1
C
E
B3
CCII
2
U1
5
+1
U1
U1 = OPA660
R
Q
= 1kΩ (sets U1’s IQ)
D
1
, D2 = 1N4148
FIGURE 7. DC Restorer.
OPA688
6
V
O
–VS = –5V
3
2
4
7
8
5
0.1µF
0.1µF
3.01kΩ 1.91kΩ
3.01kΩ 1.91kΩ
402Ω
+VS = +5V
200Ω
V
IN
133Ω
FIGURE 5. Very High Speed Schmitt Trigger.
OPA688
V
O
R
S
V
S
R
F
24.9Ω
R
C
Page 13
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®
OPA688
DESIGN-IN TOOLS
APPLICATIONS SUPPORT
The Burr-Brown Applications Department is available for
design assistance at 1-800-548-6132 (US/Canada only). The
Burr-Brown Internet web page (http://www.burr-brown.com)
has the latest data sheets and other design aids.
DEMONSTRATION BOARDS
Two PC boards are available to assist in the initial evaluation
of circuit performance of the OPA688 in both package
styles. These are available as an unpopulated PCB with
descriptive documentation. See the demonstration board
literature for more information. The summary information
for these boards is shown below:
The limiters have a very sharp transition from the linear
region of operation to output limiting. This allows the limiter
voltages to be set very near (<100mV) the desired signal
range. The distortion performance is also very good near the
limiter voltages.
CIRCUIT LAYOUT
Achieving optimum performance with the high frequency
OPA688 requires careful attention to layout design and
component selection. Recommended PCB layout techniques
and component selection criteria are:
a) Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Open a window in the ground and
power planes around the signal I/O pins, and leave the
ground and power planes unbroken elsewhere.
b) Provide a high quality power supply. Use linear regu-
lators, ground plane and power planes to provide power.
Place high frequency 0.1µF decoupling capacitors < 0.2"
away from each power supply pin. Use wide, short traces to
connect to these capacitors to the ground and power planes.
Also use larger (2.2µF to 6.8µF) high frequency decoupling
capacitors to bypass lower frequencies. They may be somewhat further from the device, and be shared among several
adjacent devices.
c) Place external components close to the OPA688. This
minimizes inductance, ground loops, transmission line effects and propagation delay problems. Be extra careful with
the feedback (RF), input and output resistors.
d) Use high frequency components to minimize parasitic
elements. Resistors should be a very low reactance type.
Surface mount resistors work best and allow a tighter layout.
Metal film or carbon composition axially-leaded resistors
can also provide good performance when their leads are as
short as possible. Never use wirewound resistors for high
frequency applications. Remember that most potentiometers
have large parasitic capacitances and inductances.
Multilayer ceramic chip capacitors work best and take up
little space. Monolithic ceramic capacitors also work very
well. Use RF type capacitors with low ESR and ESL. The
large power pin bypass capacitors (2.2µF to 6.8µF) should
be tantalum for better high frequency and pulse performance.
e) Choose low resistor values to minimize the time constant
set by the resistor and its parasitic parallel capacitance. Good
metal film or surface mount resistors have approximately
0.2pF parasitic parallel capacitance. For resistors > 1.5kΩ,
this adds a pole and/or zero below 500MHz.
Make sure that the output loading is not too heavy. The
recommended 402Ω feedback resistor is a good starting
point in your design.
LITERATURE
DEMONSTRATION REQUEST
BOARD PACKAGE PRODUCT NUMBER
DEM-OPA68xP 8-Pin DIP OPA68xP MKT-350
DEM-OPA68xU SO-8 OPA68xU MKT-351
Contact the Burr-Brown Application Department for availability of these boards.
SPICE MODELS
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for high speed
active devices, like the OPA688, where parasitic capacitance
and inductance can have a major effect on frequency response.
SPICE models are available through the Burr-Brown web
site (www.burr-brown.com). These models do a good job of
predicting small-signal AC and transient performance under
a wide variety of operating conditions. They do not do as
well in predicting the harmonic distortion, temperature effects or differential gain and phase characteristics. These
models do not distinguish between the AC performance of
different package types.
OPERATING INFORMATION
THEORY OF OPERATION
The OPA688 is a voltage feedback op amp that is unity-gain
stable. The output voltage is limited to a range set by the
voltage on the limiter pins (5 and 8). When the input tries to
overdrive the output, the limiters take control of the output
buffer. This avoids saturating any part of the signal path,
giving quick overdrive recovery and excellent limiter accuracy at any signal gain.
Page 14
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OPA688
f) Use short direct traces to other wideband devices on
the board. Short traces act as a lumped capacitive load. Wide
traces (50 to 100 mils) should be used. Estimate the total
capacitive load at the output, and use the series isolation
resistor recommended in the RS vs Capacitive Load plot.
Parasitic loads < 2pF may not need the isolation resistor.
g) When long traces are necessary, use transmission line
design techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω transmission line is not required on board—a higher characteristic
impedance will help reduce output loading. Use a matching
series resistor at the output of the op amp to drive a
transmission line, and a matched load resistor at the other
end to make the line appear as a resistor. If the 6dB of
attenuation that the matched load produces is not acceptable,
and the line is not too long, use the series resistor at the
source only. This will isolate the source from the reactive
load presented by the line, but the frequency response will
be degraded.
Multiple destination devices are best handled as separate
transmission lines, each with its own series source and shunt
load terminations. Any parasitic impedances acting on the
terminating resistors will alter the transmission line match,
and can cause unwanted signal reflections and reactive
loading.
h) Do not use sockets for high speed parts like the OPA688.
The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network. Best results are obtained by soldering the part
onto the board. If socketing for DIP prototypes is desired,
high frequency flush mount pins (e.g., McKenzie Technology #710C) can give good results.
POWER SUPPLIES
The OPA688 is nominally specified for operation using
either ±5V supplies or a single +5V supply. The maximum
specified total supply voltage of 12V allows reasonable
tolerances on the supplies. Higher supply voltages can break
down internal junctions, possibly leading to catastrophic
failure. Single supply operation is possible as long as common mode voltage constraints are observed. The common
mode input and output voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input and output headroom requirement will allow
design of non-standard or single supply operation circuits.
Figure 2 shows one approach to single-supply operation.
ESD PROTECTION
ESD damage has been known to damage MOSFET devices,
but any semiconductor device is vulnerable to ESD damage.
This is particularly true for very high speed, fine geometry
processes.
ESD damage can cause subtle changes in amplifier input
characteristics without necessarily destroying the device. In
precision operational amplifiers, this may cause a noticeable
degradation of offset voltage and drift. Therefore, ESD
handling precautions are required when handling the OPA688.
OUTPUT LIMITERS
The output voltage is linearly dependent on the input(s)
when it is between the limiter voltages VH (pin 8) and V
L
(pin 5). When the output tries to exceed VH or VL, the
corresponding limiter buffer takes control of the output
voltage and holds it at VH or VL.
Because the limiters act on the output, their accuracy does
not change with gain. The transition from the linear region
of operation to output limiting is very sharp—the desired
output signal can safely come to within 30mV of VH or V
L
with no onset of non-linearity.
The limiter voltages can be set to within 0.7V of the supplies
(VL ≥ –VS + 0.7V, VH ≤ +VS – 0.7V). They must also be at
least 200mV apart (VH – VL ≥ 0.2V).
When pins 5 and 8 are left open, VH and VL go to the
Default Voltage Limit; the minimum values are in the spec
table. Looking at Figure 8 for the zero bias current case will
show the expected range of (Vs – default limit voltages) =
headroom.
When the limiter voltages are more than 2.1V from the
supplies (VL ≥ –VS + 2.1V or VH ≤ +VS – 2.1V), you can use
simple resistor dividers to set VH and VL (see Figure 1).
Make sure you include the Limiter Input Bias Currents
(Figure 8) in the calculations (i.e., IVL ≈ –50µA out of pin 5,
and IVH ≈ +50 µA out of pin 8). For good limiter voltage
accuracy, run at least 1mA quiescent bias current through
these resistors.
When the limiter voltages need to be within 2.1V of the
supplies (VL ≤ –VS + 2.1V or VH ≥ +VS – 2.1V), consider
using low impedance buffers to set VH and VL to minimize
errors due to bias current uncertainty. This will typically be
the case for single supply operation (VS = +5V). Figure 2
runs 2.5mA through the resistive divider that sets VH and
VL. This keeps errors due to IVH and IVL < ±1% of the target
limit voltages.
FIGURE 8. Limiter Bias Current vs Bias Voltage.
100
75
50
25
0
–25
–50
–75
–100
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE
Limiter Headroom (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Limter Input Bias Current (µA)
Maximum Over Temperature
Minimum Over Temperature
Limiter Headroom = +VS – V
H
Current = IVH or –I
VL
= VL – (–VS)
Page 15
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OPA688
The limiters’ DC accuracy depends on attention to detail.
The two dominant error sources can be improved as follows:
• Power supplies, when used to drive resistive dividers that
set VH and VL, can contribute large errors (e.g., ±5%).
Using a more accurate source, and bypassing pins 5 and 8
with good capacitors, will improve limiter PSRR.
• The resistor tolerances in the resistive divider can also
dominate. Use 1% resistors.
Other error sources also contribute, but should have little
impact on the limiters’ DC accuracy:
• Reduce offsets caused by the Limiter Input Bias Currents.
Select the resistors in the resistive divider(s) as described
above.
• Consider the signal path DC errors as contributing to
uncertainty in the useable output swing.
• The Limiter Offset Voltage only slightly degrades limiter
accuracy.
Figure 9 shows how the limiters affect distortion performance. Virtually no degradation in linearity is observed for
output voltage swinging right up to the limiter voltages.
makes the OPA688 an ideal choice for a wide range of high
frequency applications.
Many high speed applications, such as driving A/D converters, require op amps with low output impedance. As shown
in the Output Impedance vs Frequency performance curve,
the OPA688 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain decreases with frequency.
THERMAL CONSIDERATIONS
The OPA688 will not require heat-sinking under most operating conditions. Maximum desired junction temperature
will set a maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and the additional power dissipated
in the output stage (PDL) while delivering load power. P
DQ
is simply the specified no-load supply current times the total
supply voltage across the part. PDL depends on the required
output signals and loads. For a grounded resistive load, and
equal bipolar supplies, it is at a maximum when the output
is at 1/2 either supply voltage. In this condition, PDL = V
S
2
/
(4RL) where RL includes the feedback network loading.
Note that it is the power in the output stage, and not in the
load, that determines internal power dissipation.
The operating junction temperature is: TJ = TA + P
D θJA
,
where TA is the ambient temperature.
For example, the maximum TJ for a OPA688U with G = +2,
RFB = 402Ω, RL = 100Ω, and ±VS = ±5V at the maximum
TA = +85°C is calculated as:
FIGURE 10. Offset Voltage Trim.
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
± Limit Voltage (V)
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
2nd and 3rd Harmonic Distortion (dBc)
VO = 0V
DC
±1Vp
f
1
= 5MHz
R
L
= 500Ω
HD2
HD3
FIGURE 9. Harmonic Distortion Near Limit Voltages.
R
2
OPA688
R3 = R1 || R
2
R
1
R
TRIM
47kΩ
+V
S
V
O
–V
S
VIN or Ground
0.1µF
NOTES: (1) R3 is optional and minimizes output offset
due to input bias currents. (2) Set R
1
<< R
TRIM
.
PDQ=10V•20mA
()
= 200mW
P
DL
=
5V
()
2
4• 100Ω||804Ω
()
=70mW
P
D
= 200mW +70mW = 270mW
T
J
=85°C+ 270mW •125°C/W=119°C
OFFSET VOLTAGE ADJUSTMENT
The circuit in Figure 10 allows offset adjustment without
degrading offset drift with temperature. Use this circuit with
caution since power supply noise can inadvertently couple
into the op amp.
Remember that additional offset errors can be created by the
amplifier’s input bias currents. Whenever possible, match
the impedance seen by both DC input bias currents using R3.
This minimizes the output offset voltage caused by the input
bias currents.
OUTPUT DRIVE
The OPA688 has been optimized to drive 500Ω loads, such
as A/D converters. It still performs very well driving 100Ω
loads; the specifications are shown for the 500Ω load. This
Page 16
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®
OPA688
CAPACITIVE LOADS
Capacitive loads, such as the input to ADCs, will decrease
the amplifier’s phase margin, which may cause high frequency peaking or oscillations. Capacitive loads ≥ 2pF
should be isolated by connecting a small resistor in series
with the output as shown in Figure 11. Increasing the gain
from +2 will improve the capacitive drive capabilities due
to increased phase margin.
In general, capacitive loads should be minimized for optimum high frequency performance. The capacitance of coax
cable (29pF/foot for RG-58) will not load the amplifier
when the coaxial cable, or transmission line, is terminated
in its characteristic impedance.
capacitance from the inverting input to ground causes peaking or oscillations. To compensate for this effect, connect a
small capacitor in parallel with the feedback resistor. The
bandwidth will be limited by the pole that the feedback
resistor and this capacitor create. In other high gain applications, use a three resistor “Tee” network to reduce the RC
time constants set by the parasitic capacitances. Be careful
to not increase the noise generated by this feedback network
too much.
PULSE SETTLING TIME
The OPA688 is capable of an extremely fast settling time in
response to a pulse input. Frequency response flatness and
phase linearity are needed to obtain the best settling times.
For capacitive loads, such as an A/D converter, use the
recommended RS in the RS vs Capacitive Load plot. Extremely fine scale settling (0.01%) requires close attention to
ground return current in the supply decoupling capacitors.
The pulse settling characteristics when recovering from
overdrive are very good.
DISTORTION
The OPA688’s distortion performance is specified for a
500Ω load, such as an A/D converter. Driving loads with
smaller resistance will increase the distortion as illustrated in
Figure 12. Remember to include the feedback network in the
load resistance calculations.
FIGURE 11. Driving Capacitive Loads.
FIGURE 12. 5MHz Harmonic Distortion vs Load Resistance.
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
HARMONIC DISTORTION vs LOAD RESISTANCE
Load Resistance (Ω)
2nd and 3rd Harmonic Distortion (dBc)
50 100 1000
VO = 2Vp-p
f
1
= 5MHz
HD2
HD3
OPA688
C
L
R
L
R
S
V
O
RL is optional
FREQUENCY RESPONSE COMPENSATION
The OPA688 is internally compensated to be unity-gain
stable, and has a nominal phase margin of 60° at a gain of
+2. Phase margin and peaking improve at higher gains.
Recall that an inverting gain of –1 is equivalent to a gain of
+2 for bandwidth purposes (i.e., noise gain = 2).
Standard external compensation techniques work with this
device. For example, in the inverting configuration, the
bandwidth may be limited without modifying the inverting
gain by placing a series RC network to ground on the
inverting node. This has the effect of increasing the noise
gain at high frequencies, which limits the bandwidth.
To maintain a wide bandwidth at high gains, cascade several
op amps, or use the high gain optimized OPA689.
In applications where a large feedback resistor is required,
such as photodiode transimpedance amplifier, the parasitic
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