Datasheet OPA658N-250, OPA658P, OPA658NB-3K, OPA658U-2K5, OPA658UB-2K5 Datasheet (Burr Brown)

1

®

OPA658

FEATURES

● UNITY GAIN STABLE BANDWIDTH:

900MHz

● LOW POWER: 50mW

● LOW DIFFERENTIAL GAIN/PHASE ERRORS:

0.025%/0.02

°

● HIGH SLEW RATE: 1700V/µs

● GAIN FLATNESS: 0.1dB to 135MHz

● HIGH OUTPUT CURRENT (80mA)

Wideband, Low Power Current Feedback

OPERATIONAL AMPLIFIER

APPLICATIONS

● MEDICAL IMAGING

● HIGH-RESOLUTION VIDEO

● HIGH-SPEED SIGNAL PROCESSING

● COMMUNICATIONS

● PULSE AMPLIFIERS

● ADC/DAC GAIN AMPLIFIER

● MONITOR PREAMPLIFIER

● CCD IMAGING AMPLIFIER

OPA658

DESCRIPTION

The OPA658 is an ultra-wideband, low power current
feedback video operational amplifier featuring high
slew rate and low differential gain/phase error. The
current feedback design allows for superior large sig­nal bandwidth, even at high gains. The low differential
gain/phase errors, wide bandwidth and low quiescent

current make the OPA658 a perfect choice for numer­ous video, imaging and communications applications.

The OPA658 is optimized for low gain operation and
is also available in dual (OPA2658) and quad
(OPA4658) configurations.

®

C

COMP

Current Mirror

In

–

In

+

V

OUT

I

BIAS

I

BIAS

+V

S

–V

S

Current Mirror

Buffer

OPA658

OPA658

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone] • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: [phone] (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

© 1994 Burr-Brown Corporation PDS-1268F Printed in U.S.A. March, 1998

2

®

OPA658

FREQUENCY RESPONSE

Closed-Loop Bandwidth

(2)

G = +1

(4)

900 ✻

(1)

MHz
G = +2 680 400 ✻ MHz
G = +5 370 ✻ MHz

G = +10 200 ✻ MHz

Slew Rate

(3)

G = +2, 2V Step 1700 1000 ✻ V/µs

At Minimum Specified Temperature 1500 900 ✻ V/µs

Settling Time: 0.01% G = +2, 2V Step 15 ✻ ns

0.1% G = +2, 2V Step 11.5 ✻ ns
1% G = +2, 2V Step 6 ✻ ns

Spurious Free Dynamic Range f = 5MHz, G = +2, V

O

= 2Vp-p 68 ✻ dBc

f = 20MHz, G= +2, V

O

= 2Vp-p 56 ✻ dBc
Third Order Intercept Point f = 10MHz, 4dBm Each Tone 40 ✻ dBm
Differential Gain G = +2, NTSC, V

O

= 1.4Vp-p, RL = 150Ω 0.025 ✻ %

Differential Phase G = +2, NTSC, V

O

= 1.4Vp-p, RL = 150Ω 0.02 ✻ degrees

Bandwidth for 0.1dB Flatness G = +2 135

(5)

✻ MHz

OFFSET VOLTAGE

Input Offset Voltage V

CM

= 0V ±3 ±5.5 ±2 ±4.5 mV

Over Temperature Range ±5 ±8 ±4 ±7mV

Power Supply Rejection Ratio V

S

= ±4.7 to ±5.5V 55 64 58 67 dB

INPUT BIAS CURRENT

Non-Inverting V

CM

= 0V ±5.7 ±30 ✻ ±18 µA

Over Temperature Range ±10 ±80 ✻ ±35 µA

Inverting V

CM

= 0V ±1.1 ±35 ✻✻ µA

Over Temperature Range ±30 ±75 ✻✻ µA

NOISE

Input Voltage Noise Density

f = 100Hz 16 ✻ nV/√Hz
f = 2kHz 4.9 ✻ nV/√Hz
f = 10kHz 3.2 ✻ nV/√Hz
f = 1MHz 3.2 ✻ nV/√Hz
f

B

= 100Hz to 200MHz 45.3 ✻ µVrms

Input Bias Current Noise Density

Inverting: f = 1MHz 32 ✻ pA/√Hz
Non-Inverting: f = 1MHz 11.9 ✻ pA/√Hz

INPUT VOLTAGE RANGE

Common-Mode Input Range

Over Temperature Range ±2.5 ±2.9 ✻✻ V

Common-Mode Rejection V

CM

= ±1V 45 50 ✻✻ dB

INPUT IMPEDANCE

Non-Inverting 500 || 1 ✻ kΩ || pF
Inverting 50 ✻ Ω

OPEN-LOOP TRANSRESISTANCE

Open-Loop Transresistance V

O

= ±2V, RL = 100Ω 150 190 200 250 kΩ

Over Temperature Range V

O

= ±2V, RL = 100Ω 100 150 kΩ

OUTPUT

Voltage Output No Load ±2.7 ±2.9 ✻✻ V

Over Temperature Range ±2.5 ±2.75 ✻✻ V

Voltage Output R

L

= 250Ω±2.7 ±2.9 ✻✻ V

Over Temperature Range ±2.5 ±2.7 ✻✻ V

Voltage Output R

L

= 100Ω±2.2 ±2.8 ✻✻ V

Over Temperature Range ±2.0 ±2.5 ✻✻ V

Output Current, Sourcing 80 120 ✻✻ mA

Over Temperature 70 ✻ mA

Output Current, Sinking 60 80 ✻✻ mA

Over Temperature 35 ✻ mA
Short Circuit Current 150 ✻ mA
Output Resistance 0.1MHz, G = +2 0.02 ✻ Ω

POWER SUPPLY

Specified Operating Voltage ±5 ✻ V
Operating Voltage Range ±4.5 ±5.5 ✻✻V
Quiescent Current V

S

= ±5V ±5 ±7.75 ±4.5 ±5.75 mA

Over Temperature Range ±5.5 ±8.5 ±4.7 ±6.5 mA

TEMPERATURE RANGE

Specification: P, U, N, UB, NB –40 +85 ✻✻°C
Thermal Resistance,

θ

JA

P 8-Pin DIP 100 ✻ °C/W

U SO-8 125 ✻ °C/W

N SOT23-5 150 ✻ °C/W

NOTES: (1) An asterisk (✻) specifies the same value as the grade to the left. (2) Frequency response can be strongly influenced by PC board parasitics. The
demonstration boards show low parasitic layouts for this part. Refer to the demonstration board layout for details. (3) Slew rate is rate of change from 10% to 90%
of output voltage step. (4) At G = +1, R

FB

= 560Ω for PDIP and 402Ω for SO-8. (5) This specification is PC board layout dependent.

SPECIFICATIONS

At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.

OPA658P, U, N OPA658UB, NB

PARAMETER CONDITION MIN TYP MAX MIN TYP MAX UNITS

3

®

OPA658

1

2
3
4

8

7
6
5

NC

+V

S

Output
NC

NC

–Input
+Input

–V

S

1

2

3

54+V

S

–Input

Output

–V

S

+Input

Top View DIP/SO-8

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

PIN CONFIGURATION

Supply ............................................................................................... ±5.5V

Internal Power Dissipation .......................... See Thermal Considerations

Differential Input Voltage .................................................................. ±1.2V

Input Voltage Range ............................................................................ ± V

S

Storage Temperature Range: P, U, UB, N, NB ............ –40°C to +125°C

Lead Temperature (soldering, 10s).............................................. +300°C

(soldering, SOIC 3s) ...................................................................... +260°C

Junction Temperature (T

J

) ............................................................ +175°C

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC
DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from per­formance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published speci­fications.

SOT23-5

PACKAGE
DRAWING TEMPERATURE PACKAGE ORDERING

PRODUCT PACKAGE NUMBER

(1)

RANGE MARKING

(2)

NUMBER

(3)

OPA658U SO-8 Surface Mount 182 –40°C to +85°C OPA658U OPA658U
OPA658UB SO-8 Surface Mount 182 –40°C to +85°C OPA658UB OPA658UB
OPA658N 5-pin SOT23-5 331 –40°C to +85°C A58 OPA658N-250

OPA658N-3k

OPA658NB 5-pin SOT23-5 331 –40°C to +85°C A58B OPA658NB-250

OPA658NB-3k

OPA658P 8-Pin Plastic DIP 006 –40°C to +85°C OPA658P OPA658P

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) The “B” grade of the SO-8 will be
marked with a “B” by pin 8. The “B” grade of the SOT23-5 will be marked with a “B” near pins 3 and 4. (3) The SOT23-5 is only available on a 7" tape and reel (e.g. ordering
250 pieces of “OPA658N-250” will get a single 250 piece tape and reel. Ordering 3000 pieces of “OPA658N-3k” will get a single 3000 piece tape and reel). Please refer
to Appendix B of Burr-Brown IC Data Book for detailed Tape and Reel Mechanical information.

PACKAGE/ORDERING INFORMATION

4

®

OPA658

TYPICAL PERFORMANCE CURVES

At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.

55

50

45

40

35

30

25

–4 –3 –2 –1 0 1 2 3 4

COMMON-MODE REJECTION

vs INPUT COMMON-MODE VOLTAGE

Common-Mode Rejection (dB)

Common-Mode Voltage (V)

SUPPLY CURRENT vs TEMPERATURE

5

4

–75 –50 –25 0 25 50 75 100 125

Ambient Temperature (°C)

Supply Current (±mA)

NON-INVERTING INPUT BIAS CURRENT

vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Ambient Temperature (°C)

Non-Inverting Input Bias Current I

B

+ (µA)

10

8

6

4

2

3.20

3.10

3.0

2.90

2.80

2.70

2.60

2.50

2.40

2.30

OUTPUT SWING vs TEMPERATURE

Temperature (°C)

–60 –40 –20 0 20 40 60 80 100

Output Swing (V)

+V

O

–V

O

RL = 250Ω

RL = 100Ω

–V

O

+V

O

PSRR AND CMR vs TEMPERATURE

75

70

65

60

55

50

45

–75 –50 –25 0 25 50 75 100 125

PSRR , CMR (dB)

CMR

PSR–

Temperature (°C)

PSR+

PSRR

120

110

100

90

80

70

–75 –50 –25 0 25 50 75 100 125

OUTPUT CURRENT vs TEMPERATURE

Ambient Temperature (°C)

Output Current (±mA)

IO–

I

O

+

5

®

OPA658

At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.

TYPICAL PERFORMANCE CURVES (CONT)

10

6

10

5

10

4

10

3

10

2

10

1

1

0

–45

–90

–135

–180

–225

1k 10k 100k 1M 10M 100M 1G

OPEN-LOOP TRANSIMPEDANCE AND PHASE

vs FREQUENCY

Frequency (Hz)

Transimpedance (Ω)

Open-Loop Phase (°)

Phase

Transimpedance

INVERTING INPUT BIAS CURRENT

vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Inverting Input Bias Current I

B

– (µA)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

OPEN-LOOP GAIN AND PHASE vs FREQUENCY

Frequency (Hz)

60

40

20

0

–20

–40

–60

0

–45

–90

–135

–180

–225

1k 10k 100k 1M 10M 100M 1G

Open-Loop Gain (dB)

Open-Loop Phase (°)

Gain

Phase

6

3

0

–3

–6

–9

1M 10M 100M 1G

CLOSED-LOOP BANDWIDTH

Frequency (Hz)

Gain (dB)

SO-8 Bandwidth = 881MHz, RFB = 402Ω

G = +1

DIP Bandwidth = 949MHz, RFB = 560Ω

9

6

3

0

–3

–6

1M 10M 100M 1G

CLOSED-LOOP BANDWIDTH

Frequency (Hz)

Gain (dB)

DIP Bandwidth = 682MHz

SO-8 Bandwidth = 680MHz

G = +2

20

17

14

11

8

5

2

1M 10M 100M 1G

CLOSED-LOOP BANDWIDTH

Frequency (Hz)

Gain (dB)

SO-8/DIP Bandwidth= 372MHz

G = +5

6

®

OPA658

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.

160
120

80
40

0
–40
–80

–120
–160

Time (5ns/div)

SMALL SIGNAL TRANSIENT RESPONSE

Output Voltage (mV)

G = +2

1.6

1.2

0.8

0.4
0

–0.4
–0.8
–1.2
–1.6

LARGE SIGNAL TRANSIENT RESPONSE

Time (5ns/div)

Output Voltage (V)

G = +2

–50

–60

–70

–80

–90

–100

100k 1M 10M 100M

HARMONIC DISTORTION vs FREQUENCY

Frequency (Hz)

Harmonic Distortion (dBc)

2f

O

3f

O

5MHz HARMONIC DISTORTION vs OUTPUT SWING

Output Swing (Vp-p)

–60
–65
–70
–75
–80
–85
–90
–95

–100

01234

Harmonic Distortion (dBc)

2f

O

3f

O

G = +2

26

23

20

17

14

11

8

1M 10M 100M 1G

CLOSED-LOOP BANDWIDTH

Frequency (Hz)

Gain (dB)

SO-8/DIP Bandwidth = 200MHz

G = +10

40

35

30

25

20

15

10

10

1009080706050403020

RECOMMENDED ISOLATION RESISTANCE

vs CAPACITIVE LOAD

Capacitive Load (pf)

Isolation Resistance

G = +2

OPA658

C

L

1kΩ

R

ISO

402Ω

402Ω

7

®

OPA658

At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted.

TYPICAL PERFORMANCE CURVES (CONT)

–60

–65

–70

–75

–80

–85

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

HARMONIC DISTORTION vs TEMPERATURE

(V

O

= 2Vp-p, G = +2)

Harmonic Distortion (dBc)

3f

O

2f

O

HARMONIC DISTORTION vs GAIN

(f

O

= 5MHz, VO = 2Vp-p)

Non-Inverting Gain (V/V)

–50

–55

–60

–65

–70

–75

Harmonic Distortion (dBc)

012345678910

3f

O

2f

O

10MHz HARMONIC DISTORTION vs OUTPUT SWING

Output Swing (Vp-p)

–60

–70

–80

–90

–100

0.01 0.1

2f

O

14V10

Harmonic Distortion (dBc)

3f

O

INPUT VOLTAGE AND CURRENT NOISE

vs FREQUENCY

Frequency (Hz)

100

10

1

Voltage Noise (nV/√Hz)

Current Noise (pA/√Hz)

10

2

10

3

10

4

10

5

10

6

10

7

Non-Inverting Noise

Inverting Current Noise

Voltage Noise

8

®

OPA658

For non-inverting operation, the input signal is applied to the
non-inverting (high impedance buffer) input. The output
(buffer) error current (IE) is generated at the low impedance
inverting input. The signal generated at the output is fed back
to the inverting input such that the overall gain is (1 + RFB/RFF).
Where a voltage-feedback amplifier has two symmetrical high
impedance inputs, a current feedback amplifier has a low
inverting (buffer output) impedance and a high non-inverting
(buffer input) impedance.

The closed-loop gain for the OPA658 can be calculated
using the following equations:

(1)

(2)

At higher gains the small value inverting input impedance
causes an apparent loss in bandwidth. This can be seen from
the equation:

(3)

This loss in bandwidth at high gains can be corrected
without affecting stability by lowering the value of the
feedback resistor from the specified value of 402Ω.

OFFSET VOLTAGE AND NOISE

The output offset is the algebraic sum of the input offset
voltage and bias current errors. The output offset for non­inverting operation is calculated by the following equation:

(4)

If all terms are divided by the gain (1 + R

FB/RFF

) it can be
observed that input referred offsets improve as gain increases.
The effective noise at the output can be determined by taking

APPLICATIONS INFORMATION

THEORY OF OPERATION

Conventional op amps depend on feedback to drive their
inputs to the same potential, however the current feedback
op amp’s inverting and non-inverting inputs are connected
by a unity gain buffer, thus enabling the inverting input to
automatically assume the same potential as the non-invert­ing input. This results in very low impedance at the inverting
input to sense the feedback as an error current signal.

DISCUSSION OF PERFORMANCE

The OPA658 is a low-power, unity gain stable, current
feedback operational amplifier which operates on ±5V power
supply. The current feedback architecture offers the follow­ing important advantages over voltage feedback architec­tures: (1) the high slew rate allows the large signal perfor­mance to approach the small signal performance, and (2)
there is very little bandwidth degradation at higher gain
settings.

The current feedback architecture of the OPA658 provides
the traditional strength of excellent large signal response
plus wide bandwidth, making it a good choice for use in high
resolution video, medical imaging and DAC I/V Conver­sion. The low power requirements make it an excellent
choice for numerous portable applications.

DC GAIN TRANSFER CHARACTERISTICS

The circuit in Figure 1 shows the equivalent circuit for
calculating the DC gain. When operating the device in the
inverting mode, the input signal error current (I

E

) is ampli-

fied by the open loop transimpedance gain (T

O

). The output

signal generated is equal to T

O

x IE. Negative feedback is

applied through R

FB

such that the device operates at a gain

equal to –R

FB/RFF

.

FIGURE 1. Equivalent Circuit.

FIGURE 2. Output Offset Voltage Equivalent Circuit.

V

O

T

O

C

C

L

SRS

(50Ω)

C

1

V

I

V

N

R

FF

R

FB

I

E

+

–

Inverting Gain =

–

R

FB

R

FF











1 +

1

Loop Gain

Non−Inverting Gain =

1 +

R

FB

R

FF











1 +

1

Loop Gain

whereLoop Gain =

T

O

RFB+ RS1 +

R

FB

R

FF































ƒ

ACTUAL

BW ≈

ƒ

AV=+2

()

BW

[]

x1.25

()

1+

R

S

R

FB











× 1 +

R

FB

R

FF























VIO1 +

R

FB

R

FF











± Ib

I

× R

FB

OutputOffsetVoltage =±IbN× RN1 +

R

F

B

R

FF











±

R

FB

R

FF

Ib

I

R

N

Ib

N

V

IO

9

®

OPA658

The 402Ω used in setting the specification achieves a nomi­nal maximally flat butterworth response while assuming a
2pF output pin parasitic. Increasing the feedback resistor
will over compensate the amplifier, rolling off the frequency
response, while decreasing it will decrease phase margin,
peaking up the frequency response. Note that a non-invert­ing, unity gain buffer application still requires a feedback
resistor for stability (560Ω for SO-8, 402Ω for PDIP, and
324Ω for SOT23).

d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100 mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R

ISO

from

the plot of recommended R

ISO

vs capacitive load. Low

parasitic loads may not need an R

ISO

since the OPA658 is

nominally compensated to operate with a 2pF parasitic load.
If a long trace is required and the 6dB signal loss intrinsic to

doubly terminated transmission lines is acceptable, imple­ment a matched impedance transmission line using microstrip
or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω environ­ment is not necessary on board, and in fact a higher imped­ance environment will improve distortion as shown in the
distortion vs load plot. With a characteristic impedance
defined based on board material and desired trace dimen­sions, a matching series resistor into the trace from the
output of the amplifier is used as well as a terminating shunt
resistor at the input of the destination device. Remember
also that the terminating impedance will be the parallel
combination of the shunt resistor and the input impedance of
the destination device; the total effective impedance should
match the trace impedance. Multiple destination devices are
best handled as separate transmission lines, each with their
own series and shunt terminations.

If the 6dB attenuation loss of a doubly terminated line is
unacceptable, a long trace can be series-terminated at the
source end only. This will help isolate the line capacitance
from the op amp output, but will not preserve signal integrity
as well as a doubly terminated line. If the shunt impedance
at the destination end is finite, there will be some signal
attenuation due to the voltage divider formed by the series
and shunt impedances.

e) Socketing a high speed part like the OPA658 is not
recommended. The additional lead length and pin-to-pin

capacitance introduced by the socket creates an extremely
troublesome parasitic network which can make it almost
impossible to achieve a smooth, stable response. Best results
are obtained by soldering the part onto the board. If socket­ing for the DIP package is desired, high frequency flush
mount pins (e.g., McKenzie Technology #710C) can give
good results.

The OPA658 is nominally specified for operation using
±5V power supplies. A 10% tolerance on the supplies, or an
ECL –5.2V for the negative supply, is within the maximum

the root sum of the squares of equation (4) and applying the
spectral noise values found in the Typical Performance Curve
graph section. This applies to noise from the op amp only.
Note that both the noise figure (NF) and the equivalent input
offset voltages improve as the closed loop gain increases (by
keeping R

FB

fixed and reducing RFF with RN = 0Ω).

INCREASING BANDWIDTH AT HIGH GAINS

The closed-loop bandwidth can be extended at high gains by
reducing the value of the feedback resistor R

FB

. This band­width reduction is caused by the feedback current being split
between RS and R

FF

(refer to Figure 1). As the gain increases

(for a fixed R

FB

), more feedback current is shunted through

R

FF

, which reduces closed-loop bandwidth.

CIRCUIT LAYOUT AND BASIC OPERATION

Achieving optimum performance with a high frequency am­plifier like the OPA658 requires careful attention to layout
parasitics and selection of external components. Recommen­dations for PC board layout and component selection include:

a) Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability; on the non­inverting input it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca­pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.

b) Minimize the distance (< 0.25") from the two power pins
to high frequency 0.1µF decoupling capacitors. At the pins,
the ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and
ground traces to minimize inductance between the pins and
the decoupling capacitors. Larger (2.2µF to 6.8µF) decoupling
capacitors, effective at lower frequencies, should also be
used. These may be placed somewhat farther from the
device and may be shared among several devices in the same
area of the PC board.

c) Careful selection and placement of external compo­nents will preserve the high frequency performance of the
OPA658. Resistors should be a very low reactance type.

Surface mount resistors work best and allow a tighter overall
layout. Metal film or carbon composition axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads as short as possible. Never use
wirewound type resistors in a high frequency application.

Since the output pin and the inverting input pin are most
sensitive to parasitic capacitance, always position the feed­back and series output resistor, if any, as close as possible to
the package pins. Other network components, such as non­inverting input termination resistors, should also be placed
close to the package.

The feedback resistor value acts as the frequency response
compensation element for a current feedback type amplifier.

10

®

OPA658

402Ω

OPA658

V

AC

402Ω

R

L

+V

S

+V

S

V

S

2

R

OUT

V

S

2

V

OUT

= + AV V

AC

AV = +2

specified total supply voltage of 11V. Higher supply voltages
can break down internal junctions possibly leading to cata­strophic failure. Single supply operation is possible as long as
common mode voltage constraints are observed. The com­mon mode input and output voltage specifications can be
interpreted as a required headroom to the supply voltage.
Observing this input and output headroom requirement will
allow non-standard or single supply operation. Figure 3
shows one approach to single-supply operation.

THERMAL CONSIDERATIONS

The OPA658 will not require heatsinking under most oper­ating conditions. Maximum desired junction temperature
will set a maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed 175°C.

Operating junction temperature (T

J

) is given by

T

A

+ PD •

θ

JA

. The total internal power dissipation (PD) is

the sum of quiescent power (P

DQ

) and additional power

dissipated in the output stage (P

DL

) to deliver load power.
Quiescent power is simply the specified no-load supply
current times the total supply voltage across the part. P

DL

will depend on the required output signal and load but
would, for a grounded resistive load, be at a maximum when
the output is fixed at a voltage equal to 1/2 either supply
voltage (for equal bipolar supplies). Under this condition
PDL = V

S

2

/(4 • RL) where RL includes feedback network

loading.
Note that it is the power in the output stage and not into the

load that determines internal power dissipation.
As an example, compute the maximum T

J

for an OPA658N

at A

V

= +2, RL = 100Ω, RFB = 402Ω, ±VS = ±5V, and the

specified maximum T

A

= +85°C. PD = 10V • 8.5mA + 52/

[4 • (100Ω || 804Ω)] = 155mW. Maximum T

J

= 85°C +

0.155W • 150°C/W = 108°C.

DRIVING CAPACITIVE LOADS

The OPA658’s output stage has been optimized to drive low
resistive loads. Capacitive loads, however, will decrease the
amplifier’s phase margin which may cause high frequency
peaking or oscillations. Capacitive loads greater than 5pF
should be buffered by connecting a small resistance, usually
10Ω to 35Ω, in series with the output as shown in Figure 5.
This is particularly important when driving high capacitance
loads such as flash A/D converters.

In general, capacitive loads should be minimized for opti­mum high frequency performance. Coax lines can be driven
if the cable is properly terminated. The capacitance of coax
cable (29pF/foot for RG-58) will not load the amplifier
when the coaxial cable or transmission line is terminated
with its characteristic impedance.

FIGURE 4. Closed-Loop Output Impedance vs Frequency.

100

10

1

0.1

0.01

0.001
10k 100k 1M 10M 100M

Output Impedance (Ω)

Frequency (Hz)

G = +2

ESD PROTECTION

ESD static damage has been well recognized for MOSFET
devices, but any semiconductor device deserves protection
from this potentially damaging source. This is particularly
true for very high speed, fine geometry processes.

ESD static damage can cause subtle changes in amplifier
input characteristics without necessarily destroying the de­vice. In precision operational amplifiers, this may cause a
noticeable degradation of offset voltage and drift. Therefore,
static protection is strongly recommended when handling
the OPA658.

OUTPUT DRIVE CAPABILITY

The OPA658 has been optimized to drive 75Ω and 100Ω
resistive loads. The device can drive 2Vp-p into a 75Ω load.
This high-output drive capability makes the OPA658 an
ideal choice for a wide range of RF, IF, and video applica­tions. In many cases, additional buffer amplifiers are un­needed.

Many demanding high-speed applications such as
ADC/DAC buffers require op amps with low wideband
output impedance. For example, low output impedance is
essential when driving the signal-dependent capacitances at
the inputs of flash A/D converters. As shown in Figure 4,
the OPA658 maintains very low closed-loop output imped­ance over frequency. Closed-loop output impedance in­creases with frequency since loop gain is decreasing with
frequency.

FIGURE 3. Single Supply Operation.

11

®

OPA658

close-in spurious tones will appear at fO ±3 • ∆f. The two
tone, third-order spurious plot shown in Figure 7 indicates
how far below these two equal power, closely spaced, tones
the intermodulation spurious will be. The single tone power
is at a matched 50Ω load. The unique design of the OPA658
provides much greater spurious free range than what a two­tone third-order intermodulation intercept specification would
predict. This can be seen in Figure 7 as the spurious free
range actually increases at the higher output power levels.

COMPENSATION

The OPA658 is internally compensated and is stable in unity
gain with a phase margin of approximately 62°, and approxi­mately 64° in a gain of +2V/V when used with the recom­mended feedback resistor value. Frequency response for
other gains are shown in the Typical Performance Curves.

The high-frequency response of the OPA658 in a good
layout is very flat with frequency.

DISTORTION

The OPA658’s Harmonic Distortion characteristics into a
100Ω load are shown versus frequency and power output in
the Typical Performance Curves. Distortion can be further
improved by increasing the load resistance as illustrated in
Figure 6. Remember to include the contribution of the
feedback resistance when calculating the effective load re­sistance seen by the amplifier.

Narrowband communication channel requirements will ben­efit from the OPA658’s wide bandwidth and low
intermodulation distortion on low quiescent power. If output
signal power at two closely spaced frequencies is required,
third-order nonlinearities in any amplifier will cause spuri­ous power at frequencies very near the two funda­mental frequencies. If the two test frequencies, f

1

and f2,
are specified in terms of average and delta frequency,
fO = (f1 + f2)/2 and ∆f =  f2 – f1, the two, third-order,

DIFFERENTIAL GAIN AND PHASE

Differential Gain (dG) and Differential Phase (dP) are among
the more important specifications for video applications. dG
is defined as the percent change in closed-loop gain over a
specified change in output voltage level. dP is defined as the
change in degrees of the closed-loop phase over the same
output voltage change. Both dG and dP are specified at the
NTSC sub-carrier frequency of 3.58MHz and the PAL sub­carrier of 4.43MHz. All NTSC measurements were per­formed using a Tektronix model VM700A Video Measure­ment Set.

dG/dP of the OPA658 were measured with the amplifier in a
gain of +2V/V with 75Ω input impedance and the output
back-terminated in 75Ω. The input signal selected from the
generator was a 0V to 1.4V modulated ramp with sync pulse.
With these conditions the test circuit shown in Figure 8
delivered a 100IRE modulated ramp to the 75Ω input of the
videoanalyzer. The signal averaging feature of the analyzer

FIGURE 5. Driving Capacitive Loads.

FIGURE 6. 5MHz Harmonic Distortion vs Load Resistance.

–55

–60

–65

–70

–75

–80

–85

5MHz HARMONIC DISTORTION vs

LOAD RESISTANCE (G = +2)

Load Resistance (Ω)

Harmonic Distortion (dBc)

10 100 1k

G = +2, VO = 2Vp-p, fO = 5MHz

3f

O

2f

O

FIGURE 7. Third-Order Spurious Level vs Frequency.

–65

–70

–75

–80

–85

–90

–18 –16 –14 –12 –10 –8 –6 –4 –2 0 2 4

Third-Order Spurious Level (dBc)

TWO TONE, THIRD-ORDER SPURIOUS LEVELS

Single Tone Power (dBm)

20MHz

10MHz

5MHz

OPA658

75Ω

75Ω

402Ω

402Ω

75Ω

75Ω

TEK TSG 130A

TEK VM700A

FIGURE 8. Configuration for Testing Differential Gain/Phase.

OPA658

50Ω

R

ISO

RLC

L

10Ω to 35Ω

402Ω402Ω

12

®

OPA658

was used to establish a reference against which the perfor­mance of the amplifier was measured. Signal averaging was
also used to measure the dg and dp of the test signal in order
to eliminate the generator’s contribution to measured ampli­fier performance. Typical performance of the OPA658 is

0.025% differential gain and 0.02° differential phase to both
NTSC and PAL standards.

SPICE MODELS AND EVALUATION BOARDS

Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and induc­tance can have a major effect on circuit performance. SPICE
models are available on a disk from the Burr-Brown Appli­cations Department.

Demonstration boards are available for each OPA658 pack­age style. These boards implement a very low parasitic
layout that will produce the excellent frequency and pulse
responses shown in the Typical Performance Curves. For
each package style, the recommended demonstration board
is:

Contact your local Burr-Brown sales office or distributor to
order demonstration boards.

DEM-OPA65xP 8-Pin DIP for the OPA658P
DEM-OPA65xU SO-8 for the OPA658U
DEM-OPA6xxN SOT23 for the OPA658N

FIGURE 9. Layout Detail For DEM-OPA65xP Demonstration Board.

R

6

R

1

OPA658

Out

J

1

1
2

GND

–5V

P2

R

7

R

5

+In

R

3

R

4

R

5

–In

J

1

J

2

2

7

4

6

3

C

2

0.1µF

C

4

2.2µF

402Ω

C

1

2.2µF

C

3

0.1µF

1
2

GND

+5V

P1

+

+

13

®

OPA658

FIGURE 10a. Evaluation Board Silkscreen (Bottom). 10b. Evaluation Board Silkscreen (Top). 10c. Evaluation Board Layout

(Solder Side). 10d. Evaluation Board Layout (Layout Side).

(C)

(D)

(A)

(B)

DEM-OPA65xP Demonstration Board Layout

TYPICAL APPLICATION

FIGURE 11. Low Distortion Video Amplifier.

OPA658

V

OUT

402Ω402Ω

Video

Input

75Ω

75Ω

75Ω Transmission Line

75Ω