Datasheet OPA552PA, OPA551FA, OPA551UA-2K5, OPA551PA, OPA551FA-500 Datasheet (Burr Brown)

1

OPA551, OPA552

®

®

OPA551
OPA552

©1999 Burr-Brown Corporation PDS-1472A Printed in U.S.A. July, 1999

High-Voltage, High-Current

OPERA TIONAL AMPLIFIERS

DESCRIPTION

The OPA551 and OPA552 are low cost op amps with
high-voltage (60V) and high-current (200mA) capa­bility.

The OPA551 is unity-gain stable and features high
slew rate (15Vµs) and wide bandwidth (3MHz). The
OPA552 is optimized for gains of 5 or greater, and
offers higher speed with a slew rate of 24V/µs and a
bandwidth of 12MHz. Both are suitable for telephony,
audio, servo, and test applications.

These laser-trimmed, monolithic integrated circuits
provide excellent low-level accuracy along with high
output swing. High performance is maintained as the
amplifier swings to its specified limits.

The OPA551 and OPA552 are internally protected
against over-temperature conditions and current over­loads. The thermal shutdown indicator “flag” provides
a current output to alert the user when thermal shut­down has occurred.

The OPA551 and OPA552 are available in DIP-8 and
SO-8 packages, as well as a DDPAK-7 surface­mount plastic power package. They are specified for
operation over the extended industrial temperature
range, –40°C to +125°C.

FEATURES

● WIDE SUPPLY RANGE: ±4V to ±30V

● HIGH OUTPUT CURRENT: 200mA Continuous

● LOW NOISE: 14nV/√Hz

● FULLY PROTECTED:

Thermal Shutdown
Output Current-Limited

● THERMAL SHUTDOWN INDICATOR

● WIDE OUTPUT SWING: 2V From Rail

● FAST SLEW RATE:

OPA551: 15V/µs
OPA552: 24V/µs

● WIDE BANDWIDTH:

OPA551: 3MHz
OPA552: 12MHz

● PACKAGES: DIP-8, SO-8, or DDPAK-7

APPLICATIONS

● TELEPHONY

● TEST EQUIPMENT

● AUDIO AMPLIFIER

● TRANSDUCER EXCITATION

● SERVO DRIVER

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone]

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

OPA551

OPA551

OPA551

For most current data sheet and other product

information, visit www.burr-brown.com

1
2
3
4

8
7
6
5

Flag
V+
Out
V–

V–
–In
+In

V–

OPA551, OPA552

SO-8 (U)
1
2
3
4

8
7
6
5

Flag
V+
Out
NC

NC
–In
+In

V–

OPA551, OPA552

DIP-8 (P)

NOTE: Tab is
connected to
V– supply.

NC

V–

V+

Out

+In

–In

1234

5

6

Flag

7

DDPAK-7 Surface-Mount (F)

OPA551, OPA552

2

OPA551, OPA552

®

SPECIFICATIONS: VS = ±30V

OPA551

At T

J

= +25°C

(1)

, RL = 3kΩ connected to ground and V

OUT

= 0V, unless otherwise noted.

Boldface limits apply over the specified junction temperature range, T

J

= –40°C to +125°C.

OPA551UA, PA, FA

PARAMETER CONDITION MIN TYP MAX UNITS
OFFSET VOLTAGE

Input Offset Voltage V

OS

VCM = 0V, IO = 0 ±1 ±3mV

T

J

= –40°C to +125°C ±5 mV

vs Temperature dVOS/dT ±7 µV/°C

vs Power Supply PSRR V

S

= ±4V to ±30V, VCM = 0V 10 30 µV/V

INPUT BIAS CURRENT

Input Bias Current I

B

±20 ±100 pA

Input Offset Current I

OS

±3 ±100 pA

NOISE

Input Voltage Noise Density, f = 1kHz e

n

14 nV/√Hz

Current Noise Density, f = 1kHz i

n

3.5 fA/√Hz

INPUT VOLTAGE RANGE

Common-Mode Voltage Range V

CM

(V–) + 2.5 (V+) – 2.5 V

Common-Mode Rejection Ratio CMRR –27.5V

< VCM < +27.5V 92 102 dB

INPUT IMPEDANCE

Differential 10

13

|| 2 Ω || pF

Common-Mode 10

13

|| 6 Ω || pF

OPEN-LOOP GAIN

Open-Loop Voltage Gain A

OL

RL = 3kΩ, –28V < VO < +28V 110 126 dB

T

J

= –40°C to +125°CR

L

= 3kΩ, –28V < VO < +28V 100 dB

R

L

= 300Ω, –27V < VO < +27V 120 dB

FREQUENCY RESPONSE

Gain-Bandwidth Product GBW 3 MHz
Slew Rate SR G = 1 ±15 V/µs
Settling Time: 0.1% G = 1, C

L

= 100pF, 10V Step 1.3 µs

0.01% G = 1, C

L

= 100pF, 10V Step 2 µs

Total Harmonic Distortion + Noise, f = 1kHz THD+N

VO = 15Vrms, RL = 3kΩ, G = 3 0.0005 %

VO = 15Vrms, RL = 300Ω, G = 3 0.0005 %

Overload Recovery Time V

IN

• Gain = V

S

1 µs

OUTPUT

Voltage Output V

OUT

IO = 200mA (V–) + 3.0 (V+) – 3.0 V

T

J

= –40°C to +125°CI

O

= 200mA (V–) + 3.5 (V+) – 3.5 V

I

O

= 10mA (V–) + 2.0 (V+) – 2.0 V

TJ = –40°C to +125°CI

O

= 10mA (V–) + 2.5 (V+) – 2.7 V

Maximum Continuous Current Output: dc I

O

Package Dependent—See Text ±200 mA

Short-Circuit Current I

SC

±380 mA

Capacitive Load Drive C

LOAD

Stable Operation See Typical Curve

SHUTDOWN FLAG

Thermal Shutdown Status Output

Normal Operation Sourcing 0.05 1 µA
Thermally Shutdown Sourcing 80 120 160 µA
Voltage Compliance Range V– (V+) – 1.5 V

Junction Temperature

Shutdown 160 °C
Reset from Shutdown 140 °C

POWER SUPPLY

Specified Voltage V

S

±30 V
Operating Voltage Range ±4 ±30 V
Quiescent Current I

Q

IO = 0 ±7 ±8.5 mA

T

J

= –40°C to +125°C ±10 mA

TEMPERATURE RANGE

Specified Range T

J

–40 +125 °C

Operating Range T

J

–55 +125 °C

Storage Range T

A

–65 +150 °C

Thermal Resistance

SO-8 Surface Mount

θ

JA

90 °C/W

DIP-8

θ

JA

100 °C/W

DDPak-7

θ

JA

65 °C/W

DDPak-7

θ

JC

3 °C/W

NOTES: (1) All tests are high-speed tested at +25°C ambient temperature. Effective junction temperature is +25°C unless otherwise noted.

3

OPA551, OPA552

®

SPECIFICATIONS: VS = ±30V

OPA552

At T

J

= +25°C

(1)

, RL = 3kΩ connected to Ground and V

OUT

= 0V, unless otherwise noted.

Boldface limits apply over the specified junciton temperature range, T

J

= –40°C to +125°C.

OPA552UA, PA, FA

PARAMETER CONDITION MIN TYP MAX UNITS
OFFSET VOLTAGE

Input Offset Voltage V

OS

VCM = 0V, IO = 0 ±1 ±3mV

TJ = –40°C to +125°C ±5 mV
vs Temperature dV

OS

/dT ±7 µV/°C

vs Power Supply PSRR V

S

= ±4V to ±30V, VCM = 0V 10 30 µV/V

INPUT BIAS CURRENT

Input Bias Current I

B

±20 ±100 pA

Input Offset Current I

OS

±3 ±100 pA

NOISE

Input Voltage Noise Density, f = 1kHz e

n

14 nV/√Hz

Current Noise Density, f = 1kHz i

n

3.5 fA/√Hz

INPUT VOLTAGE RANGE

Common-Mode Voltage Range V

CM

(V–) + 2.5 (V+) – 2.5 V

Common-Mode Rejection Ratio CMRR –27.5V

< VCM < +27.5V 92 102 dB

INPUT IMPEDANCE

Differential 1013 || 2 Ω || pF
Common-Mode 1013 || 6 Ω || pF

OPEN-LOOP GAIN

Open-Loop Voltage Gain A

OL

RL = 3kΩ, –28V < VO < +28V 110 126 dB

T

J

= –40°C to +125°CR

L

= 3kΩ, –28V < VO < +28V 100 dB

R

L

= 300Ω, –27V < VO < +27V 120 dB

FREQUENCY RESPONSE

Gain-Bandwidth Product GBW 12 MHz
Slew Rate SR G = 5 ±24 V/µs
Settling Time: 0.1% G = 5, C

L

= 100pF, 10V Step 2.2 µs

0.01% G = 5, C

L

= 100pF, 10V Step 3 µs

Total Harmonic Distortion + Noise, f = 1kHz THD+N

VO = 15Vrms, RL = 3kΩ, G = 5 0.0005 %

V

O

= 15Vrms, RL = 300Ω, G = 5 0.0005 %

Overload Recovery Time V

IN

• Gain = V

S

1 µs

OUTPUT

Voltage Output V

OUT

IO = 200mA (V–) + 3.0 (V+) – 3.0 V

T

J

= –40°C to +125°CI

O

= 200mA (V–) + 3.5 (V+) – 3.5 V

I

O

= 10mA (V–) + 2.0 (V+) – 2.0 V

T

J

= –40°C to +125°CI

O

= 10mA (V–) + 2.5 (V+) – 2.7 V

Maximum Continuous Current Output: dc IOPackage Dependent—See Text ±200 mA
Short-Circuit Current I

SC

±380 mA

Capacitive Load Drive C

LOAD

Stable Operation See Typical Curve

SHUTDOWN FLAG

Thermal Shutdown Status Output

Normal Operation Sourcing 0.05 1 µA
Thermally Shutdown Sourcing 80 120 160 µA
Voltage Compliance Range V– (V+) – 1.5 V

Junction Temperature

Shutdown 160 °C
Reset from Shutdown 140 °C

POWER SUPPLY

Specified Voltage V

S

±30 V
Operating Voltage Range ±4 ±30 V
Quiescent Current I

Q

IO = 0 ±7 ±8.5 mA

T

J

= –40°C to +125°C ±10 mA

TEMPERATURE RANGE

Specified Range T

J

–40 +125 °C

Operating Range T

J

–55 +125 °C

Storage Range T

A

–65 +150 °C

Thermal Resistance

SO-8 Surface Mount

θ

JA

90 °C/W

DIP-8

θ

JA

100 °C/W

DDPak-7

θ

JA

65 °C/W

DDPak-7

θ

JC

3 °C/W

NOTES: (1) All tests are high-speed tested at +25°C ambient temperature. Effective junction temperature is +25°C unless otherwise noted.

4

OPA551, OPA552

®

ABSOLUTE MAXIMUM RATINGS

(1)

Output Current ................................................................. See SOA Curve

Supply Voltage, V+ to V– ................................................................... 60V

Input Voltage Range ....................................... (V–) – 0.5V to (V+) + 0.5V

Operating Temperature ..................................................–55°C to +125°C

Storage Temperature .....................................................–65°C to +150°C

Junction Temperature .................................................................... +150°C

Lead Temperature (soldering 10s, DIP-8) ...................................... 300°C

(soldering 3s, SO-8 and DDPAK) .................... 240°C

ESD Capability (Human Body Model) ............................................. 3000V

NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degrada­tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or
licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support
devices and/or systems.

PACKAGE /ORDERING INFORMATION

PACKAGE SPECIFIED

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER

(1)

RANGE MARKING NUMBER

(2)

MEDIA

OPA551UA SO-8 182 –40°C to +125°C OPA551UA OPA551UA Rails

"" " " "OPA551UA/2K5 Tape and Reel

OPA551PA DIP-8 006 –40°C to +125°C OPA551PA OPA551PA Rails
OPA551FA DDPAK-7 328 –40°C to +125°C OPA551FA OPA551FA Rails

"" " " "OPA551FA/500 Tape and Reel

OPA552UA SO-8 182 –40°C to +125°C OPA552UA OPA552UA Rails

"

""""OPA552UA/2K5 Tape and Reel

OPA552PA DIP-8 006 –40°C to +125°C OPA552PA OPA552PA Rails
OPA552FA DDPAK-7 328 –40°C to +125°C OPA552FA OPA552FA Rails

"" " " "OPA552FA/500 Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Products followed by a slash
(/) are only available in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA551UA/2K5” will get
a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

5

OPA551, OPA552

®

TYPICAL PERFORMANCE CURVES

At T

J

= +25°C, VS = ±30V and RL = 3kΩ, unless otherwise noted.

All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient
temperatures for a specific configuration.

120

100

80

60

40

20

0

1 10 100 1k 10k 100k 1M 10M

Frequency (Hz)

CMRR (dB)

COMMON-MODE REJECTION RATIO vs FREQUENCY

120

100

80

60

40

20

0

1 10 100 1k 10k 100k 1M 10M

Frequency (Hz)

PSRR (dB)

POWER SUPPLY REJECTION RATIO vs FREQUENCY

–PSRR

+PSRR

140
120
100

80
60
40
20

0
–20
–40

0
–20
–40
–60
–80
–100
–120
–140
–160
–180

1 10 100 1k 10k 100k 1M 10M

Frequency (Hz)

Gain (dB)

OPEN-LOOP GAIN AND PHASE vs FREQUENCY

OPA552

Phase (°)

Phase

OPA552

Gain

10k

1k

100

10

1

INPUT VOLTAGE AND CURRENT NOISE

SPECTRAL DENSITY vs FREQUENCY

Voltage Noise (nV/√Hz)

Current Noise (fA/√Hz)

10 100 1k 10k 100k 1M

Frequency (Hz)

i

n

e

n

0.1

0.01

0.001

0.0001

TOTAL HARMONIC DISTORTION + NOISE

vs FREQUENCY

Frequency (Hz)

1 100 1k 10k 100k

THD+N (%)

VO = 15Vrms
R

L

= 3kΩ, 300Ω
G = 3 (OPA551)
G = 5 (OPA552)

140
120
100

80
60
40
20

0
–20
–40

0
–20
–40
–60
–80
–100
–120
–140
–160
–180

1 10 100 1k 10k 100k 1M 10M

Frequency (Hz)

Gain (dB)

OPEN-LOOP GAIN AND PHASE vs FREQUENCY

OPA551

Phase (°)

Phase

Gain

OPA551

6

OPA551, OPA552

®

TYPICAL PERFORMANCE CURVES (Cont.)

At T

J

= +25°C, VS = ±30V and RL = 3kΩ, unless otherwise noted.

All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient
temperatures for a specific configuration.

9
8
7
6
5
4
3
2
1
0

450
430
410
390
370
350
330
310
290
270

–75 –50 –25 0 25 50 75 100 125 150

Temperature (°C)

I

Q

(mA)

I

SC

(mA)

QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT

vs TEMPERATURE

+I

SC

–I

SC

I

Q

±30

±25

±20

±15

±10

±5

0

1 10 100 1k 10k 100k 1M 10M

Frequency (Hz)

Maximum Output Voltage (V)

MAXIMUM OUTPUT VOLTAGE SWING

vs FREQUENCY

OPA552

OPA551

Without Slew-Induced

Distortion

OUTPUT VOLTAGE SWING vs OUTPUT CURRENT

(V+)

(V+)–1

(V+)–2

(V+)–3
(V–)+3

(V–)+2

(V–)+1

(V–)

0 50 100 150 200 250 300 350 400

Output Current (mA)

Output Voltage Swing (V)

–55°C

+85°C

+85°C

–55°C

+25°C

+25°C

100k

10k

1k

100

10

1

–75 0–25–50 25 50 75 100 125

Ambient Temperature (°C)

Current (pA)

INPUT BIAS CURRENT AND INPUT OFFSET CURRENT

vs TEMPERATURE

+I

B

–I

B

–I

OS

100

10

1

–80 –60 –40 –20 0 20 40 60 80 100 120 140

Temperature (°C)

Gain Bandwidth Product (MHz)

GAIN BANDWIDTH PRODUCT vs TEMPERATURE

OPA552

OPA551

130
125
120
115
110
105
100

95
90
85
80

–75 –25 25 75 125

Ambient Temperature (°C)

Gain (dB)

OPEN-LOOP GAIN, POWER SUPPLY REJECTION RATIO,

AND COMMON-MODE REJECTION RATIO

vs TEMPERATURE

A

OL

PSRR

CMRR

7

OPA551, OPA552

®

TYPICAL PERFORMANCE CURVES (Cont.)

At T

J

= +25°C, VS = ±30V and RL = 3kΩ, unless otherwise noted.

All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient
temperatures for a specific configuration.

35

30

25

20

15

10

5

0

–60 –40 –20 0 20 40 60 80 100 120 140

Junction Temperature (°C)

Slew Rate (V/µs)

SLEW RATE vs TEMPERATURE

OPA551

OPA552

30

25

20

15

10

5

0

–5

–30 –20 –10 0 10 20 30

Common-Mode Voltage (V)

Current (pA)

INPUT BIAS CURRENT AND INPUT OFFSET CURRENT

vs COMMON-MODE VOLTAGE

+I

B

–I

B

I

OS

OFFSET VOLTAGE

PRODUCTION DISTRIBUTION

Percent of Amplifiers (%)

Offset Voltage (mV)

< –3.0

< –2.4

< –1.8

< –1.2

< –0.6

< 0.0

< 0.6

< 1.2

< 1.8

< 2.4

< 3.0

18

15

12

9

6

3

0

Typical production
distribution of
packaged units.

OFFSET VOLTAGE DRIFT

PRODUCTION DISTRIBUTION

Percent of Amplifiers (%)

Offset Drift µV/°C

< 0.0

< 1.5

< 3.0

< 4.50

< 6.0

< 7.5

< 9.0

< 10.5

< 12.0

< 13.5

< 15.0

18
16
14
12
10

8

6

4

2

0

Typical production
distribution of
packaged units.

100

10

1

1 10 100

Gain (V/V)

Settling Time (µs)

SETTLING TIME vs CLOSED-LOOP GAIN

OPA551

0.1%

OPA552

0.01%

OPA552

0.1%

OPA551

0.01%

7.6

7.2

6.8

6.4

6.0

405

395

385

375

365

0 5 10 15 20 25 30 35

Supply Voltage (V)

Quiescent Current (mA)

Short-Circuit Current (mA)

QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT

vs SUPPLY VOLTAGE

I

Q

+I

SC

–I

SC

8

OPA551, OPA552

®

TYPICAL PERFORMANCE CURVES (Cont.)

At T

J

= +25°C, VS = ±30V and RL = 3Ω, unless otherwise noted.

All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient
temperatures for a specific configuration.

SMALL-SIGNAL STEP RESPONSE

OPA552, G = 5, C

L

= 100pF

Time (1µs/div)

100mV/div

SMALL-SIGNAL STEP RESPONSE

OPA551, G = –1, C

L

= 1000pF

Time (1µs/div)

5V/div

LARGE-SIGNAL STEP RESPONSE

OPA552, G = 5, C

L

= 100pF

Time (1µs/div)

5V/div

SMALL-SIGNAL STEP RESPONSE

OPA551, G = 1, C

L

= 100pF

Time (1µs/div)

LARGE-SIGNAL STEP RESPONSE

OPA551, G = 1, C

L

= 100pF

Time (1µs/div)

5V/div

25mV/div

60

50

40

30

20

10

0

0.01 10.1 10
Load Capacitance (nF)

Overshoot (%)

SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE

OPA551, G = 1

OPA551

G = –2

OPA551

G = –1

OPA552

G = –4

OPA552

G = –6

OPA552, G = –8

OPA552

OPA552

OPA551

OPA551

OPA551

9

OPA551, OPA552

®

APPLICATIONS INFORMATION

Figure 1 shows the OPA551 connected as a basic non­inverting amplifier. The OPA551 can be used in virtually
any op amp configuration. OPA552 is designed for use in
configurations with gains of 5 or greater. Power supply
terminals should be bypassed with 0.1µF capacitors, or
greater, near the power supply pins. Be sure that the capaci­tors are appropriately rated for the power supply voltage
used. The OPA551 and OPA552 can supply output currents
up to 200mA with excellent performance.

FIGURE 1. Basic Circuit Connections.

CURRENT LIMIT

The OPA551 and OPA552 are designed with internal cur­rent-limiting circuitry that limits the output current to ap­proximately 380mA. The current limit varies with increasing
junction temperature as shown in the typical curve “Current
Limit vs Temperature.” This, in combination with the ther­mal protection circuitry, provides protection from many
types of overload conditions including short circuit to ground.

THERMAL PROTECTION

The OPA551 and OPA552 have thermal shutdown circuitry
that protects the amplifier from damage caused by overload
conditions. The thermal protection circuitry disables the
output when the junction temperature reaches approximately
160°C, allowing the device to cool. When the junction
temperature cools to approximately 140°C, the output cir­cuitry is automatically re-enabled.

The thermal shutdown function is not intended to replace
proper heat sinking. Activation of the thermal shutdown
circuitry is an indication of excessive power dissipation or
an inadequate heat sink. Continuously running the amplifier
into thermal shutdown can degrade reliability.

The Thermal Shutdown Indicator (“flag”) pin can be moni­tored to determine if shutdown is occurring. During normal
operation, the current output from the flag pin is typically
50nA. During shutdown, the current output from the flag pin
increases to 120µA (typical). This current output allows for
easy interfacing to external logic. See Figure 2 for two
examples implementing this function.

FIGURE 2. Thermal Shutdown Indicator.

G = 1+

R

2

R

1

Z

L

R

2

R

1

0.1µF

10µF

OPA551

V–

V+

+

+

V

IN

10µF

0.1µF

V

O

Flag

(optional)

Flag
80µA to

160µA

HCT

OPA551

Logic

Ground

V

OUT

+5V

27kΩ

V

LOGIC

V

OUT

CMOS

OPA551

Logic

Ground

Interfacing with CMOS Logic

Interfacing with HCT Logic

47kΩ

HP5082-2835

Interface to virtually any CMOS
logic gate by choosing resistor
value that provides a guaranteed
logic high voltage with the
minimum (80µA) flag current. A
diode clamp to the logic supply
voltage assures that the CMOS
is not damaged by overdrive.

HCT logic has relatively well­controlled logic level. A properly
chosen resistor value can
guarantee proper logic high level
throughout the full range of flag
output current.

10

OPA551, OPA552

®

POWER SUPPLIES

The OPA551 and OPA552 may be operated from power
supplies of ±4V to ±30V, or a total of 60V with excellent
performance. Most behavior remains unchanged throughout
the full operating voltage range. Parameters that vary sig­nificantly with operating voltage are shown in the Typical
Performance Curves.

For applications that do not require symmetrical output
voltage swing, power supply voltages do not need to be
equal. The OPA551 and OPA552 can operate with as little
as 8V between the supplies or with up to 60V between the
supplies. For example, the positive supply could be set to
50V with the negative supply at –10V or vice-versa.

The SO-8 package outline shows three negative supply (V–)
pins. These pins are internally connected for improved thermal
performance. Pin 4 is to be used as the primary current

carrier for the negative supply. It is recommended that
pins 1 and 5 not be directly connected to V– but, instead
be connected to a thermal mass. DO NOT lay out the PC
board to use pins 1 and 5 as feedthroughs to the negative
supply. Doing so can result in a reduction of performance.

The tab of the DDPAK-7 package is electrically connected
to the negative supply (V–), however, this connection should
not be used to carry current. For best thermal performance,
the tab should be soldered directly to the circuit board
copper area (see heat sink text).

POWER DISSIPATION

Internal power dissipation of these op amps can be quite
large. Many of the specifications for the OPA551 and
OPA552 are for a specified junction temperature. If the
device is not subjected to internal self-heating, the junction
temperature will be the same as the ambient. However, in
practical applications, the device will self-heat and the junc­tion temperature will be significantly higher than ambient.
After junction temperature has been established, perfor­mance parameters that vary with junction temperature can be
determined from the performance curves. The following
calculation can be performed to establish junction tempera­ture as a function of ambient temperature and the conditions
of the application.

Consider the OPA551 in a circuit configuration where the
load is 600Ω and the output voltage is 15V. The supplies are
at ±30V and the ambient temperature (TA) is 40°C. The

θ

JA

for the 8-pin DIP package is 100°C/W.
First, the internal heating of the op amp is as follows:
P

D(internal)

= IQ • VS = 7.2mA • 60V = 432mW

The output current (IO) can be calculated:

IO = V

OUT/RL

= 15V / 600Ω = 25mA

The power being dissipated (PD) in the output transistor of
the amplifier can be calculated:

P

D(output stage)

= IO • (VS – VO) = 25mA • (30 – 15) = 375mW

P

D(total)

= P

D(internal)

+ P

D(output stage)

= 432mW + 375mW = 807mW

The resulting junction temperature can be calculated:

TJ = TA + PD

θ

JA

TJ = 40°C + 807mW • 100°C/W = 120.7°C

Where,

TJ = junction temperature (°C)
TA = ambient temperature (°C)

θ

JA

= junction-to-air thermal resistance (°C/W)

For the DDPAK package, the

θ

JA

is 65°C/W with no heat

sinking, resulting in a junction temperature of 92.5°C.
To estimate the margin of safety in a complete design

(including heat sink), increase the ambient temperature until
the thermal protection is activated. Use worst-case load and
signal conditions. For good reliability, the thermal protec­tion should trigger more than +35°C above the maximum
expected ambient condition of your application. This en­sures a maximum junction temperature of +125°C at the
maximum expected ambient condition.

If the OPA551 or OPA552 is to be used in an application
requiring more than 0.5W continuous power dissipation, it
is recommended that the DDPAK package option be used.
The DDPAK has superior thermal dissipation characteris­tics and is more easily adapted to a heat sink.

Operation from a single power supply (or unbalanced power
supplies) can produce even larger power dissipation since a
larger voltage can be impressed across the conducting output
transistor. Consult Application Bulletin AB-039 for further
information on how to calculate or measure power dissipation.

Power dissipation can be minimized by using the lowest
possible supply voltage. For example, with a 200mA load,
the output will swing to within 3.5V of the power supply
rails. Power supplies set to no more than 3.5V above the
maximum output voltage swing required by the application
will minimize the power dissipation.

SAFE OPERATING AREA

The Safe Operating Area (SOA curves, Figures 3, 4, and 5)
shows the permissible range of voltage and current. The
curves shown represent devices soldered to a circuit board
with no heat sink. The safe output current decreases as the
voltage across the output transistor (VS – VO) increases. For
further insight on SOA, consult Application Bulletin AB-039.

Output short circuits are a very demanding case for SOA.
A short circuit to ground forces the full power supply
voltage (V+ or V–) across the conducting transistor and
produces a typical output current of 380mA. With ±30V

11

OPA551, OPA552

®

power supplies, this creates an internal dissipation of 11.4W.
This far exceeds the maximum rating and is not recom­mended. If operation in this region is unavoidable, use the
DDPAK with a heat sink.

HEAT SINKING

Power dissipated in the OPA551 or OPA552 will cause the
junction temperature to rise. For reliable operation, the
junction temperature should be limited to +125°C. Many
applications will require a heat sink to assure that the
maximum operating junction temperature is not exceeded.
The heat sink required depends on the power dissipated and
on ambient conditions.

For heat sinking purposes, the tab of the DDPAK is typically
soldered directly to a circuit board copper area. Increasing
the copper area improves heat dissipation. Figure 6 shows
typical thermal resistance from junction-to-ambient as a
function of copper area.

Depending on conditions, additional heat sinking may be
required. Aavid Thermal Products Inc. manufactures sur­face-mountable heat sinks designed specifically for use with
DDPAK packages. Further information is available on
Aavid’s web site, www.aavid.com.

To estimate the margin of safety in a complete design
(including heat sink), increase the ambient temperature until
the thermal protection is activated. Use worst-case load and
signal conditions. For good reliability, the thermal protec­tion should trigger more than +25°C above the maximum
expected ambient condition of your application. This pro­duces a junction temperature of +125°C at the maximum
expected ambient condition.

FIGURE 5. DDPAK-7 Safe Operating Area.

FIGURE 3. DIP-8 Safe Operating Area.

FIGURE 4. SO-8 Safe Operating Area.

FIGURE 6. DDPAK Thermal Resistance vs Circuit Board

Copper Area.

THERMAL RESISTANCE vs

CIRCUIT BOARD COPPER AREA

50

40

30

20

10

0

012345

Copper Area (inches

2

)

OPA551, OPA552

Surface-Mount Package

1oz. copper

Circuit Board Copper Area

OPA551, OPA552

Surface-Mount Package

Thermal Resistance,

JA

(°C/W)

θ

1000

100

10

1

0.1
1 10 100

| V

S

| – | VO | (V)

I

O

(mA)

SAFE OPERATING AREA—8-PIN DIP

125°C

85°C

25°C

1000

100

10

1

0.1
1 10 100

| V

S

| – | VO | (V)

I

O

(mA)

SAFE OPERATING AREA—SO-8

125°C

85°C

25°C

1000

100

10

1

0.1
1 10 100

| V

S

| – | VO | (V)

I

O

(mA)

SAFE OPERATING AREA—DDPAK

125°C

125°C

1" Copper

85°C

25°C

25°C

1" Copper

12

OPA551, OPA552

®

FIGURE 7. Driving Large Capacitive Loads.

CAPACITIVE LOADS

The dynamic characteristics of the OPA551 and OPA552
have been optimized for commonly encountered gains, loads,
and operating conditions. The combination of low closed­loop gain and capacitive load will decrease the phase margin
and may lead to gain peaking or oscillations. Figure 7 shows
a circuit that preserves phase margin with capacitive load.
Figure 8 shows the small-signal step response for the circuit
in Figure 7. Consult Application Bulletin AB-028 for more
information.

FIGURE 8. Small-Signal Step Response for Figure 7.

SMALL-SIGNAL STEP RESPONSE

OPA551, G = –1, C

L

= 10nF

Time (2.5µs/div)

20mV/div

FIGURE 9. Parallel Amplifers Increase Output Current Ca-

pability.

INCREASING OUTPUT CURRENT

In those applications where the 200mA of output current is
not sufficient to drive the desired load, output current can be
increased by connecting two or more OPA551s or OPA552s
in parallel as shown in Figure 9. Amplifier A1 is the
“master” amplifier and may be configured in virtually an op
amp circuit. Amplifier A2, the “slave”, is configured as a
unity gain buffer. Alternatively, external output transistors

can be used to boost output current. The circuit in Figure 10
is capable of supplying output currents up to 1A. Alterna­tively, the OPA547, OPA548, and OPA549 series power op
amps should be considered for high output current drive,
along with programmable current limit and output disable
capability.

FIGURE 10. External Output Transistors Boost Output Cur-

rent Up to 1 Amp.

R

F

4kΩ

C

S

1.8nF

10nF

OPA551

+30V

–30V

V

I

C

F

220pF

R

G

4kΩ

R

1

R

2

OPA551

OPA551

“SLAVE”

“MASTER”

V

IN

R

S

(1)

10Ω

R

S

(1)

10Ω

R

L

NOTE: (1) RS resistors minimize the circulating
current that can flow between the two devices
due to V

OS

errors.

R

1

R

2

OPA551

TIP30C

TIP29C

V

IN

+30V

–30V

V

O

R

3

(1)

100Ω

NOTE: (1) R

3

provides current limit and allows the amplifier to

drive the load when the output is between 0.7V and –0.7V.

R

4

0.2Ω

R

4

0.2Ω

LOAD

C

F

OPA551

13

OPA551, OPA552

®

INPUT PROTECTION

The OPA551 and OPA552 feature internal clamp diodes
to protect the inputs when voltages beyond the supply rails
are encountered. However, input current should be limited
to 5mA. In some cases, an external series resistor may be
required. Many input signals are inherently current-limtied,
therefore, a limiting resistor may not be required. Please
consider that a “large” series resistor, in conjunction with
the input capacitance, can affect stability.

USING THE OPA552 IN LOW GAINS

The OPA552 family is intended for applications with
signal gains of 5 or greater, but it is possible to take
advantage of their high slew rate in lower gains using an
external compensation technique in an inverting configu­ration. This technique maintains low noise characteristics
of the OPA552 architecture at low frequencies. Depending
on the application, a small increase in high frequency
noise may result. This technique shapes the loop gain for
good stability while giving an easily controlled second­order low-pass frequency response.

Considering only the noise gain (non-inverting signal
gain) for the circuit of Figure 11, the low frequency noise
gain (NG1) will be set by the resistor ratios, while the high
frequency noise gain (NG2) will be set by the capacitor
ratios. The capacitor values set both the transition fre­quencies and the high frequency noise gain. If this noise
gain, determined by NG2 = 1 + CS/CF, is set to a value
greater than the recommended minimum stable gain for
the op amp and the noise gain pole, set by 1/RFCF, is
placed correctly, a very well controlled, 2nd-order low­pass frequency response will result.

To choose the values for both CS and CF, two parameters
and only three equations need to be solved. First, the
target for the high frequency noise gain (NG2) should be
greater than the minimum stable gain for the OPA552. In
the circuit in Figure 11, a target NG2 of 10 is used.
Second, the signal gain of –1 shown in Figure 11 sets the
low frequency noise gain to NG1 = 1 + RF/RG (=2 in this
example). Using these two gains, knowing the Gain Band­width Product (GBP) for the OPA552 (12MHz), and
targeting a maximally flat 2nd-order, low-pass Butterworth
frequency response (Q = 0.707), the key frequency in the
compensation can be found.

For the values shown in Figure 11, the f

–3dB

will be
approximately 956kHz. This is less than that predicted by
simply dividing the GBP by NG1. The compensation
network controls the bandwidth to a lower value while

providing the full slew rate at the output and an excep­tional distortion performance due to increased loop gain at
frequencies below NG1 • Z0. The capacitor values shown
in Figure 11 are calculated for NG1 = 2 and NG2 = 10 with
no adjustment for parasitics.

Actual circuit values can be optimized by check the
small-signal step response with actual load conditions.
Figure 12 shows the small-signal step response of this
OPA552, G = –1 circuit with a 500pF load. It is well­behaved with no tendency to oscillate. If CS and CF were
removed, the circuit would be unstable.

FIGURE 11. Compensation of the OPA552 for G = 1.

FIGURE 12. Small-Signal Step Response for Figure 11.

SMALL-SIGNAL STEP RESPONSE

OPA552, G = –1, C

L

= 500pF

Time (1µs/div)

20mV/div

R

F

1kΩ

C

S

1.88nF

NG

1

= 1 + RF/RG = 2

NG

2

= 1 + CS/CF = 10

OPA552

+30V

–30V

V

IN

V

OUT

C

F

208pF

R

G

1kΩ

OPA552

14

OPA551, OPA552

®

The offset voltage (VOS) of the OPA51 and OPA552 is
specified with a ±30V power supply and the common­mode voltage centered between the supplies (VS/2 =
0V). Additional specifications for power supply rejec­tion and common-mode rejection are provided to allow
the user to easily calculate worst-case excepted offset
under the conditions of a given application.

Power Supply Rejection Ratio (PSRR) is specified in
µV/V. For the OPA551 and OPA552, worst-case PSRR
is 30µV/V, which means for each volt of change in total
power supply voltage, the offset may shift by up to
30µV/V. Common-Mode Rejection Ratio (CMRR) is
specified in dB, which can be converted to µV/V using
the following equation:

CMRR in (V/V) = 10

[(CMRR in dB)/–20]

(1)

For the OPA551 and OPA552, the worst-case CMRR at
±30mV supply over the full common-mode range is
96dB, or approxmately 15.8µV/V. This means that for
every volt of change in common-mode, the offset may
shift up to 15.8µV. These numbers can be used to

OFFSET VOLTAGE ERROR CALCULATION

calculate excursions from the specified offset voltage
under different applications conditions. For example, a
common application might configure the amplifier with
a –48 single supply with –6V common-mode. This
configuration represents a 12V variation in power sup­ply: ±30V or 60V in the offset specification versus 48V
in the application. In addition, this configuration has an
18V variation in common-mode voltage: VS/2 = –24V is
the specification for these power supplies, but the com­mon-mode voltage is –6V in the application.

Calculation of the worst-case expected offset would be
as follows:

Worst-case VOS = (2)

maximum specified V

OS

+ (power supply variation • PSRR
+ (common-mode variation • CMRR)

V

OSwc

= 5mV + (12V • 30µV/V) + (18V • 15.8µV/V)

= ±5.64mV