Datasheet OPA3682E-2K5, OPA3682U, OPA3682U-2K5, OPA3682E-250 Datasheet (Burr Brown)

Triple, Wideband, Fixed Gain

BUFFER AMPLIFIER W ith Disable

OPA3682

®

FEATURES

● INTERNALLY FIXED GAIN: +2 or ±1

● HIGH BANDWIDTH (G = +2): 240MHz

● LOW SUPPLY CURRENT: 6mA/ch

● LOW DISABLED CURRENT: 320µA/ch

● HIGH OUTPUT CURRENT: 150mA

● OUTPUT VOLTAGE SWING: ±4.0V

● ±5V OR SINGLE +5V OPERATION

● IMPROVED HIGH FREQUENCY PINOUT

APPLICATIONS

● RGB VIDEO LINE DRIVER

● VIDEO MULTIPLEXERS

● MULTIPLE LINE VIDEO D/As

● PORTABLE INSTRUMENTS

● ADC BUFFERS

● ACTIVE FILTERS

● WIDEBAND DIFFERENTIAL RECEIVERS

TM

DESCRIPTION

The OPA3682 provides an easy-to-use, broadband fixed
gain, triple buffer amplifier. Depending on the external
connections, the internal resistor network may be used to
provide either a fixed gain of +2 video buffer, or a gain
of +1 or –1 voltage buffer. Operating on a very low
6mA/ch supply current, the OPA3682 offers a slew rate
and output power normally associated with a much
higher supply current. A new output stage architecture
delivers high output current with minimal headroom and
crossover distortion. This gives exceptional single-sup­ply operation. Using a single +5V supply, the OPA3682
can deliver a 1V to 4V output swing with over 100mA
drive current and 200MHz bandwidth. This combination
of features makes the OPA3682 an ideal RGB line driver
or single-supply, triple ADC input driver.

The OPA3682’s low 6mA/ch supply current is precisely
trimmed at 25°C. This trim, along with low drift over
temperature, guarantees lower maximum supply current
than competing products that report only a room tempera­ture nominal supply current. System power may be further
reduced by using the optional disable control pin. Leaving
this disable pin open, or holding it high, gives normal
operation. If pulled low, the OPA3682 supply current drops
to less than 320µA/ch while the output goes into a high
impedance state. This feature may be used for either power
savings or for video MUX applications.

©

1998 Burr-Brown Corporation PDS-1496B Printed in U.S.A. June, 1999

1/3

OPA3682

400Ω400Ω

75.0Ω

75.0Ω
RG-59

V

R

1/3

OPA3682

400Ω400Ω

75.0Ω

75.0Ω
RG-59

V

G

1/3

OPA3682

400Ω400Ω

75.0Ω

75Ω Cable

75Ω Cable

75Ω Cable

75.0Ω
RG-59

V

B

Video RGB Amplifier

OPA3682 RELATED PRODUCTS

SINGLES DUALS TRIPLES

Voltage Feedback OPA680 OPA2680 OPA3680
Current Feedback OPA681 OPA2681 OPA3681
Fixed Gain OPA682 OPA2682 OPA3682

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone]

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

O

P

A

3

6

8

2

OPA3682

For most current data sheet and other product

information, visit www.burr-brown.com

2

®

OPA3682

SPECIFICATIONS: VS = ±5V

G = +2 (–IN grounded) and RL = 100Ω (Figure 1 for AC performance only), unless otherwise noted.

OPA3682E, U

TYP GUARANTEED

(1)

0°C to –40°C to

MIN/

TEST

PARAMETER CONDITIONS +25°C +25°C70°C +85°C UNITS MAX

LEVEL

(2 )

AC PERFORMANCE (Figure 1)

Small-Signal Bandwidth (V

O

< 0.5Vp-p) G = +1 330 MHz typ C

G = [phone] MHz min B
G = –1 220 MHz typ C

Bandwidth for 0.1dB Gain Flatness G = +2, V

O

< 0.5Vp-p 150 50 45 45 MHz min B

Peaking at a Gain of +1 V

O

< 0.5Vp-p 0.8 2 4 dB max B

Large-Signal Bandwidth G = +2, V

O

= 5Vp-p 210 MHz typ C
Slew Rate G = +2, 4V Step 2100 1600 1600 1200 V/µs min B
Rise/Fall Time G = +2, VO = 0.5V Step 1.7 ns typ C

G = +2, V

O

= 5V Step 2.0 ns typ C

Settling Time to 0.02% G = +2, V

O

= 2V Step 12 ns typ C

0.1% G = +2, V

O

= 2V Step 8 ns typ C

Harmonic Distortion G = +2, f = 5MHz, V

O

= 2Vp-p

2nd Harmonic R

L

= 100Ω –69 –62 –59 –57 dBc max B

R

L

≥ 500Ω –79 –70 –67 –65 dBc max B

3rd Harmonic R

L

= 100Ω –84 –75 –71 –69 dBc max B

R

L

≥ 500Ω –95 –82 –76 –74 dBc max B
Input Voltage Noise f > 1MHz 2.2 3.0 3.4 3.6 nV/√Hz max B
Non-Inverting Input Current Noise f > 1MHz 12 14 15 15 pA/√Hz max B
Inverting Input Current Noise f > 1MHz 15 18 18 19 pA/√Hz max B
Differential Gain NTSC, R

L

= 150Ω 0.001 % typ C

NTSC, R

L

= 37.5Ω 0.008 % typ C

Differential Phase NTSC, R

L

= 150Ω 0.01 deg typ C

NTSC, R

L

= 37.5Ω 0.05 deg typ C

Channel-to-Channel Crosstalk f = 5MHz, Input Referred, All Hostile –55 dBc typ C

DC PERFORMANCE

(3)

Gain Error G = +1 ±0.2 % typ C

G = +2 ±0.3

±2.0 % max A

G = –1 ±0.2 ±2.0 % max B

Internal R

F

and R

G

Maximum 400 480 510 520 Ω max A
Minimum 400 320 310 290 Ω min A
Average Drift 0.13 0.13 0.13 %/C° max B

Input Offset Voltage V

CM

= 0V ±1.3 ±5 ±6.5 ±7.5 mV max A

Average Offset Voltage Drift V

CM

= 0V +35 +40 µV/°C max B

Non-Inverting Input Bias Current V

CM

= 0V +30 +55 ±65 ±85 µA max A

Average Non-Inverting Input Bias Current Drift V

CM

= 0V –400 –450 nA/°C max B

Inverting Input Bias Current V

CM

= 0V ±10 ±40 ±50 ±55 µA max A

Average Inverting Input Bias Current Drift V

CM

= 0V –125 –150 nA°C max B

INPUT

Common-Mode Input Range ±3.5 ±3.4 ±3.3 ±3.2 V min B
Non-Inverting Input Impedance 100 || 2 kΩ || pF typ C

OUTPUT

Voltage Output Swing No Load ±4.0

±3.8 ±3.7 ±3.6 V min A

100Ω Load ±3.9

±3.7 ±3.6 ±3.3 V min A

Current Output, Sourcing +190 +160 +140 +80 mA min A

Sinking –150 –135 –130 –80 mA min A

Closed-Loop Output Impedance G = +2, f = 100kHz 0.03 Ω typ C

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

3

®

OPA3682

SPECIFICATIONS: VS = ±5V (Cont.)

G = +2 (–IN grounded) and RL = 100Ω (Figure 1 for AC performance only), unless otherwise noted.

OPA3682E, U

TYP GUARANTEED

(1)

0°C to –40°C to

MIN/

TEST

PARAMETER CONDITIONS +25°C +25°C70°C +85°C UNITS MAX

LEVEL

(2 )

DISABLE/POWER DOWN (DIS Pin)

Power Down Supply Current (+V

S

)V

DIS

= 0, All Channels –960 µA typ C
Disable Time 100 ns typ C
Enable Time 25 ns typ C
Off Isolation G = +2, 5MHz 70 dB typ C
Output Capacitance in Disable 4 pF typ C
Turn On Glitch G = +2, R

L

= 150Ω±50 mV typ C

Turn Off Glitch G = +2, R

L

= 150Ω±20 mV typ C
Enable Voltage 3.3 3.5 3.6 3.7 V min A
Disable Voltage 1.8 1.7 1.6 1.5 V max A
Control Pin Input Bias Current V

DIS

= 0, Each Channel 100 160 160 160 µA max A

POWER SUPPLY

Specified Operating Voltage ±5 V typ C
Maximum Operating Voltage Range

±6 ±6 ±6 V max A

Max Quiescent Current (3 Channels) V

S

= ±5V 18 19.2 19.5 19.8 mA max A

Min Quiescent Current (3 Channels) V

S

= ±5V 18 16.8 16.5 15.0 mA min A

Power Supply Rejection Ratio (–PSRR) Input Referred 58 52 50 49 dB min A

TEMPERATURE RANGE

Specification: E, U

–40 to +85

°C typ C

Thermal Resistance,

θ

JA

E SSOP-16 Surface Mount 100 °C/W typ C
U SO-16 Surface Mount 100 °C/W typ C

NOTES: (1) Junction temperature = ambient temperature for low temperature limit and 25°C guaranteed specifications. Junction temperature = ambient temperature
+23°C at high temperature limit guaranteed specifications. (2) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. V

CM

is the input common-mode

voltage.

4

®

OPA3682

SPECIFICATIONS: VS = +5V

G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VS/2 (Figure 2 for AC performance only), unless otherwise noted.

OPA3682E, U

TYP GUARANTEED

(1)

0°C to –40°C to

MIN/

TEST

PARAMETER CONDITIONS +25°C +25°C70°C +85°C UNITS MAX

LEVEL

(2)

AC PERFORMANCE (Figure 2)

Small-Signal Bandwidth (V

O

< 0.5Vp-p) G = +1 290 MHz typ C

G = [phone] MHz min B
G = –1 200 MHz typ C

Bandwidth for 0.1dB Gain Flatness G = +2, V

O

< 0.5Vp-p 100 50 35 23 MHz min B

Peaking at a Gain of +1 V

O

< 0.5Vp-p 0.4 2 4 dB max B
Large-Signal Bandwidth G = +2, VO = 2Vp-p 210 MHz typ C
Slew Rate G = +2, 2V Step 830 700 680 570 V/µs min B
Rise/Fall Time G = +2, V

O

= 0.5V Step 1.5 ns typ C

G = +2, V

O

= 2V Step 2.0 ns typ C

Settling Time to 0.02% G = +2, VO = 2V Step 14 ns typ C

0.1% G = +2, V

O

= 2V Step 9 ns typ C

Harmonic Distortion G = +2, f = 5MHz, V

O

= 2Vp-p

2nd Harmonic R

L

= 100Ω to VS/2 –62 –56 –55 –53 dBc max B

R

L

≥ 500Ω to VS/2 –69 –62 –61 –59 dBc max B

3rd Harmonic R

L

= 100Ω to VS/2 –71 –64 –63 –61 dBc max B

R

L

≥ 500Ω to VS/2 –73 –68 –67 –65 dBc max B
Input Voltage Noise f > 1MHz 2.2 3.0 3.4 3.6 nV/√Hz max B
Non-Inverting Input Current Noise f > 1MHz 12 14 14 15 pA/√Hz max B
Inverting Input Current Noise f > 1MHz 15 18 18 19 pA/√Hz max B

DC PERFORMANCE

(3)

Gain Error G = +1 ±0.2 % typ C

G = +2 ±0.3 ±2.0 % max A
G = –1 ±0.2 ±2.0 % max B

Internal R

F

and R

G

Minimum 400 480 510 520 Ω min B
Maximum 400 320 310 290 Ω max B
Average Drift 0.13 0.13 0.13 %/C° max B

Input Offset Voltage V

CM

= 2.5V ±1 ±4 ±6 ±7 mV max A

Average Offset Voltage Drift V

CM

= 2.5V +15 +20 µV/°C max B
Non-Inverting Input Bias Current VCM = 2.5V +40 +65 +75 +95 µA max A
Average Non-Inverting Input Bias Current Drift V

CM

= 2.5V –300 –350 nA/°C max B
Inverting Input Bias Current VCM = 2.5V ±5 ±20 ±25 ±35 µA max A
Average Inverting Input Bias Current Drift V

CM

= 2.5V –125 –175 nA°C max B

INPUT

Least Positive Input Voltage 1.5 1.6 1.4 1.8 V max B
Most Positive Input Voltage 3.5 3.4 3.3 3.2 V min B
Non-Inverting Input Impedance 100 || 2 kΩ || pF typ C

OUTPUT

Most Positive Output Voltage No Load 4.0 3.8 3.7 3.5 V min A

R

L

= 100Ω 3.9 3.7 3.6 3.4 V min A

Least Positive Output Voltage No Load 1.0 1.2 1.3 1.5 V max A

R

L

= 100Ω 1.1 1.3 1.4 1.6 V max A

Current Output, Sourcing +150 +110 +110 +60 mA min A

Sinking –110 –75 –70 –50 mA min A

Output Impedance G = +2, f = 100kHz 0.03 Ω typ C

5

®

OPA3682

SPECIFICATIONS: VS = +5V (Cont.)

G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VS/2 (Figure 2 for AC performance only), unless otherwise noted.

OPA3682E, U

TYP GUARANTEED

(1)

0°C to –40°C to

MIN/

TEST

PARAMETER CONDITIONS +25°C +25°C70°C +85°C UNITS MAX

LEVEL

(2)

DISABLE/POWER DOWN (DIS Pin)

Power Down Supply Current (+VS)V

DIS

= 0, All Channels –810 µA typ C
Disable Time 100 ns typ C
Enable Time 25 ns typ C
Off Isolation G = +2, 5MHz 65 dB typ C
Output Capacitance in Disable 4 pF typ C
Turn On Glitch G = +2, R

L

= 150Ω, VIN = 2.5V ±50 mV typ B
Turn Off Glitch G = +2, RL = 150Ω, VIN = 2.5V ±20 mV typ B
Enable Voltage 3.3 3.5 3.6 3.7 V min A
Disable Voltage 1.8 1.7 1.6 1.5 V max A
Control Pin Input Bias Current (DIS) V

DIS

= 0, Each Channel 100 µA typ C

POWER SUPPLY

Specified Single Supply Operating Voltage 5 V typ C
Maximum Single Supply Operating Voltage 12 12 12 V max A
Max Quiescent Current (3 Channels) V

S

= +5V 14.4 15.9 16.2 16.2 mA max A

Min Quiescent Current (3 Channels) V

S

= +5V 14.4 12.3 11.1 10.8 mA min A

Power Supply Rejection Ratio (+PSRR) Input Referred 50 dB typ C

TEMPERATURE RANGE

Specification: E, U

–40 to +85

°C typ C

Thermal Resistance,

θ

JA

E SSOP-16 Surface Mount 100 °C/W typ C
U SO-16 Surface Mount 100 °C/W typ C

NOTES: (1) Junction temperature = ambient temperature for low temperature limit and 25°C guaranteed specifications. Junction temperature = ambient temperature
+23°C at high temperature limit guaranteed specifications. (2) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. V

CM

is the input common-mode

voltage.

6

®

OPA3682

ABSOLUTE MAXIMUM RATINGS

Power Supply ..............................................................................±6.5VDC

Internal Power Dissipation

(1)

............................ See Thermal Information

Differential Input Voltage .................................................................. ±1.2V

Input Voltage Range ............................................................................ ±V

S

Storage Temperature Range: E, U ................................ –40 °C to +125°C

Lead Temperature (soldering, 10s) .............................................. +300°C

Junction Temperature (T

J

) ........................................................... +175°C

NOTE:: (1) Packages must be derated based on specified

θ

JA

. Maximum T

J

must be observed.

PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER

(1)

RANGE MARKING NUMBER

(2)

MEDIA

OPA3682E SSOP-16 Surface Mount 322 –40°C to +85°C OPA3682E OPA3682E/250 Tape and Reel

"""""OPA3682E/2K5 Tape and Reel

OPA3682U SO-16 Surface Mount 265 –40°C to +85°C OPA3682U OPA3682U/2K5 Tape and Reel

"""""OPA3682U Tube

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA3682E/2K5” will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

PACKAGE/ORDERING INFORMATION

PIN CONFIGURATION

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

–IN A

+IN A

DIS B

–IN B

+IN B

DIS C

–IN C

+IN C

DIS A

+V

S

OUT A

–V

S

OUT B

+V

S

OUT C

–V

S

OPA3682

400Ω

400Ω

400Ω

400Ω

400Ω

400Ω

ELECTROSTATIC
DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from perfor­mance degradation to complete device failure. Burr-Brown Corpo­ration recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.

Top View SSOP-16, SO-16

7

®

OPA3682

TYPICAL PERFORMANCE CURVES: VS = ±5V

G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1).

2

1

0
–1
–2
–3
–4
–5
–6
–7
–8

Frequency (50MHz/div)

0 500MHz250MHz

SMALL-SIGNAL FREQUENCY RESPONSE

Normalized Gain (1dB/div)

G = –1

G = +1

G = +2

8
7
6
5
4
3
2
1

0
–1
–2

Frequency (25MHz/div)

0 250MHz125MHz

LARGE-SIGNAL FREQUENCY RESPONSE

Gain (1dB/div)

2Vp-p

RL = 100Ω

1Vp-p

4Vp-p

7Vp-p

400
300
200
100

0
–100
–200
–300
–400

SMALL-SIGNAL PULSE RESPONSE

Time (5ns/div)

Output Voltage (100mV/div)

VO = 0.5Vp-p

+4
+3
+2
+1

0
–1
–2
–3
–4

LARGE-SIGNAL PULSE RESPONSE

Time (5ns/div)

Output Voltage (1V/div)

VO = 5Vp-p

2.0

1.6

1.2

0.8

0.4
0

LARGE-SIGNAL DISABLE/ENABLE RESPONSE

Time (50ns/div)

Output Voltage (400mV/div)

6.0

4.0

2.0
0

V

DIS

(2V/div)

V

DIS

Output Voltage

VIN = +1V

ALL HOSTILE CROSSTALK

–20
–30
–40
–50
–60
–70
–80
–90

–100

Frequency (MHz)

0.3 10 1001 300

Crosstalk (dB)

V

DIS

= 0V

8

®

OPA3682

TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.)

G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1).

–50

–60

–70

–80

–90

5MHz 2nd HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage Swing (Vp-p)

0.1 1 5

2nd Harmonic Distortion (dBc)

RL = 500Ω

RL = 200Ω

RL = 100Ω

–50

–60

–70

–80

–90

5MHz 3rd HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage Swing (Vp-p)

0.1 1 5

3rd Harmonic Distortion (dBc)

RL = 100Ω

RL = 200Ω

RL = 500Ω

–50

–60

–70

–80

–90

10MHz 2nd HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage Swing (Vp-p)

0.1 1 5

2nd Harmonic Distortion (dBc)

RL = 100Ω

RL = 200Ω

RL = 500Ω

–50

–60

–70

–80

–90

10MHz 3rd HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage Swing (Vp-p)

0.1 1 5

3rd Harmonic Distortion (dBc)

RL = 100Ω

RL = 200Ω

RL = 500Ω

–50

–60

–70

–80

–90

20MHz 2nd HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage Swing (Vp-p)

0.1 1 5

2nd Harmonic Distortion (dBc)

RL = 100Ω

RL = 200Ω

RL = 500Ω

–50

–60

–70

–80

–90

Output Voltage Swing (Vp-p)

0.1 1 5

3rd Harmonic Distortion (dBc)

RL = 100Ω

RL = 200Ω

RL = 500Ω

20MHz 3rd HARMONIC DISTORTION

vs OUTPUT VOLTAGE

9

®

OPA3682

TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.)

G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1).

100

10

1

INPUT VOLTAGE AND CURRENT NOISE DENSITY

vs FREQUENCY

Frequency (Hz)

100 1k 10k 100k 1M 10M

Current Noise (pA/√Hz)

Voltage Noise (nV/√Hz)

Non-Inverting Input Current Noise

Inverting Input Current Noise

12pA/√Hz

15pA/√Hz

Voltage Noise

2.2nV/√Hz

–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90

TWO-TONE, 3rd-ORDER

INTERMODULATION SPURIOUS

Single-Tone Load Power (dBm)

–8–6–4–20246810

3rd-Order Spurious Level (dBc)

dBc = dB Below Carriers

50MHz

20MHz

10MHz

Load Power at Matched 50Ω Load

60

50

40

30

20

10

0

RECOMMENDED R

S

vs CAPACITIVE LOAD

Capacitive Load (pF)

1 10 100

R

S

(Ω)

15
12

9
6
3

0
–3
–6
–9

–12
–15

Frequency (30MHz/div)

0 300MHz150MHz

FREQUENCY RESPONSE vs CAPACITIVE LOAD

Gain to Capacitive Load (3dB/div)

OPA3682

R

S

V

IN

V

O

C

L

1kΩ

400Ω

400Ω

1kΩ is optional.

CL = 22pF

CL = 10pF

CL = 47pF

CL = 100pF

–50

–60

–70

–80

–90

2nd HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1 1 10 20

2nd Harmonic Distortion (dBc)

VO = 2Vp-p
R

L

= 100Ω

G = +1

G = –1 G = +2

–50

–60

–70

–80

–90

3rd HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1 1 10 20

3rd Harmonic Distortion (dBc)

VO = 2Vp-p
R

L

= 100Ω

G = +2

G = +1

G = –1

10

®

OPA3682

TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.)

G = +2 and RL = 100Ω, unless otherwise noted (see Figure 1).

70
65
60
55
50
45
40
35
30
25
20

Frequency (Hz)

10

2

10

3

10

4

10

5

10

6

10

7

10

8

POWER SUPPLY REJECTION RATIO vs FREQUENCY

Power Supply Rejection Ratio (dB)

+PSRR
–PSRR

10

7.5

5

2.5

0

200

150

100

50

0

SUPPLY AND OUTPUT CURRENT vs TEMPERATURE

Ambient Temperature (°C)

–40 –20 0 20 40 60 80 100 120 140

Supply Current (mA/ch)

Output Current (mA)

Quiescent Supply Current

Sourcing Output Current

Sinking Output Current

0.05

0.04

0.03

0.02

0.01

0

Number of 150Ω Loads

1234

COMPOSITE VIDEO dG/dφ

Positive Video

Negative Sync

dP

dG

dG/dφ (%/°)

5
4
3
2
1

0
–1
–2
–3
–4
–5

TYPICAL DC DRIFT OVER TEMPERATURE

Ambient Temperature (°C)

–40 –20

V

IO

0 20 40 60 80 100 120 140

Input Offset Voltage (mV)

50
40
30
20
10
0
–10
–20
–30
–40
–50

Input Bias Currents (µA)

Non-Inverting Input Bias Current

Inverting Input Bias Current

10

1

0.1

0.01

CLOSED-LOOP OUTPUT IMPEDANCE

vs FREQUENCY

Frequency (Hz)

10k 100M100k 1M 10M

Output Impedance (Ω)

1/3

OPA3682

400Ω

+5

–5

400Ω

50Ω

Z

O

5
4
3
2
1

0
–1
–2
–3
–4
–5

OUTPUT VOLTAGE AND CURRENT LIMITATIONS

I

O

(mA)

–300 –200 –100 0 100 200 300

V

O

(Volts)

100Ω Load Line

50Ω Load Line

25Ω

Load Line

Output Current Limited

1W Internal
Power Limit

1W Internal

Power Limit

Output Current Limit

One Channel

Only

11

®

OPA3682

TYPICAL PERFORMANCE CURVES: VS = +5V

G = +2 and RL = 100Ω to VS/2, unless otherwise noted (see Figure 2).

2
1

0
–1
–2
–3
–4
–5
–6
–7
–8

Frequency (50MHz/div)

0 500MHz250MHz

SMALL-SIGNAL FREQUENCY RESPONSE

Normalized Gain (1dB/div)

G = +1

G = –1

G = +2

8
7
6
5
4
3
2
1

0
–1
–2

Frequency (25MHz/div)

0 250125

LARGE-SIGNAL FREQUENCY RESPONSE

Gain (1dB/div)

RL = 100Ω to 2.5V

VO = 0.5Vp-p

VO = 1Vp-p

VO = 2Vp-p

15
12

9
6
3

0
–3
–6
–9

–12
–15

FREQUENCY RESPONSE vs CAPACITIVE LOAD

Frequency (20MHz/div)

0 200MHz100MHz

Gain to Capacitive Load (3dB/div)

CL = 22pF

CL = 10pF

CL = 47pF

CL = 100pF

OPA3682

400Ω

400Ω

57.6Ω

806Ω

806Ω

1kΩ

V

IN

+5V

0.1µF

V

O

R

S

(1kΩ is optional)

C

L

0.1µF

2.10

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

SMALL-SIGNAL PULSE RESPONSE

Time (5ns/div)

Output Voltage (100mV/div)

VO = 0.5Vp-p

4.5

4.1

3.7

3.3

2.9

2.5

2.1

1.7

1.3

0.9

0.5

LARGE-SIGNAL PULSE RESPONSE

Time (5ns/div)

Output Voltage (400mV/div)

VO = 2Vp-p

70

60

50

40

30

20

10

0

RECOMMENDED R

S

vs CAPACITIVE LOAD

Capacitive Load (pF)

1 10 100

R

S

(Ω)

12

®

OPA3682

TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)

G = +2 and RL = 100Ω to VS/2, unless otherwise noted (see Figure 2).

–40

–50

–60

–70

–80

–90

TWO-TONE, 3rd-ORDER SPURIOUS LEVEL

Single-Tone Load Power (dBm)

–14 2–12 –10 –8 –6 –4 –2 0

3rd-Order Spurious (dBc)

50MHz

20MHz

10MHz

Load Power at Matched 50Ω Load

dBc = dB Below Carriers

–50

–60

–70

–80

–90

2nd HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1 1 10 20

2nd Harmonic Distortion (dBc)

VO = 2Vp-p
R

L

= 100Ω

G = –1

G = +1

G = +2

–50

–60

–70

–80

–90

3rd HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1 1 10 20

3rd Harmonic Distortion (dBc)

VO = 2Vp-p
R

L

= 100Ω

G = –1

G = +2

G = +1

2nd HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1 1 10 20

2nd Harmonic Distortion (dBc)

–50

–60

–70

–80

–90

VO = 2Vp-p

RL = 500Ω

RL = 200Ω

RL = 100Ω

3rd HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1 1 10 20

3rd Harmonic Distortion (dBc)

–50

–60

–70

–80

–90

VO = 2Vp-p

RL = 200Ω

RL = 500Ω

RL = 100Ω

13

®

OPA3682

APPLICATIONS INFORMATION

WIDEBAND BUFFER OPERATION

The OPA3682 gives the exceptional AC performance of a
wideband, current-feedback op amp with a highly linear,
high power output stage. It features internal RF and R

G

resistors which make it easy to select a gain of +2, +1 or
–1 without external resistors. Requiring only 6mA/ch quies­cent current, the OPA3682 will swing to within 1V of either
supply rail and deliver in excess of 135mA guaranteed at
room temperature. This low output headroom requirement,
along with supply voltage independent biasing, gives re­markable single (+5V) supply operation. The OPA3682 will
deliver greater than 200MHz bandwidth driving a 2Vp-p
output into 100Ω on a single +5V supply. Previous boosted
output stage amplifiers have typically suffered from very
poor crossover distortion as the output current goes through
zero. The OPA3682 achieves a comparable power gain with
much better linearity.

Figure 1 shows the DC-coupled, gain of +2, dual power
supply circuit configuration used as the basis of the ±5V
Specifications and Typical Performance Curves. For test
purposes, the input impedance is set to 50Ω with a resistor
to ground and the output impedance is set to 50Ω with a
series output resistor. Voltage swings reported in the speci­fications are taken directly at the input and output pins
while load powers (dBm) are defined at a matched 50Ω
load. For the circuit of Figure 1, the total effective load will
be 100Ω || 800Ω = 89Ω. The disable control line (DIS) is
typically left open to guarantee normal amplifier operation.
In addition to the usual power supply decoupling capacitors
to ground, a 0.1µF capacitor can be included between the
two power supply pins. This optional capacitor will typi­cally improve the 2nd harmonic distortion performance by
3dB to 6dB.

FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifi-

cation and Test Circuit.

FIGURE 2. AC-Coupled, G = +2, Single-Supply Specifica-

tion and Test Circuit.

Figure 2 shows the AC-coupled, gain of +2, single-supply
circuit configuration used as the basis of the +5V Specifica­tions and Typical Performance Curves. Though not a “rail­to-rail” design, the OPA3682 requires minimal input and
output voltage headroom compared to other very wideband,
current-feedback op amps. It will deliver a 3Vp-p output
swing on a single +5V supply with greater than 150MHz
bandwidth. The key requirement of broadband single-supply
operation is to maintain input and output signal swings
within the usable voltage ranges at both the input and the
output. The circuit in Figure 2 establishes an input midpoint
bias using a simple resistive divider from the +5V supply
(two 806Ω resistors). The input signal is then AC-coupled
into this midpoint voltage bias. The input voltage can swing
to within 1.5V of either supply pin, giving a 2Vp-p input
signal range centered between the supply pins. The input
impedance matching resistor (57.6Ω) used for testing is
adjusted to give a 50Ω input match when the parallel
combination of the biasing divider network is included. The
gain resistor (RG) is AC-coupled, giving the circuit a DC
gain of +1, which puts the input DC bias voltage (2.5V) on
the output as well. Again, on a single +5V supply, the output
voltage can swing to within 1V of either supply pin while
delivering more than 75mA output current. A demanding
100Ω load to a midpoint bias is used in this characterization
circuit. The new output stage used in the OPA3682 can
deliver large bipolar output currents into this midpoint load
with minimal crossover distortion, as shown by the +5V
supply, 3rd harmonic distortion plots.

VIDEO RGB AMPLIFIER

The front page shows an RGB amplifier based on the
OP A3682. The package pinout supports a signal flow-through
PCB layout. The internal resistors simplify the PCB even
more, while maintaining good gain accuracy . For systems that
need to conserve power, the total supply current for the
disabled OPA3682 is only 0.9mA.

1/3

OPA3682

+5V

–5V

50Ω Load

50Ω

50Ω

50Ω Source

R

G

400Ω

R

F

400Ω

+

6.8µF0.1µF

+

6.8µF0.1µF

DIS

V

IN

1/3

OPA3682

+5V

+V

S

DIS

VS/2

806Ω

100ΩV

O

V

IN

806Ω

R

G

400Ω

R

F

400Ω

0.1µF

0.1µF

+

6.8µF0.1µF

50Ω Source

57.6Ω

14

®

OPA3682

This triple op amp could also be used to drive triple video
ADCs to digitize component video.

HIGH SPEED INSTRUMENTATION AMPLIFIER

Figure 3 shows an instrumentation amplifier based on the
OPA3682. The offset matching between inputs makes this an
attractive input stage for this application. The differential-to­single-ended gain for this circuit is 2.0V/V. The inputs are
high impedance, with only 1pF to ground at each input. The
loads on the OP A3682 outputs are equal for the best harmonic
distortion possible.

MULTIPLEXED CONVERTER DRIVER

The converter driver in Figure 4 multiplexes among the
three input signals. The OPA3682s enable and disable times
support multiplexing among video signals. The “make­before-break” disable characteristic of the OP A3682 ensures
that the output is always under control. To avoid large
switching glitches, switch during the sync or retrace por­tions of the video signal—the two inputs should be almost
equal at these times. Because the output is always under
control, the switching glitches for two 0V inputs are
< 20mV. With standard video signals levels at the inputs, the

maximum differential voltage across the disabled inputs will
not exceed the ±1.2V maximum rating.

FIGURE 3. High-Speed Instrumentation Amplifier.

1/3

OPA3682

1/3

OPA3682

1/3

OPA3682

400Ω400Ω

400Ω

400Ω 400Ω

200Ω 200Ω

400Ω

V

2

V

OUT

V

1

FIGURE 4. Multiplexed Converter Driver.

1/3

OPA3682

400Ω400Ω

100Ω

V

1

1/3

OPA3682

400Ω400Ω

100Ω

V

2

1/3

OPA3682

400Ω400Ω

100Ω

V

3

Selection

Logic

ADS823

10-Bit

60MSPS

0.1µF

0.1µF

4.99kΩ

0.1µF

4.99kΩ

0.1µF

100pF

REFT
+3.5V

REFB
+1.5V

+In

–In

CM

15

®

OPA3682

The output resistors isolate the outputs from each other
when switching between channels. The feedback network of
the disabled channels forms part of the load seen by the
enabled amplifier, attenuating the signal slightly.

LOWP ASS FILTER

The circuit in Figure 5 realizes a 7th-order Butterworth
lowpass filter with a –3dB bandwidth of 20MHz. This filter
is based on the KRC active filter topology, which uses an
amplifier with the fixed gain ≥ 1. The OP A3682 makes a good
amplifier for this type of filter. The component values have
been pre-distorted to compensate for the op amp’s parasitic
effects.

DESIGN-IN TOOLS

APPLICATIONS SUPPORT

The Burr-Brown Applications department is available for
design assistance at 1-800-548-6132 (US/Canada only). The
Burr-Brown internet web page (http://www .burr-brown.com)
has the latest data sheets and other design aids.

DEMONSTRATION BOARDS

A PC board is available to assist in the initial evaluation of
circuit performance using the OPA3682E. It is available as
a free unpopulated PC board delivered with descriptive

documentation. The summary information for this board is
shown in the table below.

Contact the Burr-Brown applications support line to request
this board.

MACROMODELS AND APPLICATIONS SUPPORT

Computer simulation of circuit performance using SPICE

®

is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and induc­tance can have a major effect on circuit performance. A
SPICE model for the OPA3682 is available through the
Burr-Brown Internet web page (http://www .burr-brown.com).
The Applications department is also available for design
assistance at this number. These models do a good job of
predicting small-signal AC and transient performance under
a wide variety of operating conditions. They do not do as
well in predicting the harmonic distortion or dG/dφ charac­teristics. These models do not attempt to distinguish between
the package types in their small-signal AC performance.

DEMO LITERATURE

BOARD REQUEST

PRODUCT PACKAGE NUMBER NUMBER

OPA3682E SSOP-16 DEM-OPA368xE MKT-354

FIGURE 5. 7th-Order Butterworth Filter.

1/3

OPA3682

400Ω

400Ω

120pF

82pF

220pF

22pF

68pF

47.5Ω

124Ω

1/3

OPA3682

400Ω

56pF

110Ω

255Ω

400Ω

1/3

OPA3682

400Ω

400Ω

180pF

48.7Ω

95.3Ω

49.9Ω

(open)

(open)

V

OUT

V

IN

16

®

OPA3682

OPERATING SUGGESTIONS

GAIN SETTING

Setting the gain with the OPA3682 is very easy. For a gain
of +2, ground the –IN pin and drive the +IN pin with the
signal. For a gain of +1, leave the –IN pin open and drive the
+IN pin with the signal. For a gain of –1, ground the +IN pin
and drive the –IN pin with the signal. Since the internal
resistor values (but not their ratios) change significantly over
temperature and process, external resistors should not be
used to modify the gain.

OUTPUT CURRENT AND VOLTAGE

The OPA3682 provides output voltage and current capabili­ties that are unsurpassed in a low cost monolithic op amp.
Under no-load conditions at 25°C, the output voltage typi­cally swings closer than 1V to either supply rail; the guaran­teed swing limit is within 1.2V of either rail. Into a 15Ω load
(the minimum tested load), it is guaranteed to deliver more
than ±135mA.

The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage • current, or V-I product,
which is more relevant to circuit operation. Refer to the
“Output Voltage and Current Limitations” plot in the T ypical
Performance Curves. The X and Y axes of this graph show
the zero-voltage output current limit and the zero-current
output voltage limit, respectively. The four quadrants give a
more detailed view of the OPA3682’s output drive capabili­ties, noting that the graph is bounded by a “Safe Operating
Area” of 1W maximum internal power dissipation. Superim­posing resistor load lines onto the plot shows that the
OPA3682 can drive ±2.5V into 25Ω or ±3.5V into 50Ω
without exceeding the output capabilities or the 1W dissipa­tion limit. A 100Ω load line (the standard test circuit load)
shows the full ±3.9V output swing capability, as shown in
the Specifications Table.

The minimum specified output voltage and current over­temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold start-up will the output
current and voltage decrease to the numbers shown in the
guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
VBEs (increasing the available output voltage swing) and
increasing their current gains (increasing the available out­put current). In steady-state operation, the available output
voltage and current will always be greater than that shown
in the over-temperature specifications since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.

In order to maintain maximum output stage linearity, no
output short-circuit protection is provided. This will not
normally be a problem since most applications include a
series matching resistor at the output that will limit the
internal power dissipation if the output side of this resistor
is shorted to ground. However, shorting the output pin

directly to the adjacent positive power supply pin will, in

most cases, destroy the amplifier. If additional short-

circuit protection is required, consider a small series resistor
in the power supply leads. This will, under heavy output
loads, reduce the available output voltage swing. A 5Ω series
resistor in each power supply lead will limit the internal
power dissipation to less than 1W for an output short circuit
while decreasing the available output voltage swing only

0.5V for up to 100mA desired load currents. Always place
the 0.1µF power supply decoupling capacitors directly on
the supply pins, after these supply current-limiting resistors.

DRIVING CAPACITIVE LOADS

One of the most demanding, but yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter—including
additional external capacitance which may be recommended
to improve A/D linearity. A high-speed amplifier like the
OPA3682 can be very susceptible to decreased stability and
closed-loop response peaking when a capacitive load is placed
directly on the output pin. When the amplifier’s open-loop
output resistance is considered, this capacitive load intro­duces an additional pole in the signal path that can decrease
the phase margin. Several external solutions to this problem
have been suggested. When the primary considerations are
frequency response flatness, pulse response fidelity and/or
distortion, the simplest and most effective solution is to
isolate the capacitive load from the feedback loop by inserting
a series isolation resistor between the amplifier output and the
capacitive load. This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.

The Typical Performance Curves show the recommended R

S

verses capacitive load and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF can begin
to degrade the performance of the OPA3682. Long PC board
traces, unmatched cables, and connections to multiple devices
can easily cause this value to be exceeded. Always consider
this effect carefully, and add the recommended series resistor
as close as possible to the OPA3682 output pin (see Board
Layout Guidelines).

DISTORTION PERFORMANCE

The OPA3682 provides good distortion performance into a
100Ω load on ±5V supplies. Relative to alternative solutions,
it provides exceptional performance into lighter loads and/or
operating on a single +5V supply. Generally, until the funda­mental signal reaches very high frequency or power levels, the
2nd harmonic will dominate the distortion with a negligible
3rd harmonic component. Focusing then on the 2nd harmonic,
increasing the load impedance improves distortion directly.
Remember that the total load includes the feedback network in
the non-inverting configuration (Figure 1); this is the sum R

F

+ RG, while in the inverting configuration, it is just RF. Also,
providing an additional supply decoupling capacitor (0.1µF)
between the supply pins (for bipolar operation) improves the
2nd-order distortion slightly (3dB to 6dB).

17

®

OPA3682

In most op amps, increasing the output voltage swing increases
harmonic distortion directly. The Typical Performance Curves
show the 2nd harmonic increasing at a little less than the
expected 2X rate while the 3rd harmonic increases at a little
less than the expected 3X rate. Where the test power doubles,
the difference between it and the 2nd harmonic decreases less
than the expected 6dB while the difference between it and the
3rd decreases by less than the expected 12dB. This also shows
up in the 2-tone, 3rd-order intermodulation spurious (IM3)
response curves. The 3rd-order spurious levels are extremely
low at low output power levels. The output stage continues to
hold them low even as the fundamental power reaches very
high levels. As the Typical Performance Curves show, the
spurious intermodulation powers do not increase as predicted
by a traditional intercept model. As the fundamental power
level increases, the dynamic range does not decrease signifi­cantly. For two tones centered at 20MHz, with 10dBm/tone
into a matched 50Ω load (i.e., 2Vp-p for each tone at the load,
which requires 8Vp-p for the overall 2-tone envelope at the
output pin), the Typical Performance Curves show a 62dBc
difference between the test-tone power and the 3rd-order
intermodulation spurious levels. This exceptional performance
improves further when operating at lower frequencies.

NOISE PERFORMANCE

The OPA3682 offers an excellent balance between voltage
and current noise terms to achieve low output noise. The
inverting current noise (15pA/√Hz) is significantly lower than
earlier solutions while the input voltage noise (2.2nV√Hz) is
lower than most unity-gain stable, wideband, voltage-feed­back op amps. This low input voltage noise was achieved at
the price of higher non-inverting input current noise (12pA/
√Hz). As long as the AC source impedance looking out of the
non-inverting node is less than 100Ω, this current noise will
not contribute significantly to the total output noise. The op
amp input voltage noise and the two input current noise terms
combine to give low output noise under a wide variety of
operating conditions. Figure 6 shows the op amp noise analy­sis model with all the noise terms included. In this model, all
noise terms are taken to be noise voltage or current density
terms in either nV/√Hz or pA√Hz.

The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the output
noise voltage using the terms shown in Figure 6.

Dividing this expression by the noise gain (NG = (1+RF/RG))
will give the equivalent input-referred spot noise voltage at the
non-inverting input as shown in Equation 2.

Evaluating these two equations for the OPA3682 circuit and
component values shown in Figure 1 will give a total output
spot noise voltage of 8.4nV/√Hz and a total equivalent input
spot noise voltage of 4.2nV/√Hz. This total input-referred
spot noise voltage is higher than the 2.2nV/√Hz specifica­tion for the op amp voltage noise alone. This reflects the
noise added to the output by the inverting current noise times
the feedback resistor.

DC ACCURACY

The OP A3682 provides exceptional bandwidth in high gains,
giving fast pulse settling but only moderate DC accuracy.
The Specifications table shows an input offset voltage com­parable to high speed voltage-feedback amplifiers. However,
the two input bias currents are somewhat higher and are
unmatched. Bias current cancellation techniques will not
reduce the output DC offset for OPA3682. Since the two
input bias currents are unrelated in both magnitude and
polarity, matching the source impedance looking out of each
input to reduce their error contribution to the output is
ineffective. Evaluating the configuration of Figure 1, using
worst-case +25°C input offset voltage and the two input bias
currents, gives a worst-case output offset range equal to:

±(NG • V

OS(MAX)

) + (IBN • RS/2 • NG) ± (IBI • RF)

where NG = non-inverting signal gain
= ±(2 • 5.0mV) + (55µA • 25Ω • 2) ± (480Ω • 40µA)
= ±10mV + 2.8mV ± 19.2mV
= –26.4mV → +32.0mV

Minimizing the resistance seen by the non-inverting input
will give the best DC offset performance.

FIGURE 6. Noise Model.

4kT

R

G

R

G

R

F

R

S

OPA3682

I

BI

E

O

I

BN

4kT = 1.6E –20J

at 290°K

E

RS

E

NI

√4kTR

S

√4kTR

F

Eq.1

EO= E

NI

2

+ IBNR

S

()

2

+ 4kTR

S

()

NG2+ IBIR

F

()

2

+ 4kTRFNG

Eq. 2

EN= E

NI

2

+ IBNR

S

()

2

+ 4kTRS+

I

BIRF

NG







2

+

4kTR

F

NG

18

®

OPA3682

DISABLE OPERATION

The OPA3682 provides an optional disable feature that may
be used either to reduce system power or to implement a
simple channel multiplexing operation. If the DIS control
pin is left unconnected, the OPA3682 will operate normally.
To disable, the control pin must be asserted low. Figure 7
shows a simplified internal circuit for the disable control
feature.

The transition edge rate (dV/dt) of the DIS control line will
influence this glitch. For the plot of Figure 8, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
V

DIS

pin from a higher speed logic line. If extremely fast

transition logic is used, a 2kΩ series resistor between the
logic gate and the DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
DIS pin while still ensuring an adequate logic level swing.

THERMAL ANALYSIS

Due to the high output power capability of the OPA3682,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera­ture will set the maximum allowed internal power dissipa­tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175°C.

Operating junction temperature (TJ) is given by TA + PD •

θ

JA

.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at a
voltage equal to 1/2 either supply voltage (for equal bipolar
supplies). Under this condition PDL = V

S

2

/(4 • RL), where R

L

includes feedback network loading.
Note that it is the power in the output stage and not in the

load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an

OPA3682 in the circuit of Figure 1 operating at the maxi­mum specified ambient temperature of +85°C with all three
outputs driving a grounded 100Ω load to +2.5V:

PD = 10V • 19.8mA + 3 (52/(4 • (100Ω || 800Ω)) = 409mW
Maximum TJ = +85°C + (0.41W • 100°C/W) = 126°C
This worst-case condition is within the maximum junction

temperature. Normally, this extreme case will not be en­countered. Careful attention to internal power dissipation is
required.

In normal operation, base current to Q1 is provided through
the 110kΩ resistor while the emitter current through the
15kΩ resistor sets up a voltage drop that is inadequate to turn
on the two diodes in Q1’s emitter. As V

DIS

is pulled low,

additional current is pulled through the 15kΩ resistor even­tually turning on these two diodes (≈ 100µA). At this point,
any additional current pulled out of V

DIS

goes through those
diodes holding the emitter-base voltage of Q1 at approxi­mately zero volts. This shuts off the collector current out of
Q1, turning the amplifier off. The supply current in the
disable mode is only that required to operate the circuit of
Figure 7. Additional circuitry ensures that turn-on time
occurs faster than turn-off time (make-before-break).

When disabled, the output and input nodes go to a high
impedance state. If the OP A3682 is operating in a gain of +1,
this will show a very high impedance (4pF || 1MΩ) at the
output and exceptional signal isolation. If operating at a gain
greater than +1, the total feedback network resistance (RF +
RG) will appear as the impedance looking back into the
output but, the circuit will still show very high forward and
reverse isolation. If configured as an inverting amplifier, the
input and output will be connected through the feedback
network resistance (RF + RG) giving relatively poor input to
output isolation.

One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 8
shows these glitches for the circuit of Figure 1 with the input
signal set to zero volts. The glitch waveform at the output pin
is plotted along with the DIS pin voltage.

25kΩ 110kΩ

15kΩ

I

S

Control

–V

S

+V

S

V

DIS

Q1

FIGURE 7. Simplified Disable Control Circuit.

FIGURE 8. Disable/Enable Glitch.

40
20

0
–20
–40

Time (20ns/div)

Output Voltage (20mV/div)

Output Voltage

(0V Input)

V

DIS

0.2V

4.8V

19

®

OPA3682

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high frequency
amplifier like the OPA3682 requires careful attention to
board layout parasitics and external component types. Rec­ommendations that will optimize performance include:

a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the

output pin can cause instability: on the non-inverting input,
it can react with the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of the
ground and power planes around those pins. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.

b) Minimize the distance (< 0.25") from the power sup­ply pins to high frequency 0.1µF decoupling capacitors.

At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize inductance
between the pins and the decoupling capacitors. The power
supply connections (on pins 4 and 7) should always be
decoupled with these capacitors. An optional supply
decoupling capacitor across the two power supplies (for
bipolar operation) will improve 2nd harmonic distortion
performance. Larger (2.2µF to 6.8µF) decoupling capacitors,
effective at lower frequency , should also be used on the main
supply pins. These may be placed somewhat farther from the
device and may be shared among several devices in the same
area of the PC board.

c) Careful selection and placement of external compo­nents will preserve the high frequency performance of
the OPA3682. Resistors should be a very low reactance

type. Surface-mount resistors work best and allow a tighter
overall layout. Metal-film and carbon composition, axially­leaded resistors can also provide good high frequency per­formance. Again, keep their leads and PC board trace length
as short as possible. Never use wirewound type resistors in
a high frequency application. Other network components,
such as non-inverting input termination resistors, should also
be placed close to the package.

d) Connections to other wideband devices on the board
may be made with short direct traces or through on­board transmission lines. For short connections, consider

the trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50mils to 100mils)
should be used, preferably with ground and power planes
opened up around them. Estimate the total capacitive load
and set RS from the plot of recommended RS vs Capacitive
Load. Low parasitic capacitive loads (< 5pF) may not need
an RS since the OPA3682 is nominally compensated to
operate with a 2pF parasitic load. If a long trace is required,
and the 6dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a matched im­pedance transmission line using microstrip or stripline tech­niques (consult an ECL design handbook for microstrip and
stripline layout techniques). A 50Ω environment is normally
not necessary on board, and in fact, a higher impedance
environment will improve distortion as shown in the Distor-

tion vs Load plots. With a characteristic board trace imped­ance defined based on board material and trace dimensions,
a matching series resistor into the trace from the output of
the OPA3682 is used as well as a terminating shunt resistor
at the input of the destination device. Remember also that the
terminating impedance will be the parallel combination of
the shunt resistor and the input impedance of the destination
device: this total effective impedance should be set to match
the trace impedance. The high output voltage and current
capability of the OPA3682 allows multiple destination de­vices to be handled as separate transmission lines, each with
their own series and shunt terminations. If the 6dB attenua­tion of a doubly-terminated transmission line is unaccept­able, a long trace can be series-terminated at the source end
only. Treat the trace as a capacitive load in this case and set
the series resistor value as shown in the plot of RS vs
Capacitive Load. This will not preserve signal integrity as
well as a doubly-terminated line. If the input impedance of
the destination device is low, there will be some signal
attenuation due to the voltage divider formed by the series
output into the terminating impedance.

e) Socketing a high speed part like the OPA3682 is not
recommended. The additional lead length and pin-to-pin

capacitance introduced by the socket can create an ex­tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OP A3682
onto the board.

INPUT AND ESD PROTECTION

The OPA3682 is built using a very high-speed complemen­tary bipolar process. The internal junction breakdown volt­ages are relatively low for these very small geometry de­vices. These breakdowns are reflected in the Absolute Maxi­mum Ratings table. All device pins have limited ESD protec­tion using internal diodes to the power supplies as shown in
Figure 9.

These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with ±15V supply
parts driving into the OPA3682), current-limiting series
resistors should be added into the two inputs. Keep these
resistor values as low as possible since high values degrade
both noise performance and frequency response.

External

Pin

+V

CC

–V

CC

Internal
Circuitry

FIGURE 9. Internal ESD Protection.