The OM5234 and OM5284 single-chip 8-bit microcontrollers are
manufactured in an advanced CMOS process and are derivatives of
the 80C51 microcontroller family . The OM5234 and OM5284 are
pre-programmed devices for specific applications. Unless
specifically stated otherwise, all references to OM5234 apply equally
to OM5284.
The OM5234 contains a non-volatile 16k × 8 read-only program
memory, a volatile 256 × 8 read/write data memory, four 8-bit I/O
ports, two 16-bit timer/event counters (identical to the timers of the
80C51), a multi-source, two-priority-level, nested interrupt structure,
UART and on-chip oscillator and timing circuits.
FEA TURES
•80C51 central processing unit
•6k × 8 ROM
•256 × 8 RAM
•Two standard 16-bit timer/counters
•Four 8-bit I/O ports
•Full-duplex UART facilities
•Power control modes
– Idle mode
– Power-down mode
•ROM code protection
ORDERING INFORMATION
OM5234F T P
Device
OM5234
Frequency Range
F = 3.5 to 16MHz
I = 3.5 to 24MHz
T emperature Range
/
/ YYY
ROM code for application
5XX, etc.
Package designator
A = Plastic Leaded Chip Carrier
B = Plastic Quad Flat Package
Device
OM5284
Frequency Range
E = 3.5 to 16MHz
I = 3.5 to 24MHz
P = Plastic Dual In-Line Package
B = 0 to 70°C
PART NUMBER
TEMPERATURE RANGE °C
AND PACKAGE
OM5234/FBB/YYY0 to 70°C, Plastic Quad Flat Package16SOT307-2
OM5234/FBP/YYY0 to 70°C, Plastic Dual In-Line Package16SOT129-1
OM5234/FBA/YYY0 to 70°C, Plastic Leaded Chip Carrier16SOT187-2
OM5284EBYY0 to 70°C, Plastic Quad Flat Package16SOT307-2
OM5284EA YY0 to 70°C, Plastic Leaded Chip Carrier16SOT187-2
OM5284EPYY0 to 70°C, Plastic Dual In-Line Package16SOT129-1
OM5284 X Y ZZ
ROM code for application
01, 02, 03
Package designator
A = Plastic Leaded Chip Carier
B = Plastic Quad Flat Package
P = Plastic Dual In-Line Package
P0.0–0.743–36 37–3039–32I/OPort 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
P1.0–P1.72–940–44,
P1.6827I/OBidirectional I/O with internal pull-ups (OM5284), and open drain for (OM5234).
P1.7938I/OBidirectional I/O with internal pull-ups (OM5284), and open drain for (OM5234).
P2.0–P2.724–31 18–2521–28I/OPort 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
P3.0–P3.711,
RST1049IReset: A high on this pin for two machine cycles while the oscillator is running, resets the
ALE332730I/OAddress Latch Enable: Output pulse for latching the low byte of the address during an
PSEN322629OProgram Store Enable: Read strobe to external program memory via Port 0 and Port 2.
EA352931IExternal Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes
XTAL1211519ICrystal 1: Input to the inverting oscillator amplifier and input to the internal clock
XTAL2201418OCrystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V
226, 16,
28, 39
20IGround: 0V reference. With the QFP package, all VSS pins (V
connected.
SS1
to V
) must be
SS4
443840IPower Supply: This is the power supply voltage for normal, idle, and power-down
operation.
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory.
In this application, it uses strong internal pull-ups when emitting 1s.
1–8I/OPort 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7,
1–3
which are open drain for OM5234 (only). Port 1 pins that have 1s written to them are
pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that
are externally pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I
). Alternate functions include:
IL
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I
address byte during fetches from external program memory and during accesses to
). Port 2 emits the high-order
IL
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
10–17I/OPort 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have
13–195,7–13
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: I
the 80C51 family , as listed below:
). Port 3 also serves the special features of
IL
11510IRxD (P3.0): Serial input port
13711OTxD (P3.1): Serial output port
14812IINT0 (P3.2): External interrupt
15913IINT1 (P3.3): External interrupt
161014IT0 (P3.4): Timer 0 external input
171115IT1 (P3.5): Timer 1 external input
181216OWR (P3.6): External data memory write strobe
191317ORD (P3.7): External data memory read strobe
device. An internal diffused resistor to V
external capacitor to V
CC
.
permits a power-on reset using only an
SS
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency . Note that one ALE pulse is skipped during each access to
external data memory.
It is activated twice each machine cycle during fetches from the external program
memory. When executing out of external program memory, two activations of PSEN
skipped during each access to external data memory. PSEN
HIGH) during fetches from external program memory. PSEN
is not activated (remains
can sink/source 8 LSTTL
inputs and can drive CMOS inputs without external pull-ups.
out of the internal program memory ROM provided the Program Counter is less than
16384. If during a RESET, EA
program memory. EA
is held at TTL LOW level, the CPU executes out of external
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
= VSS + 0.5V; VIH = V
V
IL
2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
V
IH
3. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V
EA
4. 2V ≤ V
5. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
= V
–0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD; EA = RST = VSS.
DD
= RST = VSS.
≤ VDDmax.
PD
maximum value when V
6. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V . In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
7. Under steady state (non-transient) conditions, I
= 26mA total for Port 0; Maximum IOL = 15mA total for Ports 1, 2, and 3; Maximum IOL = 71mA total for all output pins. If IOL exceeds the
I
OL
test conditions, V
8. Capacitive loading on ports 0 and 2 may cause the V
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
OL
address bits are stabilizing.
9. I
for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. I
DDMAX
= 0°C to +70°C
amb
TESTLIMITS
8
1, 9
2, 9
3, 4
–0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VDD.
DD
is approximately 2V .
IN
must be externally limited as follows: Maximum IOL = 10mA per port pin; Maximum
OL
on ALE and PSEN to momentarily fall below the 0.9VDD specification when the
(1) MAXIMUM OPERATING MODE: V
(2) MAXIMUM IDLE MODE: VDD = V
These values are valid within the specified frequency range.
= V
DD
DDmax
DDmax
f
XTAL1
(MHz)
Figure 1. IDD vs. Frequency
50
I
DD
(mA)
40
30
20
10
0
0
(1) MAXIMUM OPERATING MODE: V
(2) MAXIMUM IDLE MODE: VDD = V
These values are valid within the specified frequency range.
4
81216
(1)
(2)
= V
DD
DDmax
DDmax
f
XTAL1
24
(MHz)
SU00801
AC ELECTRICAL CHARACTERISTICS
1, 2
16MHz CLOCKVARIABLE CLOCK
SYMBOLFIGUREPARAMETERMINMAXMINMAXUNIT
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
2High time
2Low time
2Rise time
2Fall time
3
3
3
3
2020t
2020t
2020ns
2020ns
CLCL –
CLCL –
t
t
LOW
HIGH
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN
= 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.
VCC–0.5
0.45V
NOTE:
AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.
1996 Nov 01
10
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