Page 1
NTE7134
Integrated Circuit
Horizontal and Vertical Deflection Controller
for Monitors
Description:
The NTE7134 is a high performance and efficient solution for autosync monitors in a 32–Lead DIP
type package. The concept is fully DC controllable and can be used in applications with a microcontroller and stand–alone in rock bottom solutions.
This device provides synchronization processing, H + V synchronization with full autosync capability ,
and very short setting times after mode changes. External power components are givena great deal
of protection. The IC generates the drive waveforms for DC–coupled vertical boosters.
The NTE7134 provides ectended functions e.g. as a flexible SMPS block and an extensive set of geometry control facilities, providing excellent picture quality.
Features:
Concept Features
D Full Horizontal (H) Plus Vertical (V) Autosync Capability
D Completely DC Controllable for Analog and Digital Concepts
D Excellent Geometry Control Functions (e.g. Automatic Correction of East–West (EW) Parabola
During Adjustment of Vertical Size and Vertical Shift)
D Felxible Switched Mode Power Supply (SMPS) Function Block for Feedback and Feed Forward
Converters.
D X–Ray Protection
D Start–Up and Switch–Off Sequences for safe Operation of All Power Components
D Very Good Vertical Linearity
D Internal Supply Voltage Stabilization
Synchronization Inputs
D Can Handle All Sync Signals (Horizontal, Vertical, Composite and Sync–On–Video)
D Combined Output for Video Clamping, Vertical Blanking and Protection Blanking
D Start of Video Clamping Pulses Externally Selectable
Horizontal Section
D Extremely Low Jitter
D Frequency Locked Loop for Smooth Catching of Line Frequrncy
D Simple Frequency Preset of f
D DC Controllable Wdie Range Linear Picture Position
D Soft Start for Horizontal Driver
Vertical Section
D Vertical Amplitude Independent of Frequency
D DC Controllable Picture Height, Picture Position and S–Correction
D Differential Current Outputs for DC Coupling to Vertical Booster
min
and f
by External Resistors
max
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Features (Cont’d):
EW Section
D Output for DC Adjustable EW Parabola
D DC Controllable Picture Width and Trapezium Correction
D Optional Tracking of EW Parabola with Line Frequency
D Prepared for Additional DC Controls of Vertical Linearity, EW–Corner, EW Pin Balance, EW
Parallelogram, Vertical Focus by Extended Application
Absolute Maximum Ratings: (All voltages measured with respect to GND)
Supply Voltage (Pin9), V
Input Voltages, V
I(n)
CC
–0.5 to +16V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin5 –0.5 to +6.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin15, Pin17, Pin18, Pin19, Pin23, Pin28, Pin30 –0.5 to +6.5V. . . . . . . . . . . . . . . . . . . . . . . .
Pin2 –0.5 to +8.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin10 –0.5 to +16V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltages, V
O(n)
Pin12, Pin13 –0.5 to +6.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin6, Pin7 –0.5 to +16V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Voltages, V
IO(n)
Pin3, Pin4 –0.5 to +6.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin14 –0.5 to +6.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Horizontal Driver Output Current, I
Horizontal Flyback Input Current, I
HDRV
HFLB
Video Clamping Pulse/Vertical Blanking Output Current, I
B+ Control OTA Output Current, I
B+ Control Driver Output Current, I
EW Driver Output Current, I
Electrostatic Discharge for All Pins (Note 1), V
BOP
BDRV
EWDRV
esd
CLBL
–10 to +10mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–10mA. . . . . . . . . . . . . . . . . . . . . . . .
50mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–5mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Machine Model ±400V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Human Body Model ±3000V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Junction Temperature, T
Operating Ambient Temperatrure Range, T
Storage Temperature Range, T
J
A
stg
Thermal Resistance, Junction–to–Ambient (In Free Air), R
–55° to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
thJA
+150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0° to +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55K/W. . . . . . . . . . . . . . . . . . . . . . . .
1mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. Machine model: 200pF, 25Ω, 2.5µH; Human body model: 100pF, 1500Ω, 7.5µH.
Electrical Characteristics: (VP = 12V, TA = +25°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Horizontal Sync Separator
Input Characteristics for DC–Coupled TTL Signals [HSYNC (Pin15)]
Sync Input Signal Voltage V
Slicing Voltage Level 1.2 1.4 1.6 V
Rise Time of Sync Pulse t
Fall Time of Sync Pulse t
Minimum Width of Sync Pulse t
Input Current I
DC(HSYNC)
r(HSYNC)
f(HSYNC)
W(HSYNC)
DC(HSYNC)VHSYNC
V
HSYNC
= 0.8V – – –200 µA
= 5.5V µA
1.7 – – V
10 – 500 ns
10 – 500 ns
0.7 – – µs
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Electrical Characteristics (Cont’d): (VP = 12V, TA = +25°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Horizontal Sync Separator (Cont’d)
Input Characteristics for AC–Coupled Video Signals (Sync–on–Video, Negative Sync Polarity)
Sync Amplitude of Video Input Signal
Voltage
Slicing Voltage Level
(Measured from Top Sync)
Top Sync Clamping Level V
Charge Current for Coupling Capacitor I
Minimum Width of Sync Pulse t
Maximum Source Resistance R
Differential Input Resistance r
Automatic Polarity Correction for Horizontal Sync
Horizontal Sync Pulse Width Related to t
Delay Time for Changing Polarity t
Vertical Sync Integrator
Integration Time for Generation of a
Vertical Trigger Pulse
Vertical Sync Slicer (DC–Coupled, TTL Compatible) [VSYNC (Pin14)]
Sync Input Signal Voltage V
Slicing Voltage Level 1.2 1.4 1.6 V
Input Current I
Vertical Sync Output at VSYNC (Pin14) During Composite Sync at HSYNC (Pin15)
Output Current I
Internal Clamping Voltage Level V
Steepness of Slopes – 300 – ns/mA
Automatic Polarity Correction for Vertical Sync
Maximum Width of Vertical Sync Pulse t
Delay for Change Polarity t
Video Clamping/Vertical Blanking Output [CLCB (Pin16)]
Width of Video Clamping Pulse t
Temperature Coefficient of V
clamp(CLCB)
Steepness of Slopes for Clamping Pulse RL = 1MΩ, CL = 20pF – 50 – ns/V
Top Voltage Level of Vertical
Blanking Pulse
Width of Vertical Blanking Pulse t
H
V
AC(HSYNC)
clamp(HSYNC)
C(HSYNC)
HSYNC(min)
S(max)
diff(HSYNC)
t
p(H)
t
H
p(H)
t
int(V)
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC(max)
d(VPOL)
clamp(CLBL)
TC
clamp
V
blank(CLBL)
blank(CLBL)
– 300 – mV
RS = 50Ω 90 120 150 mV
1.1 1.28 1.5 V
V
HSYNC
> V
clamp(HSYNC)
1.7 2.4 3.4 µA
0.7 – – µs
Duty factor = 7% – – 1500 Ω
During Sync – 80 – Ω
fH < 45kHz – – 20 %
fH > 45kHz – – 25 &
0.3 – 1.8 ms
fH = 31.45kHz,
I
= 1.052mA
HREF
fH = 64kHz,
I
= 2.141mA
HREF
fH = 100kHz,
I
= 3.345mA
HREF
7.0 10.0 13.0 µs
3.9 5.7 6.5 µs
2.5 3.8 4.5 µs
1.7 – – V
0V < V
< 5.5V – – ±10 µA
SYNC
During Internal Vertical Sync –0.7 –1.0 –1.35 mA
During Internal Vertical Sync 4.4 4.8 5.2 V
– – 300 µs
0.3 – 1.8 ms
Measured at V
= 3V 0.6 0.7 0.8 µs
CLBL
– +4 – mV/K
Note 2 1.7 1.9 2.1 V
240 300 360 µs
Note 2. Continuous blanking at CLCB (Pin16) will be activated, if one of the following conditions is true:
a) No horizontal flyback pulse at HFLB (Pin1) within a line
b) X–ray protection is triggered
c) Voltage at HPLL2 (Pin31) is low (for soft start of horizontal drive)
d) Supply voltage at VVV (Pin9) is low
e) PLL1 unlocked while frequency–locked loop is in search mode
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Electrical Characteristics (Cont’d): (VP = 12V, TA = +25°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Video Clamping/Vertical Blanking Output (Cont’d) [CLCB (Pin16)]
Temperature Coefficient of V
blank(CLBL)
Output Voltage During Vertical Scan V
Temperature Coefficient of V
scan(CLBL)
Internal Sink Current I
External Load Current I
Selection of Leading/Trailing Edge for Video Clamping Pulse
Voltage at CLSEL (Pin10) for Trigger with
Leading Edge of Horizontal Sync
Voltage at CLSEL (Pin10) for Trigger with
Trailing Edge of Horizontal Sync
Delay Between Leading Edge of
Horizontal Sync and Start of
Horizontal Clamping Pulse
Delay Between Leading Trailing of
Horizontal Sync and Start of
Horizontal Clamping Pulse
Maximum Duration of Video Clamping
Pulse After End of Horizontal Sync
Input Resistance at CLSEL (Pin10) R
PLL1 Phase Comparator and Frequency–Locked Loop [HPLL1 (Pin26) and HBUF (Pin27)]
Maximum Width of Horizontal Sync Pulse
(Referenced to Line Period)
Total Lock–In Time of PLL1 t
Control Voltage V
Buffered f/v Voltage at HBUF (Pin27) V
Maximum Load Current I
Adjustment of Horizontal Picture Position
Horizontal Shift Adjustment Range
(Referenced to Horizontal Period)
Input Current I
TC
blank
scan(CLBL)ICLBL
TC
scan
sink(CLBL)
load(CLBL)
V
CLSEL
t
d(clamp)
V
V
t
clamp(max)
V
V
CLSEL
t
HSYNC(max)fH
V
fH > 45kHz, Note 3 – – 25 %
lock(HPLL1)
HPLL1
HBUF
Note 4, Note 5
f
f
load(HBUF)
∆HPOS I
I
HPOS
∆HPOS = +10.5% –110 –120 –135 µA
∆H POS = –10.5% – 0 – µA
– +2 – mV/K
= 0 0.59 0.63 0.67 V
– –2 – mV/K
2.4 – – mA
– – –3.0 mA
7 – V
0 – 5 V
> 7V – 300 – ns
CLSEL
< 5V – 130 – ns
CLSEL
CLBL
CLBL
CLSEL
= 3V, V
= 3V, V
≤ V
CC
> 7V – – 0.15 µs
CLSEL
> 5V – – 1.0 µs
CLSEL
80 – – kΩ
< 45kHz, Note 2 – – 20 &
– 40 80 ms
, Note 6 – 5.6 – V
H(min)
, Note 6 – 2.5 – V
H(max)
– – –4.0 mA
= 0 – –10.5 – %
HSHIFT
= –135µA – +10.5 – %
HSHIFT
CC
V
Note 3. To ensure safe locking of the horizontal oscillator , one of the following procedures is required :
a) Search mode starts always from f
. Then the PLL1 filter components are a 3.3nF
min
capacitor from Pin26 to GND in parallel with an 8.2kΩ resistor in series with a 47nF
capacitor.
b) Search mode starts either from f
min
or f
with HPOS in m iddle position (I
max
HPOS
= 60µA).
Then the PLL1 filter components are a 1.5nF capacitor from Pin26 to GND in parallel
with a 27kΩ resistor in series with a 47nF capacitor.
c) After locking is achieved, HPOS can be operated in the normal way
Note 4. Loading of HPLL1 (Pin26) is not allowed.
Note 5. Oscillator frequency is f
when no sync signal is present (no continuous blanking at Pin16).
min
Note 6. V oltage at HPPL1 (Pin26) is fed to HBUF (Pin27) via a buffer. Disturbances caused by hori-
zontal sync are removed by an internal sample–and–hold circuit.
Page 5
Electrical Characteristics (Cont’d): (VP = 12V, TA = +25°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Adjustment of Horizontal Picture Position (Cont’d)
Reference Voltage at Input V
Picture Shift is Centered if
ref(HPOS)
V
off(HPOS)
HPOS (Pin30) is Forced to GND
Horizontal Oscillator [HCAP (Pin29) and HREF (Pin28)]
Free–Running Frequency Without PLL1
f
H(0)
Action (For Testing Only)
Spread of Free–Running Frequency
∆f
H(0)
(Excluding Spread of External
Components)
Temperature Coefficient of
TC –100 – +100 10–6/K
Free–Running Frequency
Maximum Oscillator Frequency f
Voltage at Input for Reference Current V
H(max)
HREF
PLL2 Phase Detector [HFLB (Pin1) and HPPL2 (Pin31)]
PLL2 Control (Advance of Horizontal
∆φ
PLL2
Drive with Respect to Middle of
Horizontal Flyback)
Delay Between Middle of Horizontal
t
d(HFLB)
Sync and Middle of Horizontal
Flyback
Maximum Voltage for PLL2 Protection
V
PROT(HPLL2)
Mode/Soft Start
Charge Current for External Capacitor
I
charge(HPLL2)VHPLL2
During Soft Start
Horizontal Flyback Input [HFLB (Pin1)]
Positive Clamping Level V
HFLB
Negative Clamping Level I
Positive Clamping Current I
HFLB
Negative Clamping Current – – –2 mA
Slicing Level V
HFLB
Output Stage for Line Driver Pulses [HDRV (Pin7)]
Open Collector Output Stage
Saturation Voltage V
Output Leakage Current I
HDRV
leakage(HDRV)VHDRV
Automatic Variation of Duty Factor
Relative t
Measured at V
HDRV Duty Factor is Determined by
HDRV Duty Factor is Determined by
the Relation I
Time of HDRV Output
OFF
= 3V,
HDRV
HREF/IVREF
t
HDRV(OFF)/tHIHDRV
Note 7 – 5.1 – V
0 – 0.1 V
R
= ∞, R
HBUF
C
= 10nF, Note 5
HCAP
HREF
= 2.4kΩ,
30.53 31.45 32.39 kHz
– – ±3.0 %
– – 130 kHz
2.43 2.55 2.68 V
Maximum Advance 36 – – %
Minimum Advance – 7 – %
HPOS (Pin30) Grounded – 200 – ns
– 4.4 – V
< 3.7V – 15 – µA
I
= 5mA – 5.5 – V
HFLB
= –1mA – –0.75 – V
HFLB
– – 6 mA
– 2.8 – V
I
= 20mA – – 0.3 V
HDRV
I
= 60mA – – 0.8 V
HDRV
= 16V – – 10 µA
= 20mA, fH = 31.45kHz 42.0 45.0 48.0 %
I
= 20mA, fH = 57kHz 45.0 46.3 47.7 %
HDRV
I
= 20mA, fH = 90kHz 46.6 48.0 49.4 %
HDRV
Note 5. Oscillator frequency is f
when no sync signal is present (no continuous blanking at Pin16).
min
Note 7. Input resistance at HPOS (Pin30):
R
HPOS
=
kT
q
x
1
I
HPOS
Page 6
Electrical Characteristics (Cont’d): (VP = 12V, TA = +25°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
X–Ray Protection [XRAY (Pin2)]
Slicing Voltage Level V
Minimum Width of Trigger Pulse t
Input Resistance at XRAY (Pin2) R
Supply Voltage for Reset of X–Ray Latch V
XRA Y
W(XRAY)
I(XRA Y)
RESET(VCC)
V
V
XRAY
XRAY
< 6.38V + V
> 6.38V + V
BE
BE
Vertical Oscillator (Oscillator Frequency in Application Without Adjustment of Free–Running Frequency f
Free–Running Frequency f
Vertical Frequency Catching Range f
V
v(o)
R
= 22kΩ,
VREF
C
= 100nF
VCAP
Constant Amplitude, Note 8,
Note 9, Note 10
Voltage at Reference Input for
V
VREF
Vertical Oscillator
Delay Between Trigger Pulsed and Start
t
d(scan)
of Ramp at VCAP (Pin24) (Width of
Vertical Blanking Pulse)
Control Currents of Amplitude Control I
External Capacitor at VAGC (Pin22) C
VAGC
VAGC
Differential Vertical Current Outputs
Adjustment of Vertical Size [VAMP (Pin18)]
Vertical Size Adjustment Range
(Referenced to Nominal Vertical Size)
Input Current for Max Amplitude (100%) I
∆VAMP I
VAMP
= 0, Note 11 – 60 – %
VAMP
I
= –135µA, Note 11 – 100 – %
VAMP
Input Current for Min Amplitude (60%) – 0 – µA
Reference Voltage at Input V
ref(V AMP)
Adjustment of Vertical Shift [VPOS (Pin17)]
Vertical Shift Adjustment Range
(Referenced to 100% Vertical Size)
Input Current for Max Shift–Up I
∆VPOS I
VPOS
= –135µA, Note 11 – –11.5 – %
VPOS
I
= 0, Note 11 – +11.5 – %
VPOS
Input Current for Max Shift–Down – 0 – µA
Reference Voltage at Input V
Vertical Shift is Centered of VPOS (Pin17)
ref(VPOS)
V
off(VPOS)
is Forced to GND
6.14 6.38 6.64 V
10 – µs
500 – – kΩ
– 5 – kΩ
– 5.6 – V
)
v(o)
40.0 42.0 43.3 Hz
50 – 110 Hz
– 3.0 – V
240 300 360 µs
±120 ±200 ±300 µA
– – 150 nF
–110 –120 –135 µA
– 5.0 – V
–110 –120 –135 µA
– 5.0 – V
0 – 0.1 V
Note 8. Full vertical sync range with constant amplitude (f
V(min)
: f
V(max)
= 1 : 2.5) can be made by
chosing an application with adjustment of free–running frequency.
Note 9. If higher vertical frequencies are reqiured, sync range can be shifted by using a smaller
capacitor at VCAP (Pin24).
Note10. Value of resistor at VREF (Pin23) may not be changed.
Note11. All vertical and EW adjustments are specified at nominal vertical settings, which means:
a) ∆VAMP = 100% (I
VAMP
= 135µA
b) ∆VSCOR = 0 (Pin19 Open–Circuit)
c) ∆VPOS centered (Pin17 forced to GND)
d) fH = 70kHz
Page 7
Electrical Characteristics (Cont’d): (VP = 12V, TA = +25°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Differential Vertical Current Outputs (Cont’d)
Adjustment of Vertical S–Correction [VSCOR (Pin19)]
Vertical S–Correction Adjustment Range ∆VSCOR I
I
Input Current for Max S–Correction I
VSCOR
Input Current for Min S–Correction – 0 – µA
Symmetry Error of S–Correction δVSCOR Maximum ∆VSCOR – – ±0.7 %
Reference Voltage at Input V
Voltage Amplitude of Superimposed
ref(VSCOR)
V
SAWM(p–p)
Note 12 – – 145 mV
Logarithmic Sawtooth
(Peak–to–Peak Value)
Vertical Output Stage [VOUT1 (Pin13) and VOUT2 (Pin12)]
Nominal Differential Output Current
∆I
VOUT(nom)
Nominal Settings, Note 11 0.76 0.85 0.94 mA
(Peak–to–Peak Value)
(|∆I
Maximum Differential Output Current
VOUT
| = I
VOUT1
– I
VOUT2
)
∆I
VOUT(max)
(Peak Value)
(|∆I
Allowed Voltage at Outputs V
Maximum Offset Error of Vertical
VOUT
| = I
VOUT1
– I
VOUT2
)
, V
VOUT1
δ
V(offset)
VOUT2
Nominal Settings, Note 11 – – ±2.5 %
Output Currents
Maximum Linearity Error of Vertical
δ
V(lin)
Nominal Settings, Note 11 ±1.5 %
Output Currents
EW Drive Output
EW Drive Output Stage [EWDRV (Pin11)]
Bottom Output Voltage
(Internally Stabilized)
V
EWDRV
V
V
EWTRP Centered
Maximum Output Voltage Note 13 7.0 – – V
Output Load Current I
Temperature Coefficient of Output Signal TC
EWDRV
EWDRV
Adjustment of EW Parabola Amplitude [EWPAR (Pin21)]
Parabola Amplitude V
PAR(EWDRV)
I
I
= 0, Note 11 – 2 – %
VSCOR
= –135µA, Note 11 – 46 – %
VSCOR
–110 –120 –135 µA
– 5.0 – V
0.47 0.52 0.57 mA
0 – 4.2 V
PAR(EWDRV)
DC(EWDRV)
= 0,
= 0,
1.05 1.20 1.35 V
– – ±2.0 mA
– – 600 10–6/K
= 0, Note 11 – 0.05 – V
EWPAR
= –135µA, Note 11 – 3 – V
EWPAR
Note11. All vertical and EW adjustments are specified at nominal vertical settings, which means:
a) ∆VAMP = 100% (I
VAMP
= 135µA
b) ∆VSCOR = 0 (Pin19 Open–Circuit)
c) ∆VPOS centered (Pin17 forced to GND)
d) fH = 70kHz
Note12. The superimposed logarithmic sawtooth at VSCOR (Pin19) tracks with VPOS, but not with
VAMP settings.
The superimposed waveform is described by
kT
q
x In
1 –d
1 + d
with ’d’ being the modulation
depth of a sawtooth from –5/6 to +5/6. A linear sawtooth with the same modulation depth can
be recovered in an external long–tail pair.
Note13. The output signal at EWDRV (Pin11) may consist of parabola + DC shift + trapezium correc-
tion. These adjustments have to be carried out in a correct relationship to each other to avoid
clipping due to the limited output voltage range at EWDRV.
Page 8
Electrical Characteristics (Cont’d): (VP = 12V, TA = +25°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
EW Drive Output (Cont’d)
Adjustment of EW Parabola Amplitude (Cont’d) [EWPAR (Pin21)]
Input Current for Maximum Amplitude I
EWPAR
Input Current for Minimum Amplitude – 0 – µA
Reference Voltage at Input V
ref(EWPAR)
Adjustment of Horizontal Size [EWWID (Pin32)]
EW Parabola DC Voltage Shift V
Input Current for Maximum DC Shift I
DC(EWDRV)
EWWID
I
EWWID
I
EWWID
= –135µA, Note 11 – 0.1 – V
= 0, Note 11 – 4.2 – V
Input Current for Minimum DC Shift –110 –120 –135 µA
Reference Voltage at Input V
ref(EWWID)
Adjustment of Trapezium Correction [EWTRP (Pin20)]
Trapezium Correction Voltage V
Input Current for Maximum Positive
TRP(EWTRP)IEWTRP
I
I
EWTRP
= 0, Note 11 – –0.5 – V
= –135µA, Note 11 – +0.5 – V
EWTRP
Trapezium Correction
Input Current for Maximum Negative
Trapezium Correction
Reference Voltage at Input V
Trapezium Correction is Centered if
ref(EWTRP)
V
off(EWTRP)
EWTRP (Pin20) is Forced to GND
Amplitude of Superimposed Logarithmic
V
PARM(p–p)
Note 14 – – 145 mV
Parabola (Peak–to–Peak Value)
Tracking of EWDRV Output Signal with fH Proportional Voltage
fH Range for Tracking f
Parabola Amplitude at EWDRV (Pin11) V
H(MUL TI)
PAR(EWDRV)
I
HREF
= 1.052mA,
FH = 31.45kHz, Note 15
I
= 2.341mA,
HREF
FH = 70kHz, Note 15
Function Disabled, Note 15 2.7 3.0 3.3 V
Linearity Error of fH Tracking δV
Voltage Range to Inhibit Tracking V
EWDRV
EWWID
B+ Control Section
Transconductance Amplifier [BIN (Pin5) and BOP (Pin3)]
Input Voltage V
Maximum Input Current I
BIN
BIN(max)
–110 –120 –135 µA
– 5.0 – V
– 0 – µA
– 5.0 – V
–110 –120 –135 µA
– 0 – µA
– 5.0 – V
0 – 0.1 V
24 – 80 kHz
1.30 1.45 1.60 V
2.7 3.0 3.3 V
– – 8 %
0 – 0.1 V
0 – 5.25 V
– – ±1 µA
Note11. All vertical and EW adjustments are specified at nominal vertical settings, which means:
a) ∆VAMP = 100% (I
VAMP
= 135µA
b) ∆VSCOR = 0 (Pin19 Open–Circuit)
c) ∆VPOS centered (Pin17 forced to GND)
d) fH = 70kHz
Note14. The superimposed logarithmic parabola at EWTRP (Pin20) tracks with VPOS, but not with
VAMP settings.
Note 15 . If fH tracking is enabled, the amplitude of the complete EWDRV output signal (parabola +
DC shift + trapezium) will be changed proportional to I
. The EWDRV low level of 1.2V
HREF
remains fixed.
Page 9
Electrical Characteristics (Cont’d): (VP = 12V, TA = +25°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
B+ Control Section (Cont’d)
Transconductance Amplifier (Cont’d) [BIN (Pin5) and BOP (Pin3)]
Reference Voltage at Internal
Non–Inverting Input of OTA
Minimum Output Voltage V
Maximum Output Voltage V
Maximum Output Current I
Transconductance of OTA g Note 16 30 50 70 mS
Open–Loop Gain G
Minimum Value of Capacitor at
BOP (Pin3)
Voltage Comparator [BSENS (Pin4)]
Voltage Range of Positive Comparator
Input
Voltage Range of Negative Comparator
Input
Maximum Leakage Current I
Open Collector Output Stage [BDRV (Pin6)]
Maximum Output Current I
Output Leakage Current I
Saturation Voltage V
Minimum Off–Time t
Delay Between BDRV Pulse and
HDRV Pulse (Rising Edges)
BSENS Discharge Circuit
Discharge Stop Level V
Discharge Current I
Threshold Voltage for Restart V
Minimum Value of Capacitor at
BSENS (Pin4)
Internal Reference, Supply Voltage and Protection
External Supply Voltage for Complete
Stabilization of All Internal
References
Supply Current I
Power Supply Rejection Ratio of
Internal Supply Voltage
V
ref(int)
BOP(min)
BOP(max)
BOP(max)
open
C
BOP
V
BSENS
V
BOP
BSENS
BDRV(max)
leakage(BDRV)
sat(BDRV)
off(min)
t
d(BDRV)
STOP(BSENS)
DISC(BSENS)
REST ART( BSENS)
C
BSENS
V
STAB( VCC)
VCC
I
< 1mA 5.0 5.3 5.6 V
BOP
Discharge Disabled – – –2 µA
V
= 16V – – 3 µA
BDRV
I
< 20mA – – 300 mV
BDRV
Measured at
V
HDRV
, V
BDRV
= 3V
Capacitive Load,
I
BSENS
V
= 0.5mA
> 2.5V 4.5 6.0 7.5 mA
BSENS
Fault Condition 1.2 1.3 1.4 V
2.37 2.50 2.58 V
– 0.4 – V
– ±500 – µA
– 86 – dB
4.7 – – nF
0 – 5 V
0 – 5 V
20 – – mA
– 250 – ns
– 500 – ns
0.85 1.0 1.15 V
2 – – nF
9.2 – 16 V
– 49 – mA
PSRR f = 1kHz 50 – – dB
Note16. First pole of the transconductance amplifier is 5MHz without an external capacitor (will be-
come the second pole, if the OTA operates as an integrator).
Page 10
Functional Description:
Horizontal Sync Separator and Polarity Correction
HSYNC (Pin 1 5 ) i s t h e i n p u t f o r h o r i z o n t a l synchronization signals, which can be DC–coupled TTL signals (horizontal or composite sync) and AC–coupled negative–going video sync signals. Video syncs
are clamped to 1.28V and sliced at 1.4V. This results in a fixed absolute slicing level of 120mV related
to sync top.
For DC–coupled TTL signals the input clamping current is limited. The slicing level for TTL signals
is 1.4V.
The separated sync signal (either video or TTL) is integrated on an internal capacitor to detect and
normalize the sync polarity.
Normalized horizontal sync pulses are used as input signals for the vertical sync integrator, the PLL1
phase detector and the frequency–locked loop.
Vertical Sync Integrator
Normalized composite sync signals from HSYNC are integrated on an internal capacitor in order to
extract vertical sync pulses. The integration time is dependent on the horizontal oscillator reference
current at HREF (Pin28). The integrator output directly triggers the vertical oscillator. This signal is
available at VSYNC (normally vertical sync input; Pin14), which is used as an output in this mode.
Vertical Sync Slicer and Polarity Correction
Vertical sync signals (TTL) applied to VSYNC (Pin14) are sliced at 1.4V. The output signal of the sync
slicer is integrated on an internal capacitor to detect and normalize the sync polarity.
If a composite sync signal is detected at HSYNC, VSYNC is used as output for the integrated vertical
sync (e.g. for power saving applications).
Video Clamping/Vertical Blanking Generator
The video clamping/vertical blanking signal at CLBL (Pin16) is a two–level sandcastle pulse which
is especially suitable for video ICs, but also for direct applications in video output stages.
The upper level is the video clamping pulse, which is triggered by the trailing edge of the horizontal
sync pulse. The width of the video clamping pulse is determined by an internal monoflop.
CLSEL (Pin10) is the selection input for the position of the video clamping pulse. If CLSEL is connected to GND, the clamping pulse is triggered with the trailing edge of horizontal sync. For a clamping
pulse which starts with the leading edge of horizontal sync, Pin10 must be connected to VCC.
The lower level of the sandcastle pulse is the vertical blanking pulse, which is derived directly from
the internal oscillator waveform. It is started by the vertical sync and stopped with the start of the vertical scan. This results in optimum vertical blanking.
Blanking will be activated continuously, if one of the following conditions is true:
No horizontal flyback pulses at HFLB (Pin1)
X–ray protection is activated
Soft start of horizontal drive (voltage at HPPL2 (Pin31) is low)
Supply voltage at VCC (Pin9) is low
PLL1 is unlocked while frequency–locked loop is in search mode
Blanking will not be activated if the horizontal sync frequency is below the valid range or there are no
sync pulses available.
Page 11
Functional Description (Cont’d):
Frequency–Locked Loop
The frequency–locked loop can lock the horizontal oscillator over a wide frequency range. This is
achieved by a combined search and PLL operation. The frequency range is preset by two external
resistors and the recommended ratio is
f
min
f
max
1
=
3.5
Larger ranges are possible by extended applications.
Without a horizontal sync signal the oscillator will be free–running at f
. Any change of sync condi-
min
tions is detected by the internal coincidence detector. A deviation of more than 4% between horizontal
sync and oscillator frequency switches the horizontal section into search mode. This means that PLL1
control currents are switched off immediately. Then the internal frequency detector starts tuning the
oscillator. Very small DC currents at HPLL1 (Pin26) are used to perform this tuning with a well defined
change rate. When coincidence between horizontal sync and oscillator frequency is detected, the
search mode is replaced by a normal PLL operation. This operation ensures a smooth tuning and
avoids fast changes of horizontal frequency during catching.
In this concept it is not allowed to load HPLL1. The frequency dependent voltage at this pin is fed internally to HBUF (Pin27) via a sample–and–hold and buffer stage. The sample–and–hold stage re-
moves all disturbances caused by horizontal sync or composite vertical sync from the buffered voltage. An external resistor from HBUF to HREF defines the frequency range.
See also hints for locking procedure in Note 2 of the “Electrical Characteristics” section of this data
sheet.
P
Phase Detector
LL1
The phase detector is a standard type using switched current sources. The middle of the horizontal
sync is compared with a fixed point of the oscillator sawtooth voltage. The PLL1 loop filter is connected
to HPLL (Pin26).
Horizontal Oscillator
This oscillator is a relaxation type and requires a fixed capacitor of 10nF at HCAP (Pin29). For optimum jitter performance the value of 10nF must not be changed.
The maximum oscillator frequency is determined by a resistor from HREF to GND. A resistor from
HREF to HBUF defines the frequency range.
The r eference c urr ent a t H R EF also defines t he i ntegration t im e c onstant o f t he v ertical s ync i ntegr ation.
Calculation of Line Frequency Range
First the oscillator frequencies f
spread of the relevant components to the highest and lowest sync frequencies f
oscillator is driven by the difference of the currents in R
quency R
due to the contribution of R
does not contribute to the spread. The spread will increase towards lower frequencies
HBUF
HBUF
The following example is a 31.45 to 64kHz application:
min
and f
have to be calculated. This is achieved by adding the
max
and R
HREF
. It is also dependent on the ratio
f
ns = = = 2.04
S(max)
f
HBUF
S(min)
and f
S(min)
S(max)
. At the highest oscillator fre-
f
S(max)
f
S(min)
64kHz
31.45kHz
. The
Table 1. Calculation of total spread
spread of: for f
max
for f
IC 3% 3%
C
HCAP
R
HREF
R
HREF
. R
HBUF
2% 2%
1% –
– 1% x (2.3 x ns –1)
Total 6% 8,69%
min
Page 12
Functional Description (Cont’d):
Calculation of Line Frequency Range (Cont’d)
Thus the typical frequency range of the oscillator in this example is:
f
= f
max
f
min
=
S(max)
f
The resistors R
R
R
HREF
HBUF
=
=
Where: n =
The spread of f
x 1.06 = 67.84kHz
S(min)
1.087
= 28.93kHz
HREF
74 x kHz x kΩ
f
[kHz]
max
R
HREF
x 1.19 x n
n – 1
f
max
= 2.35
f
min
increases with the frequency ratio
min
and R
can be calculated with the following formula:
HBUF
= 1.091kΩ
= 1.091kΩ
f
S(max)
f
S(min)
For higher ratios this spread can be reduced by using resistors with less tolerances.
P
Phase Detector
LL2
The PLL2 phase detector is similiar to the PLL1 detecrtor and compares the line flyback pulse at HFLB
(Pin1) with the oscillator sawtooth voltage. The PLL2 detector thus compensates for the delay in the
external horizontal deflection circuit by adjusting the phase of the HDRV (Pin7) output pulse.
The phase between horizontal flyback and horizontal sync can be controlled at HPOS (Pin30).
If HPLL2 is pulled to GND, horizontal output pulses, vertical output currents and B+ control pulses
are inhibited. This means, HDRV (Pin7), BDRV (Pin6) VOUT1 (Pin13) and VOUT2 (Pin12) are floating in this state. PLL2 and the frequency–locked loop are disabled, and CLCB (Pin16) provides a continuous blanking signal.
This option can be used for soft start, protection and power–down modes. When the HPLL2 voltage
is released again, an automatic soft start sequence will be performed.
The soft start timing is determined by the filter capacitor at HPLL2 (Pin31), which is charged with a
constant current during soft start. In the beginning the horizontal driver stage generates very small
output pulses. The width of thses pulses increases with the voltage at HPLL2 until the final duty factor
is reached. At this point BDRV (Pin6), VOUT1 (Pin13 and VOUT2 (Pin12) are re–enabled. The volt-
age at HPLL2 continues to rise until PLL2 enters its normal operating range. The internal charge current is now disabled. Finally PLL2 and the frequency–locked loop are enabled, and the continuous
blanking at CLBL is removed.
Horizontal Phase Adjustment
HPOS (Pin30) provides a linear adjustment of the relative phase between the horizontal sync and
oscillator sawtooth. Once adjusted, the relative pahse remains constant over the whole frequency
range.
Application hint: HPOS is a current input, which provides an internal reference voltage while I
HPOS
is in the specified adjustment current range, By grounding HPOS the symmetrical control range is
forced to its center value, therefore the pahse between horizontal sync and horizontal drive pulse is
only determined by PLL2.
Output Stage for Line Drive Pulses
An open collector output stage allows direct drive of an inverting driver transistor because of a low
saturation voltage of 0.3V at 20mA. To protect the line deflection transistor, the output stage is disabled (floating) for low supply voltage at VCC.
The duty factor of line drive pulses is slightly dependent on the actual line frequency. This ensures
optimum drive conditions over the whole frequency range.
Page 13
Functional Description (Cont’d):
X–Ray Protection
The X–ray protection input XRAY (Pin2) provides a voltage detector with a precise threshold. If the
input voltage at XRAY exceeds this threshold for a certain time, an internal latch switches the IC into
protection mode. In this mode several pins are forced into defined states:
Horizontal output stage (HDRV) is floating
B+ control driver stage (BDRV) is floating
Vertical output stages (VOUT1 and VOUT2) are floating
CLBL provides a continuous blanking signal
The capacitor connected to HPLL2 (Pin31) is discharged
To reset the latch and return to normal operation, VCC has to be temporaily switched off.
Vertical Oscillator and Amplitude Control
This stage is designed for fast stabilization of vertical amplitude after changes in sync frequency conditions. The free–running frequency f
and the capacitor C
connected to Pin24. The value of R
VCAP
is determined by the resistor R
osc(V)
VREF
connected to Pin23
VREF
is not only optimized for noise and
linearity performance in the whole vertical and EW section, but also influences several internal references, Therefore the value of R
must not be changed. capacitor C
VREF
should be used to select
VCAP
the free–running frequency of the vertical oscillator in accordance with the following formula:
fosc(V) =
10.8 x R
To achieve a stabilized amplitude the free–running frequency f
1
VREF
x C
VCAP
, without adjustment, should be
osc(V)
at least 10% lower than the minimum trigger frequency. The contributions shown in Table 2 can be
assumed.
Table 2. Calculation of f
total spreads
osc(V)
Contributing elements:
Minimum frequency offset between f
osc(V)
±10%
and lowest trigger frequency
Spread of IC ±3%
Spread of R
Spread of C
VREF
VCAP
±1%
±5%
Total 19%
Results for 50 to 110Hz application:
f
osc(V)
50Hz
= = 42Hz
1.19
Application hint: VAGC (Pin22) has a high input impedance during scan, thus the pin must not be
loaded externally. Otherwise non–linearities in the vertical output currents may occur due to the
changing charge current during scan.
Application hint: The full vertical sync range of 1 : 2.5 can be made usable by incorporating an adjustment of the free–running frequency. Also the complete sync range can be shifted to higher frequencies (e.g. 70 to 160Hz) by reducing the value of C
VCAP
.
Adjustment of Vertical Size, Vertical Shift and S–Correction
VPOS (Pin17) is the input for the DC adjustable vertical picture shift. This pin provides a phase shift
at the sawttoth output VOUT1 and VOUT2 (Pin13 and Pin12) and the EW drive output EWDRV
(Pin1 1) in such a way that the whole picture moves vertically while maintaining the correct geometry.
The amplitude of the differential output currents at VOUT1 and VOUT2 can be adjusted via input
V AMP (Pin18). This can be a combination of a DC adjustment and a dynamic waveform modulation.
VSCOR (pin19) is used to adjust the amount of vertical S–correction in the output signal.
Page 14
Functional Description (Cont’d):
Adjustment of Vertical Size, Vertical Shift and S–Correction (Cont’d)
The adjustments for vertical size and vertical shift also affect the wavweforms of the EW parabola and
the vertical S–correction. The result of this interaction is that no readjustment of these parameters
is necessary after an adjustment of vertical picture size or position.
Application hint: VPOS is a current input which provides an internal reference voltage while I
VPOS
is in the specified adjustment current range. By grounding VPOS (Pin17) the symmetrical control
range is forced to its center value.
Application hint: VSCOR is a current input at 5V. Superimposed on this level is a very small positive–going vertical sawtooth, intended to modulate an external long–tailed transistor pair. This enables further optional DC controls of functions which are not directly accessible such as vertical tilt
or vertical linearity.
EW Parabola (Including Horizontal Size and Trapezium Correction)
EWDRV (Pin11) provides a complete EW drive waveform. EW parabola amplitude, DC shift (horizontal size) and trapezium correction can be controlled via separate DC inputs.
EWPAR (Pin21) is used to adjust the parabola amplitude. This can be a combination of a DC adjustment and a dynamic waveform modulation.
The EW parabola amplitude also tracks with vertical picture size. The parabola waveform itself tracks
with the adjustment for vertical picture shift (VPOS).
EWWID (Pin32) offers two modes of operation:
Mode 1 Horizontal size is DC controlled via EWWID (Pin32) and causes a DC shift at the EWDRV
output. Also the complete waveform is multiplied internally by a signal proportional to the
line frequency (which is detected via the current at HREF (Pin28). This mode is to be used
for driving EW modulator stages which require a voltage proportional to the line frequency.
Mode 2 EWWID (Pin32) is grounded. Then EWDRV is no longer multiplied by the line frequency.
The DC adjustment for horizontal size must be added to the input of the B+ control amplifier
BIN (Pin5). This mode is to be used for driving EW modulations which require a voltage
independent of the line frequency.
EWTRP (Pin20 is used to adjust the amount of trapezium correction in the EW drive waveform.
Application hint: EWTRP (Pin20) is a current input at 5V. Superimposed on this level is a very small
vertical parabola with positive tips, intended to modulate an external long–tailed transistor pair . This
enables further optional DC controls of functions which are not directly accessible such as EW–corner, vertical focus or EW pin balance.
Application hint: By grounding EWTRP (Pin20) the symmetrical control range is forced to its center
value.
B+ Control Function Block
The B+ control function block of the EASDC consists of an Operatgional Transcondutance Amplifier
(OTA), a voltage comparator, a flip–flop and a discharge circuit. This configuration allows easy ap-
plications for different B+ control concepts.
General Description
The non–inverting input of the OTA is connected internally to a high precision reference voltage. The
inverting input is connected to BIN (Pin5). An internal clamping circuit limits the maximum positive
output voltage of the OTA. The output itself is connected to BOP (Pin3) and to the inverting inpuyt of
the voltage comparator. The non–inverting input of the voltage comparator can be accessed via
BSENS (Pin4).
Page 15
Functional Description (Cont’d):
B+ Control Function Block (Cont’d)
B+ drive pulses are generated by an internal flip–flop and fed to BDRV (Pin6) vai an open collector
output stage. This flip–flop will be set at the rising edge of the signal at HDRV (Pin7). The falling edge
of the output signal at BDRV has a defined delay of t
d(BDRV)
to the rising edge of the HDRV pulse.
When the voltage at BSENS exceeds the voltage at BOP, the voltage comparator output resets the
flip–flop and therefore, the open collector stage at BDRV is floating again.
An internal discharge circuit allows a well defined discharge of capacitors at BSENS. BDRV is active
at a low level output voltage thus, it requires an external inverting driver stage.
The B+ function block can be used for B+ deflection modulators in either of two modes:
D Feedback Mode
In this application the OTA is used as an error amplifier with a limited output voltage range. The
flip–flop will be set at the rising edge of the signal at HDRV. A reset will be generated when the
voltage at BSENS taken from the current sense resistor exceeds the voltage at BOP.
If not reset is generated within a line period, the rising edge of the next HDRV pulse forces the
flip–flop to reset. The flip–flop is set immediately after the voltage at BSENS has been dropped
below the threshold voltage V
RESTART(BSENS)
.
D Feed Forward Mode
This application uses an external RC combination at BSENS to provide a pulse width which is independent from the horizontal frequency. The capacitor is charged via an external resistor and discharged by the internal discharge circuit. For normal operation the discharge circuit is activated
when the flip–flop is reset by the internal voltage comparator. Now the capacitor will be discharged
with a constant current until the internally controlled stop level V
STOP(BSENS)
is reached. This level
will be maintained until the rising edge of the next HDR V pulse sets the flip–flop again and disables
the discharge circuit.
If no reset is generated within a line period, the rising edge of the next HDRV pulse automatically
starts the discharge sequence and resets the flip–flop. When the voltage at BSENS reaches the
threshold voltage V
RESTART(BSENS)
, the discharge circuit will be disabled automatically and the
flip–flop will be set immediately. This behaviour allows a definition of the maximum duty cycle of
the B+ control drive pulse by the relationship of charge current to discharge current.
Supply Voltage Stabilizer, Reference and Protection
The ASDC provides an internal supply voltage stabilizer for excellent stabilization of all internal references. An internal gap reference especially designed for low–noise is the reference for the internal
horizontal and vertical supply voltages. All internal reference currents and drive current for the vertical
output stage are derived from this voltage via external resistors.
A special protection mode has been implemented in order to protect the deflection stages and the
picture tube during start–up, shut–down and fault conditions. This protection mode can be activated
as shown in Table 3.
Table 3. Activation of protection mode
Activation Reset
Low Supply Voltage at Pin9 Increase Supply Voltage
X–Ray Protection XRAY (Pin2) Triggered Remove Supply Voltage
HPLL2 (Pin31) Pulled to GND Release Pin31
Page 16
Functional Description (Cont’d):
Supply Voltage Stabilizer, Reference and Protection (Cont’d)
When protection mode is active, several pins of the ASDC are forced into a defined state:
HDRV (Horizontal Driver Output) is floating
BDRV (B+ Control Driver Output) is floating
VOUT1 and VOUT2 (Vertical Outputs) are floating
CLBL provides a continuous blanking signal
The capacitor at HPLL2 is discharged
If the protection mode is activated via the supply voltage at Pin9, all thesae actions will be performed
in a well defined sequence. For activation via X–ray protection or HPLL2 all actions will occur simultaneously.
The return to normal operation is performed in accordance with the start–up sequence, if the reset
was caused by the supply voltage at Pin9. The first action with increasing supply voltage is the activation of continuous blanking at CLBL. When the threshold for activation of HDRV is passed, an internal
current begins to sharge the external capacitor at HPLL2 and PLL2 soft start sequence is performed.
In the beginning of this phase the horizontal driver stage generates very small output pulses. The
width of these pulses increases with the voltage at HPLL2 until the final duty cycle is reached. Then
the PLL2 voltage passes the threshold for activation of BDRV, VOUT1 and VOUT2.
For activation of these pins not only the PLL2 voltage, but also the supply voltage, must have passed
the appropriate threshold. A last pair of thresholds has to be passed by PLL2 voltage and supply voltage before the continuous blanking is finally removed, and the operation of PLL2 and frequency–
locked loop is enabled.
A return to the normal operation by releasing the voltage at HPLL2 will lead to a slightly different sequence. Here the activation of all functions is influenced only by the voltage at HPPL2.
Application hint: Internal discharge of the capacitor at HPLL2 will only be performed, if the protection mode was activated via the supply voltage or X–ray protection.
Page 17
Pin Connection Diagram
Horiz Flyback In
X–Ray Protection In
B+ Control OTA Out/Comparator In
B+ Control Comparator In/Out
B+ Control OTA In
B+ Control Driver Out
Horiz Driver Out
Power GND
V
CC
Selection In for Horiz Clamping Trigger
EW Parabola Out
Vert Output 2 (Ascending Sawttoth)
Vert Output 1 (Descending Sawtooth)
Vert Sync Input/Output (TTL Level)
Horiz/Composite Sync In
(TTL Level or SDync–On–Video)
Video Clamping Pulse/
Vert Blanking & Protection Out
1
2
3
4
5
6
7
8
32
31
30
29
28 Reference Current for Horiz Oscillator
27
26
25
10 23
11
12
13
14
22 External Cap for Vert Amplitude Control
21
20
19
16 17
Horiz Size In
External Filter for PLL2/Soft Start
Horiz Shift In
External Cap for Horiz Oscillator
Buffered f/v Voltage Out
External Filter for PLL1
Signal GND
External Cap for Vert Oscillator9 24
External Resistor for Vert Oscillator
EW Parabola Amplitude In
EW Trapezium Correction In
Vert S–Correction In
Vert Size In15 18
Vert Shift In
32
1
1.157 (29.4) Max
.070 ( 1.78)
1.050 (26.7)
17
16
.185 (4.7)
.110
(2.8)
Min
.358 (9.1)
Max
.480
(12.2)
Max
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