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NTE65101
Integrated Circuit
256 x 4–Bit Static Random Access Memory (SRAM)
Description:
The NTE65101 is a CMOS 1024–bit device organized in 256 words by 4 bits in a 22–Lead DIP type
package. This device offers ultra low power and fully static operation with a single 5V supply. Separate data inputs and data outputs permit maximum flexibility in bus–oriented systems. Data retention
at a power supply as low as 2V over temperature readily allows design into applications using battery
backup for nonvolatility. The NTE65101 is fully static and does not require clocking in standby mode.
Features:
D Organized as 256 Bytes of 4–Bits
D Static Operation
D Low Standby Power
D Three–State Output
D Single 5V Power Supply
D Data Retention to 2V
D TTL Compatible
D Maximum Access Time: 450ns
Absolute Maximum Ratings:
Supply Voltage, V
Input Voltage, V
Operating Temperature Range, T
Storage Temperature Range, T
Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum rated voltages to this high impedance circuit.
CC
in
(Voltages referenced to VSS Pin8)
A
stg
–0.5 to +7V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–0.3 to VCC +0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–40° to +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65° to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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DC Electrical Characteristics: (VCC = 5V ±5%, TA = 0° to +70°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Current I
Input High Voltage V
Input Low Voltage V
Output High Voltage V
Output Low Voltage V
Output Leakage Current I
Operating Current I
OH
LO
CC1
Note 3 – 5.0 – nA
in
IH
IL
IOH = –1mA 2.4 – – V
IOL = 2mA – – 0.4 V
OL
CE1 = 2.2V, VOL = 0V to VCC, Note 3 – – ±1.0 µA
Vin = VCC, except CE1 ≤ 0.65V,
Outputs open
I
CC2
Vin = 2.2V, except CE1 ≤ 0.65V,
Outputs open
Standby Current I
CCL
CE2 ≤ 0.2V, Note 3, Note 4 – – 10 µA
Note 2. Typical values are TA = +25°C and nominal voltage.
Note 3. Current through all inputs and outputs included in I
Note 4. Low current state is for CE2 = 0 only.
Capacitance:
Parameter Symbol Test Conditions Min Typ Max Unit
measurement.
CCL
2.2 – V
CC
–0.3 – 0.65 V
– 9.0 22 mA
– 13 27 mA
V
Input Capacitance C
Output Capacitance C
Vin = 0V – 4.0 8.0 pF
in
V
out
= 0V – 8.0 12.0 pF
out
Note 2. Typical values are TA = +25°C and nominal voltage.
Low V
VCC for Data Retention V
Data Retention Current I
Chip Deselect to Data Retention Time t
Operation Recovery Time t
Retention Characteristics: (TA = 0° to +70°C unless otherwise specified)
CC
Parameter Symbol Test Conditions Min Typ Max Unit
DR
CCDR1
CDR
CE2 ≤ 0.2V, VDR = 2V – 0.14 10 µA
Note 5 t
R
Note 2. Typical values are TA = +25°C and nominal voltage.
Note 5. t
AC Operating Conditions and Characteristics:
= Read Cycle Time.
RC
(Full operating voltage and temperature unless
otherwise specified)
AC Test Conditions:
Condition Value
2.0 – – V
0 – – ns
RC
– – ns
Input Pulse Levels +0.65V to 2.2V
Input Rise and Fall Times 20ns
Output Load – 1 TTL Gate and CL = 100pF
Timing Measurement Reference Level 1.5V
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AC Operating Conditions and Characteristics (Cont’d): (Full operating voltage and temperature
unless otherwise specified)
Read Cycle:
Parameter Symbol Min Max Unit
Read Cycle Time t
Access Time t
Read Cycle (Cont’d):
Parameter Symbol Min Max Unit
Address Setup Time t
Address Hold Time t
Chip Enable (CE1) to Output t
Chip Enable (CE2) to Output t
Output Disable to Output t
Data Output to High Z State t
Previous Read Data Valid with Respect to Address Change t
Previous Read Data Valid with Respect to Chip Enable t
Write Cycle:
Parameter Symbol Min Max Unit
RC
A
AS
AH
CO1
CO2
OD
DF
OH1
OH2
450 – ns
– 450 ns
20 – ns
0 – ns
– 400 ns
– 500 ns
– 250 ns
0 130 ns
0 – ns
0 – ns
Write Cycle t
Write Delay t
Chip Enable (CE1) to Write t
Chip Enable (CE2) to Write t
Data Setup t
Data Hold t
Write Pulse t
Write Recovery t
Output Disable Setup t
WC
AW
CW1
CW2
DW
DH
WP
WR
DS
Truth Table:
CE1 CE2 OD R/W D
in
H X X X X High Z Not Selected
X L X X X High Z Not Selected
X X H H X High Z Output Disable
L H H L X High Z Write
Output Mode
450 – ns
130 – ns
350 – ns
350 – ns
250 – ns
50 – ns
250 – ns
50 – ns
130 – ns
L H L L X D
L H L H X D
in
out
Write
Read
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Pin Connection Diagram
1
A3
A2
2
A1
3
A0
4
A5
5
A6
6
A7
7
GND
DI 1
DO 1
DI 2
8 15
9 14
10 13
11 12 DO 2
22 12
22
V
CC
A4
21
R/W
20
19
CE 1
18
OD
17 CD 2
DO 4
16
DI 4
DO 3
DI 3
.410
(11.41)
111
1.300 (33.0)
.400
(10.16)
.216
(5.5)
.100 (2.54)
.110 (2.79)
1.000 (25.4)
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