Page 1
NTD24N06L, STD24N06L
f
Power MOSFET
24 A, 60 V, Logic Level, N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
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Features
• S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
MAXIMUM RATINGS (T
Drain−to−Source Voltage V
Drain−to−Gate Voltage (RGS = 10 MW)
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tpv10 ms)
Drain Current
− Continuous @ T
− Continuous @ T
− Single Pulse (t
Total Power Dissipation @ T
Derate above 25°C
Total Power Dissipation @ T
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range TJ, T
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
(VDD = 50 Vdc, VGS = 5.0 Vdc,
L = 1.0 mH, IL(pk) = 18 A, VDS = 60 Vdc)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq. in. pad size.
2. When surface mounted to an FR4 board using minimum recommended pad
size.
= 25°C unless otherwise noted)
J
Rating
= 25°C
A
= 100°C
A
v10 ms)
p
= 25°C
A
= 25°C (Note 1)
A
= 25°C
J
Symbol Value Unit
stg
60 Vdc
60 Vdc
"15
"20
24
10
72
62.5
0.42
1.88
1.36
−55 to
+175
162 mJ
2.4
80
110
260 °C
Vdc
Adc
Apk
W
W/°C
W
W
°C
°C/W
V
V
V
E
R
R
R
DSS
DGR
GS
GS
I
I
I
DM
P
AS
q
q
q
T
D
D
D
JC
JA
JA
L
24 AMPERES, 60 VOLTS
R
DS(on)
G
A = Assembly Location*
Y = Year
WW = Work Week
24N6L = Device Code
G = Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 o
this data sheet.
= 0.036 W (Typ)
D
N−Channel
S
4
2
1
3
DPAK
CASE 369C
(Surface Mount)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
24
N6LG
AYWW
2
1
Gate
Drain
3
Source
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 4
1 Publication Order Number:
NTD24N06L/D
Page 2
NTD24N06L, STD24N06L
ELECTRICAL CHARACTERISTICS (T
Characteristic
= 25°C unless otherwise noted)
J
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(V
= 0 Vdc, ID = 250 mAdc)
GS
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
= 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
(V
DS
Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) I
V
(BR)DSS
I
DSS
GSS
60
−
71.9
69.6
−
−
mV/°C
mAdc
Vdc
−
−
−
−
1.0
10
− − ±100 nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
= VGS, ID = 250 mAdc)
(V
DS
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 3)
V
R
(VGS = 5.0 Vdc, ID = 10 Adc)
= 5.0 Vdc, ID = 12 Adc)
(V
GS
Static Drain−to−Source On−Resistance (Note 3)
V
(VGS = 5.0 Vdc, ID = 20 Adc)
= 5.0 Vdc, ID = 24 Adc)
(V
GS
(VGS = 5.0 Vdc, ID = 12 Adc, TJ = 150°C)
Forward Transconductance (Note 3) (VDS = 7.0 Vdc, ID = 12 Adc) g
GS(th)
DS(on)
DS(on)
FS
1.0
−
−
−
−
−
−
1.7
5.0
36
36
0.9
0.9
0.78
2.0
−
45
−
1.2
−
−
− 19 − mhos
Vdc
mV/°C
mW
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance C
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance C
C
iss
oss
rss
− 814 1140
− 258 360
− 80 115
pF
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
(V
= 30 Vdc, ID = 24 Adc,
Rise Time t
Turn−Off Delay Time t
DD
= 5.0 Vdc,
V
GS
= 9.1 W) (Note 3)
R
G
t
Fall Time t
Gate Charge
(VDS = 48 Vdc, ID = 24 Adc,
= 5.0 Vdc) (Note 3)
V
GS
d(on)
r
d(off)
f
Q
Q
Q
− 9.4 20
− 97 200
− 23 50
− 52 100
T
1
2
− 16 32
− 3.4 −
− 11 −
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
Reverse Recovery Time
Reverse Recovery Stored Charge Q
(IS = 20 Adc, VGS = 0 Vdc) (Note 3)
= 24 Adc, VGS = 0 Vdc)
(I
S
= 24 Adc, VGS = 0 Vdc, TJ = 150°C)
(I
S
(IS = 24 Adc, VGS = 0 Vdc,
dI
/dt = 100 A/ms) (Note 3)
S
V
SD
t
rr
t
a
t
b
RR
−
−
−
0.93
0.95
0.86
− 49 −
− 30 −
− 20 −
− 0.084 −
1.1
−
Vdc
−
ns
mC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
Device Package Shipping
NTD24N06LT4G DPAK
2500 / Tape & Reel
(Pb−Free)
STD24N06LT4G* DPAK
2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
†
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2
Page 3
NTD24N06L, STD24N06L
0
.8
0
50
40
VGS = 10 V
5 V
4.5 V
50
VDS ≥ 10 V
40
8 V
6 V
30
20
10
, DRAIN CURRENT (AMPS)
D
I
0
04
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
21
4 V
3.5 V
3 V
3
30
TJ = −55°C
20
10
, DRAIN CURRENT (AMPS)
D
I
0
1.6 2.4 4
, GATE−TO−SOURCE VOLTAGE (VOLTS)
V
GS
3.2 4
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
0.1
VGS = 10 V
0.08
0.06
TJ = 100°C
0.04
TJ = 25°C
0.02
, DRAIN−TO−SOURCE RESISTANCE (W)
DS(on)
R
0
0
10 40
TJ = −55°C
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
0.08
0.06
0.04
0.02
, DRAIN−TO−SOURCE RESISTANCE (W)
DS(on)
R
0.1
0
0
VGS = 5 V
TJ = 100°C
TJ = 25°C
TJ = −55°C
10 40
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source V oltage
3020
50
TJ = 25°C
3020
TJ = 100°C
5
2
ID = 12 A
= 5 V
V
1.8
GS
1.6
1.4
1.2
(NORMALIZED)
1
0.8
, DRAIN−TO−SOURCE RESISTANCE
0.6
DS(on)
−50 50250−25 75 125100
R
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
10000
1000
, LEAKAGE (nA)
100
DSS
I
1
150 175
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3
VGS = 0 V
TJ = 150°C
TJ = 100°C
0403020 6
10
50
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
versus Voltage
Page 4
NTD24N06L, STD24N06L
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
known as the plateau voltage, V
remains virtually constant at a level
GS
. Therefore, rise and fall
SGP
times may be approximated by the following:
t
= Q2 x RG/(VGG − V
r
tf = Q2 x RG/V
GSP
GSP
)
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q
and V
2
are read from the gate charge curve.
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(V
iss
In (VGG/V
iss
GG
GSP
− V
)
GSP
)]
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t
and is read at a voltage corresponding to the
d(on)
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
2800
2400
C
2000
1600
1200
C, CAPACITANCE (pF)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
iss
C
rss
800
400
0
55
10 0 10 15 20 25
V
VGS = 0 VVDS = 0 V
C
rss
GS
Figure 7. Capacitance Variation
V
DS
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4
TJ = 25°C
C
iss
C
oss
Page 5
NTD24N06L, STD24N06L
0
1000
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
6
Q
5
Q
1
4
3
2
1
0
0
GS
48 20
, TOTAL GATE CHARGE (nC)
Q
G
Figure 8. Gate−T o−Source and Drain−To−Source
V oltage versus Total Charge
T
Q
2
ID = 24 A
T
12
16
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
24
VGS = 0 V
= 25°C
T
20
J
V
GS
= 25°C
J
100
t, TIME (ns)
10
1
11010
t
r
t
f
t
d(off)
t
d(on)
RG, GATE RESISTANCE (OHMS)
VDS = 30 V
= 24 A
I
D
V
= 5 V
GS
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
16
12
8
4
, SOURCE CURRENT (AMPS)
S
I
0
0.6
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
0.68 0.76 1
0.84 0.92
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
) nor rated voltage (V
DM
transition time (t
r,tf
) do not exceed 10 ms. In addition the total
) is exceeded and the
DSS
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
− TC)/(R
).
JC
q
A Power MOSFET designated E−FET can be safely used
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
continuous current (I
), the energy rating is specified at rated
DM
), in accordance with industry c ustom.
D
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). M aximum e ner gy a t
currents below rated continuous I
D
equal the values indicated.
can safely be assumed to
in switching circuits with unclamped inductive loads. For
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5
Page 6
NTD24N06L, STD24N06L
E
100
I
, DRAIN CURRENT (AMPS)
5
180
SAFE OPERATING AREA
VGS = 15 V
SINGLE PULSE
T
= 25°C
C
10
100 ms
10 ms
1 ms
1
R
LIMIT
D
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
10 ms
0.1
0.1 1 100
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
10 17
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
1.0
D = 0.5
0.2
0.1
0.05
0.1
0.02
(NORMALIZED)
0.01
SINGLE PULSE
0.01
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
Figure 13. Thermal Response
dc
160
140
120
100
80
60
40
20
AVALANCHE ENERGY (mJ)
, SINGLE PULSE DRAIN−TO−SOURC
0
AS
E
P
(pk)
t
1
DUTY CYCLE, D = t1/t
t, TIME (ms)
ID = 18 A
25 50 75 100 125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
R
(t) = r(t) R
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
t
2
T
− TC = P
J(pk)
2
q
JC
(pk)
1.0E+00 1.0E+011.0E-011.0E-021.0E-031.0E-041.0E-05
1
R
(t)
q
JC
di/dt
I
S
t
rr
t
t
a
b
TIME
t
p
0.25 I
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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6
Page 7
L3
P
al
L4
b2
e
E
b3
4
12 3
TOP VIEW
A
B
D
NOTE 7
b
0.005 (0.13) C
DETAIL A
SIDE VIEW
NTD24N06L, STD24N06L
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE E
C
A
c2
Z
H
c
M
L2
BOTTOM VIEW
GAUGE
PLANE
L
DETAIL A
ROTATED 90 CW5
L1
H
A1
BOTTOM VIEW
ALTERNATE
CONSTRUCTION
SEATING
C
PLANE
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
3.00
0.118
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
Z
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
DIM MIN MAX MIN MAX
A 0.086 0.094 2.18 2.38
A1 0.000 0.005 0.00 0.13
b 0.025 0.035 0.63 0.89
b2 0.028 0.045 0.72 1.14
b3 0.180 0.215 4.57 5.46
c 0.018 0.024 0.46 0.61
c2 0.018 0.024 0.46 0.61
D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
H 0.370 0.410 9.40 10.41
L 0.055 0.070 1.40 1.78
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
L3 0.035 0.050 0.89 1.27
L4 −−− 0.040 −−− 1.01
Z 0.155 −−− 3.93 −−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
5.80
0.228
1.60
0.063
SCALE 3:1
6.17
0.243
ǒ
inches
mm
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/ Patent− Marking.pdf . S CILLC reserves t he right to m ake changes wit hout further notice to any products h erein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical e xperts. SCILLC does not convey any license under i ts p atent rights nor the rights of ot hers. S CILLC p roduct s a re n ot d esigned, i nt ended,
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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NTD24N06L/D
7
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