Datasheet NT5DS32M8AT-75B, NT5DS32M8AW-75B, NT5DS64M4AT-8B, NT5DS64M4AW-8B, NT5DS64M4AW-75B Datasheet (NANYA)

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Features

CAS Latency and Frequency

Maximum Operating Frequency (MHz)*

CAS Latency

2 133 100 100

2.5 143 133 125 * Values are nominal (exact tCK should be used).

• Double data rate architecture: two data transfers per clock cycle

• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver

• DQS is edge-aligned with data for reads and is centeraligned with data for writes

• Differential clock inputs (CK and CK)

DDR266A

(-7K)

DDR266B

(-75B)

DDR200

(-8B)

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• DLL aligns DQ and DQS transitions with CK transitions

• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

• Burst lengths: 2, 4, or 8

• CAS Latency: 2, 2.5

• Auto Precharge option for each burst access

• Auto Refresh and Self Refresh Modes

• 7.8µs Maximum Average Periodic Refresh Interval

• 2.5V (SSTL_2 compatible) I/O

• V

= 2.5V ± 0.2V

DDQ

• VDD = 2.5V ± 0.2V

• -7K parts support PC2100 modules.

-75B parts support PC2100 modules

-8B parts support PC1600 modules

Description

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for Writes.

The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going high and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.

The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.

An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.

The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access.

REV 1.1

12/2001

1

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Pin Configuration - 256Mb DDR SDRAM (x4 / x8)

V

NC

V

DDQ

NC

DQ0

V

SSQ

NC NC

V

DDQ

NC

DQ1

V

SSQ

NC NC

V

DDQ

NC NC

V

NU NC

WE

CAS RAS

CS NC

BA0 BA1

A10/AP

A0 A1 A2 A3

V

DD

V

DD

DQ0

V

DDQ

NC

DQ1

V

SSQ

NC

DQ2

V

DDQ

NC

DQ3

V

SSQ

NC NC

V

DDQ

NC NC

V

NU NC

WE

CAS RAS

CS

NC

BA0

BA1

A10/AP

A0 A1 A2 A3

V

DD

1 2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

33

39 38

37 36

35 34

66-pin Plastic TSOP-II 400mil

66 65

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

40

V

SS

DQ7 V

SSQ

NC DQ6 V

DDQ

NC DQ5 V

SSQ

NC DQ4 V

DDQ

NC NC V

SSQ

DQS NC V

REF

V

SS

DM* CK

CK CKE NC

A12 A11

A9 A8

A7 A6

A5 A4

V

SS

V

SS

NC V

SSQ

NC DQ3 V

DDQ

NC NC V

SSQ

NC DQ2 V

DDQ

NC NC V

SSQ

DQS NC V

REF

V

SS

DM* CK

CK CKE NC

A12 A11

A9 A8

A7 A6

A5 A4

V

SS

REV 1.1

12/2001

32Mb x 8

NT5DS32M8AT

64Mb x 4

NT5DS64M4AT

Column Address Table

Organization Column Address

64Mb x 4 A0-A9, A11 32Mb x 8 A0-A9

*DM is internally loaded to match DQ and DQS identically.

2

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package

See the balls through the package.

64 X 4

1

VSSQ

NC

2

VSS

3

A

7

VDD

8

NC

9

VDDQ

NC

VREF

1

VSSQ

NC

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

A8

A6

A4

2

DQ7

VDDQ

DQ3

NC

DQ2

DQS

DQM

CLK

CKE

A9

A7

A5

VSS

3

VSS

DQ6

B

C

D

E

F

G

H

J

K

L

M

32 X 8

A

B

DQ0

NC

DQ1

NC

WE

RAS

BA1

A0

A2

VDD

7

VDD

DQ1

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

CS

BA0

A10/AP

A1

A3

8

DQ0

VSSQ

NC

9

VDDQ

NC

REV 1.1

12/2001

NC

VREF

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

A8

A6

A4

DQ5

DQ4

DQS

DQM

CLK

CKE

A9

A7

A5

VSS

C

D

E

F

G

H

J

K

L

M

DQ2

DQ3

NC

WE

RAS

BA1

A0

A2

VDD

VDDQ

VSSQ

VDDQ

VDD

CAS

CS

BA0

A10/AP

A1

A3

NC

3

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Input/Output Functional Description

Symbol Type Function

CK, CK Input

CKE, CKE0, CKE1 Input

CS, CS0, CS1 Input

RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

DM Input

BA0, BA1 Input

A0 - A12 Input

DQ Input/Output Data Input/Output: Data bus.

DQS Input/Output

NC No Connect: No internal electrical connection is present. NU Electrical connection is present. Should not be connected at second level of assembly.

V

DDQ SSQ

DD

SS

REF

Supply DQ Power Supply: 2.5V ± 0.2V. Supply DQ Ground Supply Power Supply: 2.5V ± 0.2V. Supply Ground Supply SSTL_2 reference voltage: (V

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control of stacked devices.

Chip Select: All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. The standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in addition to CS0, to allow upper or lower deck selection on stacked devices.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. During a Read, DM can be driven high, low, or floated.

Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.

Address Inputs: Provide the row address for Active commands, and the column address and Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command.

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data.

/ 2) ± 1%.

DDQ

REV 1.1

12/2001

4

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Ordering Information

Part Number Org.

NT5DS64M4AT-7K x 4

NT5DS32M8AT-7K x 8 NT5DS64M4AT-75B x 4 NT5DS32M8AT-75B x 8

NT5DS64M4AT-8B x 4

NT5DS32M8AT-8B x 8

NT5DS64M4AW-7K x 4

NT5DS32M8AW-7K x 8 NT5DS64M4AW-75B x 4 NT5DS32M8AW-75B x 8

NT5DS64M4AW-8B x 4

NT5DS32M8AW-8B x 8

Note: At the present time, there are no plans to support DDR SDRAMs with the QFC function. All reference to QFC are for information.

CAS

Latency

2.5

Clock

(MHz)

143

133 100 DDR266B

125 100 DDR200

143

133 100 DDR266B

125 100 DDR200

CAS

Latency

2

Clock

(MHz)

133 DDR266A

Speed Package

66 pin TSOP-II

60 ball CSP

REV 1.1

12/2001

5

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Block Diagram (64Mb x 4)

CKE CK CK CS WE CAS RAS

A0-A12,

BA0, BA1

Command

Mode

Registers

15

Decode

Control Logic

13

Bank0

13

Row-Address MUX 13

2

Refresh Counter

2

Address Register

Column-Address

11

Counter/Latch

& Decoder

Row-Address Latch

Bank Control Logic

10

1

8192

(8192 x 1024 x 8) Sense Amplifiers

DM Mask Logic

Bank1

Bank0

Memory

Array

8192

I/O Gating

1024

(x8)

Column

Decoder

COL0

Bank2

Bank3

8

CK, CK

DLL

Data

8

4 4

Read Latch

COL0

Mask

Write

FIFO

&

8

Drivers

clk

in

out

Data

CK, CK

MUX

2

8

4

DQS

Generator

Input

Register

1 1 4

4

COL0

Drivers

1

DQS

1

1 4

4

Receivers

1

DQ0-DQ3, DM

DQS

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.

REV 1.1

12/2001

6

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Block Diagram (32Mb x 8)

CKE CK CK CS WE CAS RAS

A0-A12,

BA0, BA1

Command

Mode

Registers

15

Decode

Control Logic

13

8192

Bank0

13

Row-Address MUX 13

2

Refresh Counter

2

Address Register

Column-Address

10

Counter/Latch

& Decoder

Row-Address Latch

Bank Control Logic

9

1

Bank1

Bank0

Memory

Array

(8192 x 512 x 16)

Sense Amplifiers

8192

I/O Gating

DM Mask Logic

512

(x16)

Column

Decoder

COL0

Bank2

Bank3

16

CK, CK

DLL

Data

16

8 8

Read Latch

COL0

Mask

Write

FIFO

&

16

Drivers

clk

in

out

Data

CK, CK

MUX

2

16

8

DQS

Generator

Input

Register

1 1 8

8

COL0

Drivers

1

DQS

1

1 8

8

Receivers

1

DQ0-DQ7, DM

DQS

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.

REV 1.1

12/2001

7

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Functional Description

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access.

Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed infor-mation covering device initialization, register definition, command descriptions and device operation.

Initialization

Only one of the following two conditions must be met.

• No power sequencing is specified during power up or power down given the following criteria: VDD and VDDQ are driven from a single power converter output VTT meets the specification A minimum resistance of 42 ohms limits the input current from the VTT supply into any pin and VREF tracks VDDQ /2

or

• The following relationships must be followed: VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3V VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V

The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). Afterall power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command.

Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH. Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any read command. A Precharge ALL command should be applied, placing the device in the “all banks idle” state

Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.

DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a valid MRS command to either the base or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or extended mode register can be modified at any valid time during device operation without affecting the state of the internal address refresh counters used for device refresh.

REV 1.1

12/2001

8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Register Definition

Mode Register

The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing).

Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements results in unspecified operation.

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for

that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts.

REV 1.1

12/2001

9

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Mode Register Operation

BA1 BA0 A11 A10 A9

0* 0*

A12 - A9

0 0 0 Valid

0 1 0 Valid

0 0 1 VS**

A12

Operating Mode

A8 A7 A6 - A0 Operating Mode

Normal operation Do not reset DLL

Normal operation

in DLL Reset

Vendor-Specific

Test Mode

− − − Reserved

CAS Latency

A6 A5 A4 Latency

0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved

A8 A7 A6 A5 A4

CAS Latency

A3

A2 A1 A0 Burst Length

0 0 0 Reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved

A3 A2 A1 A0

Burst

Type 0 Sequential 1 Interleave

Burst Length

Address Bus

Burst LengthBT

Mode Register

VS** Vendor Specific

* BA0 and BA1 must be 0, 0 to select the Mode Register

(vs. the Extended Mode Register).

REV 1.1

12/2001

10

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Burst Definition

Burst Length

2

4

8

Starting Column Address Order of Accesses Within a Burst

A2 A1 A0 Type = Sequential Type = Interleaved

0 0-1 0-1

1 1-0 1-0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Notes:

1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.

2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.

3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition on page 11.

Read Latency

The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

REV 1.1

12/2001

11

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Operating Mode

The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode.

All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result.

CAS Latencies

CAS Latency = 2, BL = 4

CK CK

Command

DQS

DQ

CK CK

Command

DQS

DQ

Shown with nominal tAC, t

DQSCK

, and t

DQSQ

NOP NOP NOP NOP NOPRead

CL=2

NOP NOP NOP NOP NOPRead

.

CAS Latency = 2.5, BL = 4

CL=2.5

Don’t Care

REV 1.1

12/2001

12

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Extended Mode Register

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command can be issued. This is the reason for introducing timing parameter t mand). Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (t the DLL is enabled via self refresh exit command (t

, Exit Self Refresh to Non-Read Command).

XSNR

for DDR SDRAM’s (Exit Self Refresh to Read Com-

XSRD

) or 10 clocks after

MRD

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II.

QFC Enable/Disable

The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature for NTC and is not included on all DDR SDRAM devices. Refer to the DDR SDRAM Device Labeling Table for proper differentiation when ordering DDR devices with or without the QFC function. The QFC output is an open drain driver and must be connected to V is 150 ohms.

through a pull up resistor at the board level if the QFC function is enabled. The recommended pull up resistance

DDQ

REV 1.1

12/2001

13

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Extended Mode Register Definition

BA1 BA0

0* 1*

A12 - A3 A2 - A0 Operating Mode

* BA0 and BA1 must be 1, 0 to select the Extended Mode Register

(vs. the base Mode Register)

A

A11A10A

12

0 Valid Normal Operation

− −

All other states

A8A

9

Reserved

A

2

0 Disable

A6A5A

7

Operating Mode

QFC

A

4

A

3

2

QFC

Drive Strength

A

0 Normal 1 Reserved

Drive Strength

1

A

0

0 Enable 1 Disable

DLL

A1A

DS DLL

0

Address Bus Extended

Mode Register

REV 1.1

12/2001

14

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Commands

Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each commands follows.

Truth Table 1a: Commands

Name (Function) CS RAS CAS WE Address MNE Notes Deselect (Nop) H X X X X NOP 1, 9 No Operation (Nop) L H H H X NOP 1, 9 Active (Select Bank And Activate Row) L L H H Bank/Row ACT 1, 3 Read (Select Bank And Column, And Start Read Burst) L H L H Bank/Col Read 1, 4 Write (Select Bank And Column, And Start Write Burst) L H L L Bank/Col Write 1, 4 Burst Terminate L H H L X BST 1, 8 Precharge (Deactivate Row In Bank Or Banks) L L H L Code PRE 1, 5 Auto Refresh Or Self Refresh (Enter Self Refresh Mode) L L L H X AR / SR 1, 6, 7 Mode Register Set L L L L Op-Code MRS 1, 2

1. CKE is high for all commands shown except Self Refresh.

2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register.)

3. BA0-BA1 provide bank address and A0-A12 provide row address.

4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Precharge feature (nonpersistent), A10 low disables the Auto Precharge feature.

5. A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”

6. This command is auto refreshif CKE is high; Self Refresh if CKE is low.

7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts

9. Deselect and NOP are functionally interchangeable.

Truth Table 1b: DM Operation

Name (Function) DM DQs Notes

Write Enable L Valid 1

Write Inhibit H X 1

1. Used to mask write data; provided coincident with the corresponding data.

REV 1.1

12/2001

15

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Deselect

The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected.

No Operation (NOP)

The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

Mode Register Set

The mode registers are loaded via inputs A0-A12, BA0 and BA1 while issuing the Mode Register Set Command. See mode register descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until t

Active

The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank.

MRD

is met.

Read

The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent accesses.

Write

The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column location.

Precharge

The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.

REV 1.1

12/2001

16

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Auto Precharge

Auto Precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This is determined as if an explicit Precharge command was issued at the earliest possible time without violating t must not issue another command to the same bank until the precharge (tRP) is completed.

(min). The user

RAS

The NTC DDR SDRAM devices supports the optional t charge to be issued to a bank that has been activated (opened) but has not yet satisfied the t

lockout feature. This feature allows a Read command with Auto Pre-

RAS

(min) specification. The t

RAS

lockout feature essentially delays the onset of the auto precharge operation until two conditions occur. One, the entire burst length of data has been successfully prefetched from the memory array; and two, t

As a means to specify whether a DDR SDRAM device supports the t t

(RAS Command to Read Command with Auto Precharge or better stated Bank Activate to Read Command with Auto Pre-

RAP

charge). For devices that support the t Auto Precharge) to be issued to an open bank once t

t

Definition

RAP

CK CK

Command

DQ (BL=2)

NOP ACT NOP RD A NOP NOP NOP NOP ACT NOP NOP

lockout feature, t

RAS

RAP

(min) is satisfied.

RCD

t

RASmin

= t

lockout feature, a new parameter has been defined,

RAS

(min). This allows any Read Command (with or without

RCD

DQ0 DQ1

(min) has been satisfied.

RAS

t

RPmin

CL=2, tCK=10ns

*

Command

DQ (BL=4)

NOP ACT NOP RD A NOP NOP NOP NOP ACT NOP NOP

DQ0 DQ1 DQ2 DQ3

t

RPmin

*

Command

NOP ACT NOP RD A NOP NOP NOP NOP NOP ACT NOP

DQ (BL=8)

t

RCDmin

t

RAPmin

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

t

RPmin

*

Indicates Auto Precharge begins here

*

The above timing diagrams show the effects of t with Auto Precharge command (RDA) is issued with t Bank Activate command (ACT). The internal precharge operation, however, does not begin until after t

Burst Terminate

The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-cently registered Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Write burst cycles are not to be terminated with the Burst Terminate command.

REV 1.1

12/2001

for devices that support t

RAP

(min) and dataout is available with the shortest latency from the

RCD

17

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

lockout. In these cases, the Read

RAS

(min) is satisfied.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Auto Refresh

Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required.

The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8µs (maximum).

Self Refresh

The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are “Don’t Care” during Self Refresh operation.

The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for t any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.

because time is required for the completion of

XSNR

REV 1.1

12/2001

18

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Operations

Bank/Row Activation

Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued to that row, subject to the t mand to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive Active commands to the same bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive Active commands to different banks is defined by t

specification. A subsequent Active com-

RCD

.

RRD

Activating a Specific Row in a Specific Bank

CK CK

CKE

CS

RAS

CAS

WE

A0-A12

BA0, BA1 Don’t Care

HIGH

RA

BA

RA = row address. BA = bank address.

REV 1.1

12/2001

19

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

t

RCD

and t

RRD

CK CK

Definition

Command

A0-A12

BA0, BA1

ACT NOP

t

RRD

ACT NOP NOP

ROW

BA y BA yBA x

t

RCD

RD/WR

COLROW

NOP NOP

Don’t Care

Reads

Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command.

The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided t disabled.

During Read bursts, the valid data-out element from the starting column address is available following the CAS latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of CK and CK). The following timing figure entitled “Read Burst: CAS Latencies (Burst Length=4)” illustrates the general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS goes High-Z. Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure entitled “Consecutive Read Bursts: CAS Latencies (Burst Length =4 or 8)”. A Read command can be initiated on any positive clock cycle following a previous Read command. Nonconsecutive Read data is shown in timing figure entitled “Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)”. Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 25.

has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is

RAS

REV 1.1

12/2001

20

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Read Command

CK CK

CKE

CS

RAS

CAS

WE

x4: A0-A9, A11

x8: A0-A9

A10

BA0, BA1

HIGH

CA

EN AP

DIS AP

BA

CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge

Don’t Care

REV 1.1

12/2001

21

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Read Burst: CAS Latencies (Burst Length = 4)

CK CK

CAS Latency = 2

Command

Address

DQS

DQ

CK CK

Command

Address

DQS

DQ

NOP NOP NOP NOP NOPRead

BA a,COL n

CL=2

DOa-n

CAS Latency = 2.5

NOP NOP NOP NOP NOPRead

BA a,COL n

CL=2.5

DOa-n

DO a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, t

REV 1.1

12/2001

DQSCK

, and t

DQSQ

.

22

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Don’t Care

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)

CK CK

CAS Latency = 2

Command

Address

DQS

DQ

CK CK

Command

Address

DQS

DQ

NOP Read NOP NOP NOPRead

BAa, COL n BAa, COL b

CL=2

DOa-n

NOP Read NOP NOP NOPRead

BAa, COL n BAa,COL b

CL=2.5

DOa- n

DOa-b

CAS Latency = 2.5

DOa- b

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). When burst length = 4, the bursts are concatenated. When burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following DO a-n. 3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b. Shown with nominal tAC, t

REV 1.1

12/2001

DQSCK

, and t

DQSQ

Don’t Care

.

23

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)

CAS Latency = 2

CK CK

Command

Address

DQS

CK CK

Command

Address

DQS

DQ

NOP NOP Read NOP NOPRead

BAa, COL n BAa, COL b

CL=2

DQ

NOP NOP Read NOP NOPRead

BAa, COL n BAa, COL b

CL=2.5

DO a-n

DOa- b

CAS Latency = 2.5

NOP

DOa- b

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b). Shown with nominal tAC, t

REV 1.1

12/2001

DQSCK

, and t

DQSQ

.

24

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Don’t Care

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)

CK CK

CAS Latency = 2

Command

Address

DQS

DQ

CK CK

Command

Address

DQS

DQ

Read Read Read NOP NOPRead

BAa, COL n BAa, COL x BAa, COL b BAa, COL g

CL=2

DOa-n

Read Read Read NOP NOPRead

BAa, COL n BAa, COL x BAa, COL b BAa, COL g

CL=2.5

DOa-n

DOa-bDOa-n' DOa-x DOa-x' DOa-b’ DOa-g

CAS Latency = 2.5

DOa-bDOa-n' DOa-x DOa-x' DOa-b’

DO a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted). Reads are to active rows in any banks. Shown with nominal tAC, t

DQSCK

, and t

DQSQ

.

REV 1.1

12/2001

Don’t Care

25

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Data from any Read burst may be truncated with a Burst Terminate command, as shown in timing figure entitled Terminating a Read Burst: CAS Latencies (Burst Length = 8) on page 27. The Burst Terminate latency is equal to the read (CAS) latency, i.e.

the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data element pairs.

Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is necessary, the Burst Terminate command must be used, as shown in timing figure entitled Read to Write: CAS Latencies (Burst Length = 4 or 8) on page 28. The example is shown for t time. t

DQSS

(min) and t

(max) are defined in the section on Writes.

DQSS

A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge was not activated). The Precharge command should be issued x cycles after the Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure Read to Pre- charge: CAS Latencies (Burst Length = 4 or 8) on page 29 for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data elements.

In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts.

DQSS

(min). The t

(max) case, not shown here, has a longer bus idle

DQSS

REV 1.1

12/2001

26

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Terminating a Read Burst: CAS Latencies (Burst Length = 8)

CK CK

CAS Latency = 2

Command

Address

DQS

DQ

CK CK

Command

Address

DQS

DQ

NOP BST NOP NOP NOPRead

BAa, COL n

CL=2

DOa-n

No further output data after this point. DQS tristated.

CAS Latency = 2.5

NOP BST NOP NOP NOPRead

BAa, COL n

CL=2.5

DOa-n

DO a-n = data out from bank a, column n. Cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, t

REV 1.1

12/2001

DQSCK

, and t

DQSQ

No further output data after this point. DQS tristated.

.

Don’t Care

27

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Read to Write: CAS Latencies (Burst Length = 4 or 8)

CK CK

CAS Latency = 2

Command

Address

DQS

DQ

DM

CK CK

Command

Address

DQS

BST NOP Write NOP NOPRead

BAa, COL n BAa, COL b

CL=2 t

DOa-n

DI a-b

DQSS

(min)

CAS Latency = 2.5

BST NOP NOP Write NOPRead

BAa, COL n BAa, COL b

CL=2.5 t

DQSS

(min)

DQ

DM

DO a-n = data out from bank a, column n .

DI a-b = data in to bank a, column b 1 subsequent elements of data out appear in the programmed order following DO a-n. Data In elements are applied following Dl a-b in the programmed order, according to burst length. Shown with nominal tAC, t

REV 1.1

12/2001

DQSCK

, and t

DQSQ

.

28

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

DOa-n

Dla-b

Don’t Care

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Read to Precharge: CAS Latencies (Burst Length = 4 or 8)

CK CK

CAS Latency = 2

Command

Address

DQS

DQ

CK CK

Command

Address

DQS

NOP PRE NOP NOP ACTRead

BA a, COL n BA a or all

CL=2

NOP PRE NOP NOP ACTRead

BA a, COL n

BA a or all

CL=2.5

DOa-n

t

RP

BA a, ROW

CAS Latency = 2.5

t

RP

BA a, ROW

REV 1.1

12/2001

DQ

DOa-n

DO a-n = data out from bank a, column n. Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, t

DQSCK

, and t

DQSQ

.

29

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Don’t Care

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Writes

Write bursts are initiated with a Write command, as shown in timing figure Write Command on page 31. The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or dis-

abled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is disabled.

During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as the write postamble. The time between the Write command and the first corresponding rising edge of DQS (t with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e. t extremes of t

for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs

DQSS

(min) and t

(max)). Timing figure Write Burst (Burst Length = 4) on page 32 shows the two

DQSS

and DQS enters High-Z and any additional input data is ignored. Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous

flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). Timing figure Write to Write (Burst Length = 4) on page 33 shows concatenated bursts of 4. An example of nonconsecutive Writes is shown in timing figure Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) on page 34. Fullspeed random write accesses within a page or pages can be performed as shown in timing figure Random Write Cycles (Burst Length = 2, 4 or 8) on page 35. Data for any Write burst may be followed by a subsequent Read command. To follow a Write without truncating the write burst, t

(Write to Read) should be met as shown in timing figure Write to Read: Non-Interrupting

WTR

(CAS Latency = 2; Burst Length = 4) on page 36.

) is specified

DQSS

Data for any Write burst may be truncated by a subsequent (interrupting) Read command. This is illustrated in timing figures “Write to Read: Interrupting (CAS Latency =2; Burst Length = 8)”, “Write to Read: Minimum D Write), Interrupting (CAS Latency = 2; Burst Length = 8)”, and “Write to Read: Nominal D Burst Length = 8)”. Note that only the data-in pairs that are registered prior to the t

QSS

period are written to the internal array,

WTR

, Odd Number of Data (3 bit

QSS

, Interrupting (CAS Latency = 2;

and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously. Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write

burst, tWR should be met as shown in timing figure Write to Precharge: Non-Interrupting (Burst Length = 4) on page 40. Data for any Write burst may be truncated by a subsequent Precharge command, as shown in timing figures Write to Pre-

charge: Interrupting (Burst Length = 4 or 8) on page 41 to Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8) on page 43. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal

array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is met.

In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts.

REV 1.1

12/2001

30

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write Command

CK CK

CKE

CS

RAS

CAS

WE

x4: A0-A9, A11

x8: A0-A9

A10

BA0, BA1

HIGH

CA

EN AP

DIS AP

BA

CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge

Don’t Care

REV 1.1

12/2001

31

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write Burst (Burst Length = 4)

CK CK

Command

Address

DQS

DQ

DM

QFC

(Optional)

CK CK

Maximum D

T1 T2 T3 T4

NOP NOP NOPWrite

BA a, COL b

t

(max)

DQSS

Dla-b

t

(max) t

QCSW

QCHW

(min)

Minimum D

T1 T2 T3 T4

QSS

Command

Address

BA a, COL b

t

DQSS

(min)

NOP NOP NOPWrite

DQS

DQ

Dla-b

DM

QFC

QCSW

t

QCHW

(max)

t

(max)

DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. A10 is Low with the Write command (Auto Precharge is disabled). QFC is an open drain driver. Its output high level is achieved through an externally connected pull up resistor connected to V

Don’t Care

DDQ

.

REV 1.1

12/2001

32

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write to Write (Burst Length = 4)

CK CK

Command

Address

DQS

DQ

DM

CK CK

Maximum D

T1 T2 T3 T4 T5 T6

NOP Write NOP NOP NOPWrite

BAa, COL b BAa, COL n

t

(max)

DQSS

DI a-b DI a-n

Minimum D

T1 T2 T3 T4 T5 T6

QSS

Command

Address

DQS

DQ

DM

DI a-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 subsequent elements of data in are applied in the programmed order following DI a-n. A non-interrupted burst is shown. Each Write command may be to any bank.

BA, COL b BA, COL n

NOP Write NOP NOP NOPWrite

t

(min)

DQSS

DI a-b DI a-n

Don’t Care

REV 1.1

12/2001

33

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4)

T1 T2 T3 T4 T5

CK CK

Command

Address

DQS

DQ

DM

DI a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 subsequent elements of data in are applied in the programmed order following DI a-n. A non-interrupted burst is shown. Each Write command may be to any bank.

BAa, COL b

t

DQSS

NOP NOP Write NOPWrite

(max)

DI a-b

BAa, COL n

DI a-n

Don’t Care

REV 1.1

12/2001

34

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Random Write Cycles (Burst Length = 2, 4 or 8)

CK CK

Command

Address

DQS

DQ

DM

CK CK

Maximum D

T1 T2 T3 T4 T5

Write

BAa, COL b BAa, COL x BAa, COL n BAa, COL a BAa, COL g

t

DQSS

Write Write Write Write

(max)

DI a-b DI a-n

DI a-b’ DI a-x DI a-x’ DI a-n’ DI a-a DI a-a’

Minimum D

T1 T2 T3 T4 T5

QSS

Command

Address

Write

BAa, COL b BAa, COL x BAa, COL n BAa, COL a BAa, COL g

t

(min)

DQSS

Write Write Write Write

DQS

DQ

DI a-b DI a-nDI a-b’ DI a-x DI a-x’ DI a-n’ DI a-a DI a-a’

DM

DI a-b, etc. = data in for bank a, column b, etc. b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted). Each Write command may be to any bank.

DI a-g

Don’t Care

REV 1.1

12/2001

35

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)

CK CK

Command

Address

DQS

DQ

DM

CK CK

Maximum D

T1 T2 T3 T4 T5 T6

NOP NOP NOP ReadWrite

t

WTR

BAa, COL b BAa, COL n

t

DQSS

(max)

DI a-b

CL = 2

Minimum D

T1 T2 T3 T4 T5 T6

QSS

NOP

QSS

Command

Address

BAa, COL b

NOP NOP NOP ReadWrite NOP

t

(min)

DQSS

DQS

DQ

DI a-b

DM

DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. t

is referenced from the first positive CK edge after the last data in pair.

WTR

A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands may be to any bank.

t

WTR

BAa, COL n

CL = 2

Don’t Care

REV 1.1

12/2001

36

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)

CK CK

Command

Address

DQS

DQ

DM

Maximum D

T1 T2 T3 T4 T5 T6

NOP NOP NOP ReadWrite NOP

t

WTR

BAa, COL b

t

DQSS

(max)

DIa- b

BAa, COL n

CL = 2

1 1

Minimum D

T1 T2 T3 T4 T5 T6

QSS

CK CK

Command

Address

BAa, COL b

NOP NOP NOP ReadWrite NOP

t

(min)

DQSS

DQS

DQ

DM

DI a-b

1 1

DI a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b. t

is referenced from the first positive CK edge after the last data in pair.

WTR

The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = These bits are incorrectly written into the memory array if DM is low.

t

WTR

BAa, COL n

CL = 2

Don’t Care

REV 1.1

12/2001

37

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS Latency = 2; Burst Length = 8)

T1 T2 T3 T4 T5 T6

CK CK

Command

Address

DQS

DQ

DM

DI a-b = data in for bank a, column b. An interrupted burst is shown, 3 data elements are written.

2 subsequent elements of data in are applied in the programmed order following DI a-b. t

is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)

WTR

The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank.

1 = This bit is correctly written into the memory array if DM is low. 2 = These bits are incorrectly written into the memory array if DM is low.

BAa, COL b

NOP NOP NOP ReadWrite NOP

t

(min)

DQSS

DI a-b

1 2 2

t

WTR

BAa, COL n

CL = 2

Don’t Care

REV 1.1

12/2001

38

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)

T1 T2 T3 T4 T5 T6

CK CK

Command

Address

DQS

DQ

DM

DI a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b. t

is referenced from the first positive CK edge after the last desired data in pair.

WTR

The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = These bits are incorrectly written into the memory array if DM is low.

BAa, COL b

NOP NOP NOP ReadWrite NOP

t

(nom)

DQSS

DI a-b

t

WTR

BAa, COL n

CL = 2

11

Don’t Care

REV 1.1

12/2001

39

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write to Precharge: Non-Interrupting (Burst Length = 4)

CK CK

Command

Address

DQS

DQ

DM

Maximum D

T1 T2 T3 T4 T5 T6

NOP NOP NOP NOPWrite

t

WR

BA a, COL b

t

(max)

DQSS

DI a-b

Minimum D

T1 T2 T3 T4 T5 T6

QSS

PRE

BA (a or all)

QSS

t

RP

CK CK

Command

Address

BA a, COL b

NOP NOP NOP NOPWrite PRE

t

(min)

DQSS

DQS

DQ

DI a-b

DM

DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown.

tWR is referenced from the first positive CK edge after the last data in pair. A10 is Low with the Write command (Auto Precharge is disabled).

t

WR

BA (a or all)

Don’t Care

t

RP

REV 1.1

12/2001

40

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write to Precharge: Interrupting (Burst Length = 4 or 8)

CK CK

Command

Address

DQS

DQ

DM

CK CK

Command

Maximum D

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

t

WR

BA a, COL b BA (a or all)

t

(max)

DQSS

DI a-b

33

2

1 1

Minimum D

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

QSS

t

RP

QSS

Address

REV 1.1

12/2001

t

WR

BA a, COL b

t

DQSS

(min)

2

DQS

DQ

DM

DI a-b

1 1

33

DI a-b = data in for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following DI a-b. tWR is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst, for burst length = 8. A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = These bits are incorrectly written into the memory array if DM is low.

41

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

BA (a or all)

t

RP

Don’t Care

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting (Burst Length = 4 or 8)

T1 T2 T3 T4 T5 T6

CK CK

Command

Address

BA a, COL b BA (a or all)

NOP NOP NOP PREWrite NOP

t

WR

t

(min)

DQSS

DQS

DQ

DM

DI a-b = data in for bank a, column b. An interrupted burst is shown, 1 data element is written. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = This bit is correctly written into the memory array if DM is low. 4 = These bits are incorrectly written into the memory array if DM is low.

DI a-b

3 4 4

2

1 1

t

RP

Don’t Care

REV 1.1

12/2001

42

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)

T1 T2 T3 T4 T5 T6

CK CK

Command

Address

BA a, COL b

NOP NOP NOP PREWrite NOP

t

WR

BA (a or all)

t

(nom)

DQSS

DQS

DQ

DM

DI a-b = Data In for bank a, column b. An interrupted burst is shown, 2 data elements are written.

1 subsequent element of data in is applied in the programmed order following DI a-b. tWR is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point.

3 = These bits are incorrectly written into the memory array if DM is low.

DI a-b

33

2

1

t

RP

1

Don’t Care

REV 1.1

12/2001

43

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Precharge Command

CK CK

CKE

CS

RAS

CAS

WE

A0-A9, A11, A12

A10

BA0, BA1

HIGH

All Banks

One Bank

BA

BA = bank address (if A10 is Low, otherwise Don’t Care).

Don’t Care

Precharge

The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) is available for a subsequent row access some specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank.

REV 1.1

12/2001

44

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Power-Down

Power-down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the DLL prior to entering Power-down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur before a Read command can be issued. In Power Down mode, CKE Low and a stable clock signal must be maintained at the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. However, power-down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled power-down mode.

The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). A valid, executable command may be applied one clock cycle later.

Power Down

CK CK

CKE

Command

t

IS

VALID NOP VALID

No column

access in

progress

Enter Power Down mode

(Burst Read or Write operation

must not be in progress)

t

IS

NOP

Exit

power down

mode

Don’t Care

REV 1.1

12/2001

45

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Truth Table 2: Clock Enable (CKE)

1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. Command n is the command registered at clock edge n, and action n is a result of command n.

4. All states and sequences not shown are illegal or reserved.

CKE n-1 CKEn

Current State

Self Refresh L L X Maintain Self-Refresh

Self Refresh L H Deselect or NOP Exit Self-Refresh 1 Power Down L L X Maintain Power-Down Power Down L H Deselect or NOP Exit Power-Down

All Banks Idle H L Deselect or NOP Precharge Power-Down Entry All Banks Idle H L Auto Refresh Self Refresh Entry

Bank(s) Active H L Deselect or NOP Active Power-Down Entry

H H

Current

Cycle

See “Truth Table 3: Current State

Bank n - Command to Bank n (Same

Command n Action n Notes

Bank)” on page 47

1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.

) period. A minimum of

XSNR

REV 1.1

12/2001

46

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)

Current State CS RAS CAS WE Command Action Notes

Any

Idle

Row Active

Read

(Auto Precharge

Disabled)

Write

(Auto Precharge

Disabled)

H X X X Deselect NOP. Continue previous operation 1-6

L H H H No Operation NOP. Continue previous operation 1-6 L L H H Active Select and activate row L L L H Auto Refresh L L L L Mode Register Set L H L H Read Select column and start Read burst L H L L Write Select column and start Write burst L L H L Precharge Deactivate row in bank(s) L H L H Read Select column and start new Read burst L L H L Precharge Truncate Read burst, start Precharge L H H L Burst Terminate Burst Terminate L H L H Read Select column and start Read burst L H L L Write Select column and start Write burst L L H L Precharge Truncate Write burst, start Precharge

1-6, 10, 11

1-6 1-7

1-7 1-6, 10 1-6, 10

1-6, 8

1-6, 10

1-6, 8 1-6, 9

1-6, 10

1-6, 8, 11

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t met (if the previous state was self refresh).

2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and t

progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle

state.

Row Activating: Starts with registration of an Active command and ends when t

active” state.

Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been

met. Once tRP is met, the bank is in the idle state.

Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been

met. Once tRP is met, the bank is in the idle state.

Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these

states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.

5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when t

in the “all banks idle” state.

Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when t

met, the DDR SDRAM is in the “all banks idle” state.

Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle

state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.

9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.

10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled.

11. Requires appropriate DM masking.

has been met. No data bursts/accesses and no register accesses are in

RCD

is met. Once t

RCD

RFC

is met. Once t

is met, the bank is in the “row

RCD

MRD

XSNR / tXSRD

is met, the DDR SDRAM is

RFC

has been met. Once t

has been

is

MRD

REV 1.1

12/2001

47

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

(Part 1 of 2)

Current State CS RAS CAS WE Command Action Notes

Any

Idle X X X X

Row Activating,

Active, or

Precharging

Read

(Auto Precharge

Disabled)

Write

(Auto Precharge

Disabled)

H X X X Deselect NOP/continue previous operation 1-6

L H H H No Operation NOP/continue previous operation 1-6

Any Command Otherwise

Allowed to Bank m L L H H Active Select and activate row 1-6 L H L H Read Select column and start Read burst 1-7 L H L L Write Select column and start Write burst 1-7 L L H L Precharge 1-6 L L H H Active Select and activate row 1-6 L H L H Read Select column and start new Read burst 1-7 L L H L Precharge 1-6 L L H H Active Select and activate row 1-6 L H L H Read Select column and start Read burst 1-8 L H L L Write Select column and start new Write burst 1-7 L L H L Precharge 1-6

1-6

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and t

Row Active: A row in the bank has been activated, and t

in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See note 10. Write with Auto Precharge Enabled: See note 10.

4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.

5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled.

8. Requires appropriate DM masking.

9. A Write command may be applied after the completion of data output.

10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The

access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands

to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).

has been met.

RP

RCD

has been met. No data bursts/accesses and no register accesses are

XSNR / tXSRD

has been

REV 1.1

12/2001

48

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

(Part 2 of 2)

Current State CS RAS CAS WE Command Action Notes

L L H H Active Select and activate row 1-6

Read (With

Auto Precharge)

Write (With

Auto Precharge)

L H L H Read Select column and start new Read burst 1-7,10 L H L L Write Select column and start Write burst 1-7,9,10 L L H L Precharge 1-6 L L H H Active Select and activate row 1-6 L H L H Read Select column and start Read burst 1-7,10 L H L L Write Select column and start new Write burst 1-7,10 L L H L Precharge 1-6

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and t

Row Active: A row in the bank has been activated, and t

in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See note 10. Write with Auto Precharge Enabled: See note 10.

4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.

5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled.

8. Requires appropriate DM masking.

9. A Write command may be applied after the completion of data output.

10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The

access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands

to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).

has been met.

RP

RCD

has been met. No data bursts/accesses and no register accesses are

XSNR / tXSRD

has been

REV 1.1

12/2001

49

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Simplified State Diagram

Power

Applied

Power

On

Precharge

Preall

MRS

EMRS

Write

Active

Power

Down

MRS

CKEL

Write

CKEH

Write A

Idle

ACT

Row

Active

CKEH

Read A

Read

REFS

REFSX

REFA

CKEL

Read

Self

Refresh

Precharge

Power

Down

Burst Stop

Read

Auto

Refresh

REV 1.1

12/2001

Write A

Write

A

PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh

PRE

Precharge

Preall

50

Read A

Read

A

Read

PRE

CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

A

Automatic Sequence

Command Sequence

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Absolute Maximum Ratings

Symbol Parameter Rating Units

VIN, V

V

DDQ

T

STG

P

I

OUT

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Voltage on I/O pins relative to V

OUT

Voltage on Inputs relative to V

IN

Voltage on VDD supply relative to V

DD

Voltage on V Operating Temperature (Ambient) 0 to +70 °C

A

Storage Temperature (Plastic) −55 to +150 °C Power Dissipation 1.0 W

D

Short Circuit Output Current 50 mA

supply relative to V

DDQ

SS

−0.5 to V

+ 0.5 V

DDQ

−0.5 to +3.6 V

REV 1.1

12/2001

51

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Capacitance

Parameter Symbol Min. Max. Units Notes

Input Capacitance: CK, CK CI

1

Delta Input Capacitance: CK, CK delta CI Input Capacitance: All other input-only pins (except DM) CI

2

Delta Input Capacitance: All other input-only pins (except DM) delta CI Input/Output Capacitance: DQ, DQS, DM C Delta Input/Output Capacitance: DQ, DQS, DM delta C

1. V

= VDD = 2.5V ± 0.2V (minimum range to maximum range), f = 100MHz, TA = 25°C, VODC = V

DDQ

2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is

IO

2.0 3.0 pF 1

1

0.25 pF 1

2.0 3.0 pF 1

2

0.5 pF 1

4.0 5.0 pF 1, 2

0.5 pF 1

, VO

DDQ/2

Peak -Peak

=0.2V.

required to match input propagation times of DQ, DQS and DM in the system.

DC Electrical Characteristics and Operating Conditions

(0°C ≤ T

≤ 70°C; V

A

= 2.5V ± 0.2V, V

DDQ

= + 2.5V ± 0.2V, see AC Characteristics)

DD

Symbol Parameter Min Max Units Notes

V

DDQ

VSS, V

V

REF

V

IH(DC)

V

IL(DC)

V

IN(DC)

V

ID(DC)

VI

Ratio

I

OH

I

OHW

I

OLW

OZ

OL

Supply Voltage 2.3 2.7 V 1

DD

I/O Supply Voltage 2.3 2.7 V 1 Supply Voltage

SSQ

I/O Supply Voltage I/O Reference Voltage 0.49 x V I/O Termination Voltage (System) V

TT

Input High (Logic1) Voltage V Input Low (Logic0) Voltage − 0.3 V Input Voltage Level, CK and CK Inputs − 0.3 V Input Differential Voltage, CK and CK Inputs 0.30 V

0 0 V

DDQ

− 0.04 V

REF

+ 0.15 V

REF

0.51 x V

DDQ

+ 0.04 V 1, 3

REF

+ 0.3 V 1

DDQ

− 0.15 V 1

REF

+ 0.3 V 1

DDQ

+ 0.6 V 1, 4

DDQ

V-I Matching Pullup Current to Pulldown Current Ratio 0.71 1.4 5 Input Leakage Current

I

Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V) Output Leakage Current

(DQs are disabled; 0V ≤ V

out

≤ V

DDQ

Output Current: Nominal Strength Driver High current (V Low current (V

= V

OUT

DDQ

= 0.373V, max V

OUT

-0.373V, min V , max VTT)

REF

Output Current: Half- Strength Driver High current (V Low current (V

= V

OUT

DDQ

= 0.763V, max V

OUT

-0.763V, min V , max VTT)

REF

, min VTT)

− 5 5 µA 1

− 16.8

16.8

− 9.0

9.0

V 1, 2

mA 1

1. Inputs are not recognized as valid until V

2. V

is expected to be equal to 0.5 V

REF

noise on V

may not exceed ± 2% of the DC value.

REF

3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to V must track variations in tHalf-he DC level of V

4. VID is the magnitude of the difference between the input level on CK and the input level on CK.

stabilizes.

REF

of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

DDQ

.

REF

5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-ture and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.

REV 1.1

12/2001

52

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

, and

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Normal Strength Driver Pulldown and Pullup Characteristics

1. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve.

2. It is recommended that the “typical” IBIS pulldown V-I curve lie within the shaded region of the V-I curve.

Normal Strength Driver Pulldown Characteristics

140

Maximum

Typical High

(mA)

OUT

I

Typical Low Minimum

0

V

(V)

OUT

3. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve.

4. It is recommended that the “typical” IBIS pullup V-I curve lie within the shaded region of the V-I curve.

2.70

Normal Strength Driver Pullup Characteristics

0

Minimum Typical Low

(mA)

OUT

I

Typical High

-200

Maximum

2.70

V

(V)

OUT

5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltages from 0.1 to 1.0.

6. The full variation in the ratio of the “typical” IBIS pullup to “typical” IBIS pulldown current should be unity + 10%, for device drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed.

7. These characteristics are intended to obey the SSTL_2 class II standard.

8. This specification is intended for DDR SDRAM only.

REV 1.1

12/2001

53

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Normal Strength Driver Pulldown and Pullup Currents

Pulldown Current (mA) Pullup Current (mA)

Voltage (V)

0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0

0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0

0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8

0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8

0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8

0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4

0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8

0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5

0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3

1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2

1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0

1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6

1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1

1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5

1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0

1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4

1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7

1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2

1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5

2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9

2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2

2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6

2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0

2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3

2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6

2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9

2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2

Typical

Low

Typical

High

Min Max

Typical

Low

Typical

High

Min Max

Normal Strength Driver Evaluation Conditions

Typical Minimum Maximum

25 °C 70 °C 0 °C

2.5V 2.3V 2.7V

typical process slow-slow process fast-fast process

54

REV 1.1

12/2001

Temperature (T

V

DDQ

Process conditions

ambient

)

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.

4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to V

(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels

REF

under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between V V

.

IH(AC)

IL(AC)

and

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input low (high) level.

AC Output Load Circuit Diagrams

V

TT

Output (V

OUT

50Ω

)

Timing Reference Point

30pF

REV 1.1

12/2001

55

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

DQS/DQ/DM Slew Rate

DDR266A

Parameterl Symbol

DCS/DQ/DM

input slew rate

1. Measured between V IH (DC), V IL (DC), and V IL (DC), V IH (DC).

2. DQS, DQ, and DM input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-sition through the DC region must be monotonic..

DC

SLEW

(-7K)

Min Max Min Max Min Max

TBD TBD TBD TBD 0.5 4.0

DDR266B

(-75B)

DDR200

(-8B)

Unit Notes

V/ns

1,2

REV 1.1

12/2001

56

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

AC Input Operating Conditions (0 °C ≤ T

≤ 70 °C; V

A

= 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC

DDQ

Characteristics)

Symbol Parameter/Condition Min Max Unit Notes

V

IH(AC)

V

IL(AC)

V

ID(AC)

V

IX(AC)

Input High (Logic 1) Voltage, DQ, DQS, and DM Signals V

+ 0.31 V 1, 2

REF

Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals V Input Differential Voltage, CK and CK Inputs 0.62 V Input Crossing Point Voltage, CK and CK Inputs 0.5*V

− 0.2 0.5*V

DDQ

− 0.31 V 1, 2

REF

+ 0.6 V 1, 2, 3

DDQ

+ 0.2 V 1, 2, 4

DDQ

1. Input slew rate = 1V/ns.

2. Inputs are not recognized as valid until V

stabilizes.

REF

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of VIX is expected to equal 0.5*V

IDD Specifications and Conditions (0 °C ≤ T

of the transmitting device and must track variations in the DC level of the same.

DDQ

≤ 70 °C; V

A

= 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC

DDQ

Characteristics)

Symbol Parameter/Condition

Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM, and

I

DD0

DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle

Operating Current: one bank; active / read / precharge; Burst = 2; tRC = tRC

I

DD1

I

DD2P

I

DD2N

I

DD3P

(min); CL = 2.5; I cycle

= 0mA; address and control inputs changing once per clock

OUT

Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ V

IL

(max)

Idle Standby Current: CS ≥ VIH (min); all banks idle; CKE ≥ VIH (min); address and control inputs changing once per clock cycle

Active Power-Down Standby Current: one bank active; power-down mode; CKE ≤ V

IL

(max)

Active Standby Current: one bank; active / precharge; CS ≥ VIH (min);

I

DD3N

CKE ≥ VIH (min); tRC = t clock cycle; address and control inputs changing once per clock cycle

(max); DQ, DM, and DQS inputs changing twice per

RAS

Operating Current: one bank; Burst = 2; reads; continuous burst; address and

I

DD4R

control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; I

OUT

= 0mA

Operating Current: one bank; Burst = 2; writes; continuous burst; address and

I

DD4W

I

DD5

I

DD6

control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL = 2.5

Auto-Refresh Current: tRC = t

(min) 160 170 mA 1

RFC

Self-Refresh Current: CKE ≤ 0.2V 2 2 mA 1, 2 Operating current: four bank; four bank interleaving with BL = 4, address and

I

DD7

control inputs randomly changing; 50% of data changing at every transfer; t RC = t RC (min); I OUT = 0mA.

DDR200

(8B)

tCK=10ns

75 85 mA 1

90 110 mA 1

15 15 mA 1

30 35 mA 1

15 15 mA 1

50 60 mA 1

130 165 mA 1

115 150 mA 1

TBD TBD mA 1

DDR266A/B

(7K/75B)

tCK=7.5ns

Unit Notes

1. IDD specifications are tested after the device is properly initialized.

2. Enables on-chip refresh and address counters.

REV 1.1

12/2001

57

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications

(0 °C ≤ TA ≤ 70 °C; V

= 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)

DDQ

Symbol Parameter

t

DQ output access time from CK/CK − 0.75 + 0.75 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4

AC

t

DQSCK

DQS output access time from CK/CK − 0.75 + 0.75 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4

t

CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 t

CH

t

CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 t

CL

t

CK

Clock cycle time

t

CK

t

DQ and DM input hold time 0.5 0.5 0.6 ns

DH

t

DQ and DM input setup time 0.5 0.5 0.6 ns

DS

t

DQ and DM input pulse width (each input) 1.75 1.75 2 ns 1-4

DIPW

t

Data-out high-impedance time from CK/CK − 0.75 + 0.75 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4, 5

HZ

t

Data-out low-impedance time from CK/CK − 0.75 + 0.75 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4, 5

LZ

t

DQSQA

t

DQSL,H

t

WPRES

t t

DQS-DQ skew (DQS & associated DQ signals) + 0.5 + 0.5 + 0.6 ns 1-4

DQSQ

DQS-DQ skew (DQS & all DQ signals) + 0.5 + 0.5 + 0.6 ns 1-4

minimum half clk period for any given cycle;

t

HP

defined by clk high (tCH) or clk low (tCL) time

t

Data output hold time from DQS

QH

Write command to 1st DQS latching

DQSS

transition DQS input low (high) pulse width (write cycle) 0.35 0.35 0.35 t

t

DQS falling edge to CK setup time (write cycle) 0.2 0.2 0.2 t

DSS

t

DQS falling edge hold time from CK (write cycle) 0.2 0.2 0.2 t

DSH

t

Mode register set command cycle time 14 15 16 ns 1-4

MRD

Write preamble setup time 0 0 0 ns 1-4, 7 Write postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK1-4, 6

WPST

Write preamble 0.25 0.25 0.25 t

WPRE

Address and control input hold time

t

IH

(fast slew rate) Address and control input setup time

t

IS

(fast slew rate)

Address and control input hold time

t

IH

(slow slew rate)

Address and control input setup time

t

IS

(slow slew rate)

DDR266A

(-7K)

DDR266B

(-75B)

DDR200

(-8B)

Unit Notes

Min Max Min Max Min Max

1-4

CK

1-4

CK

CL = 2.5 7 12 7.5 12 8 12 ns 1-4

CL = 2.0

7.5 12 10 12 10 12 ns 1-4

10 12

1-4,

15,16

1-4,

15,16

t

CH

or

t

CL

tHP-

0.75ns

0.75 1.25 0.75 1.25 0.75 1.25 t

0.9 0.9 1.1 ns

t

CH

or

t

CL

tHP-

0.75ns

t

CH

or

t

CL

tHP-1.0ns t

t

1-4

CK

1-4

CK

1-4

CK

1-4

CK

1-4

CK

1-4

CK

1-4

CK

2-4,

9,11,12

2-4,

9,11,12

2-4,

1.0 1.0 1.1 ns

11,12,

14

2-4,

1.0 1.0 1.1 ns

11,12,

14

REV 1.1

12/2001

58

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications

(0 °C ≤ TA ≤ 70 °C; V

= 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)

DDQ

Symbol Parameter

t

Input pulse width 2.2 2.2 ns 2-4, 12

IPW

t t

Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 t

RPRE

Read postamble 0.40 0.60 0.40 0.60 0.40 0.60 t

RPST

t

Active to Precharge command 45 120,000 45 120,000 50 120,000 ns 1-4

RAS

t

Active to Active/Auto-refresh command period 65 65 70 ns 1-4

RC

Auto-refresh to Active/Auto-refresh

t

RFC

command period

t

Active to Read or Write delay 20 20 20 ns 1-4

RCD

t

Active to Read Command with Autoprecharge 20 20 20 ns 1-4

RAP

t

Precharge command period 20 20 20 ns 1-4

RP

t

Active bank A to Active bank B command 15 15 15 ns 1-4

RRD

t

Write recovery time 15 15 15 ns 1-4

WR

Auto precharge write recovery

t

DAL

+ precharge time

t

Internal write to read command delay 1 1 1 t

WTR

Exit self-refresh to non-read command 75 75 80 ns 1-4

XSNR

Exit self-refresh to read command 200 200 200 t

XSRD

t

Average Periodic Refresh Interval 7.8 7.8 7.8 µs 1-4, 8

REFI

DDR266A

(-7K)

DDR266B

(-75B)

DDR200

(-8B)

Unit Notes

Min Max Min Max Min Max

CK

75 75 80 ns 1-4

(tWR/t (tRP/t

CK)

+

CK)

(tWR/t (tRP/t

CK)

+

CK)

(tWR/t

(tRP/t

CK)

+

CK)

tCK1-4,13

CK

1-4 1-4

1-4

REV 1.1

12/2001

59

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Electrical Characteristics & AC Timing for DDR266 - Applicable Specifications Expressed in Clock Cycles (0 °C ≤ T

Symbol Parameter

t

MRD

t

WPRE

t

t t

t

WTR

t

XSNR

t

XSRD

Mode register set command cycle time 2 t Write preamble 0.25 t Active to Precharge command 6 16000 t

RAS

t

Active to Active/Auto-refresh command period 9 t

RC

Auto-refresh to Active/Auto-refresh

RFC

command period Active to Read or Write delay 3 t

RCD

Active to Read Command with Autoprecharge 3 t

RAP

t

Precharge command period 3 t

RP

Active bank A to Active bank B command 2 t

RRD

Write recovery time 2 t

WR

Auto precharge write recovery + precharge time 5 t

DAL

Internal write to read command delay 1 t Exit self-refresh to non-read command 10 t Exit self-refresh to read command 200 t

≤ 70 °C; V

A

= 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

DDQ

t

= 7.5ns

CK

Units Notes

Min Max

CK

10 t

CK

1-4 1-4 1-4 1-4

1-4

1-4 1-4 1-4 1-4 1-4 1-5 1-4 1-4 1-4

1. Input slew rate = 1V/ns

2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is V

3. Inputs are not recognized as valid until V

REF.

stabilizes.

REF

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT.

5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

REV 1.1

12/2001

60

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications Notes

1. Input slew rate = 1V/ns.

2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF.

3. Inputs are not recognized as valid until VREF stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT .

5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred

to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were prev iously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on t DQSS .

8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.

9. For command/address input slew rate ≥ 1.0V/ns. Slew rate is measured between V OH (AC) and V OL (AC).

10. For command/address input slew rate ≥ 0.5V/ns and < 1.0V/ns. Slew rate is measured between VOH (AC) and V OL (AC)

11. CK/CK slew rates are ≥ 1.0V/ns.

12.These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guara nteed by design or tester characterization.

13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. For example, for DDR266B at CL = 2.5, t DAL = (15ns/7.5ns) +(20ns/7.5ns) = 2 + 3 = 5.

REV 1.1

12/2001

61

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.

Input Slew Rate

0.5 V/ns

0.4 V/ns

0.3 V/ns

1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.

delta ( t IS) delta ( t IH)

0 0 ps 1,2

+50 0 ps 1,2

+100 0 ps 1,2

Unit Notes

15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below

0.5 V/ns.

Input Slew Rate

0.5 V/ns

0.4 V/ns

0.3 V/ns

1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.

delta ( t DS) delta ( t DH)

0 0 ps 1,2

+75 +75 ps 1,2

+150 +150 ps 1,2

Unit Notes

16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH) in the case where DQ, DM, and DQS slew rates differ.

Input Slew Rate

0.0 V/ns

0.25 V/ns

0.5 V/ns

1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising transitions.

2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.

3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns Delta rise, fall = (1/0.5) - (1/0.4) [ns/V]

= -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps.

4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

delta ( t DS) delta ( t DH)

0 0 ps 1,2,3,4

+50 +50 ps 1,2,3,4

+100 +100 ps 1,2,3,4

Unit Notes

REV 1.1

12/2001

62

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Data Input (Write) (Timing Burst Length = 4)

t

DSL

DQS

t

DS

DQ

t

DS

DM

DI n

t

DSH

t

DH

t

DH

DI n = Data In for column n. 3 subsequent elements of data in are applied in programmed order following DI n.

Data Output (Read) (Timing Burst Length = 4)

CK CK

DQS

DQ

t

HP

tHP is the half cycle pulse width for each half cycle clock. tHP is referenced to the clock duty cycle only and not to the data strobe (DQS) duty cycle.

Data Output hold time from Data Strobe is shown as tQH. tQH is a function of the clock high or low time (tHP) for that given clock cycle. Note correlation of tHP to tQH in the diagram above (t

t

(max)occurs when DQS is the earliest among DQS and DQ signals to transition.

DQSQ

t

HP

t

HP

t

DQSQ

t

HP1

t

DQSQ

t

QH1

t

HP2

QH2

t

DQSQ

t

HP3

t

DQSQ

QH3

HP1

to t

QH1

t

HP4

t

QH4

, etc.).

Don’t Care

REV 1.1

12/2001

63

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Initialize and Mode Register Sets

MRD

t

RFC

t

RFC

must be

VTD

t

200 cycles of CK**

BA

BA0=L

BA1=L

Register

Load Mode

(with A8 = L)

RP

t

IH

t

IS

t

MRD

t

MRD

t

is required before any command can be applied and

is not applied directly to the device, however t

TT

MRD

greater than or equal to zero to avoid device latchup.

200 cycles of CK are required before a Read command can be applied.

The two Autorefresh commands may be moved to follow the first MRS,

* V

but precede the second Precharge All command.

** t

CL

t

CK

t

CH

t

IH

t

IS

t

PRE EMRS MRS PRE AR AR MRSNOP ACT

IH

t

IS

t

IH

t

IS

t

IH

t

CODE CODE CODE RA

IH

t

ALL BANKS

BA0=L

BA1=L

IH

t

IS

CODE CODE CODE RA

t

IS

t

IS

BA1=L

t

BA0=H

Load Mode

Register, Reset DLL

Register Set

Extended Mode

ALL BANKS

200µs

and CK

stable

VTD

t

High-Z

LVCMOS LOW LEVEL

High-Z

Power-up:

DD

V

REV 1.1

12/2001

CK

DD

V

DDQ

V

REF

V

(System*)

TT

V

CK

CKE

DM

Command

A0-A9, A11

A10

BA0, BA1

DQ

DQS

Don’t Care

64

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Power Down Mode

Don’t Care

IS

t

CL

t

CH

t

IS

t

CK

t

NOP

Exit Power

Down Mode

NOP VALIDVALID*

Enter P ower

Down Mode

REV 1.1

12/2001

IH

t

IS

t

CK

IH

t

IS

t

CKE

IH

t

VALID VALID

IS

t

DQ

DQS

ADDR

Command

DM

No column accesses are allowed to be in progress at the time power down is entered.

* = If this command is a Precharge (or if the device is already in the idle state) then the power down mode

the power down mode shown is Active power down.

shown is Precharge power down. If this command is an Active (or if at least one row is already active), then

65

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Auto Refresh Mode

RA

ACT

RFC

t

RFC

t

RA

BA

Don’t Care

REV 1.1

12/2001

CL

t

RP

t

CH

t

VALID VALID

CK

t

IH

t

PRE NOP NOP AR NOP AR NOPNOP NOP

ALL BANKS

IH

t

IS

t

CK

IH

t

IS

t

CKE

A0-A8

Command

A10

A9, A11,A12

IS

t

ONE BANK

BANK(S)

DQ

DQS

BA0, BA1

DM

PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address; AR = Autorefresh.

NOP commands are shown for ease of illustration; other valid commands may be possible at these times.

DM, DQ, and DQS signals are all don't care/high-Z for operations shown.

66

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Self Refresh Mode

200 cycles

IH

t

VALID

IS

t

Don’t Care

IS

t

NOP

XSRN

t

XSRD,

t

Exit Self

Refresh Mode

Clock must be stable before exiting Self Refresh Mode

(200 cycles of CK).

XSRD

IS

CL

t

CK

t

CH

t

*

RP

t

IH

t

IS

t

AR VALIDNOP

Enter Self

Refresh Mode

IH

t

IS

t

REV 1.1

12/2001

is required before any non-read command can be applied, and t

XSNR

are required before a Read command can be applied.

* = Device must be in the all banks idle state before entering Self Refresh Mode.

** = t

CK

CKE

ADDR

DQ

DQS

DM

Command

67

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Read without Auto Precharge (Burst Length = 4)

VALID VALID VALID

RA

IH

t

RP

t

Don’t Care

(min)

HZ

t

(min)

RPST

t

DQSCK

t

(max)

HZ

t

RPST

t

(max)

DQSCK

t

(min)

AC

CL

t

CH

t

CK

t

IH

t

IS

t

CK

CKE

PRE NOP NOP ACT NOP NOP NOPNOP

IH

t

IS

t

IH

t

IS

NOP Read

t

ALL BANKS

IH

t

IS

t

COL n RA

A10

Command

BA x*

ONE BANK

IH

t

AP

BA x BA x

IS

t

DIS

(min)

LZ

t

RPRE

t

DM

BA0, BA1

A0-A9, A11, A12

t

DQS

Case 1:

DO n

(max)

RPRE

t

LZ

t

CL=2

DQ

= min

DQSCK

/t

AC

t

(max)

AC

t

DQS

Case 2:

DO n

(max)

LZ

t

DQ

* = Don't care if A10 is High at this point.

3 subsequent elements of data out are provided in the programmed order following DO n.

DO n = data out from column n.

PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.

NOP commands are shown for ease of illustration; other commands may be valid at these times.

DIS AP = Disable Auto Precharge.

= max

DQSCK

/t

AC

t

REV 1.1

12/2001

68

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Read with Auto Precharge (Burst Length = 4)

VALID VALID VALID

Don’t Care

RA

IH

t

RP

t

CL

t

CH

t

CK

t

IH

t

IS

t

CK

CKE

NOP NOP NOP ACT NOP NOP NOPNOP

IH

t

IH

t

IS

NOP Read

t

IH

t

IS

COL n RA

IS

t

EN AP

A10

Command

BA x

(min)

HZ

t

(min)

RPST

t

DQSCK

t

(min)

AC

t

(min)

LZ

t

IH

t

BA x

IS

t

DM

(min)

RPRE

t

HZ

t

DQS

DO n

(max)

LZ

t

CL=2

DQ

(max)

HZ

t

RPST

t

(max)

DQSCK

t

(max)

AC

t

RPRE

t

DQS

DO n

(max)

LZ

t

DO n = data out from column n.

3 subsequent elements of data out are provided in the programmed order following DO n.

EN AP = enable Auto Precharge.

ACT = active; RA = row address.

NOP commands are shown for ease of illustration; other commands may be valid at these times.

DQ

BA0, BA1

REV 1.1

12/2001

A0-A9, A11, A12

= min

Case 1:

DQSCK

/t

AC

t

= max

Case 2:

DQSCK

/t

AC

t

69

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Bank Read Access (Burst Length = 4)

VALID

RA

RC

t

ALL BANKS

BA x

(min)

HZ

t

(min)

RP

t

ONE BANKDIS AP

(min)

LZ

t

RPRE

t

RPST

t

DQSCK

t

(min)

AC

t

(min)

LZ

t

DO n

(max)

LZ

t

(max)

HZ

t

RPST

t

(max)

DQSCK

t

(max)

AC

t

RPRE

t

(max)

LZ

t

Don’t Care

DO n

CL=2CL=2

IH

t

IS

CL

t

CH

t

CK

t

Read NOP PRE NOP NOP ACT NOPNOP

COL n

IH

t

RA RA

IS

t

RARA

BA x

IH

t

BA x BA x*

IS

t

RAS

t

RCD

t

REV 1.1

12/2001

IH

t

CK

IH

t

IS

t

IS

NOP ACT

t

CKE

A10

Command

DM

DQS

BA0, BA1

A0-A9, A11, A12

DQ

= min

Case 1:

DQSCK

/t

AC

t

DQS

DQ

= max

Case 2:

DQSCK

/t

AC

t

DO n = data out from column n.

3 subsequent elements of data out are provided in the programmed order following DO n.

DIS AP = disable Auto Precharge.

* = Don't care if A10 is High at this point.

PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.

NOP commands are shown for ease of illustration; other commands may be valid at these times.

70

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write without Auto Precharge (Burst Length = 4)

RA

RP

t

VALID

ALL BANKS

ONE BANK

Don’t Care

BA x*

WR

t

IH

t

DSH

t

CL

t

CH

t

CK

t

IH

t

IS

t

NOP NOP NOP PRE NOP NOP ACT

WPRE

NOP

IH

t

IS

t

IH

t

NOP Write

IS

t

IH

t

COL n RA

IS

t

IH

t

IS

DIS AP

t

BA x BA

WPST

t

DQSL

t

DQSH

t

DQSS

t

WPRES

t

DIn

= min.

DQSS

t

DIn = Data in for column n.

3 subsequent elements of data in are applied in the programmed order following DIn.

DIS AP = Disable Auto Precharge.

* = Don't care if A10 is High at this point.

PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.

NOP commands are shown for ease of illustration; other valid commands may be possible at these times.

REV 1.1

12/2001

DQ

CK

CKE

Command

A10

DQS

BA0, BA1

DM

A0-A9, A11, A12

71

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write with Auto Precharge (Burst Length = 4)

RA

RP

t

VALID

DAL

t

WR

t

VALID VALID

DSH

t

WPST

t

Don’t Care

CL

t

CH

t

CK

t

IH

t

IS

t

NOP NOP NOP NOP NOP NOP ACT

DQSL

t

NOP

IH

t

IS

t

IH

t

NOP Write

IS

t

IH

t

COL n RA

IS

t

IH

t

BA x BA

IS

EN AP

t

DQSH

t

DIn

DQSS

t

WPRES

t

WPRE

t

= min.

DQSS

t

DIn = Data in for column n.

DQ

CK

CKE

Command

A10

DQS

BA0, BA1

DM

NOP commands are shown for ease of illustration; other valid commands may be possible at these times.

ACT = Active; RA = Row address; BA = Bank address.

3 subsequent elements of data in are applied in the programmed order following DIn.

EN AP = Enable Auto Precharge.

A0-A9, A11, A12

REV 1.1

12/2001

72

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Bank Write Access (Burst Length = 4)

VALID

BA x

ALL BANKS

ONE BANK

WR

t

WPST

t

DSH

t

RAS

t

IH

t

CL

t

CH

t

Write NOP NOP NOP NOP PRE NOPNOP

Col n

IS

t

DIS AP

BA x

t

DQSL

t

WPRE

DQSH

t

DQSS

t

WPRES

t

RCD

DIn

t

Don’t Care

REV 1.1

12/2001

CK

t

IH

t

RA

IS

t

IH

t

IS

t

IH

t

NOP ACT

IS

t

IH

t

RA

BA x

IS

t

= min.

DQSS

t

DI n = data in for column n.

3 subsequent elements of data in are applied in the programmed order following DI n.

DIS AP = Disable Auto Precharge.

* = don't care if A10 is High at this point.

PRE = Precharge; ACT = Active; RA = Row address.

NOP commands are shown for ease of illustration; other valid commands may be possible at these times.

CK

CKE

Command

A10

BA0, BA1

DQ

DQS

DM

A0-A9, A11, A12

73

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Write DM Operation (Burst Length = 4)

RA

RP

t

VALID

BA x*

ALL BANKS

ONE BANK

WR

t

DSH

t

WPST

t

Don’t Care

CL

t

CH

t

CK

t

IH

t

IS

t

NOP NOP NOP PRE NOP NOP ACT

DQSL

t

NOP

IH

t

IS

t

IH

t

NOP Write

IS

t

IH

t

COL n RA

IS

t

IH

t

BA x BA

IS

DIS AP

t

DQSH

t

DQSS

t

WPRES

t

DIn

= min.

DI n = data in for column n.

3 subsequent elements of data in are applied in the programmed order following DI n (the second element of the 4 is masked).

DIS AP = Disable Auto Precharge.

CK

CKE

Command

A10

BA0, BA1

DQ

DQS

DM

DQSS

* = Don't care if A10 is High at this point.

PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.

NOP commands are shown for ease of illustration; other valid commands may be possible at these times.

t

A0-A9, A11, A12

REV 1.1

12/2001

74

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Package Dimensions (400mil; 66 lead; Thin Small Outline Package)

22.22 ± 0.10

Detail A

10.16 ±. 0.13

11.76 ± 0.20

Lead #1

0.65 Basic 0.30

+ 0.03

- 0.08

1.20 Max

0.05 Min

0.71REF

Detail A

0.10

0.25 Basic

0.5 ± 0.1

Seating Plane

Gage Plane

REV 1.1

12/2001

75

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM

Package Dimensions ( 60 balls ; 0.8mmx1.0mm Pitch ; CSP Package)

8.5

1.05 0.80

1.000.50

Dia.

0.45

2.25

1.60

Note : All dimensions are typical unless otherwise stated. Unit : Millimeters

15.50

0.35

1.15

REV 1.1

12/2001

76

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW

256Mb Double Data Rate SDRAM Revision Log

Rev Contents of Modification 01/01 05/01

12/01

Preliminary Changed to Revision 1.0 Changed to Revision 1.1

Added CSP ball configuration Added CSP package dimensions Removed the QFC function

REV 1.1

12/2001

77

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

®

Nanya Technology Corporation.

©

The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C , or other countries, or both. NANYA NANYA logo

Other company, product and service names may be trademarks or services maeks of others.

NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC’s standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”).

NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should be directed to NTC through a local sales office.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be provided by customer to minimize the inherent or procedural hazards.

NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.

NANYA TECHNOLOGY CORPORATION HWA YA Technology Park 669, FU HSING 3rd Rd., Kueishan, Taoyuan, Taiwan, R.O.C.

The NANYA TECHNOLOGY CORPORATION home page can be found at http:\\www.nanya.com

Datasheet NT5DS32M8AT-75B, NT5DS32M8AW-75B, NT5DS64M4AT-8B, NT5DS64M4AW-8B, NT5DS64M4AW-75B Datasheet (NANYA)

Specifications and Main Features

Frequently Asked Questions

User Manual