Datasheet NT512S72V4PA0GR-8B, NT512S72V4PA0GR-7K, NT512S72V4PA0GR-75B Datasheet (NANYA)

NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module

Preliminary 06 / 2001 1

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

64Mx72 bit One Bank Registered SDRAM Module
based on 64Mx4, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD

Features

l JEDEC-standard 168-pin, dual in-line memory module

(DIMM)

l PC133- and PC100-compliant
l Registered inputs with one-clock delay
l Phase-lo ck loop (PLL) clock driver to reduce loading
l ECC-optimized pinout
l Inputs and outputs are LVTTL (3.3V) compatible
l Single 3.3V ± 0.3V Power Supply
l Fully synchronous to positive edge
l Suspend Mode and Power Down Mode
l Auto Refresh (CBR) and Self Refresh
l Automatic and controlled Precharge commands
l SDRAMs have 4 internal banks (64Mx4 SDRAM)
l Module has 1 physical bank 512MB (64 Meg x 72)
l 8192 Refresh cycles distributed across 64ms

l DIMM

CAS

latency * (Registered mode) :

Speed grade Frequency

CAS

latency

-7K 133MHz 3

-75B 133MHz 4

-8B 100MHz 3

* DIMM

CAS

latency = device CL + 1 for registered mode.

l Programmable Operation:

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, and 8

- Operation: Burst Read and Write or Multiple

Burst Read with

Single Write

l Gold contacts
l SDRAMs in TSOP Type II Package
l Serial Presence Detect (SPD) with Write Protect

Description

The NANYA NT512S72V4PA0GR is a registered 168-Pin Synchronous DRAM Dual In-Line Memory Module (DIMM) organized as a 64Mx72
high-speed memory array. The DIMM uses eighteen 64Mx4 SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed
data-transfer rates of 100MHz and 133MHz by employing a prefetch/pipeline hybrid architecture that synchronizes the output data to a system
clock.
The DIMM is intended for use in applications operating at 100MHz and 133MHz memory bus speeds. All control and address signals are
re-driven through registers/buffers to the SDRAM devices. Operating in registered mode (REGE pin tied high), the control/address input signals
are latched in the register on one rising clock edge and sent to the SDRAM devices on the following rising clock edge (data access is delayed
by one clock).
A phase-lock loop (PLL) on the DIMM is used to re-drive the clock signals to both the SDRAM devices and the registers to minimize system
clock loading. (CK0 is connected to the PLL, and CK1, CK2, and CK3 are terminated on the DIMM). A single clock enable (CKE0) controls all
devices on the DIMM, enabling the use of SDRAM Power Down modes.
Prior to any access operation, the device

CAS

latency and burst type/length/operation type must be programmed into the DIMM by address

inputs A0-A12 and I/O addresses BA0 and BA1 using the mode register set cycle. The DIMM

CAS

latency when operated in Registered mode

is one clock later than the device

CAS

latency due to the address and control signals being clocked to the SDRAM devices.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data
are programmed and locked by the DIMM manufacturer. The last 128 bytes are available to the customer and may be write protected by
providing a high level to pin 81 on the DIMM. An on-board pull-down resistor keeps this in the Write Enable mode.
All NANYA 168-pin DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint.

Ordering Information

Device Timing

Part Number

MHz. CL t RCD t RP

DIMM

CAS

latency Organization

Leads Power

143MHz 3 3 3 4

NT512S72V4PA0GR -7K

133MHz 2 2 2 3
133MHz 3 3 3 4

NT512S72V4PA0GR -75B

100MHz 2 2 2 3
125MHz 3 3 3 4

NT512S72V4PA0GR -8B

100MHz 2 2 2 3

64Mx72 Gold 3.3V

* CL = CAS Latency

NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module

Preliminary 06 / 2001 2

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Description

CK0 – CK3 Clock Inputs CB0-CB7 Check Bit Data input/output

CKE0 Clock Enable DQMB0-DQMB7 Data Mask

RAS

Row Address Strobe VDD Power (3.3V)

CAS

Column Address Strobe VSS Ground

WE Write Enable NC No Connect

S0,S2

Chip Selects SCL Serial Presence Detect Clock Input

A0-A9, A11, A12 Address Inputs SDA Serial Presence Detect Data input/output

A10 / AP Address Input/Auto-precharge SA0-2 Serial Presence Detect Address Inputs

BA0, BA1 SDRAM Bank Address Inputs WP Serial Presence Detect Write Protect Input

DQ0-DQ63 Data input/output REGE Register Enable

Pinout

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1 VSS 85 VSS 29 DQMB1

113 DQMB5

57 DQ18 141 DQ50

2 DQ0 86 DQ32 30

S0

114 NC 58 DQ19 142 DQ51

3 DQ1 87 DQ33 31 NC 115

RAS

59 VDD 143 VDD
4 DQ2 88 DQ34 32 VSS 116 VSS 60 DQ20 144 DQ52
5 DQ3 89 DQ35 33 A0 117 A1 61 NC 145 NC
6 VDD 90 VDD 34 A2 118 A3 62 NC 146 NC
7 DQ4 91 DQ36 35 A4 119 A5 63 NC 147 REGE
8 DQ5 92 DQ37 36 A6 120 A7 64 VSS 148 VSS
9 DQ6 93 DQ38 37 A8 121 A9 65 DQ21 149 DQ53

10 DQ7 94 DQ39 38 A10/AP

122 BA0 66 DQ22 150 DQ54
11 DQ8 95 DQ40 39 BA1 123 A11 67 DQ23 151 DQ55
12 VSS 96 VSS 40 VDD 124 VDD 68 VSS 152 VSS
13 DQ9 97 DQ41 41 VDD 125 CK1 69 DQ24 153 DQ56
14 DQ10 98 DQ42 42 CK0 126 A12 70 DQ25 154 DQ57
15 DQ11 99 DQ43 43 VSS 127 VSS 71 DQ26 155 DQ58
16 DQ12 100 DQ44 44 NC 128 CKE0 72 DQ27 156 DQ59
17 DQ13 101 DQ45 45

S2

129 NC 73 VDD 157 VDD

18 VDD 102 VDD 46 DQMB2

130 DQMB6

74 DQ28 158 DQ60

19 DQ14 103 DQ46 47 DQMB3

131 DQMB7

75 DQ29 159 DQ61
20 DQ15 104 DQ47 48 NC 132 NC 76 DQ30 160 DQ62
21 CB0 105 CB4 49 VDD 133 VDD 77 DQ31 161 DQ63
22 CB1 106 CB5 50 NC 134 NC 78 VSS 162 VSS
23 VSS 107 VSS 51 NC 135 NC 79 CK2 163 CK3
24 NC 108 NC 52 CB2 136 CB6 80 NC 164 NC
25 NC 109 NC 53 CB3 137 CB7 81 WP 165 SA0
26 VDD 110 VDD 54 VSS 138 VSS 82 SDA 166 SA1
27 WE 111

CAS

55 DQ16 139 DQ48 83 SCL 167 SA2

28 DQMB0

112 DQMB4

56 DQ17 140 DQ49 84 VDD 168 VDD

NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module

Preliminary 06 / 2001 3

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (1 Bank, 64Mx4 SDRAMs)

A0 - A12 : SDRAMs D0 - D17

BA0-BA1 : SDRAMs D0 - D17

RAS : SDRAMs D0- D17

CKE : SDRAMs D0- D17

CAS : SDRAMs D0- D17

WE : SDRAMs D0- D17

RDQMB0

DQ0
DQ1
DQ2
DQ3

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D0

RS0

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D6

R
E
G

I
S
T
E
R

BA0-BA1

A0 - A12

RAS
CAS

CKE0

WE

S0 / S2

PCK

RA0-RA12

RBA0-RBA1

RRAS
RCAS
RCKE0
RWE

RS0 / RS2

REGE

Notes : 1. All resistor values are 10 ohms unless otherwise specified.

Serial PD

A0 A2A1

SCL

WP

SDA

SA0 SA2SA1

DQ20
DQ21
DQ22
DQ23

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D1

DQ4
DQ5
DQ6
DQ7

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D2

DQ8

DQ9
DQ10
DQ11

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D3

DQ12
DQ13
DQ14
DQ15

RDQMB1

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D4

CB0

CB1

CB2

CB3

RS2
RDQMB2

I/O 0
I/O 1

I/O 3

I/O 2

DQS CS

D5

DQ16
DQ17
DQ18
DQ19

RDQMB3

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D7

DQ24
DQ25
DQ26
DQ27

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D8

DQ28
DQ29
DQ30
DQ31

RDQMB4

DQ32
DQ33
DQ34
DQ35

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D9

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D15

DQ52
DQ53
DQ54
DQ55

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D10

DQ36
DQ37
DQ38
DQ39

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D11

DQ40
DQ41
DQ42
DQ43

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D12

DQ44
DQ45
DQ46
DQ47

RDQMB5

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D13

CB4
CB5
CB6
CB7

RDQMB6

I/O 0
I/O 1

I/O 3

I/O 2

DQS CS

D14

DQ48
DQ49
DQ50
DQ51

RDQMB7

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D16

DQ56
DQ57
DQ58
DQ59

I/O 0
I/O 1

I/O 3

I/O 2

DQM CS

D17

DQ60
DQ61
DQ62
DQ63

DQMB0-DQMB7 RDQMB0-RDQMB7

VDD

10K

D0 - D17V

DD

V

SS

D0 - D17

CK0

CK1 - CK3

D0-D17PLL

12pF

12pF

NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module

Preliminary 06 / 2001 4

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input/Output Functional Description

Symbol Type Polarity

Function

CK0 - CK3 Input

Positive

Edge

The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of
their associated clock. CK0 drives the PLL. CK1, CK2 andCK3 are terminated.

CKE0 Input

Active

High

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By

deactivating

the clocks, CKE low initiates the Power Down mode, Suspend mode, or the Self

Refresh mode.

S0,S2

Input

Active

Low

Enables the associated SDRAM command decoder when low and disables the command decoder

when high. When the command decoder is disabled, new commands are ignored but previous

operations continue.

RAS,CAS

,WE

Input

Active

Low

When sampled at the positive rising edge of the clock,

RAS,CAS

,WE

define the operation to be

executed by the SDRAM.

BA0, BA1 Input -

Selects which SDRAM bank is to be active.

A0 - A9
A10/AP

A11, A12

Input -

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12

) when

sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA9,A11

)

when sampled at the rising clock edge. In addition to the column address, AP is used to invoke

Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is

selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which

bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of

BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

DQ0 - DQ63,

CB0 - CB7

Input

/Output

-

Data and Check Bit input/output pins .

DQMB0 -DQMB7 Input

Active

High

The Data Input/Output masks, associated with one data byte, place the DQ buffers in a high
impedance state when sampled high. In Read mode, DQMB has a latency of three clock cycles in
Registered mode, and controls the output buffers like an output enable. In Write mode, DQMB
has a latency of one clock cycle in Registered mode. In this case, DQMB operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high.

REGE

Input

Active

High

(Register

Mode

Enable)

The Register Enable pin must be held high for proper registered mode operation (signals re-driven
to the SDRAMs when the clock rises, and held valid until the next rising clock).

SA0 – SA2 Input -

Address inputs. Connected to either VDD or VSS

on the system board to configure the Serial

Presence Detect EEPROM address.

SDA

Input

/Output

-

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus time to VDD to act as a pull up.

SCL Input -

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to VDD to act as a pull up.

WP Input

Active

High

This signal is pulled low on the DIMM to enable data to be written into the last 128 bytes of the

SPD

EEPROM.

VDD , VSS Supply

Power and ground for the module.

NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module

Preliminary 06 / 2001 5

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Absolute Maximum Ratings

Symbol Parameter Rating Units Notes

V

DD

Power Supply Voltage -0.3 to +4.6

V

IN

Input Voltage -1.0 to 4.6

V

OUT

Output Voltage -1.0 to 4.6

V 1

T

A

Operating Temperature (ambient) 0 to +70 °C 1

T

STG

Storage Temperature -55 to +125 °C 1

P

D

Power Dissipation 10.3 W 1,2

I

OUT

Short Circuit Output Current 50 mA 1

Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

This is a stress rating only and functional operation of the de

vice at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Maximum power is calculated assuming the DIMM is Auto Refresh mode.

Recommended DC Operating Conditions (T A =0 to 70 °C)

Rating

Symbol Parameter

Min. Typ. Max.

Units Notes

VDD Power Voltage 3.0 3.3 3.6 V 1

VIH Input High Voltage 2.0 - V

DD

+ 0.3

V 1,2

VIL Input Low Voltage -0.3 - 0.8 V 1,3

VOH Output High Voltage 2.4 - - V

VOL Output Low Voltage - - 0.4 V

I IL Input Leakage current -10 - 10 uA

1. All voltages referenced to VSS .

2. VIH (max) = V

DD

/ V

DDQ

+ 1.2V for pulse width ≤ 5ns

3. VIL (min) = V

SS

/ V

SSQ

- 1.2V for pulse width ≤ 5ns .

Capacitance (T A =25 °C , f =1MHz, V DD =3.3 ± 0.3V)

Symbol Parameter Max.

Unit

CI1 Input Capacitance (A0-A9, A10/AP, A11, A12, BA0, BA1, CKE0,

RAS,CAS

,WE )

19
CI2 Input Capacitance (S0-S2) 15
CI3 Input Capacitance (DQMB0 - DQMB7) 14
CI4 Input Capacitance (REGE) 10
CI5 Input Capacitance (CK0) 28
CI6 Input Capacitance (CK1, CK2, CK3) 24
CI7 Input Capacitance (SA0 - SA2, SCL, WP) 9

C

IO1

Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) 13

C

IO2

Input/Output Capacitance (SDA) 11

pF

NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module

Preliminary 06 / 2001 6

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

DC Output Load Circuit

VOH(DC) = 2.4V,IOH= -2mA

VOL(DC) = 0.4V,IOL= -2mA

3.3 V

1200 ohms

870 ohms

50 pF

Output

Operating, Standby, and Refresh Currents (TA =0 to 70 °C , VDD =3.3 ± 0.3V)

Speed

Parameter

Symbol

Test condition

- 7K - 75B - 8B

Unit Note

Operating current I

CC1

1 bank operation , t

RC

= tRC(mim), t

CK

= min

Active-Precharge Command cycling
without burst operation

2600 2400 2300 mA 1

I

CC2P

CKE0 ≤ V

IL

(max), t

CK

= min,

S0,S2

= V

IH

(min)

276 276 276 mA 1

Precharge

standby current

in power-down mode

I

CC2PS

CKE0 ≤ V

IL

(max), t

CK

=oo ,

S0,S2 = V

IH

(min)

51 51 51 mA

I

CC2N

CKE0 ≥ V

IH

(min), t

CK

= min

S0,S2

= V

IH

(min)

780 780 520 mA

Precharge

standby current in non

power-down mode

I

CC2NS

CKE0 ≥ V

IH

(min), t

CK

=oo,

S0,S2

= V

IH

(min)

123 123 123 mA

I

CC3P

CKE0 ≤ V

IL

(max), t

CK

=min.

S0,S2

= V

IH

(min) (Power Down Mode)

348 348 348 mA

No Operating current

( Active state : 4 bank)

I

CC3N

CKE0 ≥ V

IH

(min), t

CK

=min

S0,S2

= V

IH

(min)

1320 1320 990 mA 1

Operating current

( Burst mode )

I

CC4

t

CK

=min , Read/ Write command cycling,

Multiple banks active, gapless data, BL=4

2400 2400 1800 mA 1,2

Auto(CBR)

refresh current

I

CC5

t

CK

=min, CBR command cycling 2850 2850 2520 mA 1

Self refresh current I

CC6

CKE0 ≤ 0.2V 69 69 69 mA

1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t CK and t RC. Input
signals are changed once during t CK (min). t CK (min) = 7.5ns.

2. The specified values are obtained with the DIMM data outputs open.

NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module

Preliminary 06 / 2001 7

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Characteristics (TA =0 to 70 °C , VDD =3.3 ± 0.3V)

1. An initial pause of 200ms, with CKE0 held high, is required after power-up. A Precharge All Banks command must be given followed by a
minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation.

2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.40V crossover point.

3. The Transition time is measured between VIH and VIL (or between VIL and VIH ).

4. AC measurements assume t T =1.2ns (1 Volt/ns rise time).

5. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH ) in a
monotonic manner.

6. A 1ms stabilization time is required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal.

7. All timings are specified at the input receiver of the signal. This allows times to be specified at the end of a transmission line versus at the
DIMM connector which may display significant reflections. Refer to the device specifications for non-skew adjusted timings.

AC Output Load Circuits

Clock

Input

Output

t

HOLD

t

SETUP

t

CKL

t

CKH

t

T

V

IH

V

IL

1.4V

1.4V

t

AC

t

LZ

tOH

1.4V

Output

Zo = 50 ohm

50 pF

AC Output Load Circuit

NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module

Preliminary 06 / 2001 8

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Timing Parameters *

(*Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters.)

Clock and Clock Enable Parameters

- 7K - 75B - 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tCK3 Clock Cycle Time,

CAS

Latency = 3 7 1000 7.5 1000 8 1000 ns

tCK2 Clock Cycle Time,

CAS

Latency = 2 7.5 1000 10 1000 10 1000 ns

tAC3(B) Clock Access Time,

CAS

Latency = 3 - 5.4 - 5.4 - 6 ns 1

tAC2(B) Clock Access Time,

CAS

Latency = 2 - 5.4 - 6 - 6 ns 1
tCKH Clock High Pulse Width 2.5 - 2.5 - 3 - ns 2
tCKL Clock Low Pulse Width 2.5 - 2.5 - 3 - ns 2
tCES Clock Enable Set-up Time 1.5 - 1.5 - 2 - ns
tCEH Clock Enable Hold Time 0.8 - 0.8 - 1 - ns
tSB Power down mode Entry Time 0 7.5 0 7.5 0 12 ns
tT Transition Time (Rise and Fall) 0.5 10 0.5 10 0.5 10 ns

1. Access time is measured at 1.4V. In AC Characteristics section, see notes.

2. t CKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). t CKL is the pulse width of
CLK measured from the negative edge to the positive edge referenced to V IL (max).

Common Parameters

- 7K - 75B - 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tCS Command Setup Time 1.5 - 1.5 - 2 - ns
tCH Command Hold Time 0.8 - 0.8 - 1 - ns
tAS Address and Bank Select Set-up Time 1.5 - 1.5 - 2 - ns
tAH Address and Bank Select Hold Time 0.8 - 0.8 - 1 - ns
tRCD

RAStoCAS

Delay 20 - 20 - 20 - ns 1
tRC Bank Cycle Time 60 - 67.5 - 70 - ns 1
tRFC Auto Refresh to Active/Auto Refresh 60 - 67.5 - 70 -
tRAS Active Command Period 45 100K 45 100K 50 100K ns 1
tRP Precharge Time 20 - 20 - 20 - ns 1
tRRD Bank to Bank Delay Time 15 - 15 - 20 - ns 1
tCCD

CAS

to

CAS

Delay Time 1 - 1 - 1 - CLK

1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).

Mode Register Set Cycle

- 7K - 75B - 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tRSC Mode Register Set Cycle Time 2 - 2 - 2 - CLK 1

1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).

NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module

Preliminary 06 / 2001 9

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read Cycle

- 7K - 75B - 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

- - - - 2.5 - ns

tOH Data Out Hold Time

2.7 - 2.7 - 3 - ns
tLZ Data Out to Low Impedance Time 0 - 0 - 0 - ns
tHZ3 Data Out to High Impedance Time 3 5.4 3 5.4 3 6 ns 1
tDQZ DQM Data Out Disable Latency 2 - 2 - 2 - CLK

1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.

Refresh Cycle

- 7K - 75B - 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tREF Refresh Period - 64 - 64 - 64 ms
tSREX Self Refresh Exit Time 10 - 10 - 10 - ns

Write Cycle

- 7K - 75B - 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tDS Data In Set-up Time 1.5 - 1.5 - 2 - ns
tDH Data In Hold Time 0.8 - 0.8 - 1 - ns
tDPL Data input to Precharge 15 - 15 - 15 - ns

tDAL3

Data In to Active Delay

CAS

Latency = 3

5 - 5 - 5 - CLK

tDAL2

Data In to Active Delay

CAS

Latency = 2

5 - - - - - CLK

tDQW DQM Write Mask Latency 0 - 0 - 0 - ns

NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module

Preliminary 06 / 2001 10

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Serial Presence Detect -- Part 1 of 2

64Mx72 SDRAM Registered DIMM based on 64Mx4, 4Banks, 8K Refresh, 3.3v SDRAMs with SPD

SPD Entry Value

Serial PD Data Entry

(Hexadecimal)

Byte

Description

-7K -75B -8B -7K -75 -8B

Note

0 Number of Serial PD Bytes Written during Production 128 80
1 Total Number of Bytes in Serial PD device 256 08
2 Fundamental Memory Type SDRAM 04
3 Number of Row Addresses on Assembly 13 0D
4 Number of Column Addresses on Assembly 11 0B
5 Number of DIMM Bank 1 01

6. Data Width of Assembly X72 48
7 Data Width of Assembly (cont’) X72 00
8 Voltage Interface Level of this Assembly LVTTL 01
9 SDRAM Device Cycle Time at CL=3 7ns 7.5ns

8ns 70 75 80

10 SDRAM Device Access Time from Clock at CL=3 5.4ns 5.4ns

6ns 54 54 60
11 DIMM Configuration Type ECC 02
12 Refresh Rate/Type SR/1x(7.8us) 82
13 Primary SDRAM Width X4 04
14 Error Checking SDRAM Device Width X4 04
15 SDRAM Device Attributes: Min CLk Delay, Random Col Access

1 Clock 01

16 SDRAM Device Attributes: Burst Length Supported 1,2,4,8 0F

17

SDRAM Device Attributes:
Number of Device Banks

4 04

18 SDRAM Device Attributes: CAS Latencies Supported 2/3 2/3 2/3 06 06 06
19 SDRAM Device Attributes: CS Latency 0 01
20 SDRAM Device Attributes: WE Latency 0 01
21 SDRAM Device Attributes Registered, Buffered, PLL 1F

22 SDRAM Device Attributes: General

Wr-1/Rd Burst, Precharge All,

Auto-Precharge, VDD +/-

10%

0E

23 Minimum Clock Cycle at CL=2 7.5ns 10ns 10ns 75 A0 A0
24 Maximum Data Access Time from Clock at CL=2 5.4ns 6ns 6ns 54 60 60
25 Minimum Clock Cycle Time at CL=1 N/A 00
26 Maximum Data Access Time from Clock at CL=1 N/A 00
27 Minimum Row Precharge Time(tRP) 15ns 20ns 20ns 0F 14 14
28 Minimum Row Active to Row Active delay (tRRD) 15ns 15ns 20ns 0F 0F 14
29 Minimum RAS to CAS delay (tRCD) 15ns 20ns 20ns 0F 14 14
30 Minimum RAS Pulse Width (tRAS) 45ns 45ns 50ns 2D 2D 32
31 Module Bank Density 512MB 80
32 Address and Command Setup Time Before Clock 1.5ns 1.5ns

2ns 15 15 20
33 Address and Command Hold Time After Clock 0.8ns 0.8ns

1ns 08 08 10
34 Data Input Setup Time Before Clock 1.5ns 1.5ns

2ns 15 15 20
35 Data Input Hold Time After Clock 0.8ns 0.8ns

1ns 08 08 10

36-61 Reserved Undefined 00

62 SPD Revision 1.2A 1.2A 1.2A 12 12 12
63 Checksum for byte 0 - 62 Checksum Data 75 BB 02

NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module

Preliminary 06 / 2001 11

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Serial Presence Detect -- Part 2 of 2

64Mx72 SDRAM Registered DIMM based on 64Mx4, 4Banks, 8K Refresh, 3.3v SDRAMs with SPD

SPD Entry Value

Serial PD Data Entry

(Hexadecimal)

Byte

Description

-7K -75B -8B -7K -75B -8B

Note

64-71 Manufacturer’s JEDED ID Code 0B hex. 7F7F7F0B00000000 3

72 Module Manufacturing Location N/A 00
73-90 Module Part number N/A N/A N/A 00 00 00
91-92 Module Revision Code N/A 00
93-94 Module Manufacturing Data Year/Week Code yy/ww 1,2
95-98 Module Serial Number Serial Number 00

99-125 Reserved Undefined 00

126 Modules Supports this Clock Frequency 100MHz 64
127 Attributes for Clock Frequency defined in byte 126 F5 F5 FF

128-255 Open for customer Use Undefined 00

1. yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)

2. ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)

3. NANYA 11decimal (bank four) 0000 1011 binary 0B Hex.

NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module

Preliminary 06 / 2001 12

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Package Dimensions

Note : All dimensions are typical unless otherwise stated.

133.250

127.330

42.16

6.667
Detail A

1.700

0.157

0.700

FRONT VIEW

Side

pin 1

0.118

1.27

6.35

Detail A

Detail C

Detail B

3.99

Unit : Millimeters

BACK VIEW

REG REG

PLL

1 84

0.079

0.098

1.27

0.039

0.008

REG

85168

5.250

5.013

Inches

43.33

4.00

17.78

0.25

6.35

0.25

1.660

2.625

0.170 MAX.

0.050

3.00

0.123

3.124

2.006

0.203

1.000

0.05

2.489