Datasheet NT3881DH-02, NT3881DH-01, NT3881DF-01, NT3881DF-02 Datasheet (NOVATEK)

NT3881D

Features

! Internal LCD drivers
16 common signal drivers
40 segment signal drivers
(can be externally extended to 400 segments
using NT3882)
! Maximum display dimensions
40 characters * 2 lines or
80 characters * 1 line

! Interfaces with 4-bit or 8-bit MPU
! Versatile display functions provided on chip:

Display Clear, Cursor Home, Display ON/OFF,
Cursor ON/OFF, Character Blinking, Cursor
Shift, and Display Shift
! Three duty factors, selected by PROGRAM:
1/8, 11/11, and 1/16
! Displays Data RAM (DD RAM): 80 X 8 bits
(displays up to 80 characters)
! Character Generator RAM (CG RAM):
64 X 8 bits for general data,
8 5 X 8 programmable dot patterns, or
4 5 X 10 programmable dot patterns

! Low voltage reset
! NOVATEK Identification code
! Bonding option for A-type and B-type waveform

Dot Matrix LCD Controller and Driver

! Character Generator ROM (CG ROM):
3 kinds of CG ROM sizes:
192 characters:
160 5 X 8 dot patterns
32 5 X 10 dot patterns
240 characters:
192 5 X 8 dot patterns
48 5 X 10 dot patterns
256 characters:
192 5 X 8 dot patterns
64 5 X 10 dot patterns
Custom CG ROM is also available

! Built-in power-on r eset function
! Logic power supply: single +5V supply

! LCD driver power supply: V

(V

+0.3 - VDD-13.5)

DD

! Three oscillator operations
(Freq. = 250KHz - 270KHz):

• Internal oscillation

• Ceramic resonator

• External clock

! CMOS Process
! Available in 80-pin QFP or in CHIP FORM

- V5

1

General Description

The NT3881D is a dot matrix LCD controller and driver
LSI that can operate with either a 4-bit or an 8-bit
microprocessor (MPU). NT3881D receives control
character codes from the MPU, stores them in an internal
RAM (up to 80 characters), transforms each character
code into a 5 X 7, 5 X 8, or 5 X 10 dot matrix character
pattern, and then displays the codes on the LCD panel.
The built-in Character Generator ROM consists of 256
different character patterns.

The NT3881D also contains Character Generator RAM
where the user can store 8 different character patterns at
run time. These memory features make character display
flexible. NT3881D also provides many display instructions
to achieve versatile LCD display functions. The NT3881D
is fabricated on a single LSI chip using the CMOS
process, resulting in very low power requirements.
With several NT3882 driver ICs connected to the
NT3881D, up to 80 characters can be displayed.

1 V2.4

Pin Configuration

S

S

C

C

C

C

C

C

E

E

O

O
G
3
9

O

G

M

M

M

4

1

1

1

0

6

5

4

C

O

O

O

O

C

C

C

C

C

C

C

C

C

D

D

D

D

D

M

M

M

M

O

O

O

O

O

O

O

O

O

B

1

1

1

1

M

M

M

M

M

M

3

2

1

0

9

8

7

M

6

5

4

3

B

M

M

7

6

2

1

D

B

B

B

B

5

4

3

2

NT3881D

SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23

6463626160595857565554535251504948474645444342

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

123456789

S

S

S

S
E
G
2
2

S

E

E

E

E

G

G

G

G

2

2

1

1

1

0

9

8

S

S

S

E

E

E

G

G

G

1

1

1

7

6

5

UM3881DF

NT3881DF

101112131415161718192021222324

S

S

S

S

S

S

S

S

S

S

E

E

E

E

E

E

G

G

G

1

1

1

4

3

2

E

G

G

G

G

1

1

9

8

1

0

S

E

E

E

E

G

G

G

G

7

6

5

4

S
E
G
3

41

40

DB1

39

DB0

38

E

37

R/W

36

RS

35

D

34

M

33

VDD

32

CL2

31

CL1

30

V5

29

V4

28

V3

27

V2

26

V1

25

OSC2

S

S

G

O

E

E

N

S

G

G

D

C

2

1

1

2 V2.4

Pad Configuration

SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10

SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1

GND

OSC1

S

S

S

S

S

S

S

S

S

S

S

E

E

E

E

E

E

E

E

G

G

G

G

G

2

2

2

3

4

5

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25 26 27 28 29 30 31 328134 35 36 37 38 39 40
O

V1V2V3V4V5C
S
C
2

G

2

2

2

6

7

8

E

G

G

G

2

3

3

9

0

1

NT3881DH

V
D
D
B

33

C

V

L

L

D

1

2

D
A

S

E

E

E

G

G

G

3

3

3

2

3

4

71727374757677787980

6970

M D RSR

NT3881D

S

S

S
E
G
3
6

E D

S

E

E

G

G

3

3

7

8

6567

66

64

SEG39

63

SEG40
COM1

62

6
COM1

61

5
COM1

60

4
COM1

59

3
COM1

58

2
COM1

57

1
COM1

56

0

55

COM9

54

COM8

53

COM7

52

COM6

51

COM5

50

COM4

49

COM3

48

COM2

47

COM1

46

DB7

45

DB6

44

DB5

43

DB4
DB3

42

DB2

41

D

B

B

0

1

E
G
3
5

68

/

W

3 V2.4

Block Diagram

V1
V2

V3
V4
V5

VDD
GND

OSC1

OSC2

8

INSTRUCTION

REGISTER

(IR)

INSTRUCTION

8

DECODER

ADDRESS
COUNTER

7

7

TIMING

GENERATOR

7

NT3881D

3

M
CL1
CL2

RS

R/W

E

DB7~DB4

DB3~DB0

7

7

I/O

BUTTER

8

DATA

REGISTER

(DR)

4

CHARACTER

GENERATOR

4

BUSY
FLAG

(BF)

64 X 8 BITS

CUR50R
ADDRESS
COURTER

78 8

RAM

(CG RAM)

PARALLEL-TO-SERIAL

CONVERTER

7

DISPLAY DATA

RAM

(DD RAM)

80 X 8 BITS

8

CHARACTER

GENERATOR

ROM

(CG ROM)

55

CURSOR

/BLINK

CONTROLLER

16-BIT

16

SHIFT

REGISTER

40-BIT

40

LATCH

CIRCUIT

40-BIT SHIFT REGISTER

COMMON

SIGNAL
DRIVER

SEGMENT

SIGNAL
DRIVER

COM1

16

|

COM16

SEG1

40

|

SEG40

D

4 V2.4

Pin and Pad Descriptions

NT3881D

Pin and Pad No. Designation I/O

External

Connection

Description

1 - 22 SEG22 - SEG1 O LCD panel Segment signal output pins

24, 25 OSC1, OSC2 Pins connected to resistor or ceramic filter for

internal clock oscillation. For external clock
operation, clock inputs to OSC1.

26 - 30

V

- V5

1

P Power supply Power supply for LCD driver

31 CL1 O NT3882 Clock to latch serial data D sent to NT3882.

32 CL2 O NT3882 Clock to shift serial data D

V

: +5V

33, 81 VDDB, VDDA P Power supply

DD

A-Type waveform: V
B-Type waveform: V

bond to VDDA

DD

bond to VDDB

DD

23 GND P Power supply GND: 0V

34 M O NT3882 Switch signal to convert LCD drive waveform to

AC

35 D O NT3882 Character pattern data corresponding to each

common signal is transmitted serially from this
output. 0-Non selection, 1-selection.

36 RS I MPU Register select signal

0: Instruction register (write)
Busy flag, address counter (read)
1: Data register (write, read)

37 R/W I MPU Read/Write control signal

0: Write
1: Read

38 E I MPU Read/Write start signal

39 - 42 DB0 - DB3 I/O MPU Lower 4 tri-state bi-directional data bus for

transmitting data between MPU and NT3881D.
Not used during 4-bit operation.

43 - 46 DB4 - DB7 I/O MPU Higher 4 tri-state bi-directional data bus for

transmitting data between MPU and NT3881D.
DB7 is also used as busy flag.

47 - 62 COM1 - COM16 O LCD panel Common signal output pins

63 - 80 SEG40 - SEG23 O LCD panel Segment signal output pins

5 V2.4

Functional Description

The NT3881D is a dot-matrix LCD controller and driver
LSI. It operates with either a 4-bit or an 8-bit
microprocessor (MPU). The NT3881D receives both
instructions and data from the MPU. Some instructions
set operation modes, such as the function mode, data
entry mode, and display mode; as well as some control
LCD display functions, such as clear display, restore
display, shift display, and cursor. Other instructions
include read and write both data and addresses. All
instructions allow users convenient and powerful functions
to control the LCD dot-matrix displays.

Data is written into and read from the Data Display RAM
(DD RAM) or the Character Generator RAM (CG RAM).
As display character codes, the data stored in the DD
RAM decodes a set of dot-matrix character patterns that
are built into the Character Generator ROM (CG ROM).
The CG ROM, with many character patterns (up to 256
patterns), defines the character pattern fonts. The
NT3881D regularly scans the character patterns through
the segment drivers. The CG RAM stores character
pattern fonts at run time if users intend to show character
patterns that are not defined in the CG ROM. This feature
makes character display flexible. Other unused bytes can
be used as general-purpose data storage.

The LCD driver circuit consists of 16 common signal
drivers and 40 segment signal drivers allowing a variety of
application configurations to be implemented. Additionally,
the user can extend display size by cascading the
segment driver LSI NT3882. The maximum display
dimensions can be either 80 characters in a 1-line display
or 40 characters in a 2-line display.

Character Generator ROM (CG ROM)

The character generator ROM generates LCD dot
character patterns from the 8-bit character pattern codes.
The NT3881D provides 3 CG ROM configurations:

1. 192 Characters:
The CG ROM contains 160 5 X 8 dot character patterns

and 32 5 X 10 dot character patterns. An example is the
NT3881D-01, in which the relation between the character
codes and character patterns is shown in Table 1. The
character codes from 00H to 0FH are used to get
character patterns from the CG RAM. Character codes
from 10H to 1FH and from 80H to 9FH map to full

NT3881D

character patterns. Character codes from E0H to FFH are
assigned to generate 5 X 10 dot character patterns, and
other codes are used to generate 5x8 dot character
patterns.

2. 240 Characters:
The CG ROM contains 192 5 X 8 dot character patterns

and 48 5 X 10 dot character patterns. An example of this
type is the NT3881D-02, in which the relation between the
character codes and character patterns is shown in Table

2.
The character codes from 00H to 0FH are used to get
character patterns from the CG RAM. Character codes
from 10H to 1FH and from E0H to FFH are assigned to
generate 5 X 10 dot character patterns, and other codes
to generate 5 X 8 dot character patterns. No null
character pattern exists in this type. Note that the
underlined cursor, displayed on the 8th duty may be
obscure if the 8th row of a dot character pattern is coded.
We recommend that users display the cursor in the
blinking mode if they code 5x8 dot character patterns is
their custom CG ROM.

3. 256 Characters:
The CG ROM contains 192 5 X 8 dot character patterns

and 64 5 X 10 dot character patterns. No adequate
example is presented here.
The only difference between this type and the just
mentioned second type is that the character codes from
00H to 0FH get character patterns from the CG ROM
rather than from the CG RAM. These character codes are
assigned to generate 5 X 10 dot character patterns. In this
application, the CG RAM would be employed as a
general-purpose data storage.

Custom character patterns are available by mask­programming ROM. For convenience of character pattern
development, NOVATEK has developed a user-friendly
editor program for the NT3881D to help determine the
character patterns users prefer. By executing the program
on the computer, users can easily create and modify their
character patterns. By transferring the resulting files
generated by the program through a modem or some
other communication method, the user and NOVATEK
have established a reliable, fast link for programming the
CG ROM.

6 V2.4

NT3881D

Absolute Maximum Ratings*

Power Supply Voltage (VDD) . . . . . . . . . . -0.3V to +0.7V

Power Supply Voltage(V
Input Voltage (V

) . . . . . . . . . . . . . . . -0.3V to VDD +0.3V

I

Operating Temperature (T
Storage Temperature (T

toV5).VDD -13.5V to VDD+0.3V

1

) . . . . . . . . -20°C to +75°C

OPR

) . . . . . . . -55°C to +125°C

STG

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.

! All voltage values are referenced to GND = 0V

to V5, must maintain VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5.

! V

1

= 5.0V, GND = VEE = 0V, TA = 25°C)

DC Electrical Characteristics

(V

DD

Symbol Parameter Min. Typ. Max. Unit Conditions Applicable Pin

V

V

V

V

"H" Level Input Voltage (1) 2.2 -

IH1

"L" Level Input Voltage (1) -0.3 - 0.8 V

IL1

"H" Level Input Voltage (2)

IH2

"L" Level Input Voltage (2) GND - 1.0 V

IL2

VDD

V

-1.0

DD

-

VDD

V

V

DB0 - DB7, RS,

R/W, E

OSC1

V

V

V

V

V

V

OH1

OL1

OH2

OL2

COM

SEG

IIL

-IP

IOP

"H" Level Output Voltage (1) 2.4 - - V

"L" Level Output Voltage (1) - - 0.4 V

"H" Level Output Voltage (2)

"L" Level Output Voltage (2) - -

Driver Voltage Descending (COM) - - 2.9 V

Driver Voltage Descending (SEG) - - 3.8 V

0.9 VDD

- - V

0.1 VDD

Input Leakage Current -1 - 1

Pull-up MOS Current 50 125 250

Supply Current Power Supply

- 0.3 0.5 mA Rf oscillation,

Current

V

A

µ

A

µ

IOH = -0.25mA

IOL = 1.2mA

= -0.04mA

I

OH

IOL = 0.04mA

ID = 0.05mA

ID = 0.05mA

VIN = 0 to VDD

VDD = 5V

from external
clock V
f

OSC

=5V,

DD

= fCP =

270KHz

DB0 - DB7

(TTL)

CL1, CL2, M, D

(CMOS)

COM1 - 16

SEG1 - 40

RS, R/W,
DB0-DB7

V

DD

7 V2.4

NT3881D

DC Electrical Character (continued)

Symbol Parameter Min. Typ. Max. Unit Conditions Applicable Pin

External Clock Operation

fCP

External Clock Operating

125 270 350 KHz

Frequency

t

DUTY

t

RCP

t

FCP

External Clock Duty Cycle 45 50 55 %

External Clock Rise Time 0.1 - 0.5

External Clock Fall Time 0.1 - 0.5

s

µ

s

µ

Internal Clock Operation (RC Oscillator)

f

OSC

Oscillator Frequency 190 270 350 KHz

Rf = 91K

Ω ±

2%

Internal Clock Operation (Ceramic Resonator Oscillator)

Oscillator Frequency 245 250 255 KHz Ceramic resonator

LCD Driving Voltage

4.6

3.0

-

V

DD

V

V

DD

- V5

1/5 bias
1/4bias

V
V

f

OSC

LCD1
LCD2

AC Characteristics

Read Cycle (VDD = 5.0V, GND = VEE = 0V, TA = 25°C)

Symbol Parameter Min. Typ. Max. Unit Conditions

t

CYCE

t

WHE

tRE, tFE

Enable Cycle Time 500 - - ns Figure 1

Enable "H" Level Pulse Width 300 - - ns Figure 1

Enable Rise/Fall Time - - 25 ns Figure 1

601

tAS

tAH

tRD

t

DHR

RS, R/W Setup Time

100

2

RS, R/W Address Hold Time 10 - - ns Figure 1

Read Data Output Delay - - 190 ns Figure 1

Read Data Hold Time 20 - - ns Figure 1

- - ns Figure 1

8 V2.4

NT3881D

AC Characteristics (continued)

Write Cycle (VDD = 5.0V, GND = VEE = 0V, TA = 25°C)

Symbol Parameter Min. Typ. Max. Unit Conditions

t

CYCE

t

WHE

tRE, tFE

Enable Cycle Time 500 - - ns Figure 2

Enable "H" Level Pulse Width 300 - - ns Figure 2

Enable Rise/Fall Time - - 25 ns Figure 2

601

tAS

tAH

tDS

t

DHR

RS, R/W Setup Time

100

2

RS, R/W Address Hold Time 10 - - ns Figure 2

Data Output Delay 100 - - ns Figure 2

Data Hold Time 10 - - ns Figure 2

- - ns Figure 2

Notes: 1: 8-bit operation mode
2: 4-bit operation mode

Timing Characteristics of Interface Signals with Segment Driver LSI NT3882

(V

= 5V, GND = V

DD

= 0V, T

EE

= 25°C)

A

Symbol Parameter Min. Typ. Max. Unit Conditions

t

CWH

Clock Pulse Width High 800 - - ns Figure 3

t

t

CWL

tSU

tDH

CSU

tDM

Clock Pulse Width Low 800 - - ns Figure 3

Data Setup Time 300 - - ns Figure 3

Data Hold Time 300 - - ns Figure 3

Clock Setup Time 500 - - ns Figure 3

M Delay Time -1000 - 1000 ns Figure 3

Power Supply Conditions Using Internal Reset Circuit

Symbol Parameter Min. Typ. Max. Unit Conditions

t

RON

t

OFF

Power Supply Rise Time 0.1 - 10 ns Figure 4

Power Supply OFF Time 1 - - ms Figure 4

9 V2.4

Timing Waveforms

Read Operation

RS

R/W

E

IH1

IH1

V

IL1

V

t

AS

WEM

t

IH1

V

IL1

V

t

RE

RD

t

V

IL1

V

t

AH

IH1

V

AH

t

FE

t

IL1

V

DHR

t

NT3881D

IL1

V

DB0~DB7

IH1

V

VALD DATA

V

IL1

CYCE

t

IH1

V
V

IL1

Figure 1. Bus Read Operation Sequence

(Reading out data from NT3881D to MPU)
Write Operation

V

RS

V

IH1

V

IL1

t

AS

IH1

V

IL1

t

AH

R/W

V

t

AH

t

FE

DHW

IL1

V
V

IH1

IL1

E

DB0 ~ DB7

V

IL1

t

WEM

V

IH1

V

IL1

t

RE

V

IH1

V

IH1

V

IL1

t

DS

t

VALD DATA

V

IL1

t

CYCE

Figure 2. Bus Write Operation Sequence

(Writing data from MPU to NT3881D)

V

IL1

10 V2.4

Timing Waveforms (continued)

Interface Signals with Segment Driver LSI

NT3881D

CLK1

CLK2

D

M

0.9 V

0.1 V

DD

DD

t

CWH

t

CSU

0.9 V

t

CSU

DD

0.9 V

t

0.1 V

DD

CWH

0.9 V

0.1 V

0.1 V
t

DD

t

DM

SU

DD

0.9 V

DD

0.1 V

DD

t

CWL

0.9 V

DD

DD

DD

0.1 V

DD

t

DH

Figure 3. Sending Data to Segment Driver LSI NT3882

Interface Signals with Segment Driver LSI (continued)

4.5V

V

DD

t

RON

> 10ms

0.1ms >

Figure 4. t
power supply to or when power supply repeats ON and OFF.

Note 1:

The NT3881D has three clock options:

A. Internal Oscillator Operation (With Ceramic Filter)

OSC1

t

RON

stipulates the time of power OFF for instantaneous

OFF

t

OFF

> 1ms

Rf : 1MΩ ± 10%

OSC2

Rd : 3.3KΩ ± 5%
C1 = C2 : 680pF ± 10%

t

OFF

0.2V0.2V0.2V

CERAMIC

FILTER

C1 C2

11 V2.4

B. Internal Oscillator (With Rf Resistor)

OSC1

Rf: 91kohm + 2%

OSC2

C. External Clock Operation

NT3881D

Only Rf may be connected between OSC1 and OSC2.
The wire connection Rf must be as short as possible.

OSC1 and OSC2.

OSC1

PULSE INPUT

OSC2

Note 2 :

Input/Output Terminals:

A. Input Terminal

Applicable Terminal : E (No Pull Up MOS)

Applicable Terminals: RS, R/W (with Pull Up MOS)

PULL UP MOS

DD

V

PMOS

NMOS

V

DD

PMOS

V

DD

PMOS

NMOS

12 V2.4

B. Output Terminal
Applicable Terminals: CL1, CL2, M, D

NT3881D

V

DD

PMOS

NMOS

C. I/O Terminal
Applicable Terminals: DB0 to DB7

V

DD

PULL UP MOS

PMOS

V

DD

PMOS

V

DD

ENABLE

PMOS

NMOS

NMOS

(OUTPUT CIRCUIT)

(TRISTATE)

DATA

13 V2.4

Table 1. Correspondence between Character Codes and Character Patterns
(NOVATEK Standard NT3881D-01)

NT3881D

14 V2.4

Table 2. Correspondence between Character Codes and Character Patterns
(NOVATEK Standard NT3881D-02)

NT3881D

15 V2.4

Instruction Set

NT3881D

Instruction Code Function Execution

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (f

Display Clear 0 0 0

Display/
Cursor Home 0 0 0

Entry Mode
Set

Display
ON/OFF

Display/
Cursor Shift

Function Set 0 0 0

RAM
Address Set

DD RAM
Address Set

Busy Flag/
Address
Counter
Read

CG RAM/
DD RAM
Data Write

CG RAM/
DD RAM
Data Read

0

0

0 0 0

0 0 0 0 0 1 S/C R/L * * Shift display or move cursor.

0 0 0

0 0 1

0 1 BF AC

1 0

1 1

0 0 0

0 0 0

0

0

0

0 0 0

0 1 DL N F

1

Write data

Read data

0 0 0

0 0 1

0

0

1 D C B

ACG

ADD

1 Clear entire display area,

restore display from shift, and
load address counter with DD
RAM address 00H.

* Restore display from shift and

load address counter with DD
RAM address 00H.

1

I/D

*

Specify direction of cursor
movement and display shift

S

mode. This operation takes
place after each data transfer
(read/write).

Specify activation of display
(D) cursor (C) and blinking of
character at cursor position
(B).

* Set interface data length (DL),

number of display line (N), and
character font (F).

Load the address counter with
a CG RAM address.
Subsequent data access is for
CG RAM data.

Load the address counter with
a DD RAM address.
Subsequent data access is for
DD RAM data.

Read Busy Flag (BF) and
contents of Address Counter
(AC).

Write data to CG RAM or DD
RAM.

Read data from CG RAM or
DD RAM.

time (max)

=

OSC

250KHz)

1.64ms

1.64ms

40µs

40µs

40µs

40µs

40µs

40µs

0µs

40µs

40µs

Note 1: Symbol "*" signifies an insignificant bit (disregard).
Note 2: Correct input value for "N" is predetermined for each model.

16 V2.4

Instruction Set (continued)

NT3881D

Instruction Code Function Execution

time (max)

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (f

OSC

=

250KHz)

I/D = 1 : Increment I/D = 0 : Decrement

S = 1 : Display Shift On
D = 1 : Display On
C = 1 : Cursor Display On
B = 1 : Cursor Blink On
S/C = 1 : Shift Display S/C
R/L

= 1 : Shift Right R/L = 0 : Shift Left
= 1 : 8-Bit DL = 0 : 4-Bit

DL
N = 1 : Dual Line

= 1 : 5x10 dots

F

= 0 : Move Cursor

N

= 0 : Signal Line

F

= 0 : 5x8 dots

DD RAM : Display Data RAM
CG RAM : Character Generator

RAM
ACG : Character Generator
RAM Address
ADD : Display Data RAM
Address

AC : Address Counter
BF = 1 : Internal Operation
BF = 0 : Ready for Instruction

Note 1: Symbol "*" signifies an insignificant bit (disregard).
Note 2: Correct input value for "N" is predetermined for each model.

17 V2.4

Interface to LCD
(1) Character Font and Number of Lines

The NT3881D provides a 5 X 7 dot character font 1-line
mode, a 5 X 10 dot character font 1-line mode and a
5 X 7 dot character font 2-line mode, as shown in the
table below.

Number of Lines Character Font Number of Common Signals Duty Factor

Three types of common signals are available as displayed
in the table. The number of lines and the font type can be
selected by the program.

NT3881D

1 5 X 7 dots + Cursor

(or 5x8 dots)

1 5 X 10 dots + Cursor 11 1/11

2 5 X 7 dots + Cursor

(or 5x8 dots)

(2) Connection to LCD

The following 4 LCD connection examples show the various combinations between characters and lines.
NT3881D can directly drive the following combinations:

(a) 5 X 8 Font - 8 character X 1 line (1/8 duty cycle, 1/4 bias)

8 1/8

16 1/16

LCD PANEL

COM1

COM8

SEG1

NT3881D

SEG40

18 V2.4

(b) 5 X 10 Font - 8 character X 1 line (1/11 duty cycle, 1/4 bias)

LCD PANEL

COM1

COM8

NT3881D

SEG1

SEG40

COM11

COM9

NT3881D

(c) 5 X 8 Font - 8 character X 2 lines (1/16 duty cycle, 1/5 bias)

LCD PANEL

COM1

COM8

NT3881D

SEG1

SEG40

COM16

COM9

19 V2.4

(d) 5 X 8 Font - 16 character X 1 line (1/16 duty cycle, 1/5 bias)

LCD PANEL

COM1

COM8

SEG1

NT3881D

SEG40

COM16

COM9

NT3881D

20 V2.4

NT3881D

(3) Bias Power Connection

NT3881D provides 1/4 or 1/5 bias for various duty cycle applications. The power division voltage is described in the following
table. The connection of NT3881D, power supply, and resistors are also shown as follows:

Power Division 1/8, 1/11 Duty Cycle - 1/4 Bias 1/16 Duty Cycle - 1/5 Bias

V1 V

V2 V

V3 V

V4 V

V5 V

- 1/4 V

DD

- 1/2 V

DD

- 1/2 V

DD

- 3/4 V

DD

DD

V

LCD

V

LCD

V

LCD

V

LCD

- V

V

LCD

- 1/5 V

DD

- 2/5 V

DD

- 3/5 V

DD

- 4/5 V

DD

DD

- V

LCD

LCD

LCD

LCD

LCD

NT3881D

VDD

V1

V2

V3

V4

V5

VDD

R

R

R

R

VR

VEE

V

LCD

NT3881D

VDD

V1

V2

V3

V4

V5

VDD

R

R

R

R

R

VR

VEE

V

LCD

Note: The resistance value depends on the LCD panel size.

21 V2.4

(4) LCD Waveform

A-type, 1/8 Duty Cycle, 1/4 Bias

COM1

V

DD

V

1

3)

V2 (V

V

4

5

V

A-type, 1/11 Duty Cycle, 1/4 Bias

COM1

V

DD

12345 812

12345 11 1 2

NT3881D

400 CLOCKS

1 FRAME

400 CLOCKS

1

V

3)

V2 (V

4

V

V

5

A-type, 1/16 Duty Cycle, 1/5 Bias

COM1

V2 (V

V

DD

V

1

3)

4

V

5

V

12345 16 1 2

1 FRAME

200 CLOCKS

1 FRAME

22 V2.4

B-type, 1/8 Duty Cycle, 1/4 Bias

COM1

DD

V

V1

V2 (V3)

V4

V5

1234 9

5678 16 21

1 Frame

NT3881D

400 CLOCKS

Frame 1 =××= 84.3Hz

B-type, 1/11 Duty Cycle, 1/4 Bias

COM1

V

DD

V1

V2 (V3)

V4

V5

1234 9

1Frame =××= 61.4Hz

B-type, 1/16 Duty Cycle, 1/5 Bias

COM1

DD

V

1234

1sec
270K

1 Frame

1sec
270K

11.9ms8400

400 CLOCKS

5678 22 2110 11 12 21

16.3ms11400

200 CLOCKS

5 32 2115 16 17 311413

Frequency Frame ==

Frequency Frame ==

1

11.9ms

16.3ms

1

V1

V2

V3

V4
V5

1 Frame

1Frame =××=

1sec

270K

11.9ms16200

Frequency Frame ==

1

11.9ms

84.3Hz

23 V2.4

NT3881D

Application Circuit

C1 - C16 S1 - S40

NT3881D

(for reference only)

D

CL2
CL1

M

V

DD

GND

LCD PANEL

DL1
CL2

CL1

M
V

GND

S1 - S40 S1 - S40

DR2

DL2
DR1
FCS

SEL1
SEL2

V

6

DD

V

1

NT3882

V

2

V

3V4V5

DL1

CL2
CL1

M
V

GND

DD

V

1

NT3882

2

V3V4V

V

DR2

DL2

DR1

FCS
SEL1
SEL2

5

6

V

1

V

2

V

V

3

V

4

V

5

R R R R R

C C C C C

VR

GND or other

negative voltage

24 V2.4

Bonding Diagram

NT3881D

71727374757677787980

6970
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25 26 27 28 29 30 31 328134 35 36 37 38 39 40

NT3881DH

Y

X

(0, 0)

33

68

6567

66

64
63
62
61
60
59
58
57
56
55
54
53

3861 µm

52
51
50
49
48
47
46
45
44
43
42
41

3175 µm

* Substrate Connect to V

or keep floating

DD

* Pad window area: 120m X 110m

25 V2.4

NT3881D

Bonding Dimensions

Pad No. Designation

1 SEG22 -1469 1743 41 DB2 1469 -1707
2 SEG21 -1469 1593 42 DB3 1469 -1557
3 SEG20 -1469 1443 43 DB4 1469 -1407
4 SEG19 -1469 1293 44 DB5 1469 -1257
5 SEG18 -1469 1143 45 DB6 1469 -1107
6 SEG17 -1469 993 46 DB7 1469 -957
7 SEG16 -1469 843 47 COM1 1469 -807
8 SEG15 -1469 693 48 COM2 1469 -657

9 SEG14 -1469 543 49 COM3 1469 -507
10 SEG13 -1469 393 50 COM4 1469 -357
11 SEG12 -1469 243 51 COM5 1469 -207
12 SEG11 -1469 93 52 COM6 1469 -57
13 SEG10 -1469 -57 53 COM7 1469 93
14 SEG9 -1469 -207 54 COM8 1469 243
15 SEG8 -1469 -357 55 COM9 1469 393
16 SEG7 -1469 -507 56 COM10 1469 543
17 SEG6 -1469 -657 57 COM11 1469 693
18 SEG5 -1469 -807 58 COM12 1469 843
19 SEG4 -1469 -957 59 COM13 1469 993
20 SEG3 -1469 -1107 60 COM14 1469 1143
21 SEG2 -1469 -1257 61 COM15 1469 1292
22 SEG1 -1469 -1407 62 COM16 1469 1443
23 GND -1469 -1557 63 SEG40 1469 1593
24 OSC1 -1469 -1707 64 SEG39 1469 1743
25 OSC2 -1183 -1862 65 SEG38 1125 1862
26 V1 -1033 -1862 66 SEG37 975 1862
27 V2 -883 -1862 67 SEG36 825 1862
28 V3 -733 -1862 68 SEG35 675 1862
29 V4 -583 -1862 69 SEG34 525 1862
30 V5 -433 -1862 70 SEG33 375 1862
31 CL1 -283 -1862 71 SEG32 225 1862
32 CL2 -133 -1862 72 SEG31 75 1862
33 VDDB 76 -1691 73 SEG30 -75 1862
34 M 268 -1862 74 SEG29 -225 1862
35 D 418 -1862 75 SEG28 -375 1862
36 RS 568 -1862 76 SEG27 -525 1862
37 R/W 719 -1862 77 SEG26 -675 1862
38 E 870 -1862 78 SEG25 -825 1862
39 DB0 1020 -1862 79 SEG24 -975 1862
40 DB1 1170 -1862 80 SEG23 -1125 1862

81 VDDA 76 -1816

X

Y

Pad No. Designation

X

Unit: µm

Y

26 V2.4

Ordering Information

Part No. Package Remarks

NT3881DH-01 CHIP FORM Refer to Table 1

NT3881DF-01 80L QFP/B-type waveform Refer to Table 1

NT3881DH-02 CHIP FORM Refer to Table 2

NT3881DF-02 80L QFP/B-type waveform Refer to Table 2

NT3881D

27 V2.4

Package Information

NT3881D

QFP 80L Outline Dimensions

1

24

e

G

See Detail F

Seating Plane

unit: inches/mm

H

D

D

6580

64

E

E

H

41

b2540

D

2

A

A

1

A

y

D

E

G

~

~~

G

D

c

L

L

1

Detail F

Symbol Dimensions in inches Dimensions in mm

A 0.130 Max. 3.30 Max.
A1 0.004 Min. 0.10 Min.
A2 0.112±0.005 2.85±0.13

b 0.014 +0.004 0.35 +0.10

c 0.006 +0.004 0.15 +0.10

D 0.551±0.005 14.00±0.13

E 0.787±0.005 20.00±0.13

e 0.031±0.006 0.80±0.15
GD 0.693 NOM. 17.60 NOM.
GE 0.929 NOM. 23.60 NOM.
HD 0.740±0.012 18.80±0.31
HE 0.976±0.012 24.79±0.31

L 0.047±0.008 1.19±0.20

L1 0.095±0.008 2.41±0.20

y 0.006 Max. 0.15 Max.

θ

0

-0.002 -0.05

-0.002 -0.05

°

~ 12° 0

°

~ 12°

Notes:

1. Dimensions D & E do not include resin fins.

2. Dimensions G

& GE are for PC Board surface mount pad pitch design reference only.

D

28 V2.4

Product Spec. Change Notice

Version Content Date

2.4

2.3 PAD 33 VDDB,PAD 81 VDDA modified( Page 5, 24) Nov.2001

2.2 Updated Page 16. Nov.2001

2.1 Updated all diagrams. Nov.1999

2.0 Modified Page1 -

1.0 NEW SPEC -

B-type waveform modified(Page 23 , Document mistake
corrected)

NT3881D

NT3881 Specification Revision History

Apr.2002

29 V2.4