Datasheet NT256S64V88A0G-8B, NT256S64V88A0G-7K, NT256S64V88A0G-75B Datasheet (NANYA)

NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module

Preliminary 08 / 2001 1

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

32Mx64 bit One Bank Unbuffered SDRAM Module
based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD

Features

l 168-Pin Unbuffered 8-Byte Dual In-Line Memory Module
l Intended for PC133 applications

- Clock Frequency: 133MHz

- Clock Cycle: 7.5ns

- Clock Assess Time: 5.4ns

l Inputs and outputs are LVTTL (3.3V) compatible
l Single 3.3V ± 0.3V Power Supply
l Single Pulsed RAS interface
l SDRAMs have 4 internal banks
l Module has 1 physical bank
l Fully Synchronous to positive Clock Edge
l Data Mask for Byte Read/Write control
l Auto Refresh (CBR) and Self Refresh

l Automatic and controlled Precharge commands

l Programmable Operation:

- CAS Latency: 2, 3

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8

- Operation: Burst Read and Write or Multiple Burst

Read with

Single Write

l Suspend Mode and Power Down Mode
l 8192 Refresh cycles distributed across 64ms
l Gold contacts
l SDRAMs in TSOP Type II Package
l Serial Presence Detect with Write Protect

Description

NT256S64V88A0G is unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMM) which is organized as 16Mx64
high-speed memory arrays and is configured as one 16M x 64 physical bank. The DIMM uses eight 32Mx8 SDRAMs in 400mil TSOP II
packages. The DIMM achieves high-speed data transfer rates of up to 133MHz by employing a prefetch / pipeline hybrid architecture that
supports the JEDEC 1N rule while allowing very low burst power.

All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs.
All inputs are sampled at the positive edge of each externally supplied clock (CK0, CK2). Internal operating modes are defined by combinations
of

RAS,CAS

, WE ,S0/S2, DQMB, and CKE0 signals. A command decoder initiates the necessary timings for each operation. A 15-bit

address bus accepts address information in a row / column multiplexing arrangement.

Prior to any Access operation, the

CAS

latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by
address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using
the two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the
customer.

Ordering Information

Speed

Part Number Organization

MHz. CL t RCD t RP

Leads Power

143MHz 3 3 3

NT256S64V88A0G-7K

133MHz 2 2 2
133MHz 3 3 3

NT256S64V88A0G-75B

100MHz 2 2 2
125MHz 3 3 3

NT256S64V88A0G-8B

32Mx64

100MHz 2 2 2

Gold 3.3V

* CL = CAS Latency

NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module

Preliminary 08 / 2001 2

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Description

CK0, CK2 Clock Inputs DQ0-DQ63 Data input/output
CK1, CK3 Unused (terminated) Clock Inputs CB0-CB7 Check Bit Data input/output

CKE0 Clock Enable DQMB0-DQMB7

Data Mask

RAS

Row Address Strobe VDD Power (3.3V)

CAS

Column Address Strobe VSS Ground

WE Write Enable NC No Connect

S0,S2

Chip Selects SCL Serial Presence Detect Clock Input

A0-A9, A11, A12

Address Inputs SDA Serial Presence Detect Data input/output

A10 / AP Address Input/Autoprecharge SA0-2 Serial Presence Detect Address Inputs

BA0, BA1 SDRAM Bank Address Inputs WP Serial Presence Detect Write Protect Input

Pinout

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1 VSS 85 VSS 29 DQMB1

113 DQMB5

57 DQ18 141 DQ50

2 DQ0 86 DQ32 30

S0

114 NC 58 DQ19 142 DQ51

3 DQ1 87 DQ33 31 NC 115

RAS

59 VDD 143 VDD
4 DQ2 88 DQ34 32 VSS 116 VSS 60 DQ20 144 DQ52
5 DQ3 89 DQ35 33 A0 117 A1 61 NC 145 NC
6 VDD 90 VDD 34 A2 118 A3 62 NC 146 NC
7 DQ4 91 DQ36 35 A4 119 A5 63 NC 147 NC
8 DQ5 92 DQ37 36 A6 120 A7 64 VSS 148 VSS
9 DQ6 93 DQ38 37 A8 121 A9 65 DQ21 149 DQ53

10 DQ7 94 DQ39 38 A10/AP

122 BA0 66 DQ22 150 DQ54
11 DQ8 95 DQ40 39 BA1 123 A11 67 DQ23 151 DQ55
12 VSS 96 VSS 40 VDD 124 VDD 68 VSS 152 VSS
13 DQ9 97 DQ41 41 VDD 125 *CK1 69 DQ24 153 DQ56
14 DQ10 98 DQ42 42 CK0 126 A12 70 DQ25 154 DQ57
15 DQ11 99 DQ43 43 VSS 127 VSS 71 DQ26 155 DQ58
16 DQ12 100 DQ44 44 NC 128 CKE0 72 DQ27 156 DQ59
17 DQ13 101 DQ45 45

S2

129 NC 73 VDD 157 VDD

18 VDD 102 VDD 46 DQMB2

130 DQMB6

74 DQ28 158 DQ60

19 DQ14 103 DQ46 47 DQMB3

131 DQMB7

75 DQ29 159 DQ61
20 DQ15 104 DQ47 48 NC 132 NC 76 DQ30 160 DQ62
21 CB0 105 CB4 49 VDD 133 VDD 77 DQ31 161 DQ63
22 CB1 106 CB5 50 NC 134 NC 78 VSS 162 VSS
23 VSS 107 VSS 51 NC 135 NC 79 CK2 163 *CK3
24 NC 108 NC 52 CB2 136 CB6 80 NC 164 NC
25 NC 109 NC 53 CB3 137 CB7 81 WP 165 SA0
26 VDD 110 VDD 54 VSS 138 VSS 82 SDA 166 SA1
27 WE 111

CAS

55 DQ16 139 DQ48 83 SCL 167 SA2

28 DQMB0

112 DQMB4

56 DQ17 140 DQ49 84 VDD 168 VDD

Note: All pin assignments are consistent for all 8-byte unbuffered versions.
*CK1 and CK3 are terminated .

NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module

Preliminary 08 / 2001 3

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

SDRAM DIMM Block Diagram (1 Bank, 32Mx8 SDRAMs)

S0

DQMB0

DQM

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS

D0

DQMB4

DQM

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS

D4

DQMB1

DQM

DQ8
DQ9

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS

D1

DQMB5

DQM

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS

D5

S2

DQMB2

DQM

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ0
DQ1
DQ2

DQ3
DQ4

DQ5
DQ6
DQ7

CS

U2

DQMB6

DQM

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS

D6

DQMB3

DQM

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6

DQ7

CS

D3

DQMB7

DQM

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

CS

D7

RAS
CAS
CKE0
WE
A0-A12
BA0
BA1

RAS : SDRAMs D0-D7
CAS : SDRAMs D0-D7
CKE0 : SDRAMs D0-D7
WE : SDRAMs D0-D7
A0-A12 : SDRAMs D0-D7
BA0 : SDRAMs D0-D7
BA1 : SDRAMs D0-D7

SPD

A0 A1 A2

SCL
WP

SA0 SA1 SA2

V

DD

V

SS

D0 - D7
D0 - D7

SDA

0.1uF

3.3pF

CK0

SDRAM
SDRAM
SDRAM
SDRAM

3.3pF

CK2

SDRAM
SDRAM
SDRAM
SDRAM

CK1,CK3

10pF

* All resistor values are 10 ohms except as shown.

*

47k

0.33uF

CK0
CK2

CLK : SDRAMs D0-D1, D4-D5, 3.3pF Cap.
CLK : SDRAMs D2-D3, D6-D7, 3.3pF Cap.

NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module

Preliminary 08 / 2001 4

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input/Output Functional Description

Symbol Type Signal Polarity

Function

CK0 , CK2 Input Pulse

Positive

Edge

The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of
their associated clock.

CKE0 Input Level

Active

High

Activates the SDRAM CK0 and CK2 sign

als when high and deactivates them when low.

By deactivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or

the Self-Refresh mode.

S0,S2

Input Pulse

Active

Low

Enables the associated SDRAM co

mmand decoder when low and disables the

command decoder when high. When the command decoder is disabled, new commands

are ignored but previous operations continue.

RAS,CAS

,WE

Input Pulse

Active

Low

When sampled at the positive rising edge of the clock,

RAS,CAS

,WE define the

operation to be executed by the SDRAM.

BA0, BA1 Input Level -

Selects which SDRAM bank is to be active.

A0 - A9
A10/AP

A11, A12

Input Level -

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12

)

when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9

)

when sampled at the rising

clock edge. In addition to the column address, AP is used to

invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,

autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,

autoprecharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which b

ank to

pre-charge.

DQ0 - DQ63,

CB0 - CB7

Input

/Output

Level -

Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

DQMB0 -DQMB7 Input Pulse

Active

High

The Data input/output mask places the DQ buffers in a high imped

ance state when

sampled high. In Read mode, DQM has a latency of two clock cycles and controls the

output buffers like an output enable. In Write mode, DQM has a latency of zero and

operates as a byte mask by allowing input data to be written if it is low

but blocks the

Write operation if DQM is high.

SA0 – SA2 Input Level -

Address inputs. Connected to either VDD or VSS

on the system board to configure the

Serial Presence Detect EEPROM address.

SDA

Input

/Output

Level -

Serial Data. Bi-directional signal

used to transfer data into and out of the Serial Presence

Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a

pull-up resistor is required on the system board.

SCL Input Pulse

-

Serial Clock. Used to clock all Serial Presenc

e Detect data into and out of the EEPROM.

Since the SCL signal is inactive in the “high” state, a pull-

up resistor is recommended on

the system board.

WP Input Level

Active

High

Hardware Write Protect. When WP is active, writing to the EEPROM array is inh

ibited.

On the DIMM, this input is connected to the EEPROM Write Protect input and is also tied

to ground through a 47K ohm pull-down resistor.

VDD , VSS Supply

Power and ground for the module.

NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module

Preliminary 08 / 2001 5

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Absolute Maximum Ratings

Symbol Parameter Rating Units Notes

V

DD

Power Supply Voltage -0.3 to +4.6

V

IN

Input Voltage -0.3 to V

DD

+0.3

V

OUT

Output Voltage -0.3 to V

DD

+0.3

V 1

T

A

Operating Temperature (ambient) 0 to +70 °C 1

T

STG

Storage Temperature -55 to +125 °C 1

P

D

Power Dissipation 5.1 W 1

I

OUT

Short Circuit Output Current 50 mA 1

Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at these or any other condit

ions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Recommended DC Operating Conditions (T A =0 to 70 °C)

Rating

Symbol Parameter

Min. Typ. Max.

Units Notes

VDD Power Voltage 3.0 3.3 3.6 V 1

VIH Input High Voltage 2.0 - V

DD

+ 0.3

V 1,2

VIL Input Low Voltage -0.3 - 0.8 V 1,3

VOH Output High Voltage 2.4 - - V

VOL Output Low Voltage - - 0.4 V

I IL Input Leakage current -10 - 10 uA

1. All voltages referenced to VSS .

2. VIH (max) = V

DD

/ V

DDQ

+ 1.2V for pulse width ≤ 5ns

3. VIL (min) = V

SS

/ V

SSQ

- 1.2V for pulse width ≤ 5ns .

Capacitance (T A =25 °C , f =1MHz, V DD =3.3 ± 0.3V)

Symbol Parameter Max.

Unit

CI1 Input Capacitance (A0-A9, A10/AP, A11, BA0, BA1,

RAS,CAS

,WE ) 74

CI2 Input Capacitance (CKE0) 54
CI3 Input Capacitance (S0-S2) 30
CI4 Input Capacitance (CK0 - CK3) 40
CI5 Input Capacitance (DQMB0 - DQMB7) 17
CI6 Input Capacitance (SA0 - SA2, SCL, WP) 9

C

IO1

Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) 10

C

IO2

Input/Output Capacitance (SDA) 11

pF

DC Output Load Circuit

VOH(DC) = 2.4V,IOH= -2mA

VOL(DC) = 0.4V,IOL= -2mA

3.3 V

1200 ohms

870 ohms

50 pF

Output

NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module

Preliminary 08 / 2001 6

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Operating, Standby, and Refresh Currents (TA =0 to 70 °C , VDD =3.3 ± 0.3V)

Speed

Parameter

Symbol

Test condition

- 7K - 75B - 8B

Unit Note

Operating current I

CC1

1 bank operation , t

RC

= tRC(mim), t

CK

= min

Active-Precharge Command cycling
without burst operation

1040 960 920 mA 1, 2

I

CC2P

CKE0 ≤ V

IL

(max), t

CK

= min,

S0,S2

= V

IH

(min)

16 16 16 mA

Precharge

standby current

in power-down mode

I

CC2PS

CKE0 ≤ V

IL

(max), t

CK

=oo ,

S0,S2 = V

IH

(min)

16 16 16 mA

I

CC2N

CKE0 ≥ V

IH

(min), t

CK

= min

S0,S2

= V

IH

(min)

240 240 160 mA 3

Precharge

standby current in non

power-down mode

I

CC2NS

CKE0 ≥ V

IH

(min), t

CK

=oo,

S0,S2

= V

IH

(min)

64 64 64 mA 4

I

CC3P

CKE0 ≤ V

IL

(max), t

CK

=min.

S0,S2

= V

IH

(min) (Power Down Mode)

48 48 48 mA 5

No Operating current

( Active state : 4 bank)

I

CC3N

CKE0 ≥ V

IH

(min), t

CK

=min

S0,S2

= V

IH

(min)

480 400 320 mA 3

Operating current

( Burst mode )

I

CC4

t

CK

=min , Read/ Write command cycling,

Multiple banks active, gapless data, BL=4

960 960 720 mA 2, 6

Auto(CBR)

refresh current

I

CC5

t

CK

=min, CBR command cycling 1400 1400 1240 mA

Self refresh current I

CC6

CKE0 ≤ 0.2V 24 24 24 mA

Serial PD Device

Standby Current

I

SB

V

IN

= GND or V

DD

30 30 30 µA 7

Serial PD Device Active

Power Supply Current

I

CCA

SCL Clock Frequency=100 MHz

1 1 1 µA 8

1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t CK and t RC . Input
signals are changed up to three times during t RC (min).

2. The specified values are obtained with the output open.

3. Input signals are changed once during three clock cycles.

4. Input signals are stable.

5. Active standby current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ).

6. Input signals are changed once during t ck(min) .

7. VDD =3.3V

8. Input pulse levels VDD x 0.1 to VDD x 0.9, input rise and fall times 10ns, input and output timing levels VDD x 0.5, output load 1 TTL gate and
CL=100pF.

NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module

Preliminary 08 / 2001 7

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Characteristics (TA =0 to 70 °C , VDD =3.3 ± 0.3V)

1. An initial pause of 200us,with DQMB0-7 and CKE0 held high, is required after power-up. A Precharge All Banks command must be given
followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation.

2. The Transition time is measured between VIH and VIL (or between VIH and VIL ).

3. In addition to meeting the transition rate specification, the CK0, CK2, and CKE0 signals must transit between VIH and VIL (or between VIL
and VIH ) in a monotonic manner.

4. AC timing tests have VIL =0.8Vand VIH = 2.0 V with the timing referenced to the 1.40V crossover point.

5. AC measurements assume t T =1.2 ns.

AC Output Load Circuits

Clock

Input

Output

t

HOLD

t

SETUP

t

CKL

t

CKH

t

T

V

IH

V

IL

1.4V

1.4V

t

AC

t

LZ

tOH

1.4V

Output

Zo = 50 ohm

50 pF

AC Output Load Circuit

NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module

Preliminary 08 / 2001 8

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

AC Timing Parameters
Clock and Clock Enable Parameters

- 7K - 75B - 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tCK3 Clock Cycle Time,

CAS

Latency = 3 7 1000 7.5 1000 8 1000 ns

tCK2 Clock Cycle Time,

CAS

Latency = 2 7.5 1000 10 1000 10 1000 ns

tAC3(B) Clock Access Time,

CAS

Latency = 3 - 5.4 - 5.4 - 6 ns 1

tAC2(B) Clock Access Time,

CAS

Latency = 2 - 5.4 - 6 - 6 ns 1
tCKH Clock High Pulse Width 2.5 - 2.5 - 3 - ns 2
tCKL Clock Low Pulse Width 2.5 - 2.5 - 3 - ns 2
tCES Clock Enable Set-up Time 1.5 - 1.5 - 2 - ns
tCEH Clock Enable Hold Time 0.8 - 0.8 - 1 - ns
tSB Power down mode Entry Time 0 7.5 0 7.5 0 12 ns
tT Transition Time (Rise and Fall) 0.5 10 0.5 10 0.5 10 ns

1. Access time is measured at 1.4V. In AC Characteristics section, see notes.

2. t CKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to V IH (min). t CKL is the pulse width of
CLK measured from the negative edge to the positive edge referenced to V IL (max).

Common Parameters

- 7K - 75B - 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tCS Command Setup Time 1.5 - 1.5 - 2 - ns
tCH Command Hold Time 0.8 - 0.8 - 1 - ns
tAS Address and Bank Select Set-up Time 1.5 - 1.5 - 2 - ns
tAH Address and Bank Select Hold Time 0.8 - 0.8 - 1 - ns
tRCD

RAStoCAS

Delay 20 - 20 - 20 - ns 1
tRC Bank Cycle Time 60 - 67.5 - 70 - ns 1
tRFC Auto Refresh to Active/Auto Refresh 60 - 67.5 - 70 -
tRAS Active Command Period 45 100K 45 100K 50 100K ns 1
tRP Precharge Time 20 - 20 - 20 - ns 1
tRRD Bank to Bank Delay Time 15 - 15 - 20 - ns 1
tCCD

CAS

to

CAS

Delay Time 1 - 1 - 1 - CLK

1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num
ber of clock cycles = specified value of timing / clock period (count fractions as a whole number).

Mode Register Set Cycle

- 7K - 75B - 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tRSC Mode Register Set Cycle Time 2 - 2 - 2 - CLK 1

1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num
ber of clock cycles = specified value of timing / clock period (count fractions as a whole number).

NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module

Preliminary 08 / 2001 9

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read Cycle

- 7K - 75B - 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

- - - - 2.5 - ns

tOH Data Out Hold Time

2.7 - 2.7 - 3 - ns
tLZ Data Out to Low Impedance Time 0 - 0 - 0 - ns
tHZ3 Data Out to High Impedance Time 3 5.4 3 5.4 3 6 ns 1
tDQZ DQM Data Out Disable Latency 2 - 2 - 2 - CLK

1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.

Refresh Cycle

- 7K - 75B - 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tREF Refresh Period - 64 - 64 - 64 ms
tSREX Self Refresh Exit Time 10 - 10 - 10 - ns

Write Cycle

- 7K - 75B - 8B

Symbol Parameter

Min. Max. Min. Max. Min. Max.

Unit Note

tDS Data In Set-up Time 1.5 - 1.5 - 2 - ns
tDH Data In Hold Time 0.8 - 0.8 - 1 - ns
tDPL Data input to Precharge 15 - 15 - 15 - ns

tDAL3

Data In to Active Delay

CAS

Latency = 3

5 - 5 - 5 - CLK

tDAL2

Data In to Active Delay

CAS

Latency = 2

5 - - - - - CLK

tDQW DQM Write Mask Latency 0 - 0 - 0 - ns

NT256S64V88A0G
256MB : 32M x 64
Unbuffered SDRAM Module

Preliminary 08 / 2001 10

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Package Dimensions

Note : All dimensions are typical unless otherwise stated.

133.35

127.33

1.660

2.625
Detail B

0.079

Detail B

1.375

0.157

0.700

FRONT VIEW

Side

pin 1

0.118

0.050

6.35

6.35

0.079

Detail A

Detail A Detail C

2.489

0.050

Detail C

0.039

0.008

2.59

Unit : Millimeters

BACK VIEW

Inches

5.013

5.250

3.0

66.67

42.17

0.250

0.250

4.00

17.78

34.925

0.106 MAX.

1.27

3.124

0.123

2.006 2.006

3.124

0.123

0.203

1.0

1.27

0.098