Datasheet NM27C512QE90, NM27C512QE150, NM27C512QE120, NM27C512N150, NM27C512QE250 Datasheet (Fairchild Semiconductor)
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NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
NM27C512
524,288-Bit (64K x 8) High Performance CMOS EPROM
General Description
The NM27C512 is a high performance 512K UV Erasable Electrically Programmable Read Only Memory (EPROM). It is manufactured using Fairchild’s proprietary CMOS AMG™ EPROM technology for an excellent combination of speed and economy while
providing excellent reliability.
The NM27C512 provides microprocessor-based systems storage
capacity for portions of operating system and application software. Its 90 ns access time provides no wait-state operation with
high-performance CPUs. The NM27C512 offers a single chip
solution for the code storage requirements of 100% firmwarebased equipment. Frequently-used software routines are quickly
executed from EPROM storage, greatly enhancing system utility.
The NM27C512 is configured in the standard JEDEC EPROM
pinout which provides an easy upgrade path for systems which are
currently using standard EPROMs.
Block Diagram
July 1998
The NM27C512 is one member of a high density EPROM Family
which range in densities up to 4 Megabit.
Features
■ High performance CMOS
— 90 ns access time
■ Fast turn-off for microprocessor compatibility
■ Manufacturers identification code
■ JEDEC standard pin configuration
— 28-pin PDIP package
— 32-pin chip carrier
— 28-pin CERDIP package
DS010834-1
AMG is a trademark of WSI, Inc.
© 1998 Fairchild Semiconductor Corporation
Output Enable and
Chip Enable Logic
Y Decoder
X Decoder
. . . . . . . . .
Output
Buffers
524,288-Bit
Cell Matrix
Data Outputs O0 - O
7
V
CC
GND
V
PP
OE
CE/PGM
A0 - A
15
Address
Inputs
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NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Connection Diagrams
Compatible EPROM pin configurations are shown in the blocks adjacement to the NM27C512 pins.
Commercial Temp Range (0°C to +70° C)
Parameter/Order Number Access Time (ns)
NM27C512 Q, N, V 90 90
NM27C512 Q, N, V 120 120
NM27C512 Q, N, V 150 150
Industrial Temp Range (-40°C to +85°C)
Parameter/Order Number Access Time (ns)
NM27C512 QE, NE, VE 120 120
NM27C512 QE, NE, VE 150 150
Q = Quartz-Windowed Ceramic DIP Package
N = Plastic DIP Package
V = PLCC Package
• All packages conform to the JEDEC standard.
• All versions are guaranteed to function for slower speeds.
Pin Names
A0–A15 Addresses
CE/PGM Chip Enable/Program
OE Output Enable
O0–O7 Outputs
NC Don’t Care (During Read)
PLCC
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O0
O
1
O
2
GND
V
CC
A
14
A
13
A
8
A
9
A
11
OE/V
PP
A
10
CE/PGM
O7
O
6
O
5
O4
O
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
XX/PGM
XX
A
14
A
13
A
8
A
9
A
11
OE
A10
CE
O7
O
6
O
5
O4
O
3
V
CC
XX/PGM
A
17
A
14
A
13
A
8
A
9
A
11
OE
A10
CE
O7
O
6
O
5
O4
O
3
V
CC
A
14
A
13
A
8
A
9
A
11
OE
A10
CE/PGM
O7
O
6
O
5
O4
O
3
27C256 27C010 27C020 27C040 27C080
V
CC
A
18
A
17
A
14
A
13
A
8
A
9
A
11
OE
A10
CE/PGM
O7
O
6
O
5
O4
O
3
V
CC
A
18
A
17
A
14
A
13
A
8
A
9
A
11
OE/
V
PP
A10
CE/PGM
O7
O
6
O
5
O4
O
3
27C080 27C040 27C020 27C010 27C256
A
19
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
XX/
V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
XX/
V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
XX/
V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
PP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
DIP
NM27C512
A8
A9
A11
NC
OE/VPP
A10
CE/PGM
O7
O8
A6
A5
A4
A3
A2
A1
A0
NC
O0
A7
A12
A15NCVCC
A14
A13
O1
O2
GND
NC
O3O4O5
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
14 15 16 17 18 19 20
4 3 2 1 32 31 30
DS010834-2
DS010834-3
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NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings (Note 1)
Storage Temperature -65°C to +150°C
All Input Voltages Except A9 with
Respect to Ground -0.6V to +7V
VPP and A9 with Respect to Ground -0.7V to +14V
VCC Supply Voltage with
Respect to Ground -0.6V to +7V
ESD Protection
(MIL Std. 883, Method 3015.2) >2000V
All Output Voltages with
Respect to Ground VCC + 1.0V to GND -0.6V
Operating Range
Range Temperature V
CC
Tolerance
Commercial 0°C to +70°C +5V ±10%
Industrial -40°C to +85°C +5V ±10%
Read Operation
DC Electrical Characteristics
Symbol Parameter Test Conditions Min Max Units
V
IL
Input Low Level -0.5 0.8 V
V
IH
Input High Level 2.0 VCC +1 V
V
OL
Output Low Voltage IOL = 2.1 mA 0.4 V
V
OH
Output High Voltage IOH = -2.5 mA 3.5 V
I
SB1
VCC Standby Current (CMOS) CE = VCC ±0.3V 100 µA
I
SB2
VCC Standby Current CE = V
IH
1mA
I
CC1
VCC Active Current CE = OE = V
IL
f = 5 MHz 40 mA
I
CC2
VCC Active Current CE = GND, f = 5 MHz
CMOS Inputs Inputs = VCC or GND, I/O = 0 mA 35 mA
C, E Temp Ranges
I
PP
VPP Supply Current VPP = V
CC
10 µA
V
PP
VPP Read Voltage VCC - 0.7 V
CC
V
I
LI
Input Load Current VIN = 5.5V or GND -1 1 µA
I
LO
Output Leakage Current V
OUT
= 5.5V or GND -10 10 µA
AC Electrical Characteristics
Symbol Parameter 90 120 150 Units
Min Max Min Max Min Max
t
ACC
Address to Output Delay 90 120 150 ns
t
CE
CE to Output Delay 90 120 150
t
OE
OE to Output Delay 40 50 50
t
DF
Output Disable to 35 25 45
Output Float
t
OH
Output Hold from Addresses, CE or OE, 0 0 0
Whichever Occurred First
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NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Capacitance T
A
= +25°C, f = 1 MHz (Note 2)
Symbol Parameter Conditions Typ Max Units
C
IN1
Input Capacitance VIN = 0V 6 12 pF
except OE/V
PP
C
OUT
Output Capacitance V
OUT
= 0V 9 12 pF
C
IN2
OE/VPP Input VIN = 0V 20 25 pF
Capacitance
AC Test Conditions
Output Load 1 TTL Gate and CL = 100 pF (Note 8)
Input Rise and Fall Times ≤5 ns
Input Pulse Levels 0.45V to 2.4V
Timing Measurement Reference Level (Note 9)
Inputs 0.8V and 2V
Outputs 0.8V and 2V
AC Waveforms (Notes 6, 7)
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to t
ACC
–tOE after the falling edge of CE without impacting t
ACC
.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE .
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA. CL: 100 pF includes fixture capacitance.
Note 9: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Address Valid
Valid Output
Hi-Z
2V
0.8V
2V
0.8V
2V
0.8V
ADDRESS
OUTPUT
CE
OE
t
CE
2V
0.8V
(Note 3)
(Note 3)
t
DF
(Note 4, 5)
(Note 4, 5)
t
OH
Hi-Z
t
OE
ACC
t
CF
t
DS010834-4
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NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Programming Characteristics (Note 10) and (Note 11)
Symbol Parameter Conditions Min Typ Max Units
t
AS
Address Setup Time 1 µs
t
OES
OE Setup Time 1 µs
t
DS
Data Setup Time 1 µs
t
VCS
VCC Setup Time 1 µs
t
AH
Address Hold Time 0 µs
t
DH
Data Hold Time 1 µs
t
CF
Chip Enable to Output Float Delay OE = V
IL
060ns
t
PW
Program Pulse Width 45 50 105 µs
t
OEH
OE Hold Time 1 µs
t
DV
Data Valid from CE OE = V
IL
250 ns
t
PRT
OE Pulse Rise Time 50 ns
during Programming
t
VR
VPP Recovery Time 1 µs
I
PP
VPP Supply Current during CE = V
IL
30 mA
Programming Pulse OE = V
PP
I
CC
VCC Supply Current 50 mA
T
R
Temperature Ambient 20 25 30 °C
V
CC
Power Supply Voltage 6.25 6.5 6.75 V
V
PP
Programming Supply Voltage 12.5 12.75 13 V
t
FR
Input Rise, Fall Time 5 ns
V
IL
Input Low Voltage 0 0.45 V
V
IH
Input High Voltage 2.4 4 V
t
IN
Input Timing Reference Voltage 0.8 2 V
t
OUT
Output Timing Reference Voltage 0.8 2 V
Programming Waveforms
Note 10:Fairchild’s standard product warranty applies to devices programmed to specifications described herein.
Note 11:VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 12:The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VCC to GND to suppress spurious voltage transients which
may damage the device.
t
AS
Program
Program Verify
Address N
t
CF
Hi-Z
t
DS
t
DH
t
VPS
t
PW
t
OEH
t
AH
2.0V
0.8V
2.0V
0.8V
6.25V
Addresses
Data
OE/V
PP
V
CC
0.8V
t
OES
Data Out Valid
ADD N
Data In Stable
ADD N
2.0V
0.8V
t
DV
t
PRT
12.75V
t
VCS
t
VR
CE/PGM
DS010834-5
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NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Turbo Programming Algorithm Flow Chart
FIGURE 1.
VCC = 6.5V VPP = 12.75V
n = 0
ADDRESS = FIRST LOCATION
CHECK ALL BYTES
1ST: V
CC
= VPP = 6.0V
2ND: V
CC
= VPP = 4.3V
PROGRAM ONE 50µs PULSE
INCREMENT n
ADDRESS = FIRST LOCATION
VERIFY
BYTE
n = 10?
DEVICE
FAILED
LAST
ADDRESS
?
INCREMENT
ADDRESS
n = 0
PROGRAM ONE
50 µs
PULSE
INCREMENT
ADDRESS
VERIFY
BYTE
LAST
ADDRESS
?
PASS
NO
FAIL
YES
YES
PASS
NO
FAIL
NO
YES
DS010834-6
Note: The standard National Semiconductor algorithm may also be used but it will take longer programming time.
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NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table1. It
should be noted that all inputs for the six modes are at TTL levels.
The power supplies required are VCC and OE/VPP. The OE/V
PP
power supply must be at 12.75V during the three programming
modes, and must be at 5V in the other three modes. The V
CC
power supply must be at 6.5V during the three programming
modes, and at 5V in the other three modes.
Read Mode
The EPROM has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip Enable
(CE/PGM) is the power control and should be used for device
selection. Output Enable (OE/VPP) is the output control and should
be used to gate data to the output pins, independent of device
selection. Assuming that addresses are stable, address access
time (t
ACC
) is equal to the delay from CE to output (tCE). Data is
available at the outputs tOE after the falling edge of OE, assuming
that CE has been low and addresses have been stable for at least
t
ACC
– tOE.
Standby Mode
The EPROM has a standby mode which reduces the active power
dissipation by over 99%, from 220 mW to 0.55 mW. The EPROM
is placed in the standby mode by applying a CMOS high signal to
the CE/PGM input. When in standby mode, the outputs are in a
high impedance state, independent of the OE input.
Output Disable
The EPROM is placed in output disable by applying a TTL high
signal to the OE input. When in output disable all circuitry is
enabled, except the outputs are in a high impedance state (TRISTATE).
Output OR-Typing
Because the EPROM is usually used in larger memory arrays,
Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control
function allows for:
1. the lowest possible memory power dissipation, and
2. complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended
that CE/PGM be decoded and used as the primary device selecting function, while OE/VPP be made a common connection to all
devices in the array and connected to the READ line from the
system control bus.
This assures that all deselected memory devices are in their low
power standby modes and that the output pins are active only
when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 22 (OE/VPP) will damage the
EPROM.
Initially, and after each erasure, all bits of the EPROM are in the
“1’s” state. Data is introduced by selectively programming “0’s”
into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word.
The only way to change a “0” to a “1” is by ultraviolet light erasure.
The EPROM is in the programming mode when the OE/VPP is at
12.75V. It is required that at least a 0.1 µF capacitor be placed
across VCC to ground to suppress spurious voltage transients
which may damage the device. The data to be programmed is
applied 8 bits in parallel to the data output pins. The levels required
for the address and data inputs are TTL.
When the address and data are stable, an active low, TTL program
pulse is applied to the CE/PGM input. A program pulse must be
applied at each address location to be programmed.
The EPROM is programmed with the Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a
series of 50 µs pulses until it verifies good, up to a maximum of 10
pulses. Most memory cells will program with a single 50 µs pulse.
(The standard National Semiconductor Algorithm may also be
used but it will have longer programming time.)
The EPROM must not be programmed with a DC signal applied to
the CE/PGM input.
Programming multiple EPROM in parallel with the same data can
be easily accomplished due to the simplicity of the programming
requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data.
A low level TTL pulse applied to the CE/PGM input programs the
paralleled EPROM.
Program Inhibit
Programming multiple EPROMs in parallel with different data is
also easily accomplished. Except for CE/PGM all like inputs
(including OE/VPP) of the parallel EPROMs may be common. A
TTL low level program pulse applied to an EPROM’s CE/PGM
input with OE/VPP at 12.75V will program that EPROM. A TTL high
level CE/PGM input inhibits the other EPROMs from being programmed.
Program Verify
A verify should be performed on the programmed bits to determine
whether they were correctly programmed. The verify is accomplished with OE/VPP and CE at VIL. Data should be verified T
DV
after the falling edge of CE.
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window to
prevent unintentional erasure. Covering the window will also
prevent temporary functional failure due to the generation of photo
currents.
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s identification code to aid in
programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then
automatically calls up the specific programming algorithm for the
part. This automatic programming control is only possible with
programmers which have the capability of reading the code.
The Manufacturer’s Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for
NM27C512 is “8F85”, where “8F” designates that it is made by
Fairchild Semiconductor, and “85” designates a 512K part.
The code is accessed by applying 12V ±0.5V to address pin A9.
Addresses A1–A8, A10–A16, and all control pins
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NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Functional Description (Continued)
are held at VIL. Address pin A0 is held at VIL for the manufacturer’s
code, and held at VIH for the device code. The code is read on the
eight data pins, O0 –O 7 . Proper code access is only guaranteed
at 25°C ±5°C.
ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that erasure
begins to occur when exposed to light with wavelengths shorter
than approximately 4000 Angstroms (Å). It should be noted that
sunlight and certain types of fluorescent lamps have wavelengths
in the 3000Å–4000Å range.
The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of
2537Å. The integrated dose (i.e., UV intensity x exposure time) for
erasure should be minimum of 15W-sec/cm2.
The EPROM should be placed within 1 inch of the lamp tubes
during erasure. Some lamps have a filter on their tubes which
should be removed before erasure
An erasure system should be calibrated periodically. The distance
from lamp to device should be maintained at one inch. The erasure
time increases as the square of the distance from the lamp (if
distance is doubled the erasure time increases by factor of 4).
Lamps lose intensity as they age. When a lamp is changed, the
distance has changed, or the lamp has aged, the system should
be checked to make certain full erasure is occurring. Incomplete
erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require careful
decoupling of the devices. The supply current, ICC, has three
segments that are of interest to the system designer: the standby
current level, the active current level, and the transient current
peaks that are produced by voltage transitions on input pins. The
magnitude of these transient current peaks is dependent on the
output capacitance loading of the device. The associated V
CC
transient voltage peaks can be suppressed by properly selected
decoupling capacitors. It is recommended that at least a 0.1 µF
ceramic capacitor be used on every device between VCC and
GND. This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor
should be used between VCC and GND for each eight devices. The
bulk capacitor should be located near where the power supply is
connected to the array. The purpose of the bulk capacitor is to
overcome the voltage drop caused by the inductive effects of the
PC board traces.
Mode Selection
The modes of operation of the NM27C512 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are
TTL levels excepts for VPP and A9 for device signature.
TABLE 1. Mode Selection
Pins CE/PGM OE/V
PP
V
CC
Outputs
Mode
Read V
IL
V
IL
5.0V D
OUT
Output Disable X (Note 13) V
IH
5.0V High Z
Standby V
IH
X 5.0V High Z
Programming V
IL
12.75V 6.25V D
IN
Program Verify V
IL
V
IL
6.25V D
OUT
Program Inhibit V
IH
12.75V 6.25V High Z
Note 13: X can be VIL or VIH.
TABLE 2. Manufacturer’s Identification Code
Pins A0 A9 07 06 05 04 03 02 01 00 Hex
(10) (24) (19) (18) (17) (16) (15) (13) (12) (11) Data
Manufacturer Code
V
IL
12V100011118F
Device Code V
IH
12V1000010185
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NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
UV Window Cavity Dual-In-Line Cerdip Package (JQ)
Order Number NM27C512Q
Package Number J28CQ
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Plastic One-Time-Programmable Dual-In-Line
Order Number NM27C512N
Package Number N28B
0.008-0.012
[0.203-0.305]
TYP
0.090-0.110
[2.286-2.794]
TYP
0.060-0.100
[1.524-2.540]
TYP
0.015-0.021
[0.381-0.533]
TYP
0.033-0.045
[0.838-1.143]
TYP
0.225 [5.715]
MAX TYP
0.125 [3.175]
MIN TYP
GLASS
SEALANT
15
14
28
1
R 0.025
[0.635]
0.290-0.310
[7.366-7.874]
U.V. WINDOW
R 0.030-0.055
[0.762-1.397]
TYP
0.515-0.530
[13.081-13.462]
1.465 MAX
[37.211]
0.050-0.060
[1.270-1.524]
TYP
0.180 [4.572]
MAX
0.010 [0.254]
MAX
0.015-0.060
[0.381-1.524]
TYP
86°-94°
TYP
0.590-0.620
[14.99-15.75]
0.685
+0.025
-0.060
[17.399 ]
+0.635
-1.524
90°-100°
TYP
0.625
+0.025
-0.015
0.008-0.015
(0.229-0.381)
15.88
+0.635
-0.381
0.580
(14.73)
95° ±5°
0.600 - 0.620
(15.24 - 15.75)
0.030
(0.762)
Max
(
(
0.108 ±0.010
(2.540 ±0.254)
0.018 ±0.003
(0.457 ±0.076)
0.20
(0.508)
0.125-0.145
(3.175-3.583)
0.125-0.165
(3.175-4.191)
0.050
(1.270)
Typ
0.053 - 0.069
(1.346 - 1.753)
0.050 ±0.015
(1.270 ±0.381)
Min
88° 94°
Typ
1234
2827 26 25
1.393 - 1.420
(35.38 - 36.07)
0.510 ±0.005
(12.95 ±0.127)
0.062
(1.575)
Pin #1
IDENT
5246
23 22 21 20 19 18 17 16
7 8 9 1011121314
15
RAD
Page 10
10
www.fairchildsemi.com
NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
32-Lead Plastic Leaded Chip Carrier (PLCC)
Order Number NM27C512V
Package Number VA32A
0.007[0.18]
A
S
S
F-G
0.007[0.18]
B
S
D-E
0.449-0.453
[11.40-11.51]
S
0.045
[1.143]
0.000-0.010
[0.00-0.25]
Polished Optional
0.585-0.595
[14.86-15.11]
0.549-0.553
[13.94-14.05]
-B-
-F-
-E-
-G-
0.050
21
29
30
1
4
2014
13
5
-D-
0.007[0.18]
B
S
D-E
S
0.002[0.05]
B
S
-A-
0.485-0.495
[12.32-12.57]
0.007[0.18]
A
S
S
F-G
A
0.002[0.05]
S
0.007[0.18]
H
S
S
D-E, F-G
0.010[0.25]
B A
S
D-E, F-G
0.118-0.129
[3.00-3.28]
L
B
B
45
°X
0.042-0.048
[1.07-1.22]
0.026-0.032
[0.66-0.81]
Typ
0.0100
[0.254]
0.030-0.040
[0.76-1.02]
R
0.005
[0.13]
Max
0.020
[0.51]
0.045
[1.14]
Detail A
Typical
Rotated 90°
0.027-0.033
[0.69-0.84]
0.025
[0.64]
Min
0.025
[0.64]
Min
0.031-0.037
[0.79-0.94]
0.053-0.059
[1.65-1.80]
0.006-0.012
[0.15-0.30]
0.019-0.025
[0.48-0.64]
0.065-0.071
[1.65-1.80]
0.021-0.027
[0.53-0.69]
Section B-B
Typical
S
0.007[0.18]
C
M
S
D-E, F-G
0.015[0.38]
C D-E, F-G
0.490-0530
[12.45-13.46]
0.078-0.095
[1.98-2.41]
0.013-0.021
[0.33-0.53]
0.004[0.10]
0.123-0.140
[3.12-3.56]
See detail A
-J-
-C-
0.400
[10.16]
( )
TYP
0.541-0.545
[13.74-13-84]
0.023-0.029
[0.58-0.74]
0.106-0.112
[2.69-2.84]
60°
0.015
[0.38]
Base
Plane
-H-
Min Typ
S
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
Life Support Policy
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(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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