Page 1
NM27P040
4,194,304-Bit (512K x 8) Processor Oriented
CMOS EPROM
General Description
The NM27P040 is a 4096K Processor Oriented EPROM
TM
(POP
) configured as 512K x 8. It’s designed to simplify
microprocessor interfacing while remaining compatible with
standard EPROMs. It can reduce both wait states and glue
logic when the specification improvements are taken advantage of in the system design. The NM27P040 is implemented in National’s advanced CMOS EPROM process to provide a reliable solution and access times as fast as 120 ns.
The interface improvements address two areas to eliminate
the need for additional devices to adapt the EPROM to the
microprocessor and to eliminate wait states at the termination of the access cycle. Even with these improvements, the
NM27P040 remains compatible with industry standard
JEDEC pinout EPROMs. The time from CE or OE being
negated until the outputs are guaranteed to be in the high
impedance state has been reduced to eliminate the need
for wait states at the termination of the memory cycle and
the data-out hold time has been extended to eliminate the
need to provide data hold time for the microprocessor by
delaying control signals or latching and holding the data in
external latches.
Features
Y
Fast output turn off to eliminate wait states
Y
Extended data hold time for microprocessor
compatibility
Y
High performance CMOS
Ð 120 ns access time
Y
JEDEC standard pin configuration
Y
Manufacturer’s identification code
NM27P040 4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM
December 1993
Block Diagram
TL/D/11367– 1
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
TM
POP
is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/D/11367
Page 2
Connection Diagrams
27C080 27C020 27C010
A19 XX/V
A16 A16 A16
A15 A15 A15
A12 A12 A12
A7 A7 A7
A6 A6 A6
A5 A5 A5
A4 A4 A4
A3 A3 A3
A2 A2 A2
A1 A1 A1
A0 A0 A0
O
0
O
1
O
2
GND GND GND
O
O
O
Commercial Temperature Range (0§Ctoa70§C)
Parameter/Order Number Access Time (ns)
NM27P040 Q 120 120
NM27P040 Q 150 150
NM27P040 Q 170 170
XX/V
PP
0
1
2
V
CC
PP
O
0
O
1
O
2
Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27P040 pin.
e
5Vg10%
DIP
NM27P040
27C010 27C020 27C080
V
CC
XX/PGM XX/PGM A18
XX A17 A17
A14 A14 A14
A13 A13 A13
A8 A8 A8
A9 A9 A9
A11 A11 A11
OE
A10 A10 A10
CE
O
7
O
6
O
5
O
4
O
3
TL/D/11367– 2
Extended Temperature Range (b40§Ctoa85§C)
e
V
5Vg10%
CC
V
CC
V
CC
OE OE/V
CE CE/PGM
O
7
O
6
O
5
O
4
O
3
O
O
O
O
O
Parameter/Order Number Access Time (ns)
NM27P040 QE 150 150
NM27P040 QE 170 170
PP
7
6
5
4
3
Military Temperature Range (b55§Ctoa125§C)
e
V
5Vg10%
CC
Parameter/Order Number Access Time (ns)
NM27P040 QM 150 150
NM27P040 QM 200 200
Pin Names
A0–A18 Addresses
CE/PGM Chip Enable/Program
OE Output Enable
O0–O7 Outputs
XX Don’t Care (During Read)
Package Types: NM27P040 QXXX
e
Q
Quartz-Windowed Ceramic DIP
All packages conform to the JEDEC standard.
#
All versions are guaranteed to function for slower
#
speeds.
2
Page 3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
All Input Voltages except A9 with
Respect to Ground (Note 10)
VPPand A9 with Respect to Ground
Supply Voltage with
V
CC
Respect to Ground
ESD Protection
All Output Voltages with
Respect to Ground (Note 10) V
b
65§Ctoa150§C
b
b
0.6V toa14V
b
a
1.0V to GNDb0.6V
CC
0.6V toa7V
0.6V toa7V
l
2000V
Read Operation
Operating Range
Range Temperature V
Commercial 0§Ctoa70§C
Industrial
Military
b
40§Ctoa85§C
b
55§Ctoa125§Cg5V
Tolerance
CC
a
g
5V
5V
g
g
g
10%
10%
10%
DC Electrical Characteristics
Over operating range with V
e
V
PP
CC
Symbol Parameter Test Conditions Min Max Units
V
IL
V
IH
VOLOutput Low Voltage I
V
OH
I
SB1
I
SB2
Input Low Level
Input High Level 2.0 V
e
2.1 mA 0.4 V
OL
Output High Voltage I
VCCStandby Current (CMOS) CEeV
(Note 11)
VCCStandby Current CEeV
eb
2.5 mA 3.5 V
OH
g
0.3V
CC
IH
ICCVCCActive Current CEeOEeVIL, I/Oe0mA
e
f
5 MHz
I
PP
V
PP
I
LI
VPPSupply Current V
VPPRead Voltage V
Input Load Current V
ILOOutput Leakage Current V
PP
IN
OUT
e
e
V
CC
5.5V or GND
e
5.5V or GND
AC Electrical Characteristics Over operating range with V
Symbol Parameter
t
ACC
t
CE
t
OE
t
DF
(Note 2) Output Float
t
CF
(Note 2) Output Float
t
OH
(Note 2) Whichever Occurred First
Address to Output Delay 120 150 170 250
CE to Output Delay 120 150 170 250
OE to Output Delay 50 50 50 50
Output Disable to 35
Chip Disable to 35
Output Hold from Addresses, CE or OE,
120 150 170 250
Min Max Min Max Min Max Min Max
7777
e
PP
b
0.2 0.8 V
a
1V
CC
100 mA
1mA
30 mA
10 m A
b
0.4 V
CC
b
11mA
b
10 10 mA
V
CC
CC
25 25 25
30 30 30
V
Units
ns
3
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Capacitance T
ea
25§C, fe1 MHz (Note 2)
A
Symbol Parameter Conditions Typ Max Units
C
IN
C
OUT
Input Capacitance V
Output Capacitance V
e
0V 9 15 pF
IN
e
0V 12 15 pF
OUT
AC Test Conditions
Output Load 1 TTL Gate and
Input Rise and Fall Times
e
C
100 pF (Note 8)
L
s
5ns
Input Pulse Levels 0.45V to 2.4V
Timing Measurement Reference Level
Inputs 0.8V and 2V
Outputs 0.8V and 2V
AC Waveforms (Notes 6, 7, and 9)
TL/D/11367– 3
Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE
Note 4: The t
Note 5: TRI-STATE may be attained using OE
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 mF ceramic capacitor be used on
every device between V
Note 7: The outputs must be restricted to V
Note 8: 1 TTL Gate: I
Note 9: V
Note 10: Inputs and outputs can undershoot to
Note 11: CMOS input: V
may be delayed up to t
and tCFcompare level is determined as follows:
DF
High to TRI-STATE
Low to TRI-STATE, the measured V
: 100 pF includes fixture capacitance.
C
L
PP
, the measured V
É
and GND.
CC
e
1.6 mA, I
OL
may be connected to VCCexcept during programming.
e
IL
b
ACC
OH1
OL1
eb
OH
GNDg0.3V, V
tOEafter the falling edge of CE without impacting t
(DC)b0.10V;
(DC)a0.10V.
or CE.
a
1.0V to avoid latch-up and device damage.
CC
400 mA.
b
2.0V for 20 ns Max.
e
g
V
IH
0.3V.
CC
ACC
.
4
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Programming Waveform (Note 3)
TL/D/11367– 4
5
Page 6
Programming Characteristics (Notes 1, 2,3&4)
Symbol Parameter Conditions Min Typ Max Units
t
AS
t
OES
t
DS
t
VPS
t
VCS
t
AH
t
DH
t
DF
t
PW
t
OE
I
PP
I
CC
T
A
V
CC
V
PP
t
FR
V
IL
V
IH
t
IN
t
OUT
Note 1: National’s standard product warranty applies only to devices programmed to specifications described herein.
Note 2: V
board with voltage applied to V
Note 3: The maximum absolute allowable voltage which may be applied to the V
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 mF capacitor is required across VPP,VCCto GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Progam Algorithm, at typical power supply voltages and timings.
Note 5: During power up the CE
Address Setup Time 1 ms
OE Setup Time 1 ms
Data Setup Time 1 ms
VPPSetup Time 1 ms
VCCSetup Time 1 ms
Address Hold Time 0 ms
Data Hold Time 1 ms
Output Enable to Output Float Delay CE/PGMeV
IH
060ns
Program Pulse Width 95 100 105 ms
Data Valid from OE CE/PGMeV
VPPSupply Current during
Programming Pulse
CE
/PGMeV
IH
IL
100 ns
30 mA
VCCSupply Current 30 mA
Temperature Ambient 20 25 30
Power Supply Voltage 6.0 6.25 6.5 V
Programming Supply Voltage 12.5 12.75 13.0 V
Input Rise, Fall Time 5 ns
Input Low Voltage 0.0 0.45 V
Input High Voltage 2.4 4.0 V
Input Timing Reference Voltage 0.8 2.0 V
Output Timing Reference Voltage 0.8 2.0 V
must be applied simultaneously or before VPPand removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a
CC
or VCC.
PP
/PGM pin must be brought high (tVIH) either coincident with or before power is applied to VPP.
pin during programming is 14V. Care must be taken when switching the V
PP
C
§
PP
6
Page 7
Fast Programming Algorithm Flow Chart
FIGURE 1
TL/D/11367– 5
7
Page 8
Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are
at TTL levels. The power supplies required are V
V
. The VPPpower supply must be at 12.75V during the
PP
three programming modes, and must be at 5V in the other
three modes. The V
ing the three programming modes, and at 5V in the other
power supply must be at 6.25V dur-
CC
three modes.
Read Mode
The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE
used for device selection. Output Enable (OE
/PGM) is the power control and should be
) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (t
from CE
to output (tCE). Data is available at the outputs t
) is equal to the delay
ACC
after the falling edge of OE, assuming that CE/PGM has
been low and addresses have been stable for at least t
t
.
OE
Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from of 165 mW to
0.55 mW. The EPROM is placed in the standby mode by
applying a CMOS high signal to the CE
/PGM input. When in
standby mode, the outputs are in a high impedance state,
independent of the OE
input.
Output Disable
The EPROM is placed in output disable by applying a TTL
high signal to the OE
input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI-STATE).
Output OR-Typing
Because the EPROM is usually used in larger memory arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recommended that CE
device selecting function, while OE
/PGM be decoded and used as the primary
be made a common
connection to all devices in the array and connected to the
READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 1 (V
EPROM.
) will damage the
PP
Initially, and after each erasure, all bits of the EPROM are in
the ‘‘1’s’’ state. Data is introduced by selectively programming ‘‘0’s’’ into the desired bit locations. Although only
‘‘0’s’’ will be programmed, both ‘‘1’s’’ and ‘‘0’s’’ can be pre-
CC
and
OE
ACC
sented in the data word. The only way to change a ‘‘0’’ to a
‘‘1’’ is by ultraviolet light erasure.
The EPROM is in the programming mode when the V
power supply is at 12.75V and OE is at VIH. It is required
that at least a 0.1 mF capacitor be placed across V
to ground to suppress spurious voltage transients which
may damage the device. The data to be programmed is
applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE
/PGM input. A program
pulse must be applied at each address location to be programmed. The EPROM is programmed with the Fast Programming Algorithm shown in
Figure 1
. Each Address is
programmed with a series of 100 ms pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100 m s pulse.
The EPROM must not be programmed with a DC signal applied to the CE
Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of the
/PGM input.
programming requirements. Like inputs of the parallel
EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied
to the CE/PGM input programs the paralleled EPROM.
Program Inhibit
Programming multiple EPROMs in parallel with different
data is also easily accomplished. Except for CE
like inputs (including OE
) of the parallel EPROMs may be
common. A TTL low level program pulse applied to an
EPROM’s CE
that EPROM. A TTL high level CE
/PGM input with VPPat 12.75V will program
/PGM input inhibits the
other EPROMs from being programmed.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with V
V
, except during programming and program verify.
CC
at 12.75V. VPPmust be at
PP
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the generation of photo currents.
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s identification code to aid
in programming. When the device is inserted in an EPROM
programmer socket, the programmer reads the code and
then automatically calls up the specific programming algorithm for the part. This automatic programming control is
only possible with programmers which have the capability of
reading the code.
The Manufacturer’s Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for NM27P040 is ‘‘8F08’’, where ‘‘8F’’ designates that
PP
PP,VCC
/PGM all
8
Page 9
Functional Description (Continued)
it is made by National Semiconductor, and ‘‘08’’ designates
a 4 Megabit (512K x 8) part.
g
The code is accessed by applying 12V
pin A9. Addresses A1–A8, A10 –A18, and all control pins
are held at V
facturer’s code, and held at V
code is read on the eight data pins, O
access is only guaranteed at 25
. Address pin A0 is held at VILfor the manu-
IL
IH
Cg5§C.
§
ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Ð). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Ж4000Рrange.
The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537Ð. The integrated dose (i.e., UV intensity X
exposure time) for erasure should be a minimum of
15W-sec/cm
2
.
The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.
An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increase as the square of the distance from the lamp. (If distance is doubled the erasure time
increases by factor of 4.) Lamps lose intensity as they age.
When a lamp is changed, the distance has changed, or the
lamp has aged, the system should be checked to make cer-
Pins
CE
Mode
Read V
Output Disable X V
Standby V
Programming V
Program Verify V
Program Inhibit V
Note 1: X can be VILor V
H
0.5V to address
for the device code. The
. Proper code
0–O7
TABLE I. Modes Selection
/PGM OE V
IL
IH
IL
IH
IH
V
IL
IH
X X 5.0V High Z
V
IH
V
IL
V
IH
tain full erasure is occurring. Incomplete erasure will cause
symptoms that can be misleading. Programmers, components, and even system designs have been erroneously
suspected when incomplete erasure was the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, I
has three segments that are of interest to the system de-
CC
signer: the standby current level, the active current level,
and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance
loading of the device. The associated V
peaks can be suppressed by properly selected decoupling
transient voltage
CC
capacitors. It is recommended that at least a 0.1 mF ceramic
capacitor be used on every device between V
This should be a high frequency capacitor of low inherent
and GND.
CC
inductance. In addition, at least a 4.7 mF bulk electrolytic
capacitor should be used between V
eight devices. The bulk capacitor should be located near
and GND for each
CC
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
Mode Selection
The modes of operation of the NM27P040 are listed in Table I. A single 5V power supply is required in the read mode.
All inputs are TTL levels except for V
signature.
PP
V
CC
X 5.0V D
(Note 1)
X 5.0V High Z
12.75V 6.25V D
12.75V 6.25V D
12.75V 6.25V High Z
and A9 for device
PP
Outputs
OUT
IN
OUT
,
TABLE II. Manufacturer’s Identification Code
Pins
A0 A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex
(12) (26) (21) (20) (19) (18) (17) (15) (14) (13) Data
Manufacturer Code VIL12V100011118F
Device Code VIH12V0000100008
9
Page 10
Physical Dimensions inches (millimeters)
32-Lead EPROM Ceramic Dual-In-Line Package (JQ)
Order Number NM27P040QXXX
NS Package Number J32AQ
LIFE SUPPORT POLICY
NM27P040 4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
Arlington, TX 76017 Email: [email protected] Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (
Fax: 1(800) 737-7018 English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Fran3ais Tel: (
Italiano Tel: (
a
49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
a
49) 0-180-530 85 85 Tsimshatsui, Kowloon
a
49) 0-180-532 78 32 Hong Kong
a
49) 0-180-532 93 58 Tel: (852) 2737-1600
a
49) 0-180-534 16 80 Fax: (852) 2736-9960
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