Page 1
INTEGRATED CIRCUITS
74F256
Dual addressable latch
Product specification
IC15 Data Handbook
1988 Nov 29
Page 2
Philips Semiconductors Product specification
74F256Dual addressable latch
FEA TURES
•Combines dual demultiplexer and 8-bit latch
•Serial-to-parallel capability
•Output from each storage bit available
•Random (addressable) data entry
•Easily expandable
•Common reset input
•Useful as dual 1-of-4 active High decoder
DESCRIPTION
The 74F256 dual addressable latch has four distinct modes of
operation which are selectable by controlling the Master Reset (MR
and Enable (E
mode, data at the Data inputs is written into the addressed latches.
The addressed latches will follow the Data input with all
unaddressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous states and are
unaffected by the Data or Address inputs. To eliminate the possibility
of entering erroneous data in the latches, the enable should be held
High (inactive) while the address lines are changing. In the dual
1-of-4 decoding or demultiplexing mode (MR
outputs will follow the level of the Data inputs, with all other outputs
Low. In the Master Reset mode, all outputs are Low and unaffected
by the Address and Data inputs.
) inputs (see Function Table). In the addressable latch
=E=Low), addressed
PIN CONFIGURATION
)
TYPE TYPICAL
PROPAGATION
74F256 7.0ns 28mA
ORDERING INFORMATION
DESCRIPTION COMMERCIAL RANGE
16-pin plastic DIP N74F256N SOT38-4
16-pin plastic SO N74F256D SOT109-1
1
A0
2
A1
3
Da
4
Q0a
5
Q1a
6
Q2a
Q3a
GND
DELAY
ORDER CODE
VCC = 5V ±10%,
T
amb
16
15
14
13
12
11
107
98
SF00805
CURRENT (TOTAL)
= 0°C to +70°C
V
CC
MR
E
Db
Q3b
Q2b
Q1b
Q0b
TYPICAL SUPPL Y
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION 74F (U.L.)
HIGH/LOW
Da, Db Port A, port B inputs 1.0/1.0 20µA/0.6mA
A0, A1 Address inputs 1.0/1.0 20µA/0.6mA
E Enable (active Low) 1.0/1.0 20µA/0.6mA
MR Master Reset inputs (active Low) 1.0/1.0 20µA/0.6mA
Q0a – Q3a Port A outputs 50/33 1.0mA/20mA
Q0b – Q3b Port B outputs 50/33 1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE
HIGH/LOW
1988 Nov 29 853–0359 95207
2
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Philips Semiconductors Product specification
OPERATING MODE
Addressable Latch
74F256Dual addressable latch
LOGIC SYMBOL
E
14
A0
1
A1
2
MR
15
VCC = Pin 16
GND = Pin 8
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
313
Da Db
4567 9101112
SF00806
IEC/IEEE SYMBOL
1
2
14
0
G
1
3
13
15
0
3
Z5
Z6
G4
5, 7D
1
0
1
2
3
6, 8D
1
0
1
2
3
C7
4R
C8
4R
4
5
6
7
9
10
11
12
SF00807
FUNCTION TABLE
INPUTS OUTPUTS
MR E D A0 A1 Q0 Q1 Q2 Q3
L H X X X L L L L Master Reset
L L d L L Q=d L L L
L L d H L L Q=d L L
L L d L H L L Q=d L
L L d H H L L L Q=d
H H X X X q0 q1 q2 q3 Store (do nothing)
H L d L L Q=d q1 q2 q3
H L d H L q0 Q=d q2 q3
H L d L H q0 q1 Q=d q3
H L d H H q0 q1 q2 Q=d
H = High voltage level
L = Low voltage level
X = Don’t care
d = High or Low data one setup time prior to the Low-to-High Enable transition
q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.
Demultiplex (active-High decoder when D=H)
1988 Nov 29
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Philips Semiconductors Product specification
74F256Dual addressable latch
LOGIC DIAGRAM
12
Q3b
11
Q2b
10
Q1b
9
Q0b
7
Q3a
6
Q2a
13
Db
3
Da
14
E
5
Q1a
MR
A1
A0
VCC = Pin 16
GND = Pin 8
1988 Nov 29
15
2
1
4
SF00808
Q0a
4
Page 5
Philips Semiconductors Product specification
74F256Dual addressable latch
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL PARAMETER RATING UNIT
V
V
V
I
OUT
T
T
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
V
I
I
T
Supply voltage
CC
Input voltage –0.5 to +7.0 V
IN
Input current
I
IN
Voltage applied to output in High output state
OUT
Current applied to output in Low output state
Operating free-air temperature range 0 to +70
amb
Storage temperature range –65 to +150
stg
PARAMETER
–0.5 to +7.0 V
–30 to +5 mA
–0.5 to V
40 mA
LIMITS UNIT
MIN NOM MAX
V
I
OH
OL
amb
Supply voltage
CC
High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
Input clamp current –18 mA
IK
High-level output current –1 mA
Low-level output current 20 mA
Operating free-air temperature range 0 70
4.5 5.0 5.5 V
CC
V
°C
°C
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
V
V
V
I
I
I
OS
I
CC
High-level output voltage VCC = MIN, VIL = MAX, ±10%V
OH
Low-level output voltage VCC = MIN, VIL = MAX, ±10%V
OL
Input clamp voltage VCC = MIN, II = I
IK
I
Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA
I
High-level input current VCC = MAX, VI = 2.7V 20 µA
IH
Low-level input current VCC = MAX, VI = 0.5V –0.6 mA
IL
Short-circuit output current
Supply current (total) I
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
3. T o reduce the ef fect of external noise during test.
4. Not more than one output should be shorted at a time. For testing I
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
PARAMETER TEST LIMITS UNIT
1
MIN TYP2MAX
2.5 V
CC
2.7 3.4 V
CC
CC
CC
0.35 0.50 V
0.35 0.50 V
–0.73 -1.2 V
33 60 mA
3
= 5V, T
CC
OS
= 25°C.
amb
tests should be performed last.
CONDITIONS
VIH = MIN, IOL = MAX ±5%V
VIH = MIN, IOL = MAX ±5%V
IK
VCC = MAX –60 –150 mA
CCHVCC
I
CCL
= MAX 21 42 mA
, the use of High-speed test apparatus and/or sample-and-hold
OS
1988 Nov 29
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Philips Semiconductors Product specification
74F256Dual addressable latch
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
= +25°C T
amb
SYMBOL PARAMETER TEST VCC = +5V VCC = +5V ± 10% UNIT
CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω
MIN TYP MAX MIN MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
Propagation delay
Dn to Qn
Propagation delay
E to Qn
Propagation delay
An to Qn
Propagation delay
MR to Qn
Waveform 2
Waveform 1
Waveform 3
4.0
3.0
4.5
3.0
5.0
4.5
7.0
5.0
8.0
5.0
10.0
8.5
9.5
7.0
10.5
7.0
14.0
9.5
Waveform 4 5.0 7.0 9.0 4.5 10.0 ns
AC SETUP REQUIREMENTS
LIMITS
T
= +25°C T
SYMBOL PARAMETER TEST VCC = +5.0V
CONDITION CL = 50pF, RL = 500Ω CL= 50pF, RL = 500Ω
ts(H)
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
Setup time, High or Low
Dn to E
Hold time, High or Low
Dn to E
Setup time, High or Low
1
An to E
Hold time, High or Low
2
An to E
Waveform 5 3.0
Waveform 5 0
Waveform 6 2.0
Waveform 6 0
tw(L) E Pulse width, Low Waveform 1 7.5 8.0 ns
tw(L) MR Pulse width, Low Waveform 4 3.0 3.0 ns
NOTES:
1. The Address to Enable setup time is the time before the High-to-Low Enable transition that the Address must be stable so that the correct
latch is addressed and the other latches are not affected.
2. The Address to Enable hold time is the time before the Low-to-High Enable transition that the Address must be stable so that the correct
latch is addressed and the other latches are not affected.
amb
MIN TYP MAX MIN MAX
6.5
0
2.0
0
= 0°C to +70°C
amb
4.0
2.5
4.5
3.0
5.0
4.0
= 0°C to +70°C
amb
10.0
7.5
12.0
7.5
14.5
10.0
VCC = +5.0V ± 10%
3.0
7.0
0
0
2.0
2.0
0
0
ns
ns
ns
UNIT
ns
ns
ns
ns
1988 Nov 29
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Philips Semiconductors Product specification
74F256Dual addressable latch
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
tW(L)
E
Q
n
t
PHL
V
M
V
M
t
PLH
V
M
Waveform 1. Propagation Delay,
Enable Input to Output, Enable Pulse Width
An
Qn
V
M
t
PHL
V
M
V
M
t
PLH
Waveform 3. Propagation Delay Address to Output
Dn
V
Qn
V
M
M
V
E
M
Q=D Q=D
V
M
ts(L) th(L)ts(H) th(H)
V
M
SF00809
V
M
V
M
SF00811
V
M
V
t
PHL
M
V
M
Dn
Qn
Waveform 2. Propagation Delay,
Data to Output
t
PHL
tW(L)
V
M
MR
Qn
V
M
Waveform 4. Master Reset Pulse Width and
Master Reset to Output Delay
V
M
An
E
V
t
s
M
Address Stable
Waveform 6. Address Setup and Hold Times
V
M
t
PLH
V
M
SF00810
V
M
SF00812
V
M
t
h
V
M
SF00814
1988 Nov 29
SF00813
Waveform 5. Data Setup and Hold Times
7
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Philips Semiconductors Product specification
74F256Dual addressable latch
TEST CIRCUIT AND WAVEFORMS
V
CC
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
R
C
L
L
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
= Load resistor;
R
L
see AC ELECTRICAL CHARACTERISTICS for value.
C
= Load capacitance includes jig and probe capacitance;
L
see AC ELECTRICAL CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
of
NEGATIVE
PULSE
POSITIVE
PULSE
family
74F
90%
10%
amplitude
t
w
V
M
10%
)
t
THL (tf
)
t
TLH (tr
90%
V
M
t
TLH (tr
t
THL (tf
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
V
rep. rate
M
3.0V 1.5V
1MHz 500ns
10%
)
)
90%
t
w
V
M
V
M
90%
10%
t
TLHtTHL
2.5ns 2.5ns
AMP (V)
0V
AMP (V)
0V
SF00006
1988 Nov 29
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Philips Semiconductors Product specification
74F256Dual addressable latch
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
1988 Nov 29
9
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Philips Semiconductors Product specification
74F256Dual addressable latch
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
1988 Nov 29
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Philips Semiconductors Product specification
74F256Dual addressable latch
NOTES
1988 Nov 29
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Philips Semiconductors Product specification
74F256Dual addressable latch
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05106
yyyy mmm dd
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