Datasheet MXD1000C-D100, MXD1000C-D125, MXD1000C-D150, MXD1000PD100, MXD1000PD125 Datasheet (Maxim)

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone].
For small orders, phone [phone] ext. 3468.

_______________General Description

The MXD1000 silicon delay line offers five equally
spaced taps with delays ranging from 4ns to 500ns and
a nominal accuracy of ±2ns or ±5%, whichever is
greater. Relative to hybrid solutions, this device offers
enhanced performance and higher reliability, and
reduces overall cost. Each tap can drive up to ten 74LS
loads.

The MXD1000 is available in multiple versions, each
offering a different combination of delay times. It comes
in the space-saving 8-pin µMAX package, as well as an
8-pin SO or DIP, allowing full compatibility with the
DS1000 and other delay line products.

________________________Applications

Clock Synchronization
Digital Systems

____________________________Features

♦ Improved Second Source to DS1000
♦ Available in Space-Saving 8-Pin µMAX Package
♦ 20mA Supply Current (vs. Dallas’ 35mA)
♦ Low Cost
♦ Delay Tolerance of ±2ns or ±5%, whichever is

Greater

♦ TTL/CMOS-Compatible Logic
♦ Leading- and Trailing-Edge Accuracy
♦ Custom Delays Available

MXD1000

5-Tap Silicon Delay Line

________________________________________________________________

Maxim Integrated Products

1

TAP3

TAP5GND

1
2

87V

CC

TAP1TAP2

TAP4

IN

DIP/SO/µMAX

TOP VIEW

3

4

6

5

MXD1000

14
13
12
11
10

9
8

1
2
3
4
5
6
7

V

CC

N.C.
TAP1
N.C.TAP2

N.C.

N.C.

IN

MXD1000

TAP3
N.C.
TAP5GND

TAP4

N.C.

DIP

16
15
14
13
12
11
10

9

1
2
3
4
5
6
7
8

IN V

CC

N.C.
N.C.
TAP1
N.C.
TAP3
N.C.
TAP5

MXD1000

SO

N.C.
N.C.

TAP4

TAP2

N.C.

N.C.

GND

__________________________________________________________Pin Configurations

19-1310; Rev 0; 10/97

PART

MXD1000C/D__
MXD1000PA__
MXD1000PD__ -40°C to +85°C

-40°C to +85°C

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

Dice*
8 Plastic DIP
14 Plastic DIP

______________Ordering Information

*

Dice are tested at TA= +25°C.
Note: To complete the ordering information, fill in the blank
with the part number extension from the Part Number and Delay
Times table (located at the end of this data sheet) to indicate
the desired delay per output.

Functional Diagram appears at end of data sheet.

MXD1000SA__
MXD1000SE__
MXD1000UA__ -40°C to +85°C

-40°C to +85°C

-40°C to +85°C 8 SO
16 Narrow SO
8 µMAX

MXD1000

5-Tap Silicon Delay Line

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VCC= +5.0V ±5%, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

TIMING CHARACTERISTICS

(VCC= +5.0V ±5%, TA = +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Note 1: Contact factory for ordering information.
Note 2: Specifications to -40°C are guaranteed by design, not production tested.
Note 3: All voltages referenced to GND.
Note 4: Measured with output open.
Note 5:

ICCis a function of frequency and TAP5 delay. Only an MXD1000_ _25 operating with a 40ns period and VCC= +5.25V will have
an I

CC

= 75mA. For example, an MXD1000_ _100 will never exceed 30mA. See Supply Current vs. Input Frequency in

Typical

Operating Characteristics.

Note 6: Guaranteed by design.
Note 7: Pulse width and/or period specifications may be exceeded, but accuracy is application sensitive (i.e., layout, decoupling,

etc.). The device will remain functional with pulse widths down to 20% of TAP5 delay, and input periods as short as 2(t

WI

).

Note 8: Typical initial tolerances are ± with respect to the nominal value at +25°C and VCC= 5V.
Note 9: Typical temperature tolerance is ± with respect to the initial delay value over a temperature range of -40°C to +85°C.
Note 10: The delay will also vary with supply voltage, typically by less than 4% over the supply range of V

CC

= +4.75V to +5.25V.

Note 11: All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP1 slows down, all other

taps will also slow down; i.e., TAP3 can never be faster than TAP2.

V

CC

to GND..............................................................-0.5V to +6V

All Other Pins..............................................-0.5V to (V

CC

+ 0.5V)

Short-Circuit Output Current (1sec)....................................50mA

Continuous Power Dissipation (T

A

= +70°C)

8-Pin Plastic DIP (derate 9.1mW/°C above +70°C) .......727mW

14-Pin Plastic DIP (derate 10.0mW/°C above +70°C) ...800mW

8-Pin SO (derate 5.9mW/°C above +70°C)....................471mW

16-Pin Narrow SO (derate 8.7mW/°C above +70°C).....696mW

8-Pin µMAX (derate 4.1mW/°C above +70°C)...............330mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range.............................-65°C to +160°C

Lead Temperature (soldering, 10sec).............................+300°C

(Note 3)

(Note 3)

(Note 3)

TA= +25°C (Note 6)

0V ≤ VIN≤ V

CC

VCC= 5.25V, period = minimum (Notes 4, 5)
VCC= 4.75V, VOH= 4.0V
VCC= 4.75V, VOL= 0.5V

CONDITIONS

V0.8V

IL

Input Voltage Low

V2.2V

IH

V4.75 5.00 5.25V

CC

Supply Voltage
Input Voltage High

pF5 10C

IN

Input Capacitance

µA-1 1I

L

Input Leakage Current

mA20 75I

CC

Active Current

mA-1I

OH

Output Current High

mA12I

OL

Output Current Low

UNITSMIN TYP MAXSYMBOLPARAMETER

(Notes 1, 8–12)

(Notes 1, 8–12)

(Note 7)

(Note 7)

CONDITIONS

ns

See

Part Number and

Delay Times

table

t

PHL

Input-to-Tap Delay
(trailing edge)

ns

See

Part Number and

Delay Times

table

t

PLH

ns

40% of TAP5

t

PLH

t

WI

Input Pulse Width
Input-to-Tap Delay

(leading edge)

ms100t

PU

Power-Up Time

ns4(tWI)Period

UNITSMIN TYP MAXSYMBOLPARAMETER

MXD1000

5-Tap Silicon Delay Line

_______________________________________________________________________________________

3

__________________________________________Typical Operating Characteristics

(VCC= +5V, TA= +25°C, unless otherwise noted.)

-2.0

-1.0

-1.5

0

-0.5

1.5

1.0

0.5

2.0

-40 0-20 20 40 60 80 100

MXD1000_ _75

PERCENT CHANGE IN DELAY

vs. TEMPERATURE

MXD1000 TOC01

TEMPERATURE (°C)

% CHANGE IN DELAY (TAP2)

t

PLH

RELATIVE TO NOMINAL (+25°C)

t

PHL

t

PHL

t

PLH

-2.0

-1.0

-1.5

0

-0.5

1.5

1.0

0.5

2.0

-40 0-20 20 40 60 80 100

MXD1000_ _100 TO MXD1000_ _200

PERCENT CHANGE IN DELAY

vs. TEMPERATURE

MXD1000 TOC2

TEMPERATURE (°C)

% CHANGE IN DELAY (TAP2)

t

PHL

RELATIVE TO NOMINAL (+25°C)

t

PHL

t

PLH

t

PLH

-2.0

-1.0

-1.5

0

-0.5

1.5

1.0

0.5

2.0

-40 0-20 20 40 60 80 100

MXD1000_ _250 TO MXD1000_ _500

PERCENT CHANGE IN DELAY

vs. TEMPERATURE

MXD1000 TOC03

TEMPERATURE (°C)

% CHANGE IN DELAY (TAP2)

t

PHL

RELATIVE TO NOMINAL (+25°C)

t

PLH

t

PLH

t

PHL

20

8

10

12

14

16

18

0.001 0.01 0.1 1 10 100

ACTIVE CURRENT

vs. FREQUENCY

MXD1000-04

FREQUENCY (MHz)

ACTIVE CURRENT (mA)

MXD1000_ _50

MXD1000_ _75

MXD1000_ _200

MXD1000_ _500

50% DUTY CYCLE

MXD1000

5-Tap Silicon Delay Line

4 _______________________________________________________________________________________

______________________________________________________________Pin Description

1 1 Signal Input

14-PIN DIP

FUNCTION

8-PIN

DIP/SO/µMAX

NAME

16-PIN SO

2 4 40% of specified maximum delay4

1 IN

TAP2

3

PIN

6 80% of specified maximum delay

4 7 Device Ground8

6 TAP4

GND
5 8 100% of maximum specified delay
6 10 60% of specified maximum delay11

9 TAP5

TAP3
7 12 20% of specified maximum delay
8 14 Power-Supply Input16

13 TAP1

V

CC

—

2, 3, 5, 9, 11,

13

No Connection. Not internally connected.

2, 3, 5, 7, 10,

12, 14, 15

N.C.

Note: Maximum delay is determined by the part number extension. See the Part Number and Delay Times table for more information.

_______________Definitions of Terms

Period: The time elapsed between the first pulse’s
leading edge and the following pulse’s leading edge.

Pulse Width (tWI): The time elapsed on the pulse
between the 1.5V level on the leading edge and the

1.5V level on the trailing edge, or vice-versa.

Input Rise Time (t

RISE

): The time elapsed between

the 20% and 80% points on the input pulse’s leading
edge.

Input Fall Time (t

FALL

): The time elapsed between

the 80% and 20% points on the input pulse’s trailing
edge.

Time Delay, Rising (t

PLH

): The time elapsed between

the 1.5V level on the input pulse’s leading edge and the
corresponding output pulse’s leading edge.

Time Delay, Falling (t

PHL

): The time elapsed between

the 1.5V level on the input pulse’s trailing edge and the
corresponding output pulse’s trailing edge.

____________________Test Conditions

Ambient Temperature: +25°C ±3°C
Supply Voltage (VCC): +5V ±0.1V
Input Pulse: High = 3.0V ±0.1V

Low = 0.0V ±0.1V
Source Impedance: 50Ω max
Rise and Fall Times: 3.0ns max
Pulse Width: 500ns max (1ns for -500)
Period: 1µs (2ns for -500)
Each output is loaded with a 74F04 input gate. Delay is

measured at the 1.5V level on the rising and falling
edges. The time delay due to the 74F04 is subtracted
from the measured delay.

__________Applications Information

Supply and Temperature

Effects on Delay

Variations in supply voltage may affect the MXD1000’s
fixed tap delays. Supply voltages beyond the specified
range may result with larger variations. The devices are
internally compensated to reduce the effects of temper­ature variations. Although these devices might vary with
supply and temperature, the delays vary unilaterally,
which suggests that TAP3 can never be faster than
TAP2.

Capacitance and Loading

Effects on Delay

The output load can affect the tap delays. Larger
capacitances tend to lengthen the rising and falling
edges, thus increasing the tap delays. As the taps are
loaded with other logic devices, the increased load will
increase the tap delays.

Board Layout Considerations/Decoupling

The device should be driven with a source that can
deliver the required current for proper operation. A

0.1µF ceramic bypassing capacitor could be used. The
board should be designed to reduce stray capaci­tance.

MXD1000

5-Tap Silicon Delay Line

_______________________________________________________________________________________ 5

V

IL

V

IH

PERIOD

t

RISE

IN

OUT

0.6V

0.6V

2.4V

2.4V

1.5V

1.5V 1.5V

1.5V

1.5V

t

FALL

t

WI

t

PLH

t

PHL

20%

50Ω

0.1µF

V

CC

IN

(+5V)

20%

TIME

MEASUREMENT

UNIT

TAP1

TAP2

TAP3

TAP4

TAP5

74FO4

20%

20%

20%

MXD1000

Figure 1. Timing Diagram

Figure 2. Test Circuit

MXD1000

5-Tap Silicon Delay Line

6 _______________________________________________________________________________________

20

(Note 1)

4 8

TAP2

2 1 12 16

TAP4

2 1

TAP3

2

TAP1

1 20

TAP5

2 2 11

25

(Note 1)

5 10 2 1 15 20 2 12 1 252 2 11

30

(Note 1)

6 12 2 1 18 24 2 12 1 302 2 11

35 7 14 2 1 21 28 2 12 1 352 2 1.11
40 8 16 2 1 24 32 2 12 1 402 2 1.21
45 9 18 2 1 27 36 2 1.12 1 452 2.3 1.41
50 10 20 2 1 30 40 2 1.22 1 502 2.5 1.51
60 12 24 2 1 36 48 2.4 1.52 1.1 602 3 1.81

75 15 30 2 1 45 60 3 1.82.3 1.4 752 3.8 2.31
100 20 40 2 1.2 60 80 4 2.43 1.8 1002 5 31
125 25 50 2.5 1.5 75 100 5 33.8 2.3 1252 6.3 3.81
150 30 60 3 1.8 90 120 6 3.64.5 2.7 1502 7.5 4.51
175 35 70 3.5 2.1 105 140 7 4.25.3 3.2 1752 8.8 5.31.1
200 40 80 4 2.4 120 160 8 4.86 3.6 2002 10 61.2
250 50 100 5 3 150 200 10 67.5 4.5 2502.5 12.5 7.51.5
500 100 200 10 6 300 400 20 1215 9 5005 25 153

_________________________________________________Part Number and Delay Times

Nom.
Delay

(ns)

Nom.
Delay

(ns)

Tolerance

(ns)

Part

Number

Extension

(MXD1000__)

Nom.
Delay

(ns)

Nom.

Delay

(ns)

Tolerance

(ns)

Tolerance

(ns)

Tolerance

(ns)

Nom.

Delay

(ns)

Tolerance

(ns)

Init. Temp. Init. Temp. Init. Temp. Init. Temp. Init. Temp.

Note 1: Contact factory for ordering information.

MXD1000

5-Tap Silicon Delay Line

_______________________________________________________________________________________ 7

___________________Chip Information

TRANSISTOR COUNT: 824

MXD1000

TAP1 TAP2 TAP3 TAP4 TAP5

IN

20% 20% 20% 20% 20%

_________________________________________________________Functional Diagram

MXD1000

5-Tap Silicon Delay Line

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

8

_____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

________________________________________________________Package Information

8LUMAXD.EPS