Datasheet MT46V32M4TG-75Z, MT46V16M8TG-75, MT46V8M16TG-8 Datasheet (MICRON)

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

‡

DOUBLE DATA RATE (DDR) SDRAM

FEATURES

•VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V

• Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two – one per byte)

• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; centeraligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data (x16 has two – one per byte)

• x16 has programmable IOL/IOH option

• Programmable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• Longer lead TSOP for improved reliability (OCPL)

• 2.5V I/O (SSTL_2 compatible)

OPTIONS MARKING

• Configuration 32 Meg x 4 (8 Meg x 4 x 4 banks) 32M4 16 Meg x 8 (4 Meg x 8 x 4 banks) 16M8 8 Meg x 16 (2 Meg x 16 x 4 banks) 8M16

MT46V32M4 – 8 Meg x 4 x 4 banks MT46V16M8 – 4 Meg x 8 x 4 banks MT46V8M16 – 2 Meg x 16 x 4 banks

For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/datasheets

PIN ASSIGNMENT (TOP VIEW)

66-Pin TSOP

V

DD

DQ0

V

SS

V

DD

DQ1

V

SS

V

DD

V

WE# CAS# RAS#

CS#

BA0 BA1

A10/AP

V

NC

NC NC

NC

NC NC

NC

A0 A1 A2 A3

DD

Q

DD

x8x4

V

DQ0

V

DD

DQ1

V

SS

DQ2

V

DD

DQ3

V

SS

V

DD

V

DNU

WE# CAS# RAS#

CS#

BA0 BA1

A10/AP

V

DD

NC

NC NC

DD

NC

A0 A1 A2 A3

DD

Q

x16

V

DQ0

VDDQ

DQ1

DQ2

VssQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VssQ

DQ7

V

DD

LDQS

V

DNU

LDM

WE# CAS# RAS#

CS#

BA0 BA1

A10/AP

V

1

DD

2 3 4 5 6 7 8 9 10 11 12 13 14

NC

15

Q

16 17

NC

18

DD

19 20 21 22 23 24 25

NC

26 27 28 29

A0

30

A1

31

A2

32

A3

33

DD

66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34

x16 V

SS

DQ15

V

SS

DQ14 DQ13

V

DD

DQ12 DQ11

V

SS

DQ10 DQ9

V

DD

DQ8

NC V

SS

UDQS

DNU

V

REF

V

SS

UDM CK# CK CKE NC NC

A11 A9 A8 A7 A6 A5 A4

V

SS

Q

x8 x4

V

SS

DQ7

V

SS

Q NC

DQ6

V

DD

Q NC

DQ5

V

SS

Q NC

DQ4

V

DD

Q NC NC V

SS

Q

DQS

DNU

V

REF

V

SS

DM CK# CK CKE NC NC

A11 A9 A8 A7 A6 A5 A4

V

SS

V NC V

SS

NC

DQ3

V

DD

NC NC V

SS

NC

DQ2

V

DD

NC NC V

SS

DQS

DNU

V

REF

V

SS

DM CK# CK CKE NC NC

A11 A9 A8 A7 A6 A5 A4

V

SS

Q

• Plastic Package – OCPL 66-pin TSOP TG (400 mil width, 0.65mm pin pitch)

• Timing – Cycle Time

7.5ns @ CL = 2 (DDR266B)

7.5ns @ CL = 2.5 (DDR266B)

10ns @ CL = 2 (DDR200)

1

2

3

-75Z

-75

-8

Configuration 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks Refresh Count 4K 4K 4K Row Addressing 4K (A0–A11) 4K (A0–A11) 4K (A0–A11) Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Column Addressing 2K (A0–A9, A11) 1K (A0–A9) 512 (A0–A8)

32 Meg x 4 16 Meg x 8 8 Meg x 16

• Self Refresh Standard none

KEY TIMING PARAMETERS

Low Power L

SPEE D CLOCK RATE DATA-OUT ACCESS DQS-DQ

NOTE: 1. Supports PC2100 modules with 2-3-3 timing

2. Supports PC2100 modules with 2.5-3-3 timing

3. Supports PC1600 modules with 2-2-2 timing

‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE

SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S

PRODUCTION DATA SHEET SPECIFICATIONS.

GRADE CL = 2** CL = 2.5** WINDOW* WINDOW SKEW

-75Z 133 MHz 133 MHz 2.5ns ±0.75ns +0.5ns

-75 100 MHz 133 MHz 2.5ns ±0.75ns +0.5ns

-8 100 MHz 125 MHz 3.4ns ±0.8ns +0.6ns

*Minimum clock rate @ CL = 2 (-75Z and -8) and CL = 2.5 (-75) **CL = CAS (Read) Latency

1

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

128MB DDR SDRAM PART NUMBERS

(Note: xx= -75, -75Z, or -8)

PART NUMBER CONFIGURATION I/O DRIVE LEVEL REFRESH OPTION

MT46V32M4TG-xx 32 Meg x 4 Full Drive Standard MT46V32M4TG-xxL 32 Meg x 4 Full Drive Low Power

MT46V16M8TG-xx 16 Me g x 8 Full Drive Standard MT46V16M8TG-xxL 16 Meg x 8 Full Drive Low Power

MT46V8M16TG-xx 8 Meg x 16 Programmable Drive Standard MT46V8M16TG-xxL 8 Meg x 16 Programmable Drive Low Power

GENERAL DESCRIPTION

The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quadbank DRAM.

The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte.

The 128Mb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a

programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.

The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access.

As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.

An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full drive strength outputs are SSTL_2, Class II compatible.

NOTE 1: The functionality and the timing specifications

discussed in this data sheet are for the DLL-enabled mode of operation.

NOTE 2: Throughout the data sheet, the various figures and

text refer to DQs as “DQ.” The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided in to two bytes — the lower byte and upper byte. For the lower byte (DQ0 through DQ7) DM refers to LDM and DQS refers to LDQS; and for the upper byte (DQ8 through DQ15) DM refers to UDM and DQS refers to UDQS.

2

PIN DESCRIPTIONS

TSOP PIN NUMBERS SYMBOL TYPE DESCRIPTION

45, 46 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#.

44 CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the

internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied.

24 CS# Input Chip Select: CS# enables (registered LOW) and disables (regis-

tered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.

23, 22, 21 RAS#, CAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

WE# command being entered.

47 DM Input Input Data Mask: DM is an input mask signal for write data. Input

20, 47 LDM, UDM data is masked when DM is sampled HIGH along with that input data

during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. For the x16 , LDM is DM for DQ0DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC on x4 and x8

26, 27 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an

ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

29-32, 35-40, A0–A11 Input Address Inputs: Provide the row address for ACTIVE commands, and

28, 41 the column address and auto precharge bit (A10) for READ/WRITE

commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command.

2, 4, 5, 7, 8, 10,11, 13, 54 DQ 0–15 I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 54, 57, 60, and 63

56, 57, 59, 60, 62, 63,65 are NC for x8), (2, 4, 7, 8,10, 13, 54, 57, 59, 60, 63, and 65 are NC

for x4).

2, 5, 8, 11, 56, 59, 62, 65 DQ0–7 I/O Data Input/Output: Data bus for x8 (2, 8, 59, and 65 are NC for x4).

5, 11, 56, 62 DQ0 –3 I/O Data Input/Output: Data bus for x4.

(continued on next page)

7

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

PIN DESCRIPTIONS (continued)

TSOP PIN NUMBERS SYMBOL TYPE DESCRIPTION

51 DQS I/O Data Strobe: Output with read data, input with write data. DQS is

16, 51 LDQS, UDQS edge-aligned with read data, centered in write data. It is used to

capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS is DQS for DQ8-DQ15. Pin 16 is NC on x4 and x8.

3, 9, 15, 55, 61 VDDQ Supply DQ Power Supply: +2.5V ±0.2V. Isolated on the die for improved

noise immunity.

6, 12, 52, 58, 64 VSSQ Supply DQ Ground. Isolated on the die for improved noise immunity.

1, 18, 33 VDD Supply Power Supply: +2.5V ±0.2V.

34, 48, 66 VSS Supply Ground.

49 VREF Supply SSTL_2 reference voltage.

14, 17, 19, 25, NC – No Connect: These pins should be left unconnected.

42, 43, 53

50 DNU – Do Not Use: Must float to minimize noise.

RESERVED NC PINS

TSOP PIN NUMBERS SYMBOL TYPE DESCRIPTION

42 A12 I Address input for 256Mb and 512Mb devices. 17 A13 I Address input for 1Gb devices.

NOTE: 1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins

deemed to be of importance.

1

8

FUNCTIONAL DESCRIPTION

The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. The 128Mb DDR SDRAM is internally configured as a quad-bank DRAM.

The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.

Initialization

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD and VDDQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VDDQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command.

Once the 200µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP com-

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

mand, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal operation.

REGISTER DEFINITION

MODE REGISTER

The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 1. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing).

Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.

Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A11 specify the operating mode.

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.

9

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given con-

0

-

A7

7

M6

0

1

M10

0

-

A6 A5 A4

654

M4

M5

0

1

0

1

0

1

0

1

M8

M9

0

1

-

A3A8A2A1A0

38210

M2

M3

0

1

M7

M6-M0

0

Valid

0

Valid

-

Address Bus

Burst LengthCAS Latency BT0*0*

M1

0

1

CAS Latency

Reserved

-

Mode Register (Mx)

Burst Length

M0

M3 = 0

0

Reserved

0

1

0

1

2

2.5

2

0

4

1

8

0

Reserved

1

Reserved

0

Reserved

1

Reserved

Burst Type

Sequential

Interleaved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

M3 = 1

Reserved

2

4

8

Reserved

BA1

13

* M13 and M12 (BA0 and BA1)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

A10

BA0

A11

11

10

12

Operating Mode

A9

9

M11

Figure 1

Mode Register Definition

figuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.

TABLE 1

BURST DEFINITION

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

A0

2

4

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

8

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

NOTE: 1. For a burst length of two, A1-Ai select the two-

data-element block; A0 selects the first access within the block.

2. For a burst length of four, A2-Ai select the fourdata-element block; A0-A1 select the first access within the block.

3. For a burst length of eight, A3-Ai select the eightdata-element block; A0-A2 select the first access within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

0 0-1 0-1 1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0

10

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 2.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 2 indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

CK#

CK

COMMAND

DQS

DQ

CK#

CK

COMMAND

DQS

DQ

T0 T1 T2 T2n T3 T3n

READ NOP NOP NOP

CL = 2

T0 T1 T2 T2n T3 T3n

READ NOP NOP NOP

CL = 2.5

TABLE 2

CAS LATENCY (CL)

ALLOWABLE OPERATING

FREQUENCY (MHz)

SPEED CL = 2 CL = 2.5

-75Z 75 ≤ f ≤ 133 75 ≤ f ≤133

-75 75 ≤ f ≤ 100 75 ≤ f ≤133

-8 75 ≤ f ≤ 100 75 ≤ f ≤125

Operating Mode

The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A11 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A11 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode.

All other combinations of values for A7-A11 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ

DON’T CARETRANSITIONING DATA

Figure 2

CAS Latency

11

EXTENDED MODE REGISTER

Operating Mode

Normal Operation

All other states reserved

0–0

–

Valid

–

0

1

DLL

Enable

Disable

DLL

110

1

A9

A7

A6 A5 A4

A3A8A2A1A0

Extended Mode Register (Ex)

Address Bus

9

7

654

382

1

0

E0

0

1

Drive Strength

Normal

Reduced

E1

2

0

–

QFC Function

Disabled

Reserved

E2

3

E0

E1,

Operating Mode

A10

A11

BA1

BA0

10

11

12

13

Notes: 1. E13 and E12 (BA0 and BA1) must be “1, 0” to select the

Extended Mode Register (vs. the base Mode Register).

2. The reduced drive strength option is not supported on the x4 and x8 versions and is only available on the D3 version of the x16 device.

3. The QFC option is not supported.

E2,E3E4

0–0–0–0

–

0

–

E6E5E7E8E9

0–0

–

E10E11

DSQFC

The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, and QFC#. These functions are controlled via the bits shown in Figure 3. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.

Output Drive Strength

The normal full drive strength for all outputs are specified to be SSTL2, Class II. The x16 supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength.

The Micron 128Mb (8 Meg x16) device supports a programmable drive strength option.

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.

Figure 3

Extended Mode Register Definition

12

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

Commands

Truth Table 1 provides a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables

TRUTH TABLE 1 – COMMANDS

(Note: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES

DESELECT (NOP) H X X X X 9

NO OPERATION (NOP) L H H H X 9

ACTIVE (Select bank and activate row) L L H H Bank/Row 3

READ (Select bank and column, and start READ burst) L H L H Bank/Col 4

WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 4

BURST TERMINATE L H H L X 8

PRECHARGE (Deactivate row in bank or banks) L L H L Code 5

AUTO REFRESH or SELF REFRESH L L L H X 6, 7 (Enter self refresh mode)

LOAD MODE REGISTER L L L L Op-Code 2

appear following the Operation section; these tables provide current state/next state information.

TRUTH TABLE 1A – DM OPERATION

NAME (FUNCTION) DM DQs NOTES

Write Enable L Valid 10

Write Inhibit HX 10

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 provide the op-code to be written to the selected mode register.

3. BA0-BA1 provide bank address and A0-A11 provide row address.

4. BA0-BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, 9 for x8, and 9, 11 for x4); A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.

5. A10 LOW: BA0-BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.

9. DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.

13

DESELECT

The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (CS# LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER

The mode registers are loaded via inputs A0-A11. See mode register descriptions in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until

t

MRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai (where i = 8 for x16, 9 for x8, or 9, 11 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0Ai (where i = 8 for x16, 9 for x8, or 9, 11 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging.

AUTO PRECHARGE

Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command.

Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS(MIN), as described for each burst type in the Operation section of this data sheet. The user must not issue another command to the same bank until the precharge time (tRP) is completed.

BURST TERMINATE

The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. The open page which the READ burst was terminated from remains open.

14

AUTO REFRESH

AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required.

The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during an AUTO REFRESH command. The 128Mb DDR SDRAM requires AUTO REFRESH cycles at an average interval of 15.625µs (maximum).

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 15.6µs (140.6µs). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in

t

AC between updates.

Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (High) during the AUTO REFRESH period. The AUTO RE-

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

FRESH period begins when the AUTO REFRESH command is registered and ends

SELF REFRESH

The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are “Don’t Care” during SELF REFRESH.

The procedure for exiting self refresh requires a sequence of commands. First, CK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for

t

XSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.

t

RFC later.

15

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

Operations

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated, as shown in Figure 4.

After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 133 MHz clock (7.5ns period) results in 2.7 clocks rounded to 3. This is reflected in Figure 5, which covers any case where 2 < tRCD (MIN)/tCK ≤ 3. (Figure 5 also shows the same case for tRCD; the same procedure is used to convert other specification limits from time units to clock cycles).

A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by

t

RRD.

CK#

CK

CKE

HIGH

CS#

RAS#

CAS#

WE#

A0-A11

BA0,1

RA

BA

RA = Row Address BA = Bank Address

Figure 4

Activating a Specific Row in

a Specific Bank

CK#

CK

COMMAND

A0-A11

BA0, BA1

T0 T1 T2 T3 T4 T5 T6 T7

ACT ACT

Row Row

Bank x Bank y

NOP

t

NOP

RRD

NOP

t

NOP

RCD

RD/WR

Col

Bank y

DON’T CARE

NOP

Figure 5

Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK < 3

16

READS

READ bursts are initiated with a READ command, as shown in Figure 6.

The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of CK and CK#). Figure 7 shows general timing for each possible CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last data-out element is known as the read postamble.

Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A detailed explanation of tDQSQ (valid dataout skew), tQH (data-out window hold), the valid data window are depicted in Figure 27. A detailed explanation of tDQSCK (DQS transition skew to CK) and tAC (data-out transition skew to CK) is depicted in Figure 28.

Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles after the first READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 8. A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive read data is shown for illustration in Figure 9. Full-speed random read accesses within a page (or pages) can be performed as shown in Figure 10.

CK#

CK

CKE

CS#

RAS#

CAS#

WE#

x4: A0–A9, A11

x8: A0–A9

x16: A0–A8

x8: A11

x16: A9, A11

A10

BA0,1

CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge

READ Command

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

HIGH

CA

EN AP

DIS AP

BA

DON’T CARE

Figure 6

17

CK#

CK

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

T0 T1 T2 T3T2n T3n T4 T5

COMMAND

ADDRESS

DQS

DQ

CK#

CK

COMMAND

ADDRESS

DQS

DQ

READ NOP NOP NOP NOP NOP

Bank a,

Col n

CL = 2

DO

n

T0 T1 T2 T3T2n T3n T4 T5

READ NOP NOP NOP NOP NOP

Bank a,

Col n

CL = 2.5

DO

n

NOTE: 1. DO n = data-out from column n.

DON’T CARE TRANSITIONING DATA

2. Burst length = 4.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Shown with nominal tAC, tDQSCK, and tDQSQ.

Figure 7

READ Burst

18

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

COMMAND

ADDRESS

DQS

DQ

CK#

CK

COMMAND

ADDRESS

T0 T1 T2 T3T2n T3n T4 T5T4n T5n

READ NOP READ NOP NOP NOP

Bank,

Col n

Bank, Col b

CL = 2

DO

n

DO

b

T0 T1 T2 T3T2n T3n T4 T5T4n T5n

READ NOP READ NOP NOP NOP

Bank,

Col n

Bank, Col b

CL = 2.5

DQS

DQ

DO

n

DO

b

DON’T CARE TRANSITIONING DATA

NOTE: 1. DO n (or b) = data-out from column n (or column b).

2. Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal

t

AC, tDQSCK, and tDQSQ.

6. Example applies only when READ commands are issued to same device.

Figure 8

Consecutive READ Bursts

19

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

COMMAND

ADDRESS

DQS

DQ

CK#

CK

COMMAND

ADDRESS

DQS

T0 T1 T2 T3T2n T3n T4 T5 T5n T6

READ NOP NOP NOP NOP NOP

Bank,

Col n

READ

Bank, Col b

CL = 2

DO

n

DO

b

T0 T1 T2 T3T2n T3n T4 T5 T5n T6

READ NOP NOP NOP NOP NOP

Bank,

Col n

READ

Bank, Col b

CL = 2.5

DQ

DO

n

DO

b

DON’T CARE TRANSITIONING DATA

NOTE: 1. DO n (or b) = data-out from column n (or column b).

2. Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal

t

AC, tDQSCK, and tDQSQ.

6. Example applies when READ commands are issued to different devices or nonconsecutive READs.

Figure 9

Nonconsecutive READ Bursts

20

CK#

CK

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

T0 T1 T2 T3T2n T3n T4 T5T4n T5n

COMMAND

ADDRESS

DQS

DQ

CK#

CK

COMMAND

ADDRESS

DQS

READ READ READ NOP NOP

Bank,

Col n

Bank,

Col x

Bank,

Col b

READ

Bank,

Col g

CL = 2

DO

n

DO

n'

DO

x

DO

x'

DO

b

DO

b'

DO

g

T0 T1 T2 T3T2n T3n T4 T5T4n T5n

READ READ READ NOP NOP

Bank,

Col n

Bank,

Col x

Bank,

Col b

READ

Bank,

Col g

CL = 2.5

DQ

DO

n

DO

n'

DO

x

DO

x'

DO

b

DO

b'

DON’T CARE TRANSITIONING DATA

NOTE: 1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).

2. Burst length = 2 or 4 or 8 (if 4 or 8, the following burst interrupts the previous).

3. n' or x' or b' or g' indicates the next data-out following DO n or DO x or DO b or DO g, respectively.

4. READs are to an active row in any bank.

t

5. Shown with nominal

AC, tDQSCK, and tDQSQ.

Figure 10

Random READ Accesses

21

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

READs (continued)

Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure

11. The BURST TERMINATE latency is equal to the READ (CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture).

Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure 12. The tDQSS (MIN) case is shown; the tDQSS (MAX) case

has a longer bus idle time. (tDQSS [MIN] and tDQSS [MAX] are defined in the section on WRITEs.)

A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto precharge was not activated. The PRECHARGE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n- prefetch architecture). This is shown in Figure 13. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until is met. Note that part of the row precharge time is hidden during the access of the last data elements.

t

RP

22

CK#

CK

COMMAND

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

T0 T1 T2 T3T2n T4 T5

READ BST

5

NOP NOP NOP NOP

ADDRESS

DQS

DQ

CK#

CK

COMMAND

ADDRESS

DQS

DQ

Bank a,

Col n

CL = 2

DO

n

T0 T1 T2 T3T2n T4 T5

READ BST

Bank a,

Col n

5

NOP NOP NOP NOP

CL = 2.5

DO

n

NOTE: 1. DO n = data-out from column n.

DON’T CARE TRANSITIONING DATA

2. Burst length = 4.

3. Subsequent element of data-out appears in the programmed order following DO n.

4. Shown with nominal tAC, tDQSCK, and tDQSQ.

5. BST = BURST TERMINATE command, page remains open.

Figure 11

Terminating a READ Burst

23

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

COMMAND

ADDRESS

DQS

DQ

DM

CK#

CK

COMMAND

ADDRESS

T0 T1 T2 T3T2n T4 T5T4n T5n

CL = 2

7

NOP NOP NOP

WRITE

Bank,

Col b

t

DQSS

(MIN)

DO

n

DI

b

READ BST

Bank,

Col n

T0 T1 T2 T3T2n T4 T5 T5n

READ BST

Bank a,

Col n

7

CL = 2.5

NOP WRITE NOP

NOP

t

DQSS

(MIN)

DQS

DQ

DO

n

DM

NOTE: 1. DO n = data-out from column n.

DON’T CARE TRANSITIONING DATA

2. DI b = data-in from column b.

3. Burst length = 4 in the cases shown (applies for bursts of 8 as well; if the burst length is 2, the BST command shown can be NOP).

4. One subsequent element of data-out appears in the programmed order following DO n.

5. Data-in elements are applied following DI b in the programmed order.

6. Shown with nominal

t

AC, tDQSCK, and tDQSQ.

7. BST = BURST TERMINATE command, page remains open.

Figure 12

READ to WRITE

DI

b

24

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

COMMAND

ADDRESS

DQS

DQ

CK#

CK

COMMAND

ADDRESS

DQS

T0 T1 T2 T3T2n T3n T4 T5

6

READ NOP PRE NOP NOP ACT

Bank a,

Col n

CL = 2

Bank a,

(a or all)

DO

n

Bank a,

t

RP

Row

T0 T1 T2 T3T2n T3n T4 T5

6

READ NOP PRE NOP NOP ACT

Bank a,

Col n

Bank a,

(a or all)

t

RP

Bank a,

Row

CL = 2.5

DQ

DO

n

DON’T CARE TRANSITIONING DATA

NOTE: 1. DO n = data-out from column n.

2. Burst length = 4, or an interrupted burst of 8.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Shown with nominal tAC, tDQSCK, and tDQSQ.

5. READ to PRECHARGE equals two clocks, which allows two data pairs of data-out.

6. A READ command with AUTO-PRECHARGE enabled would cause a precharge to be performed at x number of clock cycles after the READ command, where x = BL / 2.

7. PRE = PRECHARGE command; ACT = ACTIVE command.

Figure 13

READ to PRECHARGE

25

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

WRITES

WRITE bursts are initiated with a WRITE com-

mand, as shown in Figure 14.

The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble.

The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one clock cycle). All of the WRITE diagrams show the nominal case, and where the two extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Figure 15 shows the nominal case and the extremes of

t

DQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored.

Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any positive edge of clock following the previous WRITE command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued x cycles after the first WRITE command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture).

Figure 16 shows concatenated bursts of 4. An example of nonconsecutive WRITEs is shown in Figure

17. Full-speed random write accesses within a page or pages can be performed as shown in Figure 18.

Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without truncating the WRITE burst, tWTR should be met as shown in Figure 19.

Data for any WRITE burst may be truncated by a subsequent READ command, as shown in Figure 20. Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal

CK#

CK

CKE

HIGH

CS#

RAS#

CAS#

WE#

x4: A0–A9, A11

x8: A0–A9

CA

x16: A0–A8

x8: A11

x16: A9, A11

EN AP

A10

DIS AP

BA0,1

BA

CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge

DON’T CARE

Figure 14

WRITE Command

array, and any subsequent data-in should be masked with DM as shown in Figure 21.

Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, tWR should be met as shown in Figure 22.

Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figures 23 and 24. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data-in should be masked with DM as shown in Figures 23 and 24. After the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.

26

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

COMMAND

ADDRESS

t

DQSS (NOM)

DQS

DQ

DM

t

DQSS (MIN)

DQS

DQ

DM

t

DQSS (MAX)

DQS

T0 T1 T2 T3T2n

WRITE NOP NOP

Bank a,

Col b

t

DQSS

DI

b

t

DQSS

DI

b

t

DQSS

NOP

DQ

DI

b

DM

DON’T CARE TRANSITIONING DATA

NOTE: 1. DI b = data-in for column b.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. An uninterrupted burst of 4 is shown.

4. A10 is LOW with the WRITE command (auto precharge is disabled).

Figure 15

WRITE Burst

27

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

COMMAND

ADDRESS

t

DQSS (NOM)

DQS

DQ

DM

T0 T1 T2 T3T2n T4 T5T4n

WRITE NOP WRITE NOP NOP

Bank,

Col b

t

DQSS

DI

b

Bank,

Col n

NOP

DI

T3nT1n

n

DON’T CARE TRANSITIONING DATA

NOTE: 1. DI b, etc. = data-in for column b, etc.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. Three subsequent elements of data-in are applied in the programmed order following DI n.

4. An uninterrupted burst of 4 is shown.

5. Each WRITE command may be to any bank.

Figure 16

Consecutive WRITE to WRITE

28

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

COMMAND

ADDRESS

t

DQSS (NOM)

DQS

DQ

DM

T0 T1 T2 T3T2n T4 T5T4n

WRITE NOP NOP NOP NOP

Bank,

Col b

t

DQSS

T1n T5n

WRITE

Bank,

Col n

DI

b

DI

n

DON’T CARE TRANSITIONING DATA

NOTE: 1. DI b, etc. = data-in for column b, etc.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. Three subsequent elements of data-in are applied in the programmed order following DI n.

4. An uninterrupted burst of 4 is shown.

5. Each WRITE command may be to any bank.

Figure 17

Nonconsecutive WRITE to WRITE

29

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

COMMAND

ADDRESS

DQS

DQ

DM

T0 T1 T2 T3T2n T4 T5T4n

WRITE WRITE WRITE WRITE NOP

Bank,

Col b

t

DQSS (NOM)

Bank,

Col x

DI

b

T1n T3n T5n

WRITE

DI

b'

Bank, Col n

DI

x

DI

x'

Bank,

Col a

DI

n

DI

n'

Bank,

Col g

DI

a

DI

a'

DI

g

DON’T CARE TRANSITIONING DATA

DI

g'

NOTE: 1. DI b, etc. = data-in for column b, etc.

2. b', etc. = the next data-in following DI b, etc., according to the programmed burst order.

3. Programmed burst length = 2, 4, or 8 in cases shown.

4. Each WRITE command may be to any bank.

Figure 18

Random WRITE Cycles

30

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

T0 T1 T2 T3T2n T4 T5

T1n

CK#

CK

COMMAND

ADDRESS

t

DQSS (NOM)

WRITE NOP NOP READ NOP NOP

Bank a,

Col b

t

DQSS

NOP

t

WTR

Bank a,

Col n

DQS

DQ

DI

b

DM

t

DQSS (MIN) CL = 2

t

DQSS

DQS

DQ

DI

b

DM

t

DQSS (MAX) CL = 2

t

DQSS

CL = 2

T6 T6n

DI

n

DI

n

DQS

DQ

DI

b

DM

DON’T CARE TRANSITIONING DATA

NOTE: 1. DI b = data-in for column b.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. An uninterrupted burst of 4 is shown.

4.tWTR is referenced from the first positive CK edge after the last data-in pair.

5. The READ and WRITE commands are to same device. However, the READ and WRITE commands may be to different devices, in which case tWTR is not required and the READ command could be applied earlier.

6. A10 is LOW with the WRITE command (auto precharge is disabled).

Figure 19

WRITE to READ – Uninterrupting

DI

n

31

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

T0 T1 T2 T3T2n T4 T5 T5n

T1n

CK#

CK

COMMAND

ADDRESS

t

DQSS (NOM)

WRITE NOP NOP NOP NOP NOP

t

WTR

Bank a,

Col b

t

DQSS

READ

Bank a,

Col n

DQS

DQ

DI

b

DM

t

DQSS (MIN) CL = 2

t

DQSS

DQS

DQ

DI

b

T6

CL = 2

DI

n

DI

n

DM

t

DQSS (MAX) CL = 2

t

DQSS

DQS

DQ

DI

b

DI

n

DM

DON’T CARE TRANSITIONING DATA

NOTE: 1. DI b = data-in for column b.

2. An interrupted burst of 4 or 8 is shown; two data elements are written.

3. One subsequent element of data-in is applied in the programmed order following DI b.

4.tWTR is referenced from the first positive CK edge after the last data-in pair.

5. A10 is LOW with the WRITE command (auto precharge is disabled).

6. DQS is required at T2 and T2n (nominal case) to register DM.

7. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would mask the last two data elements.

Figure 20

WRITE to READ – Interrupting

32

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

T0 T1 T2 T3T2n T4 T5

T1n

CK#

CK

COMMAND

ADDRESS

t

DQSS (NOM)

WRITE NOP NOP NOP NOP NOP

t

WTR

Bank a,

Col b

t

DQSS

READ

Bank a,

Col n

DQS

DQ

DI

b

DM

t

DQSS (MIN) CL = 2

t

DQSS

DQS

DQ

DI

b

DM

T6 T6nT5n

CL = 2

DI

n

DI

n

t

DQSS (MAX) CL = 2

t

DQSS

DQS

DQ

DI

b

DI

n

DM

NOTE: 1. DI b = data-in for column b.

DON’T CARE TRANSITIONING DATA

2. An interrupted burst of 4 is shown; one data element is written.

3.tWTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements).

4. A10 is LOW with the WRITE command (auto precharge is disabled).

5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.

6. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would mask the last four data elements.

Figure 21

WRITE to READ – Odd Number of Data, Interrupting

33

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

COMMAND

ADDRESS

t

DQSS (NOM)

DQS

DQ

DM

t

DQSS (MIN)

DQS

DQ

DM

T0 T1 T2 T3T2n T4 T5

WRITE NOP NOP NOP PRE

Bank a,

Col b

t

DQSS

t

DQSS

DI

b

T1n

NOP

t

WR

Bank,

(a or all)

DI

b

T6

7

t

NOP

RP

t

DQSS (MAX)

t

DQSS

DQS

DQ

DI

b

DM

DON’T CARE TRANSITIONING DATA

NOTE: 1. DI b = data-in for column b.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. An uninterrupted burst of 4 is shown.

4.tWR is referenced from the first positive CK edge after the last data-in pair.

5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE commands may be to different devices, in which case tWR is not required and the PRECHARGE command could be applied earlier.

6. A10 is LOW with the WRITE command (auto precharge is disabled).

7. PRE = PRECHARGE command.

Figure 22

WRITE to PRECHARGE – Uninterrupting

34

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

COMMAND

ADDRESS

t

DQSS (NOM)

DQS

DQ

DM

t

DQSS (MIN)

DQS

DQ

DM

T0 T1 T2 T3T2n T4 T5

WRITE NOP NOP PRE

Bank a,

Col b

t

DQSS

t

DQSS

DI

b

T1n

NOP

t

WR

DI

b

9

Bank,

(a or all)

T6

NOP NOP

t

RP

t

DQSS (MAX)

t

DQSS

DQS

DQ

DI

b

DM

NOTE: 1. DI b = data-in for column b.

DON’T CARE TRANSITIONING DATA

2. Subsequent element of data-in is applied in the programmed order following DI b.

3. An interrupted burst of 4 is shown; two data elements are written.

4.tWR is referenced from the first positive CK edge after the last data-in pair.

5. The PRECHARGE and WRITE commands are to the same bank.

6. A10 is LOW with the WRITE command (auto precharge is disabled).

7. DQS is required at T2 and T2n (nominal case) to register DM.

8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE command would mask the last two data elements.

9. PRE = PRECHARGE command.

Figure 23

WRITE to Precharge – Interrupting

35

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

COMMAND

ADDRESS

t

DQSS (NOM)

DQS

DQ

DM

t

DQSS (MIN)

DQS

DQ

DM

T0 T1 T2 T3T2n T4 T5

WRITE NOP NOP PRE

Bank a,

Col b

t

DQSS

t

DQSS

DI

b

T1n

NOP

t

WR

DI

b

9

Bank,

(a or all)

T6

NOP NOP

t

RP

t

DQSS (MAX)

t

DQSS

DQS

DQ

DI

b

DM

DON’T CARE TRANSITIONING DATA

NOTE: 1. DI b = data-in for column b.

2. Subsequent element of data-in is applied in the programmed order following DI b.

3. An interrupted burst of 4 is shown; one data element is written.

4.tWR is referenced from the first positive CK edge after the last data-in pair.

5. The PRECHARGE and WRITE commands are to the same bank.

6. A10 is LOW with the WRITE command (auto precharge is disabled).

7. DQS is required at T1n, T2 and T2n (nominal case) to register DM.

8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE

command would mask the last two data elements.

9. PRE = PRECHARGE command.

Figure 24

WRITE to PRECHARGE – Odd Number of Data, Interrupting

36

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

PRECHARGE

The PRECHARGE command (Figure 25) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for

t

a subsequent row access some specified time (

RP) after

the PRECHARGE command is issued. Input A10 deter-

CK#

CK

CKE

HIGH

CS#

RAS#

CAS#

WE#

A0-A9, A11

ALL BANKS

A10

ONE BANK

BA0,1

BA

BA = Bank Address (if A10 is LOW; otherwise “Don’t Care”)

Figure 25

PRECHARGE Command

mines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.

POWER-DOWN (CKE Not Active)

Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress: from the issuing of a READ or WRITE command until completion of the burst. Thus a clock suspend is not supported. For READs, a burst completion is defined when the Read Postamble is satisfied; For WRITEs, a burst completion is defined when the Write Postamble is satisfied.

Power-down (Figure 26) is entered when CKE is registered LOW. If power-down occurs when all banks are idle, this mode is referred to as precharge powerdown; if power-down occurs when there is a row active in any bank, this mode is referred to as active powerdown. Entering power-down deactivates the input and output buffers, excluding CK, CK#, and CKE. For maximum power savings, the DLL is frozen during a precharge power-down. Exiting power-down requires the device to be at the same voltage and frequency as when it entered power-down. However, power-down duration is limited by the refresh requirements of the device (tREFC).

While in power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR SDRAM, while all other input signals are “Don’t Care.”

The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later.

CK#

CK

CKE

COMMAND

No READ/WRITE access in progress

T0 T1 T2 Ta0 Ta1 Ta2

t

IS

VALID

NOP

Enter power-down mode

()(

)

()(

)

()(

)

()(

)

()(

)

t

IS

NOP VALID

Exit power-down mode

DON’T CARE

Figure 26

Power-Down

37

TRUTH TABLE 2 – CKE

(Notes: 1-4)

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CKE

n-1

CKE

CURRENT STATE COMMAND

n

ACTION

n

L L Power-Down X Maintain Power-Down

Self Refresh X Maintain Self Refresh

L H Power-Down DESELECT or NOP Exit Power-Down

Self Refresh DESELECT or NOP Exit Self Refresh 5

H L All Banks Idle DESELECT or NOP Precharge Power-Down Entry

Bank(s) Active DESELECT or NOP Active Power-Down Entry

All Banks Idle AUTO REFRESH Self Refresh Entry

NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKE

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 200 clock cycles is needed before applying a READ command for the DLL to lock.

was the state of CKE at the previous clock edge.

n-1

NOTES

38

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

TRUTH TABLE 3 – CURRENT STATE BANK n – COMMAND TO BANK n

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND/ACTION NOTES

An y H X X X DESELECT (NOP/continue previous operation)

L H H H NO OPERATION (NOP/continue previous operation)

L L H H ACTIVE (select and activate row)

Idle L L L H AUTO REFRESH 7

LLLLLOAD MODE REGISTER 7

L H L H READ (select column and start READ burst) 10

Row Active L H L L WRITE (select column and start WRITE burst) 10

L L H L PRECHARGE (deactivate row in bank or banks) 8

Read L H L H READ (select column and start new READ burst) 10

(Auto- L H L L WRITE (select column and start WRITE burst) 10, 12

Precharge L L H L PRECHARGE (truncate READ burst, start PRECHARGE) 8

Disabled) L H H L BURST TERMINATE 9

Write L H L H READ (select column and start READ burst) 10, 11

(Auto- L H L L WRITE (select column and start new WRITE burst) 10

Precharge L L H L PRECHARGE (truncate WRITE burst, start PRECHARGE) 8, 11

Disabled)

NOTE:

1. This table applies when CKE met (if the previous state was self refresh).

2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses

and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4.

Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once

Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met.

Read w/Auto-

Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends

Write w/Auto-

Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends

t

RP is met, the bank will be in the idle state.

Once tRCD is met, the bank will be in the “row active” state.

when tRP has been met. Once tRP is met, the bank will be in the idle state.

was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been

n-1

39

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

NOTE (continued):

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met.

Accessing Mode

Register: Starts with registration of a LOAD MODE REGISTER command and ends when

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.

8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.

10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

11. Requires appropriate DM masking.

12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.

t

RC is met, the DDR SDRAM will be in the all banks idle state.

Once

t

MRD

has been met. Once tMRD is met, the DDR SDRAM will be in the all banks idle state.

Once tRP is met, all banks will be in the idle state.

40

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

TRUTH TABLE 4 – CURRENT STATE BANK n – COMMAND TO BANK m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND/ACTION NOTES

An y H X X X DESELECT (NOP/continue previous operation)

L H H H NO OPERATION (NOP/continue previous operation)

Idle XXXXAny Command Otherwise Allowed to Bank m

Row L L H H ACTIVE (select and activate row)

Activating, L H L H READ (select column and start READ burst) 7

Active, or L H L L WRITE (select column and start WRITE burst) 7

Precharging L L H L PRECHARGE

Read L L H H ACTIVE (select and activate row)

(Auto- L H L H READ (select column and start new READ burst) 7

Precharge L H L L WRITE (select column and start WRITE burst) 7, 9

Disabled) L L H L PRECHARGE

Write L L H H ACTIVE (select and activate row)

(Auto- L H L H READ (select column and start READ burst) 7,8

Precharge L H L L WRITE (select column and start new WRITE burst) 7

Disabled) L L H L PRECHARGE

Read L L H H ACTIVE (select and activate row)

(With Auto- L H L H READ (select column and start new READ burst) 7, 3a

Precharge) L H L L WRITE (select column and start WRITE burst) 7, 9, 3a

L L H L PRECHARGE

Write L L H H ACTIVE (select and activate row)

(With Auto- L H L H READ (select column and start READ burst) 7, 3a

Precharge) L H L L WRITE (select column and start new WRITE burst) 7, 3a

L L H L PRECHARGE

NOTE:

1. This table applies when CKE met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.

(Notes continue on next page)

was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been

n-1

41

NOTE (continued):

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses

and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Read with Auto

Precharge Enabled: See following text – 3a

Write with Auto

Precharge Enabled: See following text – 3a

3a. The READ with auto precharge enabled or WRITE with auto precharge enabled states can each be

broken into two parts: the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For WRITE with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the READ with auto precharge enabled or WRITE with auto precharge enabled states, ACTIVE, PRECHARGE, READ, and WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands to the other bank may be applied. In either case, all other related limitations apply (e.g., contention between read data and write data must be avoided). This means concurrent auto precharge is not supported.

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

8. Requires appropriate DM masking.

9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.

42

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

ABSOLUTE MAXIMUM RATINGS*

VDD Supply Voltage

Relative to V

VDDQ Supply

Voltage Relative to V

VREF and Inputs Voltage

Relative to VSS .......................................-1V to +3.6V

I/O Pins Voltage

Relative to VSS ......................... -0.5V to VDDQ +0.5V

Operating Temperature, T

Storage Temperature (plastic) ........... -55°C to +150°C

Power Dissipation ................................................... 1W

Short Circuit Output Current ............................ 50mA

SS ......................................-1V to +3.6V

SS ........................-1V to +3.6V

(ambient) .. 0°C to +70°C

A

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1–5, 16; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD 2.3 2.7 V 36, 41

I/O Supply Voltage VDDQ 2.3 2.7 V 36, 41,

44

I/O Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 6, 44

I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 44

Input High (Logic 1) Voltage VIH(DC)VREF + 0.15 VDD + 0.3 V 28

Input Low (Logic 0) Voltage VIL(DC) -0.3 VREF - 0.15 V 28

INPUT LEAKAGE CURRENT Any input, 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V II -2 2 µA (All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT IOZ -5 5 µA (DQs are disabled; 0V ≤ VOUT ≤ VDDQ)

OUTPUT LEVELS: Full drive option - x4 , x8, x16 High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT)IOH -16.8 – mA 37, 39 Low Current (VOUT = 0.373V, maximum VREF,maximum VTT)IOL 16.8 – mA

OUTPUT LEVELS: Reduced drive option - x16 only High Current (VOUT = VDDQ-0.763V, minimum VREF, minimum VTT)IOHR -9 – mA 38, 39 Low Current (VOUT = 0.763V, maximum VREF,maximum VTT)IOLR 9 – mA

AC INPUT OPERATING CONDITIONS

(Notes: 1–5, 14, 16; notes appear on pages 50–53) (0°C ≤ TA ≤ + 70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH(AC)VREF + 0.310 – V 14, 28, 40

Input Low (Logic 0) Voltage VIL(AC) – VREF - 0.310 V 14, 28, 40

I/O Reference Voltage VREF(AC) 0.49 x VDDQ 0.51 x VDDQV 6

43

V

DD

Q (2.3V minimum)

V

OH(MIN)

(1.670V1 for SSTL2 termination)

System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation)

1.560V

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

V

IH

AC

Transmitter

1.400V

1.300V

1.275V

1.250V

1.225V

1.200V

1.100V

0.940V

IN

V between V

- Provides margin

AC

OL

(MAX) and V

V

OL

(MAX) (0.83V2 for

SSTL2 termination)

VSSQ

V

IH

DC

REF

+AC Noise

V V

REF

+DC Error

V

REF

-DC Error

V

REF

-AC Noise

V

IL

DC

V

IL

AC

IL

AC

Receiver

NOTE: 1. VOH (MIN) with test load is 1.927V

2. V

3. Numbers in diagram reflect nomimal values utilizing circuit below.

OL

(MAX) with test load is 0.373V

V

TT

25

Ω

25

Ω

Reference Point

Figure 27

Input Voltage Waveform

44

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CLOCK INPUT OPERATING CONDITIONS

(Notes: 1–5, 15, 16, 30; notes appear on pages 50–53) (0°C ≤ TA ≤ + 70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Clock Input Mid-Point Voltage; CK and CK# VMP(DC) 1.15 1.35 V 6, 9

Clock Input Voltage Level; CK and CK# VIN(DC) -0.3 VDDQ + 0.3 V 6

Clock Input Differential Voltage; CK and CK# VID(DC) 0.36 VDDQ + 0.6 V 6, 8

Clock Input Differential Voltage; CK and CK# VID(AC) 0.7 VDDQ + 0.6 V 8

Clock Input Crossing Point Voltage; CK and CK# VIX(AC) 0.5 x VDDQ - 0.2 0.5 x VDDQ + 0.2 V 9

2.80v

1.45v

1.25v

1.05v

CK#

- 0.30v

CK

Maximum Clock Level

X

VMP (DC)

1

IX

V

X

Minimum Clock Level

NOTE: 1. This provides a minimum of 1.15v to a maximum of 1.35v, and is always half of VDDQ.

2. CK and CK# must cross in this region.

3. CK and CK# must meet at least V

4. CK and CK# must have a minimum 700mv peak to peak swing.

5. CK or CK# may not be more positive than V

6. For AC operation, all DC clock requirements must also be satisfied.

7. Numbers in diagram reflect nominal values.

ID

(DC) min when static and is centered around VMP(DC)

DD

Q + 0.3v or more negative than Vss - 0.3v.

(AC)

5

3

V

ID

(DC)

2

5

4

V

ID

(AC)

Figure 28 – SSTL_2 Clock Input

45

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CAPACITANCE (x4, x8)

(Note: 13; notes appear on pages 50–53)

PARAMETER SYMBOL MIN MAX UNITS NOTES

Delta Input/Output Capacitance: DQs, DQS, DM DCIO – 0.50 p F 24

Delta Input Capacitance: Command and Address DCI1 – 0.50 pF 29

Delta Input Capacitance: CK, CK# DCI2 – 0.25 pF 29

Input/Output Capacitance: DQs, DQS, DM CIO 4.0 5.0 p F

Input Capacitance: Command and Address CI1 2.0 3.0 p F

Input Capacitance: CK, CK# CI2 2.0 3.0 p F

Input Capacitance: CKE CI3 2.0 3.0 p F

IDD SPECIFICATIONS AND CONDITIONS (x4, x8)

(Notes: 1–5, 10, 12, 14; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

MAX

PARAMETER/CONDITION SYMBOL

OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); I

t

CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock

cyle; Address and control inputs changing once every two clock cycles;

OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; I

t

RC = tRC (MIN); tCK = tCK (MIN); I

OUT

= 0mA; Address and control

inputs changing once per clock cycle

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; I Power-down mode; tCK = tCK (MIN); CKE = LOW;

IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK (MIN); I CKE = HIGH; Address and other control inputs changing once per clock cycle.

VIN

=

VREF

for DQ, DQS, and DM

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; I Power-down mode; tCK = tCK (MIN); CKE = LOW

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; I

DD

Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; I

DD

One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); I

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank I

OUT

= 0mA

DD

active; Address and control inputs changing once per clock cycle;

t

CK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle

AUTO REFRESH CURRENT

t

RC = tRFC (MIN) I

t

RC = 15.625µs I

SELF REFRESH CURRENT: CKE ≤ 0.2V Standard I

Low power (L) I

OPERATING CURRENT: Four bank interleaving READs (BL=4) with I

auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and control

inputs change only during Active, READ, or WRITE commands.

-75/-75Z -8

DD

0 105 100 mA 22, 48

DD

1 120 110 mA 22,48

DD

2P 3 3 mA 23, 32, 50

DD

2F 45 35 mA 51

DD

3P 18 18 mA 23, 32, 50

3N 45 35 mA 47

4R 110 90 mA 22, 48

4W 110 90 mA 22

DD

5 220 205 mA 22, 50

DD

6 5 5 mA 27, 50

DD

7 23mA11

DD

7 11mA11

DD

8 325 260 mA 22,49

UNITS NOTES

46

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CAPACITANCE (x16)

(Note: 13; notes appear on pages 50–53)

PARAMETER SYMBOL MIN MAX UNITS NOTES

Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM DCIOL – 0.50 p F 24

Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM DCIOU – 0.50 p F 24

Delta Input Capacitance: Command and Address DCI1 – 0.50 pF 29

Delta Input Capacitance: CK, CK# DCI2 – 0.25 pF 29

Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM CIO 4.0 5.0 pF

Input Capacitance: Command and Address CI1 2.0 3.0 p F

Input Capacitance: CK, CK# CI2 2.0 3.0 p F

Input Capacitance: CKE CI3 2.0 3.0 p F

IDD SPECIFICATIONS AND CONDITIONS (x16)

(Notes: 1–5, 10, 12, 14; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

MAX

PARAMETER/CONDITION SYMBOL

OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); I

t

CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock

cyle; Address and control inputs changing once every two clock cycles; OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; I

t

RC = tRC (MIN); tCK = tCK (MIN); I

OUT

= 0mA; Address and control

inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; I

Power-down mode; tCK = tCK (MIN); CKE = LOW; IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK (MIN); I

CKE = HIGH; Address and other control inputs changing once per clock cycle.

VIN

=

VREF

for DQ, DQS, and DM

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; I Power-down mode; tCK = tCK (MIN); CKE = LOW

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; I

DD

Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; I One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); I

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank I

OUT

= 0mA

DD

active; Address and control inputs changing once per clock cycle;

t

CK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle

AUTO REFRESH CURRENT

t

RC = tRFC (MIN) I

t

RC = 15.625µs I

SELF REFRESH CURRENT: CKE ≤ 0.2V Standard I

Low power (L) I

OPERATING CURRENT: Four bank interleaving READs (BL=4) with I

auto precharge, tRC =tRC (MIN); tCK =tCK (MIN); Address and control

inputs change only during Active, READ, or WRITE commands.

-75/-75Z -8

DD

0 TBD TBD mA 22, 48

DD

1 TBD TBD mA 22,48

DD

2P 3 3 mA 23, 32, 50

DD

2F TBD TBD mA 51

DD

3P TBD TBD mA 23, 32, 50

3N TBD TBD mA 47

DD

4R TBD TBD mA 22, 48

4W TBD TBD mA 22

DD

5 250 220 mA 22, 50

DD

6 5 5 mA 27, 50

DD

7 23mA11

DD

7 11mA11

DD

8 TBD TBD mA 22,49

UNITS NOTES

47

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 1–5, 14–17, 33; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

AC CHARACTERISTICS -75Z -75 -8 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time CL = 2.5tCK (2.5) 7.5 13 7.5 13 8 13 ns 45, 52

CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per accesstDQSQ 0.5 0.5 0.6 ns 25, 26 Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access

Data hold skew factor ACTIVE to PRECHARGE command

ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window na REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command

t

AC -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

t

CH -0.45 +0.55 0.45 0.55 0.45 0.55

t

CL 0.45 0.55 0.45 0.55 0.45 0.55

t

CK (2) 7.5 13 10 13 10 13 ns 45, 52

t

DH 0.5 0.5 0.6 ns 26, 31

t

DS 0.5 0.5 0.6 ns 26, 31

t

DIPW 1.75 1.75 2 ns 31

t

DQSCK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

t

DQSH 0.35 0.35 0.35

t

DQSL 0.35 0.35 0.35

t

DQSS 0.75 1.25 0.75 1.25 0.75 1.25

t

DSS 0.2 0.2 0.2

t

DSH 0.2 0.2 0.2

t

HPtCH,tCL

t

HZ +0.75 +0.75 +0.8 ns 18, 42

t

LZ -0.75 -0.75 -0.8 ns 18, 43

t

IH

t

IS

t

IH

t

IS

t

MRD 15 15 16 ns

t

QH

t

QHS 0.75 0.75 1 ns

t

RAS 40 120,000 40 120,000 40 120,000 ns 35

t

RAP

t

RC 65 65 70 ns

t

RFC 75 75 80 ns 50

t

RCD 20 20 20 ns

t

RP 20 20 20 ns

t

RPRE 0.9 1.1 0.9 1.1 0.9 1.1

t

RPST 0.4 0.6 0.4 0.6 0.4 0.6

t

RRD 15 15 15 ns

t

WPRE 0.25 0.25 0.25

t

WPRES 0 0 0 ns 20, 21

t

WPST 0.4 0.6 0.4 0.6 0.4 0.6

t

WR 15 15 15 ns

t

WTR 1 1 1

t

REFC 140.6 140.6 140.6 µs 23

t

REFI 15.6 15.6 15.6 µs 23

t

VTD 0 0 0 ns

t

XSNR 75 75 80 ns

t

XSRD 200 200 200

.90 .90 1.1 ns 14

F

.90 .90 1.1 ns 14

F

1 1 1.1 ns 14

S

1 1 1.1 ns 14

S

t

HP -tQHS

t

QH - tDQSQtQH - tDQSQ

t

CH,tCL

t

HP -tQHS

t

RAS(MIN) - (burst length

t

CH,tCL ns 34

t

HP-tQHS ns 25, 26

t

CK/2) ns 46

*

t

QH - tDQSQ ns 25

t

CK 30

t

CK 30

t

CK

t

CK

t

CK

t

CK

t

CK

t

CK 42

t

CK

t

CK

t

CK 19

t

CK

t

CK

48

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

SLEW RATE DERATING VALUES

(Note: 14; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

ADDRESS / COMMAND

SPEED SLEW RATE

-75/-75Z 0.500V / ns 1 1 ns 14

-75/-75Z 0.400V / ns 1.05 1 ns 14

-75/-75Z 0.300V / ns 1.10 1 ns 14

-75/-75Z 0.200V / ns 1.15 1 ns 14

-8 0.500V / ns 1.1 1.1 ns 14

-8 0.400V / ns 1.15 1.1 ns 14

-8 0.300V / ns 1.20 1.1 ns 14

-8 0.200V / ns 1.25 1.1 ns 14

t

IS

SLEW RATE DERATING VALUES

(Note: 31; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

DQ, DQS, DM

SPEED SLEW RATE

-75/-75Z 0.500V / ns 0.50 0.50 ns 31

-75/-75Z 0.400V / ns 0.55 0.55 ns 31

-75/-75Z 0.300V / ns 0.60 0.60 ns 31

-75/-75Z 0.200V / ns 0.65 0.65 ns 31

-8 0.500V / ns 0.60 0.60 ns 31

-8 0.400V / ns 0.65 0.65 ns 31

-8 0.300V / ns 0.70 0.70 ns 31

-8 0.200V / ns 0.75 0.75 ns 31

t

DS

t

IH UNITS NOTES

t

DH UNITS NOTES

49

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

NOTES

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load:

V

TT

50

Ω

Output (V

OUT

)

4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level).

6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor.

7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.

8. VID is the magnitude of the difference between the input level on CK and the input level on CK#.

9. The value of VIX and VMP are expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same.

10. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -75Z and -8, CL = 2.5 for -75 with the outputs open.

11. Enables on-chip refresh and address counters.

Reference Point

30pF

12. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate.

13. This parameter is sampled. VDD = +2.5V ±0.2V,

DDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz,

V T

= 25°C, VOUT(DC) = VDDQ/2, VOUT (peak to

A

peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.

14. Command/Address input slew rate = 0.5V/ns.

t

For -75 with slew rates 1V/ns and faster,

t

IH are reduced to 900ps. If the slew rate is less

IS and

than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in

t

slew rate from the 500mV/ns.

IH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.

15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is V

REF.

16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW.

17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT.

18.tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).

19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.

20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround.

21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS.

22. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS.

50

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

NOTES (continued)

23. The refresh period 64ms. This equates to an average refresh rate of 15.625µs. However, an AUTO REFRESH command must be asserted at least once every 140.6µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed.

24. The I/O capacitance per DQS and DQ byte/ group will not differ by more than this maximum amount for any given device.

25. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and

t

QH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55.

26. Referenced to each output group: x4 = DQS with DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15.

27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby).

28. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current

AC level through to the target AC level, VIL(AC)

or V

IH(AC).

b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or V

IH(DC).

29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device..

30. JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns differentially).

31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/ DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain.

ns

DERATING DATA VALID WINDOW

3.8

3.750

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

2.500

50/50 49.5/ 50.5 49/51 48.5/52.5 48/52 47.5/ 53.5 47/ 53 46.5/ 54.5 46/54 45.5/55.5 45/55

3.700

3.400

—— -75 @ tCK = 10ns

u

—— -8 @

#

—— -75 @

n

—— -8 @

l

3.350

t

CK = 10ns

t

CK = 7.5ns

t

CK = 8ns

2.463

3.650

3.300

2.425

3.600

3.250

2.388

t

QH - tDQSQ)

(

3.550

3.200

2.350

Clock Duty Cycle

3.500

3.150

2.313

3.450

3.100

2.275

3.400

3.050

2.238

3.350

3.000

2.200

3.300

2.950

2.163

3.250

2.900

2.125

51

NOTES (continued)

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

32. VDD must not vary more than 4% if CKE is not active while any bank is active.

33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount.

t

HP min is the lesser of tCL minimum and tCH

34. minimum actually applied to the device CK and CK/ inputs, collectively during bank active.

35. READs and WRITEs with auto precharge are not allowed to be issued until

t

RAS(MIN) can be satisfied prior to the internal precharge command being issued.

36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9 volts, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either

-300mV or 2.2 volts, whichever is more positive.

37. Normal Output Drive Curves: a) The full variation in driver pull-down current

from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A.

b) The variation in driver pull-down current

within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A.

c) The full variation in driver pull-up current

from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B.

d)The variation in driver pull-up current within

nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B.

e) The full variation in the ratio of the maximum

to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature.

f) The full variation in the ratio of the nominal

pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.

38. Reduced Output Drive Curves: a) The full variation in driver pull-down current

from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure C.

b) The variation in driver pull-down current

within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C.

c) The full variation in driver pull-up current

from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure D.

d)The variation in driver pull-up current within

nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D.

e) The full variation in the ratio of the maximum

to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage.

f) The full variation in the ratio of the nominal

pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V.

Figure A

160

140

120

100

80

(mA)

OUT

I

60

40

20

0

0.0 0.5 1.0 1.5 2.0 2.5

Pull-Down Characteristics

OUT

V

(V)

52

0

-20

-40

-60

-80

-100

(mA)

OUT

I

-120

-140

-160

-180

-200

0.0 0.5 1.0 1.5 2.0 2.5

Figure B

Pull-Up Characteristics

VDDQ - V

OUT

(V)

NOTES (continued)

39. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values.

40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a

pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.

41. VDD and VDDQ must track each other.

42. This maximum value is derived from the

referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ(MAX) and the last DVW. tHZ(MAX) will prevail over

t

DQSCK(MAX) + tRPST(MAX) condition.

t

LZ(MIN) will prevail over tDQSCK(MIN) +

t

RPRE(MAX) condition.

43. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier.

44. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin.

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

45. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option.

46.tRAP ≥ tRCD.

47. For the -75 and -75Z, IDD3N is specified to be 35mA at 100 MHz.

48. Random addressing changing 50% of data changing at every transfer.

49. Random addressing changing 100% of data changing at every transfer.

50. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later.

51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”

52. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles.

Figure D

0

-20

Pull-Up Characteristics

53

-40

-60

(mA)

OUT

I

-80

-100

-120

0.00.51.01.52.02.5

DDQ - VOUT (V)

V

80

70

60

50

40

(mA)

OUT

I

30

20

10

0

0.00.51.01.52.02.5

Pull-Down Characteristics

Figure C

OUT (V)

V

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

NORMAL OUTPUT DRIVE CHARACTERISTICS

PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA)

VOLTAGE NOMINAL NOMINAL NOMINAL NOMINAL

(V) LOW HIGH MINIMUM MAXIMUM LOW HIGH MINIMUM MAXIMUM

0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10

0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20

0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8

0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8

0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8

0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4

0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8

0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5

0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3

1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2

1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0

1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6

1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1

1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5

1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0

1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4

1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7

1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2

1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5

2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9

2.1 62.8 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2

2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6

2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0

2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3

2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6

2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9

2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2

NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions.

54

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

REDUCED OUTPUT DRIVE CHARACTERISTICS

PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA)

VOLTAGE NOMINAL NOMINAL NOMINAL NOMINAL

(V) LOW HIGH MINIMUM MAXIMUM LOW HIGH MINIMUM MAXIMUM

0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0

0.2 6.9 7.6 5.2 9.9 -6.9 -7.8 -5.2 -9.9

0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6

0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2

0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6

0.6 19.9 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0

0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2

0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8

0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5

1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2

1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7

1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0

1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1

1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1

1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7

1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4

1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5

1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6

1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7

2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8

2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6

2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3

2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9

2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4

2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7

2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8

2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7

NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions.

55

CK#

CK

DQS

QFC#

128Mb: x4, x8, x16

T1 T2 T3 T4T2n T3n

5

t

DQSQ

t

HP

3

t

DQSQ

5

t

HP

1

5

t

HP

t

DQSQ

5

t

HP

3

PRELIMINARY

DDR SDRAM

5

t

HP

3

t

HP

t

DQSQ

5

3

DQ (Last data valid)

2

DQ

2

DQ

2

DQ

2

DQ

2

DQ

2

DQ

DQ (First data no longer valid)

DQ (Last data valid)

DQ (First data no longer valid)

All DQs and DQS, collectively

6

Earliest signal transition

Latest signal transition

t

QH

4

T2

Data

Valid

window

t

QH

4

T2n

Data Valid

window

t

QH

4

T3

Data Valid

window

t

QH

4

T3n

Data

Valid

window

NOTE: 1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an “early DQS,”

at T3 is a “nominal DQS,” and at T3n is a "late DQS"

2. For a x4, only two DQs apply.

3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid transition of DQs .

4. tQH is derived from tHP : tQH = tHP - tQHS.

5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.

6. The data valid window is derived for each DQS transitions and is defined as

t

QH minus tDQSQ.

Figure 29 – x4, x8

Data Output Timing – tDQSQ, tQH and Data Valid Window

56

CK#

CK

LDQS

T1 T2 T3 T4T2n T3n

5

t

HP

1

5

t

HP

t

DQSQ

5

t

HP

3

t

DQSQ

5

t

HP

3

t

DQSQ

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

5

t

HP

3

t

HP

t

DQSQ

5

3

DQ (Last data valid)

DQ (First data no longer valid)

DQ (Last data valid)

DQ (First data no longer valid)

DQ0 - DQ7 and LDQS, collectively

DQ (Last data valid)

DQ (First data no longer valid)

DQ DQ DQ DQ DQ DQ

UDQS

DQ DQ DQ DQ DQ DQ

2

2 2 2 2

2

6

1

7

7 7 7 7

7

4

t

QH

Data Valid

t

DQSQ

T2

window

3

4

t

QH

T2n

Data Valid

window

t

DQSQ

T2n

3

4

t

QH

Data Valid

window

t

DQSQ

T3

3

t

QH

t

DQSQ

Lower Byte

4

T3n

Data Valid

window

3

Upper Byte

4

t

DQ (Last data valid)

DQ (First data no longer valid)

DQ8 - DQ15 and UDQS, collectively

NOTE: 1. DQs transitioning after DQS transition define tDQSQ window. LDQS defines the lower byte and UDQS defines the upper byte.

2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.

3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition

7

6

4. tQH is derived from tHP: tQH = tHP - tQHS.

5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.

6. The data valid window is derived for each DQS transition and is tQH minus tDQSQ.

7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.

QH

T2

Data Valid

window

4

t

QH

T2n

Data Valid

window

T2n

4

t

QH

T3

Data Valid

window

T3

4

t

QH

Data Valid

window

T3n

and ends with the last valid transition of DQs .

Figure 29A - x16

Data Output Timing – tDQSQ, tQH and Data Valid Window

57

CK#

CK

T0

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

7

t

T1 T2 T3 T4 T5

LZ

(MIN)

t

DQSCK

t

DQSCK

T2n

1

(MAX)

(MIN)

T3n T4n T5n

t

DQSCK

t

DQSCK

1

(MAX)

1

(MIN)

t

HZ

T6

(MAX)

DQS, or LDQS/UDQS

DQ (Last data valid)

DQ (First data valid)

All DQs collectively

T5

t

HZ

t

RPST

T5n

(MAX)

t

2

3

RPRE

t

LZ

(MIN)

T2

T2 T3 T4

T2n T3n T4n T5n

T2n

t

AC

4

(MIN)

T3

T3n

t

AC

4

(MAX)

T4

T4n

NOTE: 1.tDQSCK is the DQS output window relative to CK and is the“long term” component of DQS skew.

2.

DQs transitioning after DQS transition define tDQSQ window.

3. All DQs must transition by tDQSQ after DQS transitions, regardless of tAC.

4.tAC is the DQ output window relative to CK, and is the“long term” component of DQ skew.

5.tLZ

6.tHZ

(MIN)

(MAX

and

,and

t

AC

(MIN)

are the first valid signal transition.

t

AC

(MAX)

are the latest valid signal transition.

7. READ command with CL = 2 issued at T0.

Figure 30

Data Output Timing – tAC and tDQSCK

T0 T1 T1n T2 T2n T3

CK#

CK

t

DQSS

t

DSH

1

t

DSS

2

t

DSH

1

t

DSS

2

DQS

t

WPRE

DI

b

t

DQSL

t

DQSH

t

WPST

DQ

t

WPRES

DM

t

DS

t

DH

DON’T CARE TRANSITIONING DATA

NOTE: 1.tDSH(MIN) generally occurs during tDQSS(MIN).

2.tDSS

(MIN) generally occurs during

t

DQSS(MAX).

Figure 31

Data Input Timing

58

128Mb: x4, x8, x16

6

INITIALIZE AND LOAD MODE REGISTERS

(

)

VDD

VDDQ

t

1

VTD

1

VTT

VREF

CK#

CK

CKE

COMMAND

66

LVCMOS LOW LEVEL

DM

A0-A9,

A11

A10

BA0, BA1

DQS

DQ

T = 200µs

Power-up: VDD and CK stable

NOTE: 1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up.

VDDQ, V V

TT,

and V

DD/VDD

Q are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin.

2. Reset the DLL with A8 = H.

3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued.

4. The two AUTO REFRESH commands at Tc0 and Td0 may be applied prior to the LOAD MODE REGISTER (LMR) command at Ta0.

5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank.

6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address

)

(

)

(

)

(

)

T0

t

CHtCL

t

IH

IS

(

)

tISt

IH

t

CK

High-Z

(

)

High-Z

(

)

REF,

must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if

T1

PRE

ALL BANKS

tISt

IH

T2 Ta0 Tb0 Tc0 Td0 Te0

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

tISt

()(

)

()(

)

tISt

()(

)

()(

)

tISt

()(

)

()(

)

()(

)

()(

)

t

RP

Load Extended Mode Register

()(

)

()(

)

()(

)

()(

)

()(

)

LMRNOP PRELMR AR

()(

)

()(

)

()(

)

IH

()(

CODE CODE

BA0 = H,

BA1 = L

)

()(

)

IH

()(

)

()(

)

IH

()(

)

BA0 = L,

()(

BA1 = L

)

()(

)

()(

)

t

MRD

Load Mode

Register

t

MRD

2

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

ALL BANKS

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

tISt

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

IH

()(

)

()(

)

()(

)

()(

)

t

RP

200 cycles of CK3

t

RFC

PRELIMINARY

DDR SDRAM

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

AR ACT

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

t

5

RFC

5

RA

BA

DON’T CARE

TIMING PARAMETERS

-75Z -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

CH 0.45 0.55 0.45 0.55 0.45 0.55tCK

t

CL 0.45 0.55 0.45 0.55 0.45 0.55

t

CK (2.5) 7.5 13 7.5 13 8 13 ns

t

C K ( 2) 7. 5 13 10 13 10 13 n s

t

IH 1 1 1.1 ns

t

CK

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

IS 1 1 1.1 n s

t

MRD 15 15 16 ns

t

R FC 75 75 80 ns

t

RP 20 20 20 ns

t

VTD 0 0 0 ns

59

-75Z -75 -8

POWER-DOWN MODE

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

CKE

COMMAND

ADDR

DQS

DQ

DM

T0 T1 Ta0 Ta1 Ta2T2

t

IS

t

IS

VALID

tISt

t

CK

t

IH

t

IH

1

IH

t

IS

NOP

Enter

2

t

CH

t

CL

Power-Down

Mode

()(

)

()(

)

t

IS

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

t

REFC

NOP

VALID

VALIDVALID

Exit

Power-Down

Mode

DON’T CARE

NOTE: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the

power-down mode shown is precharge power-down. If this command is an ACTIVE (or if

at least one row is already active), then the power-down mode shown is active power-down.

2. No column accesses are allowed to be in progress at the time power-down is entered.

TIMING PARAMETERS

-75Z -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

CH 0.45 0.55 0.45 0.55 0.45 0.55tCK

t

CL 0.45 0.55 0.45 0.55 0.45 0.55

t

CK (2.5) 7.5 13 7.5 13 8 13 ns

t

CK

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

C K ( 2) 7. 5 13 10 13 10 13 n s

t

IH 1 1 1.1 ns

t

IS 1 1 1.1 n s

60

-75Z -75 -8

AUTO REFRESH MODE

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

CKE

COMMAND

A0-A9, A11

A10

BA0, BA1

DQS

DQ

DM

T0

t

IS

IH

t

IS

IH

1

4

NOP

2

T1

PRE

ALL BANKS

ONE BANK

tISt

Bank(s)

t

CK

IH

3

T2 T3

t

CHtCL

VALID VALID

NOP

2

t

RP

NOP

2

T4

AR NOP

Ta0

()(

)

()(

)

()(

)

()(

)

()(

)

2

()(

)

t

RFC

Ta1

AR

Tb0

()(

)

()(

)

()(

)

()(

)

()(

)

5

()(

2

NOP

)

Tb1 Tb2

2

t

5

RFC

ACTNOP

RA

BA

NOTE: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.

2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active (high) during clock positive transitions.

3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks).

4. QFC, DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.

5. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.

TIMING PARAMETERS

-75Z -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

CH 0.45 0.55 0.45 0.55 0.45 0.55tCK

t

CL 0.45 0.55 0.45 0.55 0.45 0.55

t

CK (2.5) 7.5 13 7.5 13 8 13 ns

t

C K ( 2) 7. 5 13 10 13 10 13 n s

DON’T CARE

-75Z -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

CK

IH 1 1 1.1 ns

t

IS 1 1 1.1 n s

t

R FC 75 75 80 ns

t

RP 20 20 20 ns

61

SELF REFRESH MODE

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

CKE

COMMAND

ADDR

DQS

DQ

DM

T0 T1

1

4

t

IS

IH

t

IS

IH

NOP AR

2

t

RP

CH

t

CL

t

IS

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

Ta0

1

t

CK

t

IS

()(

t

XSNR/

t

XSRD

Tb0Ta1

)

VALIDNOP

)

tISt

IH

)

VALID

)

3

Enter Self Refresh Mode

Exit Self Refresh Mode

DON’T CARE

NOTE: 1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling within

specifications by Ta0.

2. Device must be in the all banks idle state prior to entering self refresh mode.

3.

t

XSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK)

is required before a READ command can be applied.

4. AR = AUTO REFRESH command.

TIMING PARAMETERS

-75Z -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

CH 0.45 0.55 0.45 0.55 0.45 0.55tCK

t

CL 0.45 0.550.45 0.55 0.45 0.55

t

CK (2.5) 7.5 13 7.5 13 8 13 ns

t

C K ( 2) 7. 5 13 10 13 10 13 n s

t

IH 1 1 1.1 ns

t

CK

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

IS 1 1 1.1 n s

t

RP 20 20 20 ns

t

XSNR 75 75 80 ns

t

XSRD 200 200 200

62

-75Z -75 -8

t

CK

128Mb: x4, x8, x16

BANK READ – WITHOUT AUTO PRECHARGE

PRELIMINARY

DDR SDRAM

CK#

CK

CKE

COMMAND

x4: A0-A9, A11

x8: A0-A9

x16: A0-A8

x8: A11

x16: A9, A11

A10

BA0, BA1

DM

T0

t

IS

IH

t

IS

IH

5

NOP

6

T1

ACT

t

IS

RA

tISt

Bank x

T2 T3 T4 T5 T5n T6nT6 T7 T8

t

CK

t

IH

NOP

t

CHtCL

6

READ

Col n

t

IS

3

2

t

IH

NOP

6

7

PRE

ALL BANKS

ONE BANK

NOP

6

NOP

6

ACT

RA

IH

4

t

RP

Bank xBank x

t

RCD

t

RAS

Bank x

CL = 2

7

t

RC

RPRE

DO

t

n

t

Case 1:

AC

DQS

1

DQ

Case 2: tAC

(MIN)

and tDQSCK

(MAX)

and tDQSCK

(MIN)

(MAX)

t

RPRE

t

LZ

(MIN)

t

LZ

(MIN)

t

DQS

1

DQ

NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order.

2. Burst length = 4 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T5.

5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.

6. NOP commands are shown for ease of illustration; other commands may be valid at these times.

7. The PRECHARGE command can only be applied at T5 if

t

RAS minimum is met.

8. Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.

DQSCK

t

AC

t

DQSCK

DO

n

t

AC

(MIN)

(MAX)

t

RPST

t

HZ

t

RPST

(MAX)

TRANSITIONING DATA

DON’T CARE

63

BANK READ – WITH AUTO PRECHARGE

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CKE

COMMAND

x4: A0-A9, A11

x8: A0-A9

x16: A0-A8

x8: A11

x16: A9, A11

A10

BA0, BA1

DM

CK

T0

t

IS

IH

t

IS

IH

4

NOP

5

T1

t

CK

ACT

t

IS

IH

RA

T2 T3 T4 T5 T5n T6nT6 T7 T8

t

CHtCL

NOP

5

READ

Col n

3

t

IS

2,6

t

IH

NOP

5

NOP

5

NOP

5

NOP

5

ACT

RA

IS IH

Bank x

t

RAP

RAS

t

RC

Bank x

6

CL = 2

t

RP

Bank x

t

AC

(MIN)

Case 1:

DQS

1

DQ

Case 2: tAC

and tDQSCK

(MAX)

and tDQSCK

(MIN)

(MAX)

t

RPRE

t

LZ

(MIN)

DO

t

LZ

(MIN)

t

RPRE

DQS

1

DQ

NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order.

2. Burst length = 4 in the case shown.

3. Enable auto precharge.

4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.

5. NOP commands are shown for ease of illustration; other commands may be valid at these times.

6. The READ command can only be applied at T3 if

t

RAP minimum is met, tRAP tRCD.

>

_

7. Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.

DQSCK

n

t

AC

t

DQSCK

DO

n

(MIN)

(MAX)

t

AC

(MAX)

t

RPST

t

HZ

t

RPST

(MAX)

TRANSITIONING DATA

DON’T CARE

64

128Mb: x4, x8, x16

BANK WRITE – WITHOUT AUTO PRECHARGE

PRELIMINARY

DDR SDRAM

CK#

CKE

COMMAND

x4: A0-A9, A11

x8: A0-A9

x16: A0-A8

x8: A11

x16: A9, A11

A10

BA0, BA1

DQS

DQ

DM

T0

CK

t

IS

IH

t

IS

IH

5

1

NOP

6

T1

ACT

t

IS

RA

tISt

Bank x

T2 T3 T4 T5 T5n T6 T7 T8T4n

t

CK

t

IH

t

RCD

t

RAS

NOP

t

CHtCL

6

WRITE

Col n

t

IS

3

Bank x

2

t

IH

t

DQSS

t

WPRES

(NOM)

NOP

t

WPRE

DI

6

t

7

DSH

b

6

NOP

t

8 t

DSH

7 t

DSS

t

DQSLtDQSHtWPST

8

NOP

6

t

NOP

WR

6

PRE

ALL BANKS

ONE BANK

Bank x

4

t

RP

NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.

2. Burst length = 4 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T8.

5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.

6. NOP commands are shown for ease of illustration; other commands may be valid at these times.

7.tDSH is applicable during tDQSS

8.tDSS is applicable during tDQSS

(MIN)

and is referenced from CK T4 or T5.

(MAX)

and is referenced from CK T5 or T6.

TIMING PARAMETERS

-75Z -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

CH 0.45 0.55 0.45 0.55 0.45 0.55tCK

t

CL 0.45 0.55 0.45 0.55 0.45 0.55

t

CK (2.5) 7.5 13 7.5 13 8 13 ns

t

C K ( 2) 7. 5 13 10 13 10 13 n s

t

DH 0.5 0.5 0.6 ns

t

DS 0.5 0.5 0.6 n s

t

DQSH 0.35 0.35 0.35

t

DQSL 0.35 0.35 0.35

t

DQSS 0.75 1.2 0.75 1.25 0.75 1.25tCK

t

DS S 0.2 0.2 0.2

t

DS

DH

TRANSITIONING DATA

DON’T CARE

-75Z -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

CK

DS H 0.2 0.2 0.2

t

IH 1 1 1.1 ns

t

IS 1 1 1.1 n s

t

CK

tRAS 45 120,000 45 120,000 50 120,000 ns

t

R CD 20 20 20 n s

t

CK

t

CK

t

CK

RP 20 20 20 ns

t

WPRE 0.25 0.25 0.25

t

WPRES 0 0 0 ns

t

WPST 0.4 0.6 0.4 0.6 0.4 0.6

t

WR 15 15 15 ns

t

CK

t

CK

65

BANK WRITE – WITH AUTO PRECHARGE

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

CKE

COMMAND

x4: A0-A9, A11

x8: A0-A9

x16: A0-A8

x8: A11

x16: A9, A11

A10

BA0, BA1

DQS

DQ

T0

t

IS

IH

t

IS

IH

4

1

NOP

5

T1

ACT

t

IS

RA

tISt

Bank x

T2 T3 T4 T5 T5n T6 T7 T8T4n

t

CK

t

IH

NOP

t

CHtCL

5

WRITE

Col n

3

t

IS

2

t

IH

NOP

5

NOP

5

NOP

5

NOP

5

NOP

5

IH

Bank x

t

RCD

t

RAS

t

DQSS(NOM)

t

WPRES

t

WPRE

DI

t

6

t

7 t

6 t

DSH

DSS

DSH

t

DQSLtDQSHtWPST

b

DSS

7

WR

t

RP

DM

NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.

2. Burst length = 4 in the case shown.

3. Enable auto precharge.

4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.

5. NOP commands are shown for ease of illustration; other commands may be valid at these times.

6.tDSH is applicable during tDQSS(MIN) and is referenced from CK T4 or T5.

7.tDSS is applicable during tDQSS(MAX) and is referenced from CK T5 or T6.

TIMING PARAMETERS

-75Z -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

CH 0.45 0.55 0.45 0.55 0.45 0.55tCK

t

CL 0.45 0.55 0.45 0.55 0.45 0.55

t

CK (2.5) 7.5 13 7.5 13 8 13 ns

t

C K ( 2) 7. 5 13 10 13 10 13 n s

t

DH 0.5 0.5 0.6 ns

t

DS 0.5 0.5 0.6 n s

t

DQSH 0.35 0.35 0.35

t

DQSL 0.35 0.35 0.35

t

DQSS 0.75 1.25 0.75 1.25 0.75 1.25tCK

t

DS S 0.2 0.2 0.2

t

DS

t

DH

TRANSITIONING DATA

DON’T CARE

-75Z -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

CK

t

IH 1 1 1.2 ns

t

IS 1 1 1.2 n s

tDS H 0.2 0.2 0.2

t

CK

tRAS 45 120,000 45 120,000 50 120,000 n s

t

R CD 20 20 20 n s

t

CK

t

CK

t

CK

RP 20 20 20 ns

t

WPRE 0.25 0.25 0.25

t

WPRES 0 0 0 ns

t

WPST 0.4 0.6 0.4 0.6 0.4 0.6

t

WR 15 15 15 ns

t

CK

t

CK

66

WRITE – DM OPERATION

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

CK#

CK

CKE

COMMAND

x4: A0-A9, A11

x8: A0-A9

x16: A0-A8

x8: A11

x16: A9, A11

A10

BA0, BA1

DQS

DQ

T0

t

IS

IH

t

IS

IH

5

1

NOP

6

T1

ACT

t

IS

RA

tISt

Bank x

T2 T3 T4 T5 T5n T6 T7 T8T4n

t

CK

t

IH

t

RCD

t

RAS

NOP

t

CHtCL

6

WRITE

Col n

t

IS

3

Bank x

2

t

IH

t

DQSS

t

(NOM)

WPRES

NOP

t

WPRE

6

t

7

DSH

DI

b

6

NOP

t

8

t

7

DSH

t

DSS

t

DQSLtDQSHtWPST

8

NOP

6

t

NOP

WR

6

PRE

ALL BANKS

ONE BANK

Bank x

4

t

RP

DM

t

NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.

2. Burst length = 4 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T8.

5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.

6. NOP commands are shown for ease of illustration; other commands may be valid at these times.

7.tDSH is applicable during tDQSS

8.tDSS is applicable during tDQSS

(MIN)

and is referenced from CK T4 or T5.

(MAX)

and is referenced from CK T5 or T6.

DS

t

DH

TIMING PARAMETERS

-75Z -75 -8

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

CH 0.45 0.55 0.45 0.55 0.45 0.55tCK

t

CL 0.45 0.55 0.45 0.55 0.45 0.55

t

CK (2.5) 7.5 13 7.5 13 8 13 ns

t

C K ( 2) 7. 5 13 10 13 10 13 n s

t

DH 0.5 0.5 0.6 ns

t

DS 0.5 0.5 0.6 n s

t

DQSH 0.35 0.35 0.35

t

DQSL 0.35 0.35 0.35

t

DQSS 0.75 1.25 0.75 1.25 0.75 1.25tCK

t

DS S 0.2 0.2 0.2

t

CK

t

CK

t

CK

t

CK

SYMBOL MIN MAX MIN MAX MIN MAX UNITS

t

DS H 0.2 0.2 0.2

t

IH 1 1 1.1 ns

t

IS 1 1 1.1 n s

tRAS 45 120,000 45 120,000 50 120,000 n s

t

R CD 20 20 20 n s

t

RP 20 20 20 ns

t

WPRE 0.25 0.25 0.25

t

WPRES 0 0 0 ns

t

WPST 0.4 0.6 0.4 0.6 0.4 0.6

t

WR 15 15 15 ns

TRANSITIONING DATA

DON’T CARE

-75Z -75 -8

t

CK

t

CK

t

CK

67

66-PIN PLASTIC TSOP (400 mil)

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

PIN #1 ID

0.65 TYP

22.22 ± 0.08

0.32 ± .075 TYP

1.20 MAX

0.71

0.10 (2X)

10.16 ±0.08

11.76 ±0.10

0.15

0.10

SEE DETAIL A

+0.03

-0.02

0.10

+0.10

-0.05

DETAIL A

GAGE PLANE

0.25

0.80 TYP

0.50 ±0.10

NOTE: 1. All dimensions in millimeters

MAX

or typical here noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.

68

Datasheet MT46V32M4TG-75Z, MT46V16M8TG-75, MT46V8M16TG-8 Datasheet (MICRON)

FEATURES

OPTIONS MARKING

PIN ASSIGNMENT (TOP VIEW)

KEY TIMING PARAMETERS

128MB DDR SDRAM PART NUMBERS

GENERAL DESCRIPTION

TABLE OF CONTENTS

32 Meg x 4

16 Meg x 8

8 Meg x 16

PIN DESCRIPTIONS

RESERVED NC PINS

FUNCTIONAL DESCRIPTION

Initialization

REGISTER DEFINITION

MODE REGISTER

Burst Length

Burst Type

Read Latency

Operating Mode

EXTENDED MODE REGISTER

Output Drive Strength

DLL Enable/Disable

Commands

DESELECT

NO OPERATION (NOP)

LOAD MODE REGISTER

ACTIVE

READ

WRITE

PRECHARGE

AUTO PRECHARGE

BURST TERMINATE

AUTO REFRESH

SELF REFRESH

Operations

BANK/ROW ACTIVATION

READS

WRITES

PRECHARGE

POWER-DOWN (CKE Not Active)

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

AC INPUT OPERATING CONDITIONS

CLOCK INPUT OPERATING CONDITIONS

CAPACITANCE (x4, x8)

IDD SPECIFICATIONS AND CONDITIONS (x4, x8)

CAPACITANCE (x16)

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

SLEW RATE DERATING VALUES

SLEW RATE DERATING VALUES

NOTES

NORMAL OUTPUT DRIVE CHARACTERISTICS

REDUCED OUTPUT DRIVE CHARACTERISTICS

INITIALIZE AND LOAD MODE REGISTERS

POWER-DOWN MODE

AUTO REFRESH MODE

SELF REFRESH MODE

66-PIN PLASTIC TSOP (400 mil)