Datasheet MT46V32M8FJ-75Z, MT46V32M8FJ-6, MT46V64M4TG-6, MT46V64M4TG-6T, MT46V64M4TG-75Z Datasheet (MICRON)

PRELIMINARY

256Mb: x4, x8, x16

DDR333 SDRAM Addendum

‡

DOUBLE DATA RATE
(DDR) SDRAM

FEATURES

• 167 MHz Clock, 333 Mb/s/p data rate

•VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V

• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two - one per byte)

• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center­aligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data (x16 has
two - one per byte)

• Programmable burst lengths: 2, 4, or 8

• Concurrent Auto Precharge option supported

• Auto Refresh and Self Refresh Modes

• FBGA package available

• 2.5V I/O (SSTL_2 compatible)

•tRAS lockout (tRAP = tRCD)

• Backwards compatible with DDR200 and DDR266

MT46V64M4 – 16 Meg x 4 x 4 banks
MT46V32M8 – 8 Meg x 8 x 4 banks
MT46V16M16 – 4 Meg x 16 x 4 banks

For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/dramds

DDR333 COMPATIBILITY

DDR333 meets or surpasses all DDR266 timing re­quirements thus assuring full backwards compatibility
with current DDR designs. In addition, these devices
support concurrent auto-precharge and tRAS lockout
for improved timing performance. The 256Mb,
DDR333 device will support an (tREFI) average peri­odic refresh interval of 7.8us.

The standard 66-pin TSOP package is offered for
point-to-point applications where the FBGA package
is intended for the multi-drop systems.

The Micron 256Mb data sheet provides full specifi­cations and functionality unless specified herein.

CONFIGURATION

Architecture 64 Meg x 4 32 Meg x 8 16 Meg x 16

Configuration 16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
Refresh Count 8K 8K 8K
Row Addressing 8K (A0–A12) 8K (A0–A12) 8K (A0–A12)
Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
Column Addressing 2K (A0–A9, A11) 1K (A0–A9) 512 (A0– A8)

OPTIONS PART NUMBER

• Configuration
64 Meg x 4 (16 Meg x 4 x 4 banks) 64M4
32 Meg x 8 (8 Meg x 8 x 4 banks) 32M8
16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16

• Plastic Package
66-Pin TSOP (OCPL) TG
60-Ball FBGA (16x9mm) FJ

• Timing - Cycle Time

6ns @ CL = 2.5 (DDR333B–FBGA)
6ns @ CL = 2.5 (DDR333B–TSOP)

7.5ns @ CL = 2 (DDR266A)

• Self Refresh
Standard none

NOTE: 1. Supports PC2700 modules with 2.5-3-3 timing

2. Supports PC2100 modules with 2-3-3 timing

256Mb: x4, x8, x16 DDR333 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01 ©2001, Micron Technology, Inc.

‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION AND DATA SHEET SPECIFICATIONS.

2

1

-6

1

-6T

-75Z

KEY TIMING PARAMETERS

SPEED CLOCK RATE DATA-OUT ACCESS DQS-DQ

GRADE CL = 2

-6 133 MHz 167 MHz 2.15ns ±0.70ns +0.35ns

-6T 133 MHz 167 MHz 2.0ns ±0.75ns +0.45ns

-75Z 133 MHz 133 MHz 2.5ns ±0.75ns +0.50ns

NOTE: 1. CL = CAS (Read) Latency

2. With a 50/50 clock duty cycle and a minimum clock

3. -75, -8 are also available; see base data sheet.

1

CL = 2.51WINDOW2WINDOW SKEW

rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).

1

3

PRELIMINARY

256Mb: x4, x8, x16

DDR333 SDRAM Addendum

FBGA 60-BALL PACKAGE DIMENSION

0.850 ±0.075

SEATING PLANE

C

0.10 C

6.40

1.80

61X ∅0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE­REFLOW DIAMETER IS Ø 0.40

BALL A9

11.00

5.50 ±0.05

CTR

Bottom View

C

L

3.20 ±0.05

4.50 ±0.05
9 .00 ±0.10

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2%Ag
SOLDER BALL PAD: Ø .33mm

0.80 TYP

BALL A1

C

L

PIN A1 ID

8.00 ±0.05

1.00
TYP

1.20 MAX

16.00 ±0.10

SUBSTRATE: PLASTIC LAMINATE

MOLD COMPOUND: EPOXY NOVOLAC

FBGA PACKAGE MARKING

Due to the physical size of the FBGA package, the full
ordering part number is not printed on the package.
Instead the following package code is utilized.

FBGA PACKAGE PINOUT

x4 (Top View)

123456 789

A

V

B
C
D
E

V

F
G
H

J

K
L

M

A

V

B
C

D

E

F
G
H

J

K

L
M

NC

SS

NC
NC
NC
NC

REF

Q

V

V

V

V

DD

SS

DD

SS

SS

V

CK

A12
A11

A8

A6

A4

VSS

Q

DQ3

Q

NC

Q

DQ2

Q

DQS

DM
CK#
CKE

A9
A7
A5

SS

V

x8 (Top View)

123456 789

DQ7

SS

V

NC
NC
NC
NC

Q

V

V

V

V

REF

DD

SS

DD

SS

SS

V

CK

A12
A11

A8

A6

A4

VSS

Q

DQ6

Q

DQ5

Q

DQ4

Q

DQS

DM
CK#
CKE

A9
A7
A5

SS

V

A
B
C
D
E
F
G
H

J

K
L
M

A
B
C
D
E
F
G
H

J

K
L

M

V

DD

DQ0

NC

DQ1

NC
NC

WE#

RAS#

BA1

A0
A2

DD

V

V

DD

DQ1
DQ2
DQ3

NC
NC

WE#

RAS#

BA1

A0
A2

DD

V

NC

SS

V

DD

V

V

SS

DD

V

DD

V

CAS#

CS#

BA0
A10

A1

A3

DQ0

SS

V

DD

V

SS

V

DD

V

DD

V

CAS#

CS#

BA0
A10

A1
A3

V

DD

Q

Q

NC

Q

NC

Q

NC

Q

NC

A13

V

DD

Q

Q

NC

Q

NC

Q

NC

Q

NC

A13

Top mark contains five fields 12345

• Field 1 (Product Family)
DRAM D
DRAM - ES Z

• Field 2 (Product Type)

2.5 Volt, DDR SDRAM, 60-ball L

• Field 3 (Width)
x4 devices B
x8 devices C
x16 devices D

123456 789

A
B
C
D
E
F
G
H

J

K
L

M

V

SS

Q

DQ14
DQ12
DQ10

DQ8

REF

V

DQ15

DD

V

V

SS

Q

DD

V

SS

Q

V

SS

V

CK

A12
A11

A8

A6

A4

Q
Q

VSS

DQ13
DQ11

DQ9

UDQS

UDM

CK#
CKE

A9

A7

A5

V

x16 (Top View)

SS

A
B
C
D
E
F
G
H

J

K
L

M

V

DD

DQ2
DQ4
DQ6

LDQS

LDM
WE#

RAS#

BA1

A0
A2

DD

V

DQ0

SS

V

DD

V

SS

V

DD

V

V

DD

CAS#

CS#

BA0
A10

A1
A3

V

DD

Q

Q

DQ1

Q

DQ3

Q

DQ5

Q

DQ7

A13

• Field 4 (Density / Size)
256Mb H

• Filed 5 (Speed Grade)

-6 J

-75Z P

-75 F

-8 C

Example top mark for a MT46V32M4FJ-6: DLBFJ

256Mb: x4, x8, x16 DDR333 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01 ©2001, Micron Technology, Inc.

2

PRELIMINARY

256Mb: x4, x8, x16

DDR333 SDRAM Addendum

66-PIN TSOP PACKAGE DIMENSION

PIN #1 ID

0.10

0.65 TYP

+0.10

-0.05

22.22 ± 0.08

0.32 ± .075 TYP

DETAIL A

1.20 MAX

GAGE PLANE

0.71

0.10 (2X)

11.76 ±0.10

10.16 ±0.08

0.10

0.25

0.80 TYP

0.50 ±0.10

0.15

SEE DETAIL A

+0.03

-0.02

66-PIN TSOP PACKAGE PIN ASSIGMENT

(TOP VIEW)

V

NC

V

DD

NC

DQ0

V

SS

NC
NC

V

DD

NC

DQ1

V

SS

NC
NC

V

DD

NC
NC

V

DNU

NC

WE#
CAS#
RAS#

CS#

NC

BA0
BA1

A10/AP

A0

A1

A2

A3

V

DD

Q

Q

Q

Q

Q

DD

DD

x8x4

V

DQ0

V

DD

DQ1

V

SS

DQ2

V

DD

DQ3

V

SS

V

DD

V

DNU

WE#
CAS#
RAS#

CS#

BA0
BA1

A10/AP

V

DD

NC

NC

NC

NC
NC

NC
NC

DD

NC

NC

A0
A1
A2
A3

DD

Q

Q

Q

Q

Q

x16

VDD

DQ0

VDDQ

DQ1

DQ2

VssQ

DQ3

DQ4

VDDQ

DQ5
DQ6

VssQ

DQ7

V

DD

LDQS

VDD

DNU

LDM

WE#
CAS#
RAS#

CS#

BA0
BA1

A10/AP

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14

NC

15

Q

16
17

NC

18
19
20
21
22
23
24
25

NC

26
27
28
29

A0

30

A1

31

A2

32

A3

33

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

x16
V

SS

DQ15

V

SS

Q

DQ14
DQ13

V

DD

DQ12
DQ11

V

SS

Q

DQ10
DQ9

V

DD

DQ8

NC
V

SS

Q

UDQS

DNU

V

REF

V

SS

UDM
CK#
CK
CKE
NC

A12
A11
A9
A8
A7
A6
A5
A4

V

SS

Q

Q

x8 x4

V

SS

DQ7

V

SS

Q
NC

DQ6

V

DD

Q
NC

DQ5

V

SS

Q
NC

DQ4

V

DD

Q
NC
NC
V

SS

Q

DQS

DNU

V

REF

V

SS

DM
CK#
CK
CKE
NC

A12
A11
A9
A8
A7
A6
A5
A4

V

SS

V

SS

NC
V

SS

NC

DQ3

V

DD

NC
NC
V

SS

NC

DQ2

V

DD

NC
NC
V

SS

DQS

DNU

V

REF

V

SS

DM
CK#
CK
CKE
NC

A12
A11
A9
A8
A7
A6
A5
A4

V

SS

Q

Q

Q

Q

Q

NOTE: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm
per side.

256Mb: x4, x8, x16 DDR333 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01 ©2001, Micron Technology, Inc.

3

PRELIMINARY

256Mb: x4, x8, x16

DDR333 SDRAM Addendum

PIN DESCRIPTIONS

BALL / PIN NUMBERS

FBGA TSOP SYMBOL TYPE DESCRIPTION

G2, G3

H3 44 CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the

H8 24 CS# Input Chip Select: CS# enables (registered LOW) and disables (regis-

H7, G8, G7 23, 22, 21 RAS#, CAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

3F 47 DM Input Input Data Mask: DM is an input mask signal for write data. Input

F7, 3F 20, 47 LDM, UDM data is masked when DM is sampled HIGH along with that input

J8,J7 26, 27 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an

K7, L8, L7 29-32 A0, A1, A2 Input Address Inputs: Provide the row address for ACTIVE commands, and

M8, M2, L3 32, 35, 36 A3, A4, A5 the column address and auto precharge bit (A10) for READ/WRITE

L2, K3, K2 36, 38, 39 A6, A7, A8 commands, to select one location out of the memory array in the

J3, K8, J2 40, 29, 41 A9, A10, A11 respective bank. A10 sampled during a PRECHARGE command

H2 42 A12 determines whether the PRECHARGE applies to one bank (A10 LOW,

45, 46 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.

internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous
for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER­DOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after VDD is applied.

tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.

WE# command being entered.

data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins. For the x16 , LDM is
DM for DQ0-DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC
on x4 and x8

ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET command. BA0
and BA1 define which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER command.

(continued on next page)

256Mb: x4, x8, x16 DDR333 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01 ©2001, Micron Technology, Inc.

4

PRELIMINARY

256Mb: x4, x8, x16

DDR333 SDRAM Addendum

PIN DESCRIPTIONS (continued)

BALL / PIN NUMBERS

FBGA TSOP SYMBOL TYPE DESCRIPTION

A8, B9, B7
C9, C7, D9

D7, E9, E1
D3, D1, C3
C1, B3, B1,

A2

A8, B7, C7,

D7, D3, C3,

B3, A2

B7, D7, D3,

B3 62 DQ2

E3

E7, E3

B2, D2, C8, 3, 9, 15, 55, VDDQ Supply DQ Power Supply: +2.5V ±0.2V. Isolated on the die for improved

E8, A9 61 noise immunity.

A1, C2, E2, 6, 12, 52, VSSQ Supply DQ Ground. Isolated on the die for improved noise immunity.

B8, D8 58, 64

F8, M7, A7 1, 18, 33 VDD Supply Power Supply: +2.5V ±0.2V.

A1, A3, F2, 34, 48, 66 VSS Supply Ground.

M3

F1 49 VREF Supply SSTL_2 reference voltage.

F9 17 A13 I Address input A13 for 1Gb devices.

2, 4, 5, DQ0-2 I/O Data Input/Output: Data bus for x16

7, 8, 10 DQ3-5
11, 13, 54 DQ6-8
56, 57, 59 DQ9-11

60, 62, 63, DQ12-14

65 DQ15

2, 5, 8, DQ0-2 I/O Data Input/Output: Data bus for x8

11, 56, 59 DQ3-5

62, 65 DQ6-7

5, 11, 56 DQ0-2 I/O Data Input/Output: Data bus for x4

51 DQS I/O Data Strobe: Output with read data, input with write data. DQS is

16, 51

14, 17, 25,

43, 53

19, 50 DNU – Do Not Use: Must float to minimize noise on Vref

LDQS, UDQS

NC -

edge-aligned with read data, centered in write data. It is used to
capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS
IS DQS for DQ8-DQ15. Pin 16 (H7) is NC on x4 and x8.

No Connect: These pins should be left unconnected.

256Mb: x4, x8, x16 DDR333 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01 ©2001, Micron Technology, Inc.

5

PRELIMINARY

256Mb: x4, x8, x16

DDR333 SDRAM Addendum

GENERAL DESCRIPTION

The DDR333 SDRAM is a high-speed CMOS, dy­namic random-access memory that operates at a fre­quency of 167 MHz (tCK=6ns) with a peak data trans­fer rate of 333Mb/s/p. DDR333 continues to use the
JEDEC standard SSTL_2 interface and the 2n-prefetch
architecture.

The standard DDR200/DDR266 data sheets also
pertain to the DDR333 device and should be referenced
for a complete description of DDR SDRAM function-

CAPACITANCE (FBGA)

(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ T

PARAMETER SYMBOL MIN MAX UNITS NOTES

Delta Input/Output Capacitance:

DQs, DQS, DM (for x4 or x8 devices) DCIO – 0.50 pF 13, 24

DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices), DCIO – 0.50 pF 13, 24

DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices) DCIO – 0.50 pF 13, 29

Delta Input Capacitance: Command and Address DCI1 – 0.50 pF 13, 29

Delta Input Capacitance: CK, CK# DCI2 – 0.25 p F 13, 29

Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM) CIO 3.50 4.00 pF 13

Input Capacitance: Command and Address CI1 1.50 2.50 pF 13

Input Capacitance: CK, CK# CI2 1.50 2.50 p F 13

Input Capacitance: CKE CI3 1.50 2.50 pF 13

≤ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

A

ality and operating modes. However, to meet the faster
DDR333 operating frequencies, some of the AC timing
parameters are slightly tighter. This addendum data
sheet will concentrate on the key differences required
to support the enhanced speeds.

In addition to the standard 66-pin TSOP package,
a 60-ball FBGA package is utilized for DDR333. This
JEDEC-defined package promotes better package para­sitic parameters and a smaller footprint.

CAPACITANCE (TSOP)

(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ TA ≤ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

PARAMETER SYMBOL MIN MAX UNITS NOTES

Delta Input/Output Capacitance:

DQs, DQS, DM (for x4 or x8 devices) DCIO – 0.50 pF 13, 24

DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices), DCIO – 0.50 pF 13, 24

DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices) DCIO – 0.50 pF 13, 24

Delta Input Capacitance: Command and Address DCI1 – 0.50 pF 13, 29

Delta Input Capacitance: CK, CK# DCI2 – 0.25 p F 13, 29

Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM) CIO 4.0 5.0 pF 13

Input Capacitance: Command and Address CI1 2.0 3.0 pF 13

Input Capacitance: CK, CK# CI2 2.0 3.0 p F 13

Input Capacitance: CKE CI3 2.0 3.0 pF 13

256Mb: x4, x8, x16 DDR333 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01 ©2001, Micron Technology, Inc.

6

PRELIMINARY

256Mb: x4, x8, x16

DDR333 SDRAM Addendum

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ TA ≤ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

AC CHARACTERISTICS -6 (FBGA) -6T (TSOP) -75Z
PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

Access window of DQs from CK/CK#
CK high-level width
CK low-level width

Clock cycle time CL = 2.5tCK (2.5) 6 13 6 13 7.5 13 ns 45,52

CL = 2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per accesstDQSQ 0.35 0.45 0.50 ns 25, 26
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access

Data Hold Skew Factor

ACTIVE to AUTOPRECHARGE command
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window na
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VDD

Exit SELF REFRESH to non-READ command

Exit SELF REFRESH to READ command

t

AC -0.7 +0.7 -0.7 +0.7 -0.75 +0.75 ns

t

CH 0.45 0.55 0.45 0.55 0.45 0.55tCK 30

t

CL 0.45 0.55 0.45 0.55 0.45 0.55tCK 30

t

CK (2) 7.5 13 7.5 13 7.5 13 ns 45,52

t

DH 0.45 0.45 0.50 ns 26,31

t

DS 0.45 0.45 0.50 ns 26,31

t

DIPW 1.75 1.75 1.75 ns 31

t

DQSCK -0.60 +0.60 -0.60 +0.60 -0.75 +0.75 ns

t

DQSH 0.35 0.35 0.35

t

DQSL 0.35 0.35 0.35

t

DQSS 0.75 1.25 0.75 1.25 0.75 1.25tCK

t

DSS 0.2 0.2 0.2

t

DSH 0.2 0.2 0.2

t

HP

t

HZ +0.70 +0.70 +0.75 ns 18,42

t

t

IH

t

t

IH

t

t

IPW 2.2 2.2 2.2 ns

t

MRD 12 12 15 ns

t

QH

t

QHS 0.50 0.60 0.75 ns

t

RAP 18 18 20 ns 46

t

RAS 42 70,000 42 70,000 40 120,000 ns 35

t

RC 60 60 65 ns

t

RFC 72 72 75 ns 50

t

RCD 18 18 20 ns

t

RP 18 18 20 ns

t

RPRE 0.9 1.1 0.9 1 .1 0.9 1.1

t

RPST 0.4 0.6 0.4 0.6 0.4 0.6

t

RRD 12 12 15 ns

t

WPRE 0.25 0.25 0.25

t

WPRES 0 0 0 ns 20, 21

t

WPST 0.4 0.6 0.4 0.6 0.4 0.6

t

WR 15 15 15 ns

t

WTR 1 1 1

t

REFC 70.3 70.3 70.3 µs 23

t

REFI 7.8 7.8 7.8 µs 23

t

VTD 0 0 0 ns

t

XSNR 75 75 75 ns

t

XSRD 200 200 200

t

CH,tCL

t

CH,tCL

t

CH,tCL ns 34

LZ -0.70 -0.70 -0.75 ns 18,43

0.75 0.75 0.90 ns 14

F

IS

IS

0.75 0.75 0.90 ns 14

F

0.80 0.80 1 ns 14

S

0.80 0.80 1 ns 14

S

t

HP

t

QHS

-

t

QH - tDQSQ tQH - tDQSQ

-

t

HP

t

QHS

t

HP ns 25, 26

t

QHS

-

t

QH - tDQSQ ns 25

t

CK

t

CK

t

CK

t

CK

t

CK 42

t

CK

t

CK

t

CK 19

t

CK

t

CK

256Mb: x4, x8, x16 DDR333 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01 ©2001, Micron Technology, Inc.

7

PRELIMINARY

256Mb: x4, x8, x16

DDR333 SDRAM Addendum

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: [phone]

E-mail: [e-mail], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.

256Mb: x4, x8, x16 DDR333 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01 ©2001, Micron Technology, Inc.

8