Datasheet MSP3460G Datasheet (Micronas Intermetall)

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MSP 34x0G Multistandard Sound Processor Family

Edition Jan. 19, 2001 6251-476-4PD

PRELIMINARY DATA SHEET

MICRONAS

Page 2

MSP 34x0G PRELIMINARY DATA SHEET

Contents

Page Section Title

5 1. Introduction

6 1.1. Features of the MSP 34x0G Family and Differences to MSPD 6 1.2. MSP 34x0G Version List 7 1.3. MSP 34x0G Versions and their Application Fields

8 2. Functional Description

9 2.1. Architecture of the MSP 34x0G Family 9 2.2. Sound IF Processing 9 2.2.1. Analog Sound IF Input 9 2.2.2. Demodulator: Standards and Features 10 2.2.3. Preprocessing of Demodulator Signals 10 2.2.4. Automatic Sound Select 10 2.2.5. Manual Mode

12 2.3. Preprocessing for SCART and I 12 2.4. Source Selection and Output Channel Matrix 12 2.5. Audio Baseband Processing 12 2.5.1. Automatic Volume Correction (AVC) 12 2.5.2. Loudspeaker and Headphone Outputs 12 2.5.3. Subwoofer Output 12 2.5.4. Quasi-Peak Detector 13 2.5.5. Micronas Dynamic Bass (MDB) 13 2.5.5.1. Dynamic Amplification 13 2.5.5.2. Adding Harmonics 13 2.5.5.3. MDB Parameters 13 2.6. SCART Signal Routing 13 2.6.1. SCART DSP In and SCART Out Select 13 2.6.2. Stand-by Mode

14 2.7. I

S Bus Interface 14 2.8. ADR Bus Interface 14 2.9. Digital Control I/O Pins and Status Change Indication 14 2.10. Clock PLL Oscillator and Crystal Specifications

S Input Signals

15 3. Control Interface

15 3.1. I

C Bus Interface 15 3.1.1. Internal Hardware Error Handling 16 3.1.2. Description of CONTROL Register 16 3.1.3. Protocol Description

17 3.1.4. Proposals for General MSP 34x0G I

C Telegrams 17 3.1.4.1. Symbols 17 3.1.4.2. Write Telegrams 17 3.1.4.3. Read Telegrams 17 3.1.4.4. Examples

17 3.2. Start-Up Sequence: Power-Up and I

C-Controlling 17 3.3. MSP 34x0G Programming Interface 17 3.3.1. User Registers Overview 21 3.3.2. Description of User Registers 22 3.3.2.1. STANDARD SELECT Register

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PRELIMINARY DATA SHEET

Contents, continued

Page Section Title

22 3.3.2.2. Refresh of STANDARD SELECT Register 22 3.3.2.3. STANDARD RESULT Register 24 3.3.2.4. Write Registers on I 26 3.3.2.5. Read Registers on I2C Subaddress 11 27 3.3.2.6. Write Registers on I2C Subaddress 12 40 3.3.2.7. Read Registers on I2C Subaddress 13

C Subaddress 10

hex hex hex hex

41 3.4. Programming Tips 41 3.5. Examples of Minimum Initialization Codes 41 3.5.1. B/G-FM (A2 or NICAM) 41 3.5.2. BTSC-Stereo 41 3.5.3. BTSC-SAP with SAP at Loudspeaker Channel 42 3.5.4. FM-Stereo Radio 42 3.5.5. Automatic Standard Detection 42 3.5.6. Software Flow for Interrupt driven STATUS Check

MSP 34x0G

44 4. Specifications

44 4.1. Outline Dimensions 46 4.2. Pin Connections and Short Descriptions 49 4.3. Pin Descriptions 52 4.4. Pin Configurations 56 4.5. Pin Circuits 58 4.6. Electrical Characteristics 58 4.6.1. Absolute Maximum Ratings 59 4.6.2. Recommended Operating Conditions (T

= 0 to 70 °C)

59 4.6.2.1. General Recommended Operating Conditions 59 4.6.2.2. Analog Input and Output Recommendations 60 4.6.2.3. Recommendations for Analog Sound IF Input Signal 61 4.6.2.4. Crystal Recommendations 62 4.6.3. Characteristics 62 4.6.3.1. General Characteristics 63 4.6.3.2. Digital Inputs, Digital Outputs 64 4.6.3.3. Reset Input and Power-Up

65 4.6.3.4. I 66 4.6.3.5. I

C-Bus Characteristics

S-Bus Characteristics 68 4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC 69 4.6.3.7. Sound IF Inputs 69 4.6.3.8. Power Supply Rejection 70 4.6.3.9. Analog Performance 73 4.6.3.10. Sound Standard Dependent Characteristics

77 5. Appendix A: Overview of TV-Sound Standards

77 5.1. NICAM 728 78 5.2. A2-Systems 79 5.3. BTSC-Sound System 79 5.4. Japanese FM Stereo System (EIA-J) 80 5.5. FM Satellite Sound 80 5.6. FM-Stereo Radio

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MSP 34x0G PRELIMINARY DATA SHEET

Contents, continued

Page Section Title

81 6. Appendix B: Manual/Compatibility Mode

81 6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode 82 6.2. DSP Write and Read Registers for Manual/Compatibility Mode 83 6.3. Manual/Compatibility Mode: Description of Demodulator Write Registers 83 6.3.1. Automatic Switching between NICAM and Analog Sound 83 6.3.1.1. Function in Automatic Sound Select Mode 83 6.3.1.2. Function in Manual Mode 85 6.3.2. A2 Threshold 85 6.3.3. Carrier-Mute Threshold 86 6.3.4. Register AD_CV 87 6.3.5. Register MODE_REG 89 6.3.6. FIR-Parameter, Registers FIR1 and FIR2 89 6.3.7. DCO-Registers 91 6.4. Manual/Compatibility Mode: Description of Demodulator Read Registers 91 6.4.1. NICAM Mode Control/Additional Data Bits Register 91 6.4.2. Additional Data Bits Register 91 6.4.3. CIB Bits Register 92 6.4.4. NICAM Error Rate Register 92 6.4.5. PLL_CAPS Readback Register 92 6.4.6. AGC_GAIN Readback Register 92 6.4.7. Automatic Search Function for FM-Carrier Detection in Satellite Mode 93 6.5. Manual/Compatibility Mode: Description of DSP Write Registers 93 6.5.1. Additional Channel Matrix Modes 93 6.5.2. Volume Modes of SCART1/2 Outputs 93 6.5.3. FM Fixed Deemphasis 93 6.5.4. FM Adaptive Deemphasis 94 6.5.5. NICAM Deemphasis 94 6.5.6. Identification Mode for A2 Stereo Systems 94 6.5.7. FM DC Notch 94 6.6. Manual/Compatibility Mode: Description of DSP Read Registers 94 6.6.1. Stereo Detection Register for A2 Stereo Systems 94 6.6.2. DC Level Register 95 6.7. Demodulator Source Channels in Manual Mode 95 6.7.1. Terrestric Sound Standards 95 6.7.2. SAT Sound Standards 97 6.8. Exclusions of Audio Baseband Features 97 6.9. Phase Relationship of Analog Outputs 97 6.10. Compatibility Restrictions to MSP 34x0D

98 7. Appendix D: MSP 34x0G Version History

99 8. Appendix E: Application Circuit

100 9. Data Sheet History

License Notice:

“Dolby Pro Logic” is a trademark of Dolby Laboratories. Supply of this implementation of Dolby T echnolog y does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.

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PRELIMINARY DATA SHEET MSP 34x0G

Multistandard Sound Processor Family

Release Note: Revision bars indicate significant changes to the previous edition. The hardware and software description in this document is valid for the MSP 34x0G version B8 and following versions.

1. Introduction

The MSP 34x0G family of single-chip Multistandard Sound Processors covers the sound processing of al l analog TV-Standards worldwide, as well as the NICAM digital sound standar ds. The full TV sound process in g, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure 1–1 shows a simplified functional block diagram of the MSP 34x0G.

This new generation of TV sound processing ICs now includes versions for processing the multichan nel television sound (MTS) s ignal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free.

Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.

Current ICs have to perform adjustment procedu res in order to achieve good stereo sepa ration for BTSC and EIA-J. The MSP 34x0G has optimum stereo performance without any adjustments.

All MSP 34xxG versions are pin compatible to the MSP 34xxD. Only minor modifications are necessary to adapt a MSP 34xxD controlling software to the MSP 34xxG. The MSP 34x0G further simplifies controlling software. St andard selection requi res a single

C transmission only.

I The MSP 34x0G has built-in automatic functions: The

IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification sign als can be evaluated internally with subsequent switching between mono/ stereo/bilingual; no I

C interaction is ne cessar y (Auto-

matic Sound Selectio n) . The MSP 34x0G can handl e very high FM deviations

even in conjunction with NICAM processing. This is especially impor tant for the introduction of NICAM in China.

The ICs are produced in submicron CMOS technology. The MSP 34x0G is available in the following packages: PLCC68 (not intended for new design), PSDIP64, PSDIP52, PQFP80, and PLQFP64.

Sound IF1

Sound IF2

I2S1 I2S2

SCART1

SCART2

SCART3

SCART4

MONO

ADC

SCART

DSP

Input

Select

De-

modulator

ADC

Pre-

processing

Prescale

Fig. 1–1: Simplified functional block diagram of the MSP 34x0G

Loud-

speaker

Sound

Processing

Headphone

Sound

Processing

Source Select

DAC

SCART Output

Select

Loudspeaker

Subwoofer

Headphone

I2S

SCART1

SCART2

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MSP 34x0G PRELIMINARY DATA SHEET

1.1. Features of the MSP 34x0G Family and Differences to MSPD

Feature (New features not available for MSPD are shaded gray. ) 3400 3410 3420 3440 3450 3460

Standard Selection with single I Automatic Standard Detection of terrestrial TV standards/Automatic Carrier Mute function X X XXXX

C transmission XXXXXX

Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS Two selectable sound IF (SIF) inputs X X XXXX Automatic Carrier Mute function XXXXXX Interrupt output programmable (indicating status change) Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness X X XXXX Loudspeaker channel with MDB (Micronas Dynamic Bass) AVC: Automatic Volume Correction XXXXXX Subwoofer output with programmable low-pass and complementary high-pass filter X X XXXX 5-band graphic equalizer for loudspeaker channel X X XXXX Spatial effect for loudspeaker channel X X XXXX Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs X X XXXX Complete SCART in/out switching matrix XXXXXX

Two I

S inputs; one I2S output XXXXXX All analog Mono sound carriers including AM-SECAM L XXXXXX All analog FM-Stereo A2 and satellite standards X X X Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification) X X X X

X X X X X

X X X X X X

X X

ASTRA Digital Radio (ADR) together with DRP 3510A X X X X All NICAM standards XX Demodulation of the BTSC multiplex signal and the SAP channel Alignment free digital DBX noise reduction for BTSC Stereo and SAP Alignment free digital Micronas Noise Reduction (MNR) for BTSC Stereo and SAP BTSC stereo separation (MSP 3420/40G also EIA-J) significantly better than spec. SAP and stereo detection for BTSC system Korean FM-Stereo A2 standard X X X X X Alignment-free Japanese standard EIA-J Demodulation of the FM-Radio multiplex signal

X X X

X X X X X X X X X

X X X X X X

1.2. MSP 34x0G Version List

Version Status Description

MSP 3400G available FM Stereo (A2) Version MSP 3410G available NICAM and FM Stereo (A2) Version MSP 3420G available NTSC Version (A2 Korea, BTSC with Micronas Noise Reduction (MNR), Japanese EIA-J system) MSP 3440G available NTSC Version (A2 Korea, BTSC with DBX noise reduction, Japanese EIA-J system) MSP 3450G available Global Version (all sound standards) MSP 3460G not confirmed Global Mono Version (all sound standards)

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PRELIMINARY DATA SHEET MSP 34x0G

1.3. MSP 34x0G Versions and their Application Fields

Table 1–1 provides an overview of TV sound standards that can be processed by the MSP 34x0G family. In addition, the MSP 34x0G is able to handle the FMRadio standard. With the MSP 34x0G, a complete

multimedia receiver covering all TV sound standards together with te rrestr ial/ cable and satel lite radio sou nd can be built; even ASTRA Digital Radio can be processed (with a DRP 3510A coprocessor).

Table 1–1: TV Stereo Sound Standards covered by the MSP 34x0G IC Family (details see Appendix A)

MSP Version

3400

3410

TVSystem

B/G

L 6.5/5.85 AM-Mono/NICAM SECAM-L France I 6.0/6.552 FM-Mono/NICAM PAL UK, Hong Kong

D/K

3450

Satellite

Position of Sound Carrier /MHz

5.5/5.7421875 FM-Stereo (A2) PAL Germany

5.5/5.85 FM-Mono/NICAM PAL Scandinavia, Spain

6.5/6.2578125 FM-Stereo (A2, D/K1) SECAM-East Slovak. Rep.

6.5/6.7421875 FM-Stereo (A2, D/K2) PAL currently no broadcast

6.5/5.7421875 FM-Stereo (A2, D/K3) SECAM-East Poland

6.5/5.85 FM-Mono/NICAM (D/K, NICAM) PAL China, Hungary

6.5

7.02/7.2

7.38/7.56 etc.

Sound Modulation

FM-Mono FM-Stereo

ASTRA Digital Radio (ADR) with DRP 3510A

Color System

PAL

Broadcast e.g. in:

Europe Sat. ASTRA

4.5/4.724212 FM-Stereo (A2) NTSC Korea

M/N

3420, 3440

FM-Radio 10.7 FM-Stereo Radio USA, Europe

3460 all Standards as above but Mono demodulation only.

SAW Filter

Tuner

Composite Video

4.5 FM-FM (EIA-J) NTSC Japan

4.5 BTSC-Stereo + SAP NTSC, PAL USA, Argentina

33 34 39 MHz 4.5 9 MHz

Sound IF Mixer

Vision Demodulator

SCART Inputs

Mono

SCART1 SCART2 SCART3

SCART4

MSP 34x0G

SCART1 SCART2

Loudspeaker

Subwoofer

Headphone

SCART Outputs

I2S2ADRI2S1

Dolby Pro Logic Processor DPL 351xA

ADR Decoder DRP 3510A

Fig. 1–2: Typical MSP 34x0G application

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ANA_IN1+

ANA_IN2+

ADR-Bus Interface

AGC

Standard Selection

DEMODULATOR

(incl. Carrier Mute)

Decoded Standards:

− NICAM

− A2

− AM

− BTSC

− EIA-J

− SAT

− FM-Radio

Deemphasis: 50/75 µs, J17 DBX/MNR Panda1

Deemphasis

J17

Standard

and Sound

Detection

FM/AM

Prescale

(0E

NICAM

Prescale

(10

I2C

Read

Sound Select

)

hex

)

hex

Automatic

FM/AM

Stereo or A/B

Stereo or A

Stereo or B

2. Functional Description

Loud-

speaker Channel

Matrix

(08

)

hex

AVC

(29

Bass/

Treble

Equalize

)

hex

)

(02

hex

(03

)

hex

Loudness

(04

hex

Beeper

(14

)

hex

Comple-

Spatial

mentary

Highpass

)(05

(2D

0.5

hex

Lowpass

(2D

hex

Balance

Level

Adjust

Volume

)

hex

(00

)

hex

Effects

)(01

)

hex

)(2C

DACM_L

DACM_R

MDB

)

hex

DACM_SUB

MSP 34x0G PRELIMINARY DATA SHEET

I2S_DA_IN1

I2S_DA_IN2

SC1_IN_L

Headphone

I2S

Interface

I2S

Interface

I2S1

Prescale

)

(16

hex

I2S2

Prescale

(12

)

hex

SCART

Prescale

(0D

)

hex

SCART DSP Input Select

(13

)

hex

Source Select

Channel

Matrix

(09

I2S

Channel

Matrix

(0B

Quasi-Peak

Channel

Matrix

(0C

SCART1

Channel

Matrix

(0A

SCART2

Channel

Matrix

(41

)

hex

I2S

Interface

)

hex

Quasi-Peak

Detector

)

hex

Volume

(07

)

hex

Volume

)(40

hex

Bass/

Treble

(31/32

)(33

hex

I2C

Read

Loudness

hex

(19

)

hex

)

(1A

hex

)

SCART1_L/R

SCART2_L/R

)

SC1_IN_R SC2_IN_L SC2_IN_R SC3_IN_L

SCART Output Select

SC3_IN_R SC4_IN_L

SC4_IN_R MONO_IN

Fig. 2–1: Signal flow block diagram of the MSP 34x0G (input and output names correspond to pin names)

)

I2S_DA_OUT

)

(13

hex

SC1_OUT_L

SC1_OUT_R

SC2_OUT_L

SC2_OUT_R

Balance

(30

Volume

DACA_L

)

(06

hex

)

hex

DACA_R

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PRELIMINARY DATA SHEET MSP 34x0G

2.1. Architecture of the MSP 34x0G Family

Fig. 2–1 on page 8 shows a simplified block diagram of the IC. The block diagram contains all features of the MSP 3450G. Other members of the MSP 34x0G family do not have the complete set of features: The demodulator handles only a subset of the standards presented in the demodulator block; NICAM processing is only possible in the MSP 3410G and MSP 3450G.

2.2. Sound IF Processing

2.2.1. Analog Sound IF Input

The input pins ANA_IN1+, ANA_IN2+, and ANA_IN− offer the possibility to connect two different sound IF (SIF) sources to the MSP 34x0G. The analog-to-digital conversion of the preselected sound IF sign al is done by an A/D-converter. An analog automatic gain ci rcuit (AGC) allows a wide range of input levels. The highpass filters formed by the coupling capacitors at pins ANA_IN1+ and ANA_IN2+ see Section 8. “Appendix E: Applicati on C ircui t” on page 99 are sufficient in most cases to suppr es s vid eo c omp one nts. S ome combinations of SAW filters and sound IF mi xer ICs, however, show large picture components on their outputs. In this case, further filtering is recommended.

2.2.2. Demodulator: Standards and Features

The MSP 34x0G is able to demodulate all TV-sound standards worldwide inc luding the digital NICAM system. Depending on the MSP 34x0G version, the following demodulation modes can be performed:

A2 Systems: Detection and demodu lation of two separate FM carriers ( FM1 and FM2), demodulation and evaluation of the identification signal of carrier FM2.

NICAM Systems: Demodulati on and decoding of t he NICAM carrier, detection and demodulation of the analog (FM or AM) carrier. For D/K-NICAM, the FM carrier may have a maximum deviation of 384 kHz.

Very high deviation FM-Mono: Detection and robust demodulation of on e FM carr ier with a maximum deviation of 540 kHz.

BTSC-Stereo: Detection a nd FM demodulati on of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carr ier, AM demodulation of the (L−R)-carr ier a nd detecti on of the S AP subcarrier. Processing of DBX noise reduction or Micronas Noise Reduction (MNR).

BTSC-Mono + SAP: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot car rier, detection and FM demodulation of the SAP s ubcarrie r. Processing of DBX n oise reducti on or Micr onas Noise Reduction (MNR).

Japan Stereo: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Demodulation and evaluation of the identification signal and FM demodulation of the (L−R)-carrier.

FM-Satellite Sound: Demodulation of one or two FM carriers. Processi ng of high-deviation mono or na rrow bandwidth mono, stereo, or bilingual satellite sound according to the ASTRA specification.

FM-Stereo-Radio: Detection and FM d emodulati on of the aural carrier resu lting in the MPX si gnal. Detecti on and evaluation of the pilot carrier and AM demodulation of the (L−R)-carrier.

The demodulator blocks of all MSP 34x0G versions have identical user interfaces. Even completely different systems like the BTSC and NICAM systems are controlled the same way. Standards are selected by means of MSP Standard Cod es. Automatic processes handle standard detection and identification without controller interaction. The key features of the MSP 34x0G demodulator blocks are:

Standard Selection: The controlling of the de modula tor is minimized: All parameters, such as tuning frequencies or filter bandwidth, are adjusted automatically by transmitting one single value to the STANDARD SELECT reg ister. For all standards, specific MSP standard codes are defined.

Automatic Standar d Detecti on: If the TV sound standard is unknown, the MSP 34x0G can automatically detect the actual standard, switch to that standard, and respond the actual MSP standard code.

Automatic Carrier Mute: To prevent noise effects or FM identification problems in the absence of an FM carrier, the MSP 34x0G offers a configurable carrier mute feature, which is activated automatically if th e T V sound standard is selected by means of the STANDARD SELECT register. If no FM carrier is detected at one of the two MSP demodulator channels, the corresponding demodulator output is muted. This is indicated in the STATUS register.

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MSP 34x0G PRELIMINARY DATA SHEET

2.2.3. Preprocessing of Demodulator Signals

The NICAM signals must be processed by a deemphasis filter and adjusted in level. The analog demodulated signals must b e processed by a deemphas is filter, adjusted in level, and dematrixed. The correct deemphasis filters are already selected by setting th e standard in the STANDARD SELECT register. The level adjustment has to be done by means of the FM/ AM and NICAM prescale registers. The necessary dematrix function depends on the selected sound standard and the actual broadcasted sound mode (mono, stereo, or bilingual). It can be manually set by the FM Matrix Mode register or automatically by the Automatic Sound Selection.

2.2.4. Automatic Sound Select

In the Automatic Sound Select mode, the dematrix function i s aut om a t ica l ly s el ec t ed ba se d on th e id ent if i cation information in the ST ATUS register. No I

C interaction is necessary when the broadcasted sound mode changes (e.g. from mono to stereo).

The demodulator sup ports the identification ch eck by switching between mono-compatible standards (standards that have the same FM-Mon o carrier) automatically and non-audible. If B/G-FM or B/G-NICAM is selected, the MSP will switch between these standards. The same action is performed for the standards: D/K1-FM, D/K2-FM, D/K3-FM and D/K-NICAM. Switching is only d one in th e abse nce of a ny ste reo or bilingual identification. If identification is found, the MSP keeps the detected standard.

In case of high bit-error rates, the MSP 34x0G automatically falls back from digital NI CAM sound to analog FM or AM mono.

– “Stereo or A” channel: Analog or digital mono

sound, stereo if available. In case of bilingual broadcast, it contains language A (on left and right).

– “Stereo or B” channel: Analog or digital mono

sound, stereo if available. In case of bilingual broadcast, it contains language B (on left and right).

Fig. 2–2 and Table 2–2 show the source channel assignment of the demodulated signals in case of Automatic Sound Select mode for all sound standards.

Note: The analog primar y input channel contains the signal of the mono FM/AM c arrie r or the L+R sig nal of the MPX carrier. The secondary input channel contains the signal of the 2nd FM c arrier, the L-R signal of the MPX carrier, or the SAP signal.

Source Select

LS Ch. Matrix

Output-Ch. matrices must be set once to stereo.

primary channel

secondary channel

NICAM A

NICAM B

FM/AM

Prescale

NICAM

Prescale

Automatic

Sound Select

FM/AM

Stereo or A/B

Stereo or A

Stereo or B

Fig. 2–2: Source channel assignment of demodulated signals in Automatic Sound Select Mode

2.2.5. Manual Mo de

Fig. 2–3 shows the source channel assignment of demodulated signals in ca se of manual mode. If manual mode is required, more information can be found in Section 6.7. “Demodulator Source Channels in Manual Mode” on page 95.

Table 2–1 summarizes all actions that take place when Automatic Sound Select is switched on.

To provide more fl exibility, the Automatic Sound Select block prepares four different source channels of demodulated sound (Fi g. 2–2). By choosing one of the four demodulator channels, the p referred sound mode can be selected for each of the output chann els (loudspeaker, headphone, etc.). This is done by means of

primary channel

secondary channel

NICAM A

NICAM B

FM/AM

Prescale

NICAM

Prescale

FM-Matrix

FM/AM

NICAM

(Stereo or A/B)

Source Select

LS Ch. Matrix

Output-Ch. matrices must be set according to the standard.

the Source Select registers. The following source chan nels of demodulated sound

are defined:

Fig. 2–3: Source channel assignment of demodulated signals in Manual Mode

– “FM/AM” channel: Analog mono sound, stereo if

available. In case of NICAM, analog mono only (FM or AM mono).

– “Stereo or A/B” channel: Analog or digital mono

sound, stereo if available. In case of bilingual broadcast, it contains both languages A (left) and B (right).

2.3. Preprocessing for SCART and

S Input Signals

The SCART and I

S inputs need only be a djusted in level by means of the SCART and I ters.

S prescale regi s-

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PRELIMINARY DATA SHEET MSP 34x0G

Table 2–1: Performed actions of the Automatic Sound Selection

Selected TV Sound Standard Performed Actions

B/G-FM, D/K-FM, M-Korea, and M-Japan

B/G-NICAM, L-NICAM, I-NICAM, D/K-NICAM

Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2–2.

Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2–2.

In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches back to NICAM if possible. A hys teresis prevents periodical switching.

B/G-FM, B/G-NICAM or D/K1-FM, D/K2-FM, D/K3-FM,

and D/K-NICAM

Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and nonaudible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-mono sound carrier. Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP keeps the corresponding standard.

BTSC-STEREO, FM Radio Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator

source channels according to Table2–2. Detection of the SAP carrier.

M-BTSC-SAP In the absence of SAP, the MSP switches to BTSC-stereo if available. If SAP is detected, the MSP

switches automatically to SAP (see Table 2–2).

Table 2–2: Sound modes for the demodulator source channels with Automatic Sound Select

Source Channels in Automatic Sound Select Mode

Broadcasted Sound Standard

Selected MSP Standard

Code

Broadcasted Sound Mode

FM/AM

(source select: 0)

Stereo or A/B

(source select: 1)

Stereo or A

(source select: 3)

Stereo or B

(source select: 4)

M-Korea B/G-FM D/K-FM M-Japan

B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM

(with high deviation FM)

03, 08 04, 05, 07, 0B 30

08, 03 09 0A

, 05

0B, 04 0C, 0D

MONO Mono Mono Mono Mono

STEREO Stereo Stereo Stereo Stereo BILINGUAL:

Languages A and B Right = B NICAM not available or

analog Mono analog Mono analog Mono analog Mono

Left = A Right = B

error rate too high MONO analog Mono NICAM Mono NICAM Mono NICAM Mono STEREO analog Mono NICAM Stereo NICAM Stereo NICAM Stereo BILINGUAL:

Languages A and B

analog Mono Left = NICAM A

Right = NICAM B

NICAM A NICAM B

20, 21 MONO Mono Mono Mono Mono

STEREO Stereo Stereo Stereo Stereo

20 MONO + SAP Mono Mono Mono Mono

BTSC

21 MONO + SAP Left = Mono

STEREO + SAP Stereo Stereo Stereo Stereo

Right = SAP

STEREO + SAP Left = Mono

Right = SAP

Left = Mono Right = SAP

Mono SAP

FM Radio 40 MONO Mono Mono Mono Mono

STEREO Stereo Stereo Stereo Stereo

The Automatic Sound Select process will automatically switch to the mono compatible analog standard.

The Automatic Sound Select process will automatically switch to the mono compatible digital standard.

The MSP Standard Codes are defined in (see Table 3–7 on page 21).

Micronas 11

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MSP 34x0G PRELIMINARY DATA SHEET

−30 −24 −18 −12 −6

input level

−18

−24

output level

[dBr]

2.4. Source Selection and Output Channel Matrix

The Source Selec tor makes it possible to di stribute all source signals (o ne of the demodulator source ch annels, SCART, or I

S input) to the desir ed output ch annels (loudspeaker, headphone, etc.). Al l inpu t and o utput signals can be processed simultaneously. Each source channel is identified by a unique source address.

For each output channel, the soun d mode can be set to sound A, sound B, stereo, or mono by means of the output channel matrix.

If Automatic Sound Select is on, the output channel matrix can stay fixed to stereo (transparent) for demodulated signals.

2.5. Audio Baseband Processing

2.5.1. Automatic Volume Correction (AVC)

Different sound sources (e.g. terrestr ial chann els, SAT channels, or SCART) fairly often do not have the same volume level. Advertisements during movies usually have a higher volume level than the movie itself. This results in annoying volume changes. The Automatic V olume Correction (AVC) solves this problem by equalizing the volume level.

To prevent clipping, the AVC’s gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low level inputs. The decay time is programmable by means of the AVC register (see page 31).

2.5.2. Loudspeaker and Headphone Outputs

The following baseband features are implemented in the loudspeaker and headphone output channels: bass/treble, loudness, balan ce, and volume. A square wave beeper can be added to the loudspeaker and headphone channel. The loudspeaker channel additionally performs: equalizer (not simultaneously with bass/treble), spatial effects, and a subwoofer crossover filter.

2.5.3. Subwoofer Output

The subwoofer signal is cre ated by combining the le ft and right ch annels directly behind the loudness block using the formula (L+R)/2. Due to the division by 2, the D/A converter will not be overloaded, even with full scale input signals. The subwoofer signal is fi ltered by a third-order low-pass with programmable corner frequency followed by a level adjustment. At the loudspeaker channels, a complementary high-pass filter can be switched on. Subwoofer and loudspeaker output use the same volume (Loudspeaker Volume Register).

2.5.4. Quasi-Peak Detector

The quasi-peak r eadout register can be used to read out the quasi-peak level of any input source. The feature is based on following filter time constants:

attack time: 1.3 ms decay time: 37 ms

For input signals ranging from −24 dBr to 0 dBr, the AVC maintai ns a fixed output level of −18 dBr. Fig. 2–4 shows the AVC output level versus its input level. For prescale and volume r egisters set to 0 dB, a level of 0 dBr corresponds to full scale input/output. This is

– SCART input/output 0 dBr = 2.0 V

rms

– Loudspeaker and Aux output 0 dBr = 1.4 V

Fig. 2–4: Simplified AVC characteristics

rms

12 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

2.5.5. Micronas Dynamic Bass (MDB)

The Micronas Dynamic Bass system (MDB) extends the frequency range of loudspeakers or headphones.

Amplitude (db)

After the adaption of MDB to the loudspeakers and the cabinet, fur ther customizing of MDB a llows individual fine tuning of the sound.

The MDB is placed in the subwoofer path. For applications without a subwoofer, the enhanced bass signal can be added back onto the Left/Right chan nels (see Fig. 2–1 on page 8). Micronas Dynamic Bass combines two effects: dynamic amplification and adding harmonics.

2.5.5.1. Dynamic Amplification

Low frequency signals can be boosted while the output signal amplitude is measu red. If the amplitude comes close to a definable limit, the gain is reduced automatically in dynamic Volume mode. Therefore, the system adapts to the signal amplitu de which is really present at the output of the MSP device. Clipping effects are avoided.

(db)

Amplitude

MDB_LIMIT

Signal Level

MDB_HP

Frequency

Fig. 2–6: Adding harmonics

2.5.5.3. MDB Parameters

Several parameters allow tuning the characteri stics of MDB according to the TV loudspeaker, the cabinet, and personal preferences (see Table 3–11). For more detailed information on how to set up MDB, please refer to the corresponding application note on the Micronas homepage.

2.6. SCART Signal Routing

2.6.1. SCART DSP In and SCART Out Select

The SCART DSP Input Select and SCART Output Select blocks include full matrix switching facilities. To design a TV set with four pairs of SCART-inputs and two pairs of SCART-outputs, no external switching hardware is required. The switches are controlled by the ACB user register (see page 39).

MDB_HP MDB_LP

SUBW_FREQ

Frequency

Fig. 2–5: Dynamic amplification

2.5.5.2. Adding Harmonics

MDB exploits the psychoacou stic phenomenon of the ‘missing fundamental’. Adding harmonics of the frequency components b elow the cutoff frequency gives the impression of actually hearing the low frequency fundamental. In other words: The listener has the impression that a lo udspe aker sys tem see ms to repr oduce frequencies alt hou g physically not possi ble.

2.6.2. Stand-by Mode

If the MSP 34x0G is switched off by first pulling STANDBYQ low and t hen (a fter >1 µs delay) switching off DVSUP and AVSUP, but keeping AHVSUP (‘Stand-by’-mode), the SCART switches maintain their position and function. This allows the copying from SCART-input to SCART-output in the TV set’s stand-by mode.

In case of power on or starti ng from stand-by (switching on the DVSUP and AVSUP, RESETQ going high 2 ms later), all internal registers except th e ACB register (see page 39 ) are rese t to th e default conf iguration (see Table 3–5 on page 18). The reset position of the ACB register becomes active after the first I

C transmission into the Bas eband Processing par t. By transmitting the ACB register first, the reset state can be redefined.

Micronas 13

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MSP 34x0G PRELIMINARY DATA SHEET

2.7. I2S Bus Interface

The MSP 34x0G has a synchronous master/slave input/output interface running on 32 kHz.

The interface accepts two formats:

S_WS changes at the word boundary

1. I

2. I

S_WS changes one I2S-clock period before the

word boundaries.

S options are set by means of the MO DUS and

All I the I2S_CONFIGURATION registers.

S bus interface consists of five pins:

The I – I 2 S _ D A _ I N 1 , I 2 S _ D A _ I N 2 :

S serial data input: 16, 18....32 bits per sample

– I2S_DA_OUT:

S serial data output: 16, 18...32 bits per sample

– I2S_CL:

S serial clock

– I2S_WS:

S word strobe signal defines the left and right

sample

If the MSP 34x0G serves as the master on the I

interface, the clock and word strobe lines are driven by the IC. In this mode, only 16 or 32 bits per sample can be selected. In slave mode, these lines are input to the IC and the MSP clock is synchronized to 576 times the I2S_WS rate (32 kHz). NICAM o peration is not possible in slave mode.

S timing diagram is shown in Fig. 4–28 on

An I page 67.

2.8. ADR Bus Interface

For the ASTRA Digital Radio System (ADR), the MSP 3400G, MSP 3410G, and MS P 3450G performs preprocessing such as carrier selection and filtering. Via the 3-line ADR-bus, the resulting signals are transferred to the DRP 3510A coprocessor, where the source decoding is per formed. To be prepared for an upgrade to ADR with an additional DRP board, the following lines of MSP 34x0G should be provided on a feature connector:

– AUD_CL_OUT – I2S_DA_IN1 or I2S_DA_IN2 – I2S_DA_OUT – I2S_WS – I2S_CL – ADR_CL, ADR_WS, ADR_DA

For more details, please refer to the DRP 35 10A data sheet.

2.9. Digital Control I/O Pins and Status Change Indication

The static level of the digital input/output pins D_CTR_I/O_0/1 is switchable between HIGH and LOW via the I (see page 39). This enables the control ling of exter nal hardware switches or other devices via I

C-bus by means of the ACB register

C-bus.

The digital input/outpu t pins can be set to hig h impedance by means of the MODUS register (see page 24). In this mode, the pi ns can be used as input. The current state can be read o ut of the STATUS register (see page 26).

Optionally, the pin D_CTR_I/O_1 can be used as an interrupt request signa l to the c ontrol ler, indicating any changes in the read register STATUS. This makes polling unnecessary, I

C bus interactions are reduced to a minimum (see STATUS register on page 26 and MODUS register on page 24).

2.10. Clock PLL Oscillator and Crystal Specifications

The MSP 34x0G derives all internal system clocks from the 18.432 MHz oscillator. In NICAM or in I

SSlave mode, the clock is phase-locked to the corresponding source. Therefore, it is not possible to use NICAM and I

S-Slave mode at the same time.

For proper performance, the MSP clock oscillator requires a 18.432 MHz crystal. Note that for the phase-locked modes (NICAM, I

S-Slave), crystals with

tighter tolerance are required.

14 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

3. Control Interface

C Bus Interface

3.1. I

The MSP 34x0G is controlled via the I

C bus slave

interface. The IC is selected by transmitting one of the

MSP 34x0G device addresses. In order to allow up to three MSP ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high, low, or left open, the MSP 34x0G responds to different device address es. A device address pair is defined as a write address and a read address (see Table 3–1).

Writing is done by sending the write device address, followed by the subaddress byte, two address bytes, and two data bytes.

Reading is done by sending the wr ite device address, followed by the subaddress byte and two address bytes. Without sending a stop c ondi tion, r ea din g of t he addressed data is completed by sending the device read address and reading two bytes of data.

Refer to Section 3.1.3. for the I Section 3.4. “Programming T ips” on page 41 for proposals of MSP 34x0G I

C telegrams. See Table 3–2

C bus protocol and to

for a list of available subaddresses.

response time is about 0.3 ms. If the MSP cannot accept another byte of data (e.g. while servicing an internal int err upt), it ho lds th e clock line I2C_CL l ow to force the transmitter into a wait state. The I Master must read back the clock line to detect when the MSP is ready to r ecei ve the next I

C transmission.

C Bus

The positions within a transmission where this may happen are indicated by ’Wait’ in Section 3.1.3. The maximum wait period of the MSP during normal operation mode is less than 1 ms.

3.1.1. Inte rn al Hardware Error Handling

In case of any hardware problems (e.g. interruption of the power supply of the MSP), the MSP’s wait period is extended to 1.8 ms. After this time period elapses, the MSP releases data and clock lines.

Indication and solving the error status:

To indicate the error status, the remaining acknowledge bits of the actual I Additionally, bit[14] of CONTROL is set to one. The MSP can then be r eset via the I

C-protocol will be left high.

C bus by transmitting

the RESET condition to CONTROL.

Indication of reset:

Besides the possibility of hardware reset, the MSP can also be reset by means of the RE SET bit in the CONTROL register by the controller via I

Due to the architecture o f the MS P 34x0G, the IC cannot react immediately to an I

Table 3–1: I

ADR_SEL Low

Mode Write Read Write Read Write Read

MSP device address 80

C Bus Device Addresses

C bus.

C request. The typical

(connected to DVSS)

hex

Any reset, even caused by an unstable reset line etc., is indicated in bit[15] of CONTROL.

A general timing diagram of the I

C bus is shown in

Fig. 4–27 on page 65.

(connected to DVSUP)

hex

High

hex

Left Open

Table 3–2: I2C Bus Subaddresses

Name Binary Value Hex Value Mode Function

CONTROL 0000 0000 00 Read/Write Write: Software reset of MSP (see Table 3–3)

Read: Hardware error status of MSP

WR_DEM 0001 0000 10 Write write address demodulator

hex

RD_DEM 0001 0001 11 Write read address demodulator WR_DSP 0001 0010 12 Write wr i te address DSP RD_DSP 0001 0011 13 Write read address DSP

Micronas 15

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MSP 34x0G PRELIMINARY DATA SHEET

3.1.2. Descr ipti on of CONTROL Register

Table 3–3: CONTROL as a Write Register

Name Subaddress Bit[15] (MSB) Bits[14:0]

CONTROL 00

hex

1 : RESET 0 : normal

Table 3–4: CONTROL as a Read Register

Name Subaddress Bit[15] (MSB) Bit[14] Bits[13:0]

CONTROL 00

hex

RESET status after last reading of CONTROL:

0 : no reset occured

Internal hardware status: 0 : no error occured 1 : internal error occured

not of interest

1 : reset occured

Reading of CONTROL will reset the bits[15,14] of CONTROL. After Powe r-on,

bit[15] of CONTROL will be set; it must be

read once to be reset.

3.1.3. Protocol Description

Write to DSP or Demodulator

Swrite

device

address

Wait

ACK sub-addr ACK addr-byte

high

ACK addr-byte

low

ACK data-byte

high

ACK data-byte

low

ACK P

Read from DSP or Demodulator

Swrite

device

address

Wait

ACK sub-addr ACK addr-byte

high

ACK addr-byte

low

ACK S read

device

address

Wait

ACK data-byte-

high

ACK data-byte

Write to Control Register

Swrite

device

address

Wait

ACK sub-addr ACK data-byte

high

ACK data-byte

low

ACK P

Read from Control Register

Swrite

device

address

Wait

Note: S = I

P = I

ACK 00hex ACK S read

C-Bus Start Condition from master

C-Bus Stop Condition from master

device

address

Wait

ACK data-byte-

high

ACK data-byte

low

NAK P

ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray) NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’

or from MSP indicating internal error state

Wait = I

C-Clock line is held low, while the MSP is processing the I2C command.

This waiting time is max. 1 ms

NAK P

low

16 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

I2C_DA

1 0

S P

I2C_CL

Fig. 3 –1: I2C bus protocol (MSB first; data must be stable while clock is high)

3.1.4. Proposals for General MSP 34x0G

C Telegrams

3.1.4.1. Symbols

3.2. Start-Up Sequence: Power-Up and I

After POWER-ON or RE SET (s ee F ig. 4–26), the IC is in an inactive state. All registers are in the Res et posi-

daw write device address (80 dar read device address (81 < Start Condition

hex

, 85

hex

or 88

or 89

hex

)

tion (see Table 3–5 and Table 3–6), the analog outputs are muted. The controll er has to initialize all register s for which a non-default setting is necessary.

, 84

> Stop Condition aa Address Byte dd Data Byte

3.3. MSP 34x0G Programming Interface

C-Controlling

3.1.4.2. Write Telegrams

<daw 00 d0 00> write to CONTROL register <daw 10 aa aa dd dd> write data into demodulator <daw 12 aa aa dd dd> write data into DSP

3.1.4.3. Read Telegrams

<daw 00 <dar dd dd> read data from

CONTROL register

<daw 11 aa aa <dar dd dd> read data from demodulator <daw 13 aa aa <dar dd dd> read data from DSP

3.1.4.4. Examples

<80 00 80 00> RESET MSP statically <80 00 00 00> Clear RESET <80 10 00 20 00 03> Set demodulator to stand. 03 <80 11 02 00 <81 dd dd> Read STATUS <80 12 00 08 01 20> Set loudspeaker channel

source to NICAM and Matrix to STEREO

hex

3.3.1. User Registers Overview

The MSP 34x0G is control led by means of user r egisters. The complete list of all user regist ers ar e given in Table 3–5 and Table 3–6. The registers are par titioned into the Demodulator section (Subaddress 10 writing, 11 ing sections (Subaddress 12

for reading) and the Baseband Process -

hex

for writing, 13

hex

for for

reading). Write and rea d registers are 16 bit wide, whereby the

MSB is denoted bit[15]. Transmissions via I

C bus have to take place in 16-bit words (two byte transfers, with the most significant byte transferred first). All write register s, except the demodulator write registers are readable.

Unused parts of the 16-bit write registers must be zero.

Addresses not given in this table must not be accessed.

For reasons of software compatibility to the MSP 34xxD, a Manual/Compatibility Mode is available. More read and wri te registers toge ther with a detailed description can be found in “Appendix B: Manual/Compatibility Mode” on page 81.

More examples of typical application protocols are listed in Section 3.4. “Programming Tips” on page 41.

Micronas 17

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MSP 34x0G PRELIMINARY DATA SHEET

Table 3–5: List of MSP 34x0G Write Registers

Write Register Address

(hex)

I2C Subaddress = 10

; Registers are not readable

hex

Bits Description and Adjustable Range Reset See

Page

STANDARD SELECT 00 20 [15:0] Initial Programming of the Demodulator 00 00 22

MODUS 00 30 [15:0] Demodulator, Automatic and I

S CONFIGURATION 00 40 [15:0] Configuration of I2S options 00 00 25

I2C Subaddress = 12

; Registers are all readable by using I2C Subaddress = 13

hex

S options 00 00 24

Volume loudspeaker channel 00 00 [15:8] [+12 dB ... −114 dB, MUTE] MUTE 30 Volume / Mode loudspeaker channel [7:0] 1/8 dB Steps,

Reduce Volume / Tone Control / Compromise/

hex

Dynamic

Balance loudspeaker channel [L/R] 00 01 [15:8] [0...100 / 100% and 100 / 0...100%]

100%/100% 31

[−127...0 / 0 and 0 / −127...0 dB] Balance mode loudspeaker [7:0] [Linear / logarithmic mode] linear mode Bass loudspeaker channel 00 02 [15:8] [+20 dB ... −12 dB] 0 dB 32 Treble loudspeaker channel 00 03 [15:8] [+15 dB ... −12 dB] 0 dB 33 Loudness loudspeaker channel 00 04 [15:8] [0 dB ... +17 dB] 0 dB 34 Loudness filter characteristic [7:0] [NORMAL, SUPER_BASS] NORMAL Spatial effect strength loudspeaker ch. 00 05 [15:8] [−100%...OFF...+100%] OFF 35 Spatial effect mode/customize [7:0] [SBE, SBE+PSE] SBE+PSE Volume headphone channel 00 06 [15:8] [+12 dB ... −114 dB, MUTE] MUTE 30 Volume / Mode headphone channel [7:0] 1/8 dB Steps, Reduce Volume / Tone Control 00

hex

Volume SCART1 output channel 00 07 [15:8] [+12 dB ... −114 dB, MUTE] MUTE 38

Loudspeaker source select 00 08 [15:8] [FM/AM, NICAM, SCART, I

S1, I2S2] FM/AM 29 Loudspeaker channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 29 Headphone source select 00 09 [15:8] [FM/AM, NICAM, SCART, I

S1, I2S2] FM/AM 29 Headphone channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 29

SCART1 source select 00 0A [15:8] [FM/AM, NICAM, SCART, I

S1, I2S2] FM/AM 29 SCART1 channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 29

S source select 00 0B [15:8] [FM/AM, NICAM, SCART, I2S1, I2S2] FM/AM 29

S channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 29

I Quasi-peak detector source select 00 0C [15:8] [FM/AM, NICAM, SCART, I

S1, I2S2] FM/AM 29 Quasi-peak detector matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 29 Prescale SCART input 00 0D [15:8] [00 Prescale FM/AM 00 0E [15:8] [00

hex

]00

hex

... 7F

]00

hex

28 27

... 7F

FM matrix [7:0] [NO_MAT, GSTEREO, KSTEREO] NO_MAT 28

... 7F

Prescale NICAM 00 10 [15:8] [00

Prescale I

S2 00 12 [15:8] [00

hex

] (MSP 3410G, MSP 3450G only) 00

hex

... 7F

]10

hex

ACB : SCART Switches a. D_CTR_I/O 00 13 [15:0] Bits [15..0] 00

... 7F

]/[00

Beeper 00 14 [15:0] [00

Prescale I

S1 00 16 [15:8] [00

hex

... 7F

hex

]10

... 7F

hex

] 00/00

hex

28 28 39 39 28

18 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

Table 3–5: List of MSP 34x0G Wr i te Regi st er s, co ntinue d

Write Register Address

(hex)

Mode tone control 00 20 [15:8] [BASS/TREBLE, EQUALIZER] BASS/TREB 32 Equalizer loudspeaker ch. band 1 00 21 [15:8] [+12 dB ... −12 dB] 0 dB 33 Equalizer loudspeaker ch. band 2 00 22 [15:8] [+12 dB ... −12 dB] 0 dB 33 Equalizer loudspeaker ch. band 3 00 23 [15:8] [+12 dB ... −12 dB] 0 dB 33 Equalizer loudspeaker ch. band 4 00 24 [15:8] [+12 dB ... −12 dB] 0 dB 33 Equalizer loudspeaker ch. band 5 00 25 [15:8] [+12 dB ... −12 dB] 0 dB 33 Automatic Vo lume Correc tion 00 29 [15:8] [off, on, decay time] off 31 Subwoofer level adjust 00 2C [15:8] [+12 dB ... −30 dB, mute] 0 dB 36 Subwoofer corner frequency 00 2D [15:8] [50 Hz ... 400 Hz] 00 Subwoofer complementary high-pass [7:0] [off, on, MDB to Main] off 36 Balance headphone channel [L/R] 00 30 [15:8] [0...100 / 100% and 100 / 0...100%]

Balance mode headphone [7:0] [Linear mode / logarithmic mode] linear mode Bass headphone channel 00 31 [15:8] [+20 dB ... −12 dB] 0 dB 32 Treble headphone channel 00 32 [15:8] [+15 dB ... −12 dB] 0 dB 33 Loudness headphone channel 00 33 [15:8] [0 dB ... +17 dB] 0 dB 34

Bits Description and Adjus table Range Reset See

hex

100 %/100 % 31

[−127...0 / 0 and 0 / −127...0 dB]

Page

Loudness filter characteristic [7:0] [NORMAL, SUPER_BASS] NORMAL Volume SCAR T2 output channel 00 40 [15:8] [+12 dB ... −114 dB, MUTE] 00

SCART2 source select 00 41 [15:8] [FM, NICAM, SCART, I SCART2 channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 29 MDB Effect Strength 00 68 [15:8] [0 dB ... 127 dB, off] off 36 MDB Amplitude Limit 00 69 [15:8] [0 dBFS... –32 dBFS] 0 dBFS 36 MDB Harmonic Content 00 6A [15:8] [0% ... 100%] 0% 37 MDB Low Pass Corner Frequency 00 6B [15:8] [50 Hz ... 300 Hz] 0 Hz 37 MDB High Pass Corner Frequency 00 6C [15:8] [20 Hz ... 300 Hz] 0 Hz 37

S1, I2S2] FM 29

hex

Micronas 19

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MSP 34x0G PRELIMINARY DATA SHEET

Table 3–6: List of MSP 34x0G Read Registers

Read Register Address

(hex)

I2C Subaddress = 11

; Registers are not writable

hex

Bits Description and Adjustable Range See

Page

STANDARD RESULT 00 7E [15:0] Result of Automatic Standard Detection (see Table3–8 on page 23) 26 STATUS 02 00 [15:0] Monitoring of inter nal settings e.g. Stereo, Mono, Mute etc. . 26

I2C Subaddress = 13

Quasi peak readout left 00 19 [15:0] [00 Quasi peak readout right 00 1A [15:0] [00 MSP hardware version code 00 1E [15:8] [00 MSP major revision code [7:0] [00 MSP product code 00 1F [15:8] [00 MSP ROM version code [7:0] [00

; Registers are not writable

hex

... 7FFF

hex

... 7FFF

hex

... FF

hex

... FF

hex

... FF

hex

... FF

hex

]16 bit tw o’s complement 40

hex

]16 bit tw o’s complement 40

hex

]40

hex

]40

hex

]40

hex

]40

hex

20 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

3.3.2. Description of User Registers

Table 3–7: Standard Codes for STANDARD SELECT register

MSP Standard Code (Data in hex)

TV Sound Standard Sound Carrier

Frequencies in MHz

MSP 34x0G Version

Automatic Standard Detection

00 01 Start Automatic Standard Detection and

all

sets detected standards

Standard Selection

00 02 M-Dual FM-Stereo 4.5/4.724212 3400, -10, -20, -40, -50 00 03 B/G -Dual FM-Stereo 00 04 D/K1-Dual FM-Stereo 00 05 D/K2-Dual FM-Stereo

00 06 D/K -FM-Mono with HDEV3

Standard Detection,

HDEV3

SAT-Mono (i.e. Eutelsat, s. Table 6–18)

, not detectable by Aut om atic

5.5/5.7421875 3400, -10, -50

6.5/6.2578125

6.5/6.7421875

6.5

00 07 D/K3-Dual FM-Stereo 6.5/5.7421875 00 08 B/G -NICAM-FM

5.5/5.85 3410, -50 00 09 L -NICAM-AM 6.5/5.85 00 0A I -NICAM-FM 6.0/6.552 00 0B D/K -NICAM-FM

00 0C D/K -NICAM-FM with HDEV2

, not detectabl e by Autom a ti c

6.5/5.85

Standard Detection, for China

00 0D D/K -NICAM-FM with HDEV3

, not detectabl e by Autom a ti c

6.5/5.85

Standard Detection, for China 00 20 BTSC-Stereo 4.5 3420, -40, -50 00 21 BTSC-Mono + SAP 00 30 M-EIA-J Japan Stereo 4.5 00 40 FM-Stereo Radio with 75 µs Deemphasis 10.7 00 50 SAT-Mono (s . Table 6–18) 6.5 3400, -10, -50 00 51 SAT-Stereo (s. Table 6–18) 7.02/7.20 00 60 SAT ADR (Astra Digital Radio) 6.12

In case of Automatic Sound Select, the B/G-codes 3

In case of Automatic Sound Select, the D/K-codes 4

HDEV3: Max. FM deviation must not exceed 540 kHz

HDEV2: Max. FM deviation must not exceed 360 kHz

hex hex

and 8

, 5

hex

are equivalent.

hex

, 7

and B

hex

are equivalent.

hex

Micronas 21

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MSP 34x0G PRELIMINARY DATA SHEET

3.3.2.1. STANDARD SELECT Register

The TV sound standar d of the MSP 34x0G demodulator is determined by the STANDARD SELECT register. There are two ways to use the STANDARD SELECT register:

– Setting up the demodulator for a TV sound standard

by sending the corresponding standard code with a single I

– Starting the Automatic Standard Detection for ter-

restrial TV standards. This is the most comfortable way to set up the demodulator. Within 0.5 s, the detection and setup of the actual TV sound standard is performed. The detected standard can be read out of the STANDARD RESULT register by the control processor. This feature is recommended for the primary setup of a TV set. Outputs should be muted

during Automatic Standard Detection. The Standard Codes are listed in Table 3–7. Selecting a TV sound standard via the STANDARD

SELECT register initializes the demodulator. This includes: AGC-settings and carrier mute, tuning frequencies, FIR-filter set tings, demodulation mode ( FM, AM, NICAM), deemphasis and identification mode.

TV stereo sound standa rds that are unavailable for a specific MSP version are processed in analog mono sound of the standard. In that cas e, stereo or bilingual processing will not be possible.

For a complete setup of the TV sound processing from analog IF input to the source selection, the transmissions as shown in Section 3.5. are necessary.

C bus transmission.

3.3.2.2. Refresh of STANDARD SELECT Register

A general refresh o f th e S TANDARD SELECT register is not allowed. However, the following method enables watching the MSP 34x0G “alive” status and detection of accidental resets (only versions B6 and later):

– After Power-on, bit[15] of CONTROL will be set; it

must be read once to enable the reset-detection feature.

– Reading of the CONTROL register and checking

the reset indicator bit[15] .

– If bit[15] is “0”, any refresh of the STANDARD

SELECT register is not allowed.

– If bit[15] is “1”, indicating a reset, a refresh of the

STANDARD SELECT register and all other MSPG registers is required.

3.3.2.3. STANDARD RESULT Register

If Automatic Standard Detection is selected in the STANDARD SELECT regi ster, status and result o f the Automatic Standard Detection process can be read out of the STANDARD RESULT register. The possible results are based on the mentioned Standard Code and are listed in Table 3–8.

In cases where n o sound st andard h as been detected (no standard present, too mu ch noise, strong interferers, etc.) the STANDARD RESULT register contains 00 00 actions (for example set the standard according to a preference list or by manual input).

. In that case, the controller has to start further

hex

For reasons of software compatibility to the MSP 34xxD, a Manual/Compatibility mode is available. A detailed description of this mode can be found on page 81.

As long as the STANDA RD RESULT register contains a value greater than 07 FF Detection is still active. During this period, the MODUS and STANDARD SELECT register must no t be written. The STATUS register will be updated when the Automatic Standard Detection has finished.

If a present sound standard is unavailable for a specific MSP-version, it detects and switches to the analog mono sound of this standard.

Example: The MSPs 3420G and 3440G will detect a B/G-NICAM signal as standa rd 3 a nd will switch to the analog FMMono sound.

, the Automatic Standard

hex

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PRELIMINARY DATA SHEET MSP 34x0G

Table 3–8: Results of the Automatic Standard Detection

Broadcasted Sound Standard

Automatic Standard Detection could not

STANDARD RESULT Register

Read 007E

0000

hex

find a sound standard B/G-FM 0003 B/G-NICAM 0008 I000A FM-Radio 0040 M-Korea

M-Japan M-BTSC

L-AM D/K1 D/K2 D/K3

L-NICAM D/K-NICAM

0002 0020 0030 0009 0004

0009 000B

hex

(if MODUS[14,13]=00)

hex

(if MODUS[14,13]=01)

hex

(if MODUS[14,13]=10)

hex

(if MODUS[12]=0)

hex

(if MODUS[12]=1)

hex

(if MODUS[12]=0)

hex

(if MODUS[12]=1)

hex

Automatic Standard Detection still active

>07FF

hex

Micronas 23

Page 24

MSP 34x0G PRELIMINARY DATA SHEET

3.3.2.4. Write Registers on I2C Subaddress 10

Table 3–9: Write registers on I2C subaddress 10

Function Name

Address

00 20

hex

STANDARD SELECTION Register

Defines TV-Sound or FM-Radio Standard bit[15:0] 00 01

00 02

start Automatic Standard Detection

hex

MSP Standard Codes (see Table 3–7)

hex

...

hex

00 30

hex

00 60

MODUS Register

Preference in Automatic Standard Detection: bit[15] 0 undefined, must be 0 bit[14:13] detected 4.5 MHz carrier is interpreted as:

0 standard M (Korea) 1 standard M (BTSC) 2 standard M (Japan) 3 chroma carrier (M/N standards are ignored)

bit[12] detected 6.5 MHz carrier is interpreted as:

0 standard L (SECAM) 1 standard D/K1, D/K2, D/K3, or D/K NICAM

hex

STANDARD_SEL

MODUS

General MSP 34x0G Options bit[11:9] 0 undefined, must be 0 bit[8] 0/1 ANA_IN1+/ANA_IN2+; select analog sound IF input pin bit[7] 0/1 active/tristate state of audio clock output pin

AUD_CL_OUT

bit[6] I

S word strobe alignment 0 WS changes at data word boundary 1 WS changes one clock cycle in advance

bit[5] 0/1 master/slave mode of I

S interface (must be set to 0

(= Master) in case of NICAM mode)

bit[4] 0/1 active/tristate state of I

S output pins

bit[3] state of digital output pins D_CTR_I/O_0 and _1

0 active: D_CTR_I/O_0 and _1 are output pins

(can be set by means of the ACB register. see also: MODUS[1])

1 tristate: D_CTR_I/O_0 and _1 are input pins

(level can be read out of STATUS[4,3]) bit[2] 0 undefined, must be 0 bit[1] 0/1 disable/enable STATUS change indication by means of

the digital I/O pin D_CTR_I/O_1

Necessary condition: MODUS[3] = 0 (active) bit[0] 0/1 off/on: Automatic Sound Select

Valid at the next start of Automatic Standard Detection.

24 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

Table 3–9: Write registers on I

C subaddress 10

, continued

hex

00 40

hex

Function Name

I2S CONFIGURATION Register

I2S_CONFIG bit[15:1] 0 not used, must be set to “0” bit[0] I2S_CL frequency and I

S data sample length for

master mode 0 2 x 16 bit (1.024 MHz) 1 2 x 32 bit (2.048 MHz)

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MSP 34x0G PRELIMINARY DATA SHEET

3.3.2.5. Read Registers on I2C Subaddress 11

hex

Table 3–10: Read Registers on I2C Subaddress 11

Function Name

Address

00 7E

hex

STANDARD RESULT Register

Readback of the detected TV sound or FM-Radio Standard bit[15:0] 00 00

Automatic Standard Detection could not find

hex

a sound standard

00 02

MSP Standard Codes (see Table 3–8 on page 23)

hex

...

02 00

hex

00 40

>07 FF

STATUS Register

hex

Automatic Standard Detection still active

hex

Contains all user relevant internal information about the status of the MSP bit[15:10] undefined bit[8] 0/1 “1” indicates bilingual sound mode or SAP present

(internally evaluated from received analog or digital identification signa ls)

hex

STANDARD_RES

STATUS

bit[7] 0/1 “1” indicates independent mono sound (only for

NICAM)

bit[6] 0/1 mono/s ter eo ind icati on

(internally evaluated from received analog or digital identification signa ls)

bit[5,9] 00 analog sound standard (FM or AM) active

01 this pattern will not occur 10 digital sound (NICAM) available 11 bad reception condition of digital sound (NICAM) due

to: a. high error rate b. unimplemented sound code

c. data transmission only bit[4] 0/1 low/high level of digital I/O pin D_CTR_I/O_1 bit[3] 0/1 low/high level of digital I/O pin D_CTR_I/O_0 bit[2] 0 detected secondary carrier (2nd A2 or SAP sub-carrier)

1 no secondary carrier detected

bit[1] 0 detected primary carrie r (Mono or MPX carrier)

1 no primary carrier detected

bit[0] undefined If STATUS change indication is activated by means of MODUS[1]: Each

change in the STATUS register sets the digit al I/O pin D_CTR_I/O_1 to high level. Reading the STATUS register resets D_CTR_I/O_1.

26 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

3.3.2.6. Write Registers on I2C Subaddress 12

hex

Table 3–11: Write Registers on I2C Subaddress 12

Function Name

Address PREPROCESSING

00 0E

hex

FM/AM Prescale

bit[15:8] 00

hex

Defines the input prescale gain for the demodulated ... FM or AM signal 7F

hex

off (RESET condition)

For all FM modes except satel lite FM a nd AM-m ode, the com binations of pre scale value and FM deviation listed below lead to internal full scale.

FM mode bit[15:8] 7F

48 30 24 18 13

hex hex hex hex hex hex

28 kHz FM deviation

50 kHz FM deviation

75 kHz FM deviation

100 kHz FM deviation

150 kHz FM deviation

180 kHz FM deviation (limit)

hex

PRE_FM

FM high deviation mode (HDEV2, MSP Standard Code = C bit[15:8] 30

hex hex

150 kHz FM deviation

360 kHz FM deviation (limit)

hex

)

FM very high deviation mode (HDEV3, MSP Standard Code = 6 and D bit[15:8] 20

hex

450 kHz FM deviation

540 kHz FM deviation (limit)

Satellite FM with adaptive deemphasis bit[15:8] 10

hex

recommendation

AM mode (MSP Standard Code = 9) bit[15:8] 7C

hex

recommendation for SIF input levels from

0.1 V

to 0.8 V

(Due to the AGC being switched on, the AM-output level

remains stable and independent of the actual SIF-level in

the mentioned input range)

hex

)

Micronas 27

Page 28

MSP 34x0G PRELIMINARY DATA SHEET

Table 3–11: Write Registers on I

C Subaddress 12

, continued

hex

(continued)

00 0E

hex

00 10

hex

Function Name

FM Matrix Modes

FM_MATRIX

Defines the dematrix function for the demodulated FM signal bit[7:0] 00

01 02 03

hex hex hex hex

no matrix (used f or b ili ng ua l an d unma t rixed stereo sound) German stereo (Standard B/G) Korean stereo (also used for BTSC, EIA-J and FM Radio) sound A mono (left and right channel contain the mono sound of the FM/AM mono carrier)

hex

sound B mono

In case of Automatic Sound Select = on, the FM Matrix Mode is set auto mat ically. Writing to the FM/AM prescale register (00 0E In order not to disturb th e automatic process, the low par t of any I

high part) is still allowed.

hex

C transmission to this reg ister is ignor ed. Therefore, any FM-Matr ix readback values may differ from data written previously.

In case of Automatic Sound Select = off, the FM Matrix Mode must be set as shown in Table 6–17 of Appendix B.

To enable a Forced Mono Mode set A2 THRESHOLD as described in Section 6.3.2.on page 85

NICAM Prescale

PRE_NICAM

00 16 00 12

00 0D

hex hex

hex

Defines the input prescale value for the digital NICAM signal bit[15:8] 00

hex

... 7F

prescale gain

hex

examples: 00 20 5A 7F

hex hex hex hex

off 0dB gain 9 dB gain (recommendation) +12 dB gain (maximum gain)

I2S1 Prescale I2S2 Prescale

Defines the input prescale value for digital I bit[15:8] 00

hex

... 7F

prescale gain

hex

S input signals

examples: 00 10 7F

hex hex hex

off 0 dB gain (recommendation) +18 dB gain (maximum gain)

SCART Input Prescale

Defines the input prescale value for the analog SCART input signal bit[15:8] 00

hex

... 7F

prescale gain

hex

examples: 00 19 7F

hex hex hex

off 0dB gain (2 V

input leads to digital full scale)

RMS

+14 dB gain (400 mV

input leads to digital full scale)

RMS

PRE_I2S1 PRE_I2S2

PRE_SCART

28 Micronas

Page 29

PRELIMINARY DATA SHEET MSP 34x0G

Table 3–11: Write Registers on I

C Subaddress 12

, continued

hex

Function Name

Address SOURCE SELECT AND OUTPUT CHANNEL MATRIX

Source for:

00 08 00 09 00 0A 00 41 00 0B 00 0C

hex hex

hex

hex hex

Loudspeaker Output Headphone Output SCART1 DA Output SCART2 DA Output

S Output

I Quasi-Peak Detector

bit[15:8] 0 “FM/AM”: demodulated FM or AM mono signal

1 “Stereo or A/B”: demodulator Stereo or A/B signal

(in manual mode, this source is identical to the NICAM source in the MSP 3410D)

3 “Stereo or A”: demodulator Stereo Sound or

Language A (only defined for Automatic Sound Select)

4 “Stereo or B”: demodulator Stereo Sound or

Language B (only defined for Automatic Sound Select) 2SCART input 5I 6I

S1 input

S2 input

SRC_MAIN SRC_AUX SRC_SCART1 SRC_SCART2 SRC_I2S SRC_QPEAK

00 08 00 09 00 0A 00 41 00 0B 00 0C

hex hex

hex

hex hex

For demodulator sources, see Table 2–2.

Matrix Mode for:

Loudspeaker Output Headphone Output SCART1 DA Output SCART2 DA Output

S Output

I Quasi-Peak Detector

bit[7:0] 00

10 20 30

hex hex hex hex

Sound A Mono (or Left Mono)

Sound B Mono (or Right Mono)

Stereo (transparent mode)

Mono (sum of left and right inputs divided by 2) special modes are available (see Section 6.5.1. on page 93)

In Automatic Sound Select mode, the demodulator source channels are set according to Table 2–2. Therefore, the matrix modes of th e corresponding output channels should be set to “Stereo” (transparent).

MAT_MAIN MAT_AUX MAT_SCART1 MAT_SCART2 MAT_I2S MAT_QPEAK

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MSP 34x0G PRELIMINARY DATA SHEET

Table 3–11: Write Registers on I

C Subaddress 12

, continued

hex

Function Name

Address LOUDSPEAKER AND HEADPHONE PROCESSING

00 00 00 06

hex hex

Volume Loudspeaker Volume Headphone

bit[15:8] volume table with 1 dB step size

7F 7E

hex hex

+12 dB (maximum volume) +11 dB

... 74 73 72

hex hex hex

+1dB

0dB

−1dB ... 02 01 00 FF

hex hex hex hex

−113 dB

−114 dB

Mute (reset condition) Fast Mute (needs about 75 ms until the signal is completely ramped down)

bit[7:5] higher resolution volume table

0 +0dB 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table

VOL_MAIN VOL_AUX

bit[4] 0 must be set to 0 bit[3:0] clipping mode

0 reduce volume 1 reduce tone control 2 compromise 3dynamic

With large scale inp ut signals, positive volume settings may lead to signal clipping.

The MSP 34x0G loudspea ker and headp hone volume fu nction is divided in to a digital and an analog sectio n. With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any audible DC plops. To turn volume on again, the volume step that has been used before Fast Mute was activated must be transmitted.

If the clipping mode is set to “reduce volume”, the following rule is used: T o prevent severe clipping effects with bass, treble, or equalizer boosts, the internal volume is automatically limited to a level where, in combination with either bass, treble, or equalizer setting, the amplification does not exceed 12 dB.

If the clipping mode is “reduce tone control”, the bass or treble value is reduced if ampli fication exceeds 12 dB. If the e quali zer is switched on , th e gain of those bands is reduced, where amplific ation together with volume exceeds 12 dB.

If the clipping mode is “compromise”, the bass or tr eble value and volume a re reduced half and half i f amp li fic ati on exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced half and half, where amplification together with volume exceeds 12 dB.

If the clipping mode is “dynamic”, volume is re duced autom aticall y if the signal amplitudes would exceed −2 dBFS within the IC. For operation of MDB, dyna-

mic mode must be switched on.

30 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

Table 3–11: Write Registers on I

C Subaddress 12

, continued

hex

00 29

hex

00 01

hex

00 30

hex

Function Name

Automatic Volume Correction (AVC) Loudspeaker Channel

bit[15:12] 00

bit[11:8] 08

04 02 01

hex hex

hex hex hex hex

AVC off (and reset internal variables) AVC on

8 sec decay time 4 sec decay time 2 sec decay time 20 ms decay time (should be used for approx. 100 ms

AVC

after channel change)

Note: AVC should not be used in any Dolby Prologic mode (with DP L 35xx), except in PANORAMA or 3D-PANORAMA mode, when only the loudspeaker output is active.

Balance Loudspeaker Channel Balance Headphone Channel

BAL_MAIN BAL_AUX

bit[15:8] Linear Mode

7F 7E

hex

Left muted, Right 100%

Left 0.8%, Right 100% ... 01 00 FF

hex hex

hex

Left 99.2%, Right 100%

Left 100%, Right 100%

Left 100%, Right 99.2% ... 82 81

hex hex

Left 100%, Right 0.8%

Left 100%, Right muted

bit[15:8] Logarithmic Mode

7F 7E

hex

Left −127 dB, Right 0 dB

Left −126 dB, Right 0 dB ... 01 00 FF

hex hex

hex

Left −1 dB, Right 0 dB

Left 0 dB, Right 0 dB

Left 0 dB, Right −1dB ... 81 80

hex hex

Left 0 dB, Right −127 dB

Left 0 dB, Right −128 dB

bit[7:0] Balance Mode

00 01

hex hex

linear

logarithmic

Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected.

Micronas 31

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MSP 34x0G PRELIMINARY DATA SHEET

Table 3–11: Write Registers on I

C Subaddress 12

, continued

hex

00 20

hex

00 02

hex

00 31

hex

Function Name

Tone Control Mode Loudspeaker Channel

bit[15:8] 00

hex hex

bass and treble is active equalizer is active

TONE_MODE

Defines whether Bass/Treble or Equalizer is activated for the loudspeaker channel. Bass and Eq ual izer c ann ot work simultaneously. If Equalizer is used, Bass, and Treble coefficients must be set to zero and vice versa.

Bass Loudspeaker Channel Bass Headphone Channel

BASS_MAIN BASS_AUX

bit[15:8] extended range

7F 78 70 68

hex hex hex hex

+20 dB +18 dB +16 dB +14 dB

normal range 60 58

hex hex

+12 dB +11 dB

... 08 00 F8

hex hex hex

+1dB

0dB

−1dB ... A8 A0

hex hex

−11 dB

−12 dB

Higher resolution is pos sible: an LSB step in the nor mal range r esults in a g ain step of about 1/8 dB, in the extended range about 1/4 dB.

With positive bass settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped ou tput signal. Therefore, it is not recommended to set bass to a value tha t, in conjunct ion with volume, would result in an overall positive gain.

32 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

Table 3–11: Write Registers on I

C Subaddress 12

, continued

hex

00 03

hex

00 32

hex

00 21

hex

00 22

hex

00 23

hex

00 24

hex

00 25

hex

Function Name

Treble Loudspeaker Channel Treble Headphone Channel

bit[15:8] 78

hex hex

+15 dB +14 dB

TREB_MAIN TREB_AUX

... 08 00 F8

hex hex hex

+1dB

0dB

−1dB ... A8 A0

hex hex

−11 dB

−12 dB

Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB. With positive treble settings, inter nal clipping may occur even with overall vol-

ume less than 0 dB. This will lead to a clipped output si gnal. Therefore, it is not recommended to set treble to a value that, in conjun ction with volume, would result in an overall positive gain.

Equalizer Loudspeaker Channel Band 1 (below 120 Hz) Equalizer Loudspeaker Channel Band 2 (center: 500 Hz) Equalizer Loudspeaker Channel Band 3 (center: 1.5 kHz) Equalizer Loudspeaker Channel Band 4 (center: 5 kHz) Equalizer Loudspeaker Channel Band 5 (above: 10 kHz)

bit[15:8] 60

hex hex

+12 dB +11 dB

EQUAL_BAND1 EQUAL_BAND2 EQUAL_BAND3 EQUAL_BAND4 EQUAL_BAND5

... 08 00 F8

hex hex hex

+1dB

0dB

−1dB ... A8 A0

hex hex

−11 dB

−12 dB

Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB. With positive equalizer settings, internal clipping may occur even with overall

volume less than 0 dB. This will lead to a c lipped output s ignal. Therefore, it is not recommended to set equalizer bands to a value that, in conjunction with volume, would result in an overall positive gain.

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MSP 34x0G PRELIMINARY DATA SHEET

Table 3–11: Write Registers on I

C Subaddress 12

, continued

hex

00 04

hex

00 33

hex

Function Name

Loudness Loudspeaker Channel Loudness Headphone Channel

LOUD_MAIN LOUD_AUX

bit[15:8] Loudness Gain

44 40

hex hex

+17 dB +16 dB

... 04 03 02 01 00

hex hex hex hex hex

+1dB +0.75 dB +0.5 dB +0.25 dB

0dB

bit[7:0] Loudness Mode

00 04

hex hex

normal (constant volume at 1 kHz) Super Bass (constant volume at 2 kHz)

Higher resolutio n of Loudness Gain i s possible: An LSB step results in a g ain step of about 1/4 dB.

Loudness increas es the volume of low- an d hi gh-fr equ enc y si gna ls, whil e keeping the amplitud e of the reference frequency c onstant. The intended l oudness has to be set according to the actual volume setting. Because loudnes s introduces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain.

The corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is sh ift ed up. The poin t of c ons tan t volume is shifted from 1 kHz to 2 kHz.

34 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

Table 3–11: Write Registers on I

C Subaddress 12

, continued

hex

00 05

hex

Function Name

Spatial Effects Loudspeaker Channel

SPAT_MAIN

bit[15:8] Effect Strength

7F 3F

hex hex

Enlargement 100%

Enlargement 50% ... 01 00 FF

hex hex

hex

Enlargement 1.5%

Effect off

reduction 1.5% ... C0 80

hex

reduction 50%

reduction 100%

bit[7:4] Spatial Effect Mode

hex

Stereo Basewidth Enlargement (SBE) and

Pseudo Stereo Effect (PSE). (Mode A) 2

hex

Stereo Basewidth Enlargement (SBE) only. (Mode B)

bit[3:0] Spatial Effect High-Pass Gain

hex

max. high-pass gain

2/3 high-pass gain

1/3 high-pass gain

min. high-pass gain

automatic

There are several spatial effect modes available: In mode A (low byte = 00

), the spatial effect depends on the sou rce mode. If

hex

the incoming signal is mono, Pseudo Stere o Effect is active; for stereo s ignals, Pseudo Stereo Effect and Stereo Basewidth Enlargement is effective. The strength of the effect is controllable by the upper byte. A negative value reduces the stereo image. A strong spatial effect is recommended for small TV sets where loudspeaker spacing is rather close. For large screen TV se ts, a more moderate spatial effect is recommended.

In mode B, only Stereo Basewidth Enla rgement is effective. For mono input signals, the Pseudo Stereo Effect has to be switched on.

It is worth mentioning, that all spatial effects affect amplitude and phase response. With the lower 4 bits, the fre quency respon se can be customized. A value of 0 function for L or R only signals. A value of 6 only signals, but a low-pass function for center signals. By u sing 8

yields a flat r esponse for center signals (L = R), but a high-pass

hex

has a flat respons e for L or R

hex

, the fre-

hex

quency response is automatically adapted to the sound material by choosing an optimal high-pass gain.

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MSP 34x0G PRELIMINARY DATA SHEET

Table 3–11: Write Registers on I

C Subaddress 12

, continued

hex

Function Name

Address SUBWOOFER OUTPUT CHANNEL

00 2C

hex

Subwoofer Level Adjustment

bit[15:8] 0C

hex

+12 dB ... 01 00 FF

hex hex hex

+1 dB

−1dB ... E3 E2

hex hex

−29 dB

−30 dB

... 80

bit[7:0] 00

hex hex

Mute

must be zero

If MDB is added onto the main channel, this register should be set to 00

00 2D

hex

Subwoofer Corner Frequency

bit[15:8] 5...40 corner frequency in 10 Hz steps

(range: 50...400 Hz)

If MDB is active, SUBW_FREQ must be set to a value higher than the MDB Lowpass Frequency (MDB_LP). Choosing the corner frequency of the subwoofer closer to MDB_LP results in a narrower MDB frequency range. Recommended value:

1.5×MDB_LP

SUBW_LEVEL

0 dB (default)

hex

SUBW_FREQ

Subwoofer Complementary High-Pass Filter

bit[7:0] 00

hex hex

hex

MDB CONTROL REGISTERS

00 68

hex

MDB Effect Strength

bit[15:8] 00

bit[7:0] 00

hex hex

hex

The MDB effect strength can be adjusted in 1dB steps. A value of 44 a medium MDB effect.

00 69

hex

MDB Amplitude Limit

bit[15:8] 00

hex hex

... E0

hex

bit[7:0] 00

hex

The MDB Amplitude Limit defines the maximum allowed amplitude at the output of the MDB relative to 0 dbFS. If the amplitu de exceeds MDB_LIM, the gain o f the MDB is automatically reduced. Note that the Volume Clipping Mode must be set to “dynamic” (see page 30).

loudspeaker channel unfilte re d a complementary high-pass is processed in the loudspeaker output channel

MDB added onto main channel

MDB OFF (default)

maximum MDB

must be zero

0 dB F S (default limitation)

−1dBFS

−32 dBFS

must be zero

will yield

hex

SUBW_HP

MDB_STR

MDB_LIM

36 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

Table 3–11: Write Registers on I

C Subaddress 12

, continued

hex

00 6A

hex

00 6B

hex

Function Name

MDB Harmonic Content

bit[15:8] 00

bit[7:0] 00

no harmonics are added (default) 64 7F

hex hex hex

hex

50% fundamentals + 50% harmonics 100% harmonics

must be zero

MDB_HMC

MDB creates har moni cs of the fr equen cies below the MDB highp ass freq uency (MDB_HP). The variable MDB_HMC describes the ratio of the harmonics towards the original signal.

MDB Low Pass Corner Frequency

MDB_LP

bit[15:8] 5 50 Hz

660Hz ... 30 300 Hz

bit[7:0] 00

must be zero

hex

The MDB lowpass cor ner frequenc y (range 50... 300 Hz) defines the upper co rner frequency of the MDB band pass filte r. Recommended values are th e same as for the MDB highpass corner frequency (MDB_HP).

00 6C

hex

MDB High Pass Corner Frequency

bit[15:8] 2 20 Hz

330Hz ... 30 300 Hz

bit[7:0] 00

must be zero

hex

The MDB highpass cor ner freq uency d efines th e lower cor ner fr equency of the MDB bandpass filter. The highpass filter avoids loading the lou dspeakers with low frequency components that a re below the s peakers’ cut off fre quenc y. Recommended values for subwoofer systems are around 5 (=50 Hz), for regular TV sets around 10 (=100 Hz).

MDB_HP

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MSP 34x0G PRELIMINARY DATA SHEET

Table 3–11: Write Registers on I

C Subaddress 12

, continued

hex

Function Name

Address SCART OUTPUT CHANNEL

00 07 00 40

hex hex

Volume SCART1 Output Channel Volume SCART2 Output Channel

bit[15:8] volume table with 1 dB step size

hex

... 74

hex

... 02

hex

bit[7:5] higher resolution volume table

0 +0 dB 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table

bit[4:0] 01

hex

+12 dB (maximum volume) +11 dB

+1dB

0dB

−1dB

−113 dB

−114 dB

Mute (reset condition)

this must be 01

hex

VOL_SCART1 VOL_SCART2

38 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

Table 3–11: Write Registers on I

C Subaddress 12

, continued

hex

Function Name

Address SCART SWITCHES AND DIGITAL I/O PINS

00 13

hex

ACB Register

Defines the level of the digital output pins and the position of the SCART switches

bit[15] 0/1 low/high of digital output pin D_CTR_I/O_1

(MODUS[3]=0)

bit[14] 0/1 low/high of digital output pin D_CTR_I/O_0

(MODUS[3]=0)

bit[13:5] SCART DSP Input Select

xxxx00xx0 SCART1 to DSP input (RESET position) xxxx01xx0 MONO to DSP input (Sound A Mono must be selected in

the channel matrix mode for the corresponding output channels)

xxxx10xx0 SCART2 to DSP input xxxx11xx0 SCART3 to DSP input xxxx00xx1 SCART4 to DSP input xxxx11xx1 mute DSP input

bit[13:5] SCART1 Output Select

xx00xxx0x SCART3 input to SCART1 output (RESET position)

xx01xxx0x S CART2 input to SCART1 output xx10xxx0x MONO input to SCART1 output xx11xxx0x SCART1 DA to SCART1 output xx00xxx1x SCART2 DA to SCART1 output xx01xxx1x S CART1 input to SCART1 output xx10xxx1x S CART4 input to SCART1 output xx11xxx1x mute SCART1 output

ACB_REG

BEEPER

00 14

hex

bit[13:5] SCART2 Output Select

00xxxx0xx SCART1 DA to SCART2 output (RESET position) 01xxxx0xx SCART1 input to SCART2 output 10xxxx0xx MONO input to SCART2 output 00xxxx1xx SCART2 DA to SCART2 output 01xxxx1xx SCART2 input to SCART2 output 10xxxx1xx SCART3 input to SCART2 output 11xxxx1xx SCART4 input to SCART2 output 11xxxx0xx mute SCART2 output

The RESET position become s active at the time of the first write t ransmission on the control bus to the audio process ing part. By wr iting to the ACB register first, the RESET state can be redefined.

Beeper Volume and Frequency

bit[15:8] Beeper Volume

00 7F

hex hex

off maximum volume

bit[7:0] Beeper Frequency

01 40 FF

hex hex

hex

16 Hz (lowest) 1kHz 4kHz

BEEPER

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MSP 34x0G PRELIMINARY DATA SHEET

3.3.2.7. Read Registers on I2C Subaddress 13

hex

Table 3–12: Read Registers on I2C Subaddress 13

Function Name

Address QUASI-PEAK DETECTOR READOUT

00 19 00 1A

hex

Quasi-Peak Detector Readout Left Quasi-Peak Detector Readout Right

bit[15:0] 0

... 7FFF

hex

values are 16 bit two’s complement (only positive)

hex

MSP 34x0G VERSION READOUT REGISTERS

00 1E

hex

MSP Hardware Version Code

bit[15:8] 02

hex

MSP 34x0G - B8

A change in the hardware version cod e defines hardware optimizations that may have influence on the chip’s behavior. The readout of this register i s identical to the hardware version code in the chip’s imprint.

MSP Major Revision Code

bit[7:0] 07

hex

MSP 34x0G - B8

hex

QPEAK_L QPEAK_R

MSP_HARD

MSP_REVISION

00 1F

hex

The major revision code of the MSP 34x0G is 7.

MSP Product Code

bit[15:8] 00

0A 14 28 32 3C

hex hex hex hex hex

hex

MSP 3400G - B8 MSP 3410G - B8 MSP 3420G - B8 MSP 3440G - B8 MSP 3450G - B8 MSP 3460G - B8

By means of the MSP-Prod uct Code, the control processor is able to decide which TV sound standards have to be considered.

MSP ROM Version Code

bit[7:0] 45

46 48

hex hex hex

MSP 34x0G - B5 MSP 34x0G - B6 MSP 34x0G - B8

A change in the ROM version code defines internal software optimizations, that may have influence on the chip’s behavior, e.g. new features may have been included. W hile a software change i s intende d to create no compati bility problems, customers that want to use the new functions can identify new MSP 34x0G versions according to this number.

To avoid compatibility pr oblems with M SP 3410B and MSP 34x0 D, an offset of

is added to the ROM version code of the chip’s imprint.

hex

MSP_PRODUCT

MSP_ROM

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PRELIMINARY DATA SHEET MSP 34x0G

3.4. Programming Tips

This section descr ibes the pre ferred method for initializing the MSP 34x0G. The initialization is group ed into four sections:

– SCART Signal Path (analog signal path) – Demodulator – SCART and I

S Inputs

– Output Channels See Fig. 2–1 on page 8 for a complete signal flow.

SCART Signal Path

1. Select analog input for the SCART baseband processing (SCART DSP Input Select) by means of the ACB r egist er.

2. Select the source for each analog SCART output (SCART Output Select) by means of the ACB register.

Demodulator

For a complete setup of the TV sound processing from analog IF input to the source selection, the following steps must be performed:

1. Set MODUS register to the preferred mode and Sound IF input.

3.5. Examples of Minimum Initialization Codes

Initialization of the MS P 34x0G acco rding to thes e list ings reproduces sound of the selected standard on the loudspeaker output. All numbers are hexadecimal. The examples have the following structure:

1. Perform an I

C controlled reset of the IC.

2. Write MODUS register (with Automatic Sound Select).

3. Set Source Selection for loudspeaker channel (with matrix set to STEREO).

4. Set Prescale (FM and/or NICAM and dummy FM matrix).

5. Write STANDARD SELECT register.

6. Set Volume loudspeaker channel to 0 dB.

3.5.1. B/G-FM (A2 or NICAM)

<80008000> // Softreset <80000000> <801000302003> // MODUS-Register: Automatic = on <801200080320> // Source Sel. = (St or A) & Ch. Matr. = St

hex

<8012000E2403> // FM/AM-Prescale = 24

FM-Matrix = MONO/SOUNDA

<801200105A00> // NICAM-Prescale = <801000200003> // Standard Select: A2 B/G or NICAM B/G

<801000200008> <801200007300> // Loudspeaker Volume 0 dB

2. Choose prefer re d p re sca le ( FM an d NI CA M ) values.

3. Write STANDARD SELECT register.

4. If Automatic Sound Select is not active: Choose FM matrix repeatedly according to the sound mode indicated in the STATUS register.

SCART and I

S Inputs

1. Select preferred prescale for SCART.

2. Select preferred prescale for I

S inputs

(set to 0 dB after RESET).

Output Channels

1. Select the source channel and matrix for each output channel.

2. Set audio baseband processing.

3. Select volume for each output channel.

3.5.2. BTSC-Stereo

<80008000> // Softreset <80000000> <801000302003> // MODUS-Register: Automatic = on <801200080320> // Source Sel. = (St or A) & Ch. Matr. = St <8012000E2403> // FM/AM-Prescale = 24

FM-Matrix = Sound A Mono

<801000200020> // Standard Select: BTSC-STEREO <801200007300> // Loudspeaker Volume 0 dB

hex

3.5.3. BTSC-SAP with SAP at Loudspeaker Channel

<80008000> // Softreset <80000000> <801000302003> // MODUS-Register: Automatic = on <801200080420> // Source Sel. = (St or B) & Ch. Matr. = St <8012000E2403> // FM/AM-Prescale = 24

FM-Matrix = Sound A Mono

<801000200021> // Standard Select: BTSC-SAP <801200007300> // Loudspeaker Volume 0 dB

hex

Micronas 41

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MSP 34x0G PRELIMINARY DATA SHEET

3.5.4. FM-Stereo Radio

<80008000> // Softreset <80000000> <801000302003> // M O DUS- Regist er: Automatic = on <801200080320> // Source Sel. = (St or A) & Ch. Matr. = St

hex

<8012000E2403> // FM/AM-Prescale = 24

FM-Matrix = Sound A Mono

<801000200040> // Standard Select: FM-STEREO-RADIO <801200007300> // Loudspeaker Volume 0 dB

3.5.5. Automatic Standard Detection

A detailed software flow diagram is shown in Fig. 3–2 on page 43.

<80008000> // Softreset <80000000> <801000302003> // M O DUS- R egister: Automatic = on <801200080320> // Source Sel. = (St or A) & Ch. Matr. = St <8012000E2403> // FM/AM-Prescale = 24

FM-Matrix = Sound A Mono

<801200105A00> // NICAM-Prescale = <801000200001> // Standard Select:

Automatic Standard Detection // Wait till STANDARD RESULT contains a value ≤ 07FF // IF STANDARD RESULT contains 0000

// do some error handling // ELSE <801200007300> // Loudspeaker Volume 0 dB

3.5.6. Software Flow for Interrupt driven STATUS

Check

A detailed software flow diagram is shown in Fig. 3–2 on page 43.

If the D_CTR_I/O_1 pin of the MSP 34x0G is connected to an interrupt input pin of the controller, the following interrupt handler can be applied to be automatically called with each status change of the MSP 34x0G. The interru pt handler may adjust the TV display according to the new status information.

Interrupt Handler: <80 11 02 00 <81 dd dd> // Read STATUS // adjust TV display with given status information // Return from Interrupt

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PRELIMINARY DATA SHEET MSP 34x0G

Write MODUS Register

Example [0] = 1 Automatic Sound Select = on

[1] = 1 Enable interrupt if STATUS changes [8] = 0 ANA_IN1+ is selected Define Preference for Automatic Standard Detection: [12] = 0 If 6.5 MHz, set SECAM-L [14:13] = 3 Ignore 4.5 MHz carrier

for the essential bits:

Write SOURCE SELECT Settings

Example:

set loudspeaker Source Select to "Stereo or A" set headphone Source Select to "Stereo or B" set SCART_Out Source Select to "Stereo or A/B"

set Channel Matrix mode for all outputs to "Stereo"

Write FM/AM-Prescale Write NICAM-Prescale

set previous standard or

set standard manually according

picture informat ion

In case of MSPG-

Interrupt to Controller:

Write 01 into

STANDARD SELECT Register

(Start Automatic Standard Detection)

yes

Result = 0

expecting MSPG-interrupt

Read STATUS

Adjust TV-Display

If Bilingual, adjust Source Select setting if required

Fig. 3–2: Software flow diagram for a Minimum demodulator setup for a European Multistandard TV set applying the Automatic Sound Select feature

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MSP 34x0G PRELIMINARY DATA SHEET

132

3364

57.7

±0.1

0.8

±0.2

3.8

±0.1

3.2

±0.2

1.778

±0.05

31 x 1.778 = 55.1

±0.1

0.48

±0.06

20.3

±0.5

0.28

±0.06

±0.05

19.3

±0.1

SPGS703000-1(P64)/1E

4. Specifications

4.1. Outline Dimensions

0.2±

x 45

0.12±

25.14

0.12±

25.14

619

4327

1.1

±0.05

1.9

±0.1

4.05

±0.15

4.75

0.05±

0.71

0.04±

0.23

0.06±

0.48

0.9

0.3±

23.3

0.1

0.1±

24.2

Fig. 4–1: 68-Pin Plastic Leaded Chip Carrier Package (not intended for new designs) (PLCC68)

Weight approximately 4.8 g Dimensions in mm

16 x 1.27 = 20.32

1.27

24.2

0.1±

1.2 x 45°

1.27

7.5

0.1±

SPGS704000-1(P68)/1E

0.1±

16 x 1.27 = 20.32

Fig. 4–2:

64-Pin Plastic Shrink Dual-Inline Package

(PSDIP64)

Weight approximately 9.0 g Dimensions in mm

2752

126

47.0

1.778 25 x 1.778 = 44.4

±0.1

±0.05

±0.1

0.48

±0.06

±0.1

±0.2

4.0

0.6

±0.2

2.8

SPGS703000-1(P52)/1E

15.6 14

±0.06

0.28

16.3

Fig. 4–3:

52-Pin Plastic Shrink Dual-Inline Package

(PSDIP52)

Weight approximately 5.5 g Dimensions in mm

±0.1

±1

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PRELIMINARY DATA SHEET MSP 34x0G

0.15±

17.2

0.15±

23.2

Fig. 4–4:

80-Pin Plastic Quad Flat Pack

(PQFP80)

Weight approximately 1.61 g Dimensions in mm

3348

0.2±

1.75

116

1.75

0.2±

4164

241

0.145

1.5

0.04±

0.17

0.04±

0.37

0.05±

1.3

±0.2

0.055±

0.1±

0.05±

0.22

0.05±

1.4

0.1

0.1±

2.7

0.1

15 x 0.5 = 7.5

0.5

0.1±

0.5

0.1±

23 x 0.8 = 18.4

0.8

0.1±

15 x 0.5 = 7.5

0.1±

0.8

15 x 0.8 = 12.0

0.1±

SPGS705000-3(P80)/1E

Fig. 4–5:

64-Pin Plastic Low-Profile Quad Flat Pack

(PLQFP64)

Weight approximately 0.35 g Dimensions in mm

D0025/3E

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MSP 34x0G PRELIMINARY DATA SHEET

4.2. Pin Connections and Short Descriptions

NC = not connected; leave vacant LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram DVSS: if not used, connect to DVSS AHVSS: connect to AHVSS

PLCC 68-pin

PSDIP 64-pin

Pin No. Pin Name Type Connection

PSDIP 52-pin

PQFP 80-pin

PLQFP 64-pin

(if not used)

Short Description

1 16 14 9 8 ADR_WS OUT LV ADR word strobe 2 −−−−NC LV Not connected 3 15 13 8 7 ADR_DA OUT LV ADR data output 4141276I2S_DA_IN1IN LV I 5131165I2S_DA_OUTOUTLV I 6121054I2S_WS IN/OUTLV I 711943I2S_CL IN/OUTLV I 810832I2C_DA IN/OUTX I 99721I2C_CL IN/OUTX I

S1 data input

S data output

S word strobe

S clock

C data

C clock 10 8 − 1 64 NC LV Not connected 11 7 6 80 63 STANDBYQ IN X Stand-by (low-active) 126 5 7962ADR_SEL IN X I

C Bus address select 13 5 4 78 61 D_CTR_I/O_0 IN/OUT LV D_CTR_I/O_0 14 4 3 77 60 D_CTR_I/O_1 IN/OUT LV D_CTR_I/O_1 15 3 − 76 59 NC LV Not connected 16 2 − 75 58 NC LV Not connected 17 −−−−NC LV Not connected 18 1 2 74 57 AUD_CL_OUT OUT LV Audio clock output

(18.432 MHz) 19 64 1 73 56 TP LV Test pin 20 63 52 72 55 XTAL_OUT OUT X Crystal oscillator 21 62 51 71 54 XTAL_IN IN X Crystal oscillator 22 61 50 70 53 TESTEN IN X Test pin 23 60 49 69 52 ANA_IN2+ IN AVSS via

56 pF / LV

24 59 48 68 51 ANA_IN− IN AVSS via

56 pF / LV

IF input 2

vacant, only if IF input 1 is

also not in use)

(can be left

IF common (can be left

vacant, only if IF input 1 is

also not in use)

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PRELIMINARY DATA SHEET MSP 34x0G

PLCC 68-pin

PSDIP 64-pin

Pin No. Pin Name Type Connection

PSDIP 52-pin

PQFP 80-pin

PLQFP 64-pin

(if not used)

Short Description

25 58 47 67 50 ANA_IN1+ IN LV IF input 1 26 57 46 66 49 AVSUP X Analog power supply 5 V

−−−65 − AVSUP X Analog power supply 5 V

−−−64 − NC LV Not connected

−−−63 − NC LV Not connected

27 56 45 62 48 AVSS X Analog ground

−−−61 − AVSS X Analog ground 28 55 44 60 47 MONO_IN IN LV Mono input

−−−59 − NC LV Not connected 29 54 43 58 46 VREFTOP X Reference voltage IF

A/D converter 30 53 42 57 45 SC1_IN_R IN LV SCART 1 input, right 31 52 41 56 44 SC1_IN_L IN LV SCART 1 input, left 32 51 − 55 43 ASG AHVSS Analog Shield Ground 33 50 40 54 42 SC2_IN_R IN LV SCART 2 input, right 34 49 39 53 41 SC2_IN_L IN LV SCART 2 input, left 35 48 − 52 40 ASG AHVSS Analog Shield Ground 36 47 38 51 39 SC3_IN_R IN LV SCART 3 input, right 37 46 37 50 38 SC3_IN_L IN LV SCART 3 input, left 38 45 − 49 37 ASG AHVSS Analog Shield Ground 39 44 − 48 36 SC4_IN_R IN LV SCART 4 input, right 40 43 − 47 35 SC4_IN_L IN LV SCART 4 input, left 41 −−46 − NC LV or AHVSS Not connected 42 42 36 45 34 AGNDC X Analog reference voltage 43 41 35 44 33 AHVSS X Analog ground

−−−43 − AHVSS X Analog ground

−−−42 − NC LV Not connected

−−−41 − NC LV Not connected

44 40 34 40 32 CAPL_M X Volume capacitor MAIN 45 39 33 39 31 AHVSUP X Analog power supply 8 V 46 38 32 38 30 CAPL_A X Volume capacitor AUX 47 37 31 37 29 SC1_OUT_L OUT LV SCART output 1, left

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MSP 34x0G PRELIMINARY DATA SHEET

PLCC 68-pin

PSDIP 64-pin

Pin No. Pin Name Type Connection

PSDIP 52-pin

PQFP 80-pin

PLQFP 64-pin

(if not used)

Short Description

48 36 30 36 28 SC1_OUT_R OUT LV SCART output 1, right 49 35 29 35 27 VREF1 X Reference ground 1 50 34 28 34 26 SC2_OUT_L OUT LV SCART output 2, left 51 33 27 33 25 SC2_OUT_R OUT LV SCART output 2, right 52 −−32 − NC LV Not connected 53 32 − 31 24 NC LV Not connected 54 31 26 30 23 DACM_SUB OUT LV Subwoofer output 55 30 − 29 22 NC LV Not connected 56 29 25 28 21 DACM_L OUT LV Loudspeaker out, left 57 28 24 27 20 DACM_R OUT LV Loudspeaker out, right 58 27 23 26 19 VREF2 X Reference ground 2 59 26 22 25 18 DACA_L OUT LV Headphone out, left 60 25 21 24 17 DACA_R OUT LV Headphone out, right

−−−23 − NC LV Not connected

−−−22 − NC LV Not connected

61 24 20 21 16 RESETQ IN X Power-on-reset 62 23 − 20 15 NC LV Not connected 63 22 − 19 14 NC LV Not connected 64 21 19 18 13 NC LV Not connected 65 20 18 17 12 I2S_DA_IN2 IN LV I

S2-data input

66 19 17 16 11 DVSS X Digital ground

−−−15 − DVSS X Digital ground

−−−14 − DVSS X Digital ground

67 18 16 13 10 DVSUP X Digital power supply 5 V

−−−12 − DVSUP X Digital power supply 5 V

−−−11 − DVSUP X Digital power supply 5 V

68 17 15 10 9 ADR_CL OUT LV ADR clock

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PRELIMINARY DATA SHEET MSP 34x0G

4.3. Pin Descriptions

Pin numbers refer to the 80-pin PQFP package. Pin 1, NC – Pin not connected.

Pin 2, I2C_CL – I Via this pin, the I

C Clock Input/Output (Fig. 4–18)

C-bus clock signal has to be supplied. The signal can be pulled down by the MSP in case of wait conditions.

Pin 3, I2C_DA – I Via this pin, the I

C Data Input/Output (Fig. 4–18)

C-bus data is written to or read from

the MSP.

Pin 4, I2S_CL – I Clock line for the I driven by the MSP; in slave mode, an external I

S Clock Input/Output (Fig. 4–19)

S bus. In master mode, this line is

clock has to be supplied.

Pin 5, I2S_WS – I (Fig. 4–19) Word strobe line for the I line is driven by the MSP; in slave mode, an external

S word strobe has to be supplied.

Pin 6, I2S_DA_OUT – I Output of digital seri al sound data of the MSP on the

S bus.

I Pin 7, I2S_DA_IN1 – I

First input of digital se rial sound data to the MSP via

S bus.

the I

S Word Strobe Input/Output

S bus. In master mode, this

S Data Output (Fig. 4–23)

S Data Input 1 (Fig. 4–15)

Pin 8, ADR_DA – ADR Bus Data Output (Fig. 4–23) Output of digital ser ial data to the DRP 3510A via the ADR bus.

Pin 9, ADR_WS – ADR Bus Word Strobe Output (Fig. 4–23) Word strobe output for the ADR bus.

Pin 10, ADR_CL – ADR Bus Clock Output (Fig. 4–23) Clock line for the ADR bus.

Pins 11, 12, 13, DVSUP* – Digital Supply Voltage Power supply for the digital circuitry of the MSP. Must be connected to a +5 V power supply.

Pins 22, 23, NC – Pins not connected. Pins 24, 25, DACA_R/L – Headphone Outputs

(Fig. 4–21) Output of the headphone signal. A 1-nF capacitor to AHVSS must be conn ected to t hese pins. The D C offset on these pins de pen ds on t he sel ec ted head pho ne volume.

Pin 26, VREF2 – Reference Ground 2 Reference analog ground. This pi n must be connected separately to ground (AHVSS). VREF2 serves as a clean ground and sh ould be used as the reference for analog connections to the loudspeaker and headphone outputs.

Pins 27, 28, DACM_R/L – Loudspeaker Outputs (Fig. 4–21) Output of the loudspe aker signal. A 1-nF capacitor to AHVSS must be conn ected to t hese pins. The D C offset on these pins depends on the selected loudspeaker volume.

Pin 29, NC – Pin not connected. Pin 30, DACM_SUB – Subwoofer Output (Fig. 4–21)

Output of the subwoofer signal. A 1-nF capacitor to AHVSS must be conn ected to this pin. Due to t he low frequency content of the s ubwoofer output, the value of the capacitor may be increa sed for better suppression of high-frequency noi se. The DC offs et on thi s pin depends on the selected loudspeaker volume.

Pins 31, 32, NC – Pin not connected. Pins 33, 34, SC2_OUT_R/L – SCART2 Outputs

(Fig. 4–22) Output of the SCART2 signal. Connections to these pins must use a 100-Ω series resistor and are intended to be AC-coupled.

Pin 35, VREF1 – Reference Ground 1 Reference analog ground. This pi n must be connected separately to ground (AHVSS). VREF1 serves as a clean ground and sh ould be used as the reference for analog connections to the SCART outputs.

Pins 14, 15, 16, DVSS* – Digita l Gr oun d Ground connection for the digital circuitry of the MSP.

Pin 17, I2S_DA_IN2 – I Second input of digital s erial sound data to the MSP via the I

S bus.

S Data Input 2 (Fig. 4–15)

Pins 36, 37, SC1_OUT_R/L – SCART1 Outputs (Fig. 4–22) Output of the SCART1 signal. Connections to these pins must use a 100-Ω series resistor and are intended to be AC-coupled.

Pins 18, 19, 20, NC – Pins not connected. Pin 21, RESETQ – Reset Input (Fig. 4–11)

In the steady state, high level is required. A low level resets the MSP 34x0G.

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MSP 34x0G PRELIMINARY DATA SHEET

Pin 38, CAPL_A – Volume Capacitor Headphone (Fig. 4–24) A 10-µF capacitor to AHVSUP must be connected to this pin. It ser ves as a smoothin g filter for headphone volume changes in order to suppress audible plops. The value of the capa citor can be lowered to 1-µF if faster response is requir ed. The area en circled by the trace lines should be minimized; keep traces as short as possible. This input is sens itive for magnetic induction.

Pin 39, AHVSUP* – Analog Power Supply High Volt- age Power is supplied via this pin for the analog c ircu itry of the MSP (except IF input). This pin must be connected to the +8V supply.

Pin 40, CAPL_M – Volume Capacitor Loudspeaker (Fig. 4–24) A 10-µF capacitor to AHVSUP must be connected to this pin. It serves as a smoothing fi lter for loudspeaker volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1 µF if faster response is requir ed. The area en circled by the trace lines should be minimized; keep traces as short as possible. This input is sens itive for magnetic induction.

Pins 41, 42, NC – Pins not connected. Pins 43, 44, AHVSS* – Ground for Analog Power

Supply High Voltage Ground connection for the analog c ircuitr y o f the MSP (except IF input).

Pin 45, AGNDC – Internal Analog Reference Voltage This pin ser ves as the internal ground c onnection for the analog circuitr y (except IF input). It must be connected to the VREF pins with a 3.3-µF and a 10 0-nF capacitor in parallel. This pins shows a DC level of typically 3.73 V.

Pin 46, NC – Pin not connected. Pins 47, 48, SC4_IN_L/R – SCART4 Inputs

(Fig. 4–14) The analog input signa l for SCART4 is fed to this pin. Analog input connection must be AC-coupled.

Pin 49, ASG – Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs.

Pins 50, 51, SC3_IN_L/R – SCART3 Inputs (Fig. 4–14) The analog input signa l for SCART3 is fed to this pin. Analog input connection must be AC-coupled.

Pin 52, ASG – Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs.

Pins 53, 54, SC2_IN_L/R – SCART2 Inputs (Fig. 4–14) The analog input sign al for SCART2 is fed to this pin. Analog input connection must be AC-coupled.

Pin 55, ASG – Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs.

Pins 56, 57, SC1_IN_L/R – SCART1 Inputs (Fig. 4–14) The analog input sign al for SCART1 is fed to this pin. Analog input connection must be AC-coupled.

Pin 58, VREFTOP – Reference Voltage IF A/D Con- verter (Fig. 4–16) Via this pin, the reference voltage for the IF A/D converter is decoupled. It must be connected to AVSS pins with a 10-µF and a 100-nF capacitor in parallel. Traces must be kept short.

Pin 59, NC – Pin not connected. Pin 60, MONO_IN – Mono Input (Fig. 4–14)

The analog mono inp ut s ignal i s fed to thi s p in. Analog input connection must be AC-coupled.

Pins 61, 62, AVSS* – Ground for Analog Power Supply Voltage Ground connection for the analo g IF input circuitry of the MSP.

Pins 63, 64, NC – Pins not connected. Pins 65, 66, AVSUP* – Analog Power Supply Voltage

Power is supplied via this pin for the analog IF input circuitry of the MSP. This pin must b e connected to the +5 V supply.

Pin 67, ANA_IN1+ – IF Input 1 (Fig. 4–16) The analog sound IF signal is supplied to this pin. Inputs must be AC-coupled. This pin is designed as symmetrical input: ANA_IN1+ is internally connected to one input of a symmetri cal op amp, ANA_IN- to the other.

Pin 68, ANA_IN− – IF Common (Fig. 4–16) This pins serves as a common reference for ANA_IN1/ 2+ inputs.

Pin 69, ANA_IN2+ – IF Input 2 (Fig. 4–16) The analog sound if signal is supplied to this pin. Inputs must be AC-coupled. This pin is designed as symmetrical input: ANA_IN2+ is internally connected to one input of a symm etri cal o p amp, ANA_IN− to the other.

Pin 70, TESTEN – Test Enable Pin (Fig. 4–12) This pin enables factory test modes. For normal operation, it must be connected to ground.

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PRELIMINARY DATA SHEET MSP 34x0G

Pins 71, 72, XTAL_IN, XTAL_OUT – Crysta l Inpu t and Output Pins (Fig. 4–20) These pins are connected to an 18.432 MHz crystal oscillator which is digitally tuned by integrated shunt capacitances. An external clock can be fed into XTAL_IN. The audio clock output signal AUD_CL_OUT is derived from the oscillator. External capacitors at each crystal pin to ground (AVSS) are required. It should be verifie d by layout, that no sup ply curr ent for the digital circuitr y is flowing through the ground c onnection p oint.

Pin 73, TP – This pin enables factor y test modes. For normal operation, it must be left vacant.

Pin 74, AUD_CL_OUT – Audio Clock Output (Fig. 4–20) This is the 18.432 MHz main clock output.

Pins 75, 76, NC – Pins not connected. Pins 77, 78, D_CTR_I/O_1/0 – Digital Control Input/

Output Pins (Fig. 4–19) General purpos e input/output pins. Pin D_CT R_I/O_1 can be used as an in terrup t request pin to the c ontroller.

Pin 79, ADR_SEL – I

C Bus Address Sele ct (Fig. 4–17) By means of this pin, one of three device addresses for the MSP can be selected. The pin can be connected to ground (I ply (84/85

C device addresses 80/81

), or left open (88/89

hex

), to +5 V sup-

Pin 80, STANDBYQ – Stand-by In normal operation, this pin must be high. If the MSP 34x0G is switched off by first pullin g STANDBYQ low and then (after >1µs d elay) switching off DVSUP and AVSUP, but keeping AHVSUP (‘Standby’-mode), the SCART switches maintain their position and function.

* Application Note:

All ground pins shoul d be connecte d to one low-re sistive ground plane. All supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from DVSUP to DVSS, AVSUP to AVSS, and AHVSUP to AHVS S are recommended as closely as possible to these pins. Decoupling of DVSUP and DVSS is most important. We recommend using more than one capacitor. By choosing different values, the frequency range of active decoupling can be extended. In our application boards we use: 220 pF, 470 pF, 1. 5 nF, and 10 µF. The capacitor with the lowest value should be place d nea rest to the DVSUP and DVSS pins.

The ASG pins should be conn ected as cl osely as possible to the MSP ground. If they are lead with the SCART-inputs as shielding lines, they should not be connected to ground at the SCART connector.

Micronas 51

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MSP 34x0G PRELIMINARY DATA SHEET

4.4. Pin Configurations

ADR_WS

ADR_DA

I2S_DA_IN1

I2S_DA_OUT

I2S_WS

I2S_CL

I2C_DA

I2C_CL

9876543216867666564636261

STANDBYQ

ADR_SEL D_CTR_I/O_0 D_CTR_I/O_1

AUD_CL_OUT

XTAL_OUT

XTAL_IN

TESTEN

ANA_IN2+

ANA_IN−

ANA_IN1+

11 12 13 14

17 18

19 20 21 22 23 24 25

AVSUP CAPL_M

26 44

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

MSP 34x0G

ADR_CL

DVSUP

DVSS

I2S_DA_IN2

RESETQ

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45

DACA_R DACA_L VREF2 DACM_R DACM_L NC DACM_SUB NC NC SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP

AVSS MONO_IN

VREFTOP

SC1_IN_R

SC1_IN_L

ASG

SC2_IN_R

SC2_IN_L

SC4_IN_L

SC4_IN_R

ASG

SC3_IN_L

SC3_IN_R

ASG

AHVSS

AGNDC

Fig. 4–6: 68-pin PLCC package (not intended for new designs)

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PRELIMINARY DATA SHEET MSP 34x0G

VREF2

DACM_R

DACM_L

DACM_SUB

1AUD_CL_OUT 2NC 3NC 4D_CTR_I/O_1 5D_CTR_I/O_0 6ADR_SEL 7STANDBYQ 8NC 9I2C_CL 10I2C_DA 11I2S_CL 12I2S_WS 13I2S_DA_OUT 14I2S_DA_IN1 15ADR_DA 16ADR_WS 17ADR_CL 18DVSUP 19DVSS

MSP 34x0G

20I2S_DA_IN2 21NC 22NC 23NC 24RESETQ 25DACA_R 26DACA_L 27 28 29 30 31 32

38 37 36 35 34 33

TP64 XTAL_OUT63 XTAL_IN62 TESTEN61 ANA_IN2+60 ANA_IN−59 ANA_IN+58 AVSUP57 AVSS56 MONO_IN55 VREFTOP54 SC1_IN_R53 SC1_IN_L52 ASG51 SC2_IN_R50 SC2_IN_L49 ASG48 SC3_IN_R47 SC3_IN_L46 ASG45 SC4_IN_R44 SC4_IN_L43 AGNDC42 AHVSS41 CAPL_M40 AHVSUP39 CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R

AUD_CL_OUT

D_CTR_I/O_1 D_CTR_I/O_0

ADR_SEL

STANDBYQ

I2S_DA_OUT

I2S_DA_IN1

ADR_DA

ADR_WS

ADR_CL

I2S_DA_IN2

RESETQ DACA_R

DACA_L

DACM_R

DACM_L

DACM_SUB

Fig. 4–8: 52-pin PSDIP package

I2C_CL

I2C_DA

I2S_CL

I2S_WS

DVSUP

DVSS

VREF2

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

MSP 34x0G

52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN− ANA_IN1+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L SC3_IN_R SC3_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R

Fig. 4–7: 64-pin PSDIP package

Micronas 53

Page 54

MSP 34x0G PRELIMINARY DATA SHEET

SC2_IN_L ASG

AVSUP AVSUP

ANA_IN1+

ANA_IN−

ANA_IN2+

TESTEN

XTAL_IN

XTAL_OUT

AUD_CL_OUT

NC D_CTR_I/O_1 D_CTR_I/O_0

ADR_SEL

STANDBYQ

SC2_IN_R

ASG

SC1_IN_L

SC1_IN_R

VREFTOP

MONO_IN

AVSS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

65 66 67 68 69 70 71 72 73

74 75 76 77 78 79 80

1 2 3 4 5 6 7 8 9 101112131415161718192021222324

MSP 34x0G

SC3_IN_R

SC3_IN_L

ASG

SC4_IN_R

SC4_IN_L

AGNDC

AHVSS

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L

NC I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

ADR_DA

ADR_WS

ADR_CL

Fig. 4–9: 80-pin PQFP package

DVSUP

DVSUP DVSUP

DACA_R

RESETQ

I2S_DA_IN2

DVSS

54 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

AVSUP

ANA_IN1+

ANA_IN−

ANA_IN2+

TESTEN XTAL_IN

XTAL_OUT

AUD_CL_OUT

NC D_CTR_I/OUT1 D_CTR_I/OUT0

ADR_SEL

STANDBYQ

SC2_IN_L

SC2_IN_R

ASG

SC1_IN_L

SC1_IN_R

VREFTOP

MONO_IN

AVSS

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

12345678910111213141516

MSP 34x0G

ASG

SC3_IN_R

SC3_IN_L

ASG

SC4_IN_R

SC4_IN_L

AGNDC

AHVSS

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L DACA_R

I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

ADR_DA

ADR_WS

Fig. 4–10: 64-pin PLQFP package

RESETQ

I2S_DA_IN2

DVSS

DVSUP

ADR_CL

Micronas 55

Page 56

MSP 34x0G PRELIMINARY DATA SHEET

DVSS

>300 k

AVSUP

200 k

≈ 3.75 V

24 kΩ

≈ 3.75 V

40 kΩ

4.5. Pin Circuits

ANA_IN1+ ANA_IN2+

Fig. 4–11: Input Pin: RESETQ

Fig. 4–12: Input Pin TESTEN

Fig. 4–13: Input Pin: MONO_IN

ANA_IN− VREFTOP

Fig. 4–16: Input Pins: VREFTOP, ANA_IN1+, ANA_IN-, ANA_IN2+

DVSUP

23 kΩ

GND

ADR_SEL

Fig. 4–17: Input Pin: ADR_SEL

Fig. 4–14: Input Pins: SC4-1_IN_L/R

Fig. 4–15: Input Pins: I2S_DA_IN1, I2S_DA_IN2, STANDBYQ

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PRELIMINARY DATA SHEET MSP 34x0G

AHVSUP

GND

Fig. 4–18: Input/Output Pins: I2C_CL, I2C_DA

DVSUP

GND

Fig. 4–19: Input/Output Pins: I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0

0...1.2 mA

3.3 kΩ

Fig. 4–21: Output Pins: DACA_R/L, DACM_R/L, DACM_SUB

26 pF

120 kΩ

300 Ω

≈ 3.75 V

Fig. 4–22: Output Pins: SC_2_OUT_R/L, SC_1_OUT_R /L

3−30 pF

500 kΩ

Fig. 4–20: Input/Output Pins: XTAL_IN, XTAL_OUT, AUD_CL_OUT

2.5 V

DVSUP

GND

Fig. 4–23: Output Pins: I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL

0...2 V

Fig. 4–24: Capacitor Pins: CAPL_A, CAPL_M

125 kΩ

≈ 3.75 V

Fig. 4–25: Pin: AGNDC

Micronas 57

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MSP 34x0G PRELIMINARY DATA SHEET

4.6. Electrical Characteristics

4.6.1. Absolute Maximum Ratings

Symbol Parameter Pin Name Min. Max. Unit

T T V V V dV

V I

Idig

Iana

SUP1

SUP2

SUP3

SUP23

TOT

Idig

Iana

Ambient Operating Temperature − 070°C Storage Temperature −−40 125 °C First Supply Voltage AHVSUP −0.3 9.0 V Second Supply Voltage DVSUP −0.3 6.0 V Third Supply Voltage AVSUP −0.3 6.0 V Voltage between AVSUP

and DVSUP Power Dissipation

PLCC68 PSDIP64 PSDIP52 PQFP80 PLQFP64

Input Voltage, all Digital Inputs −0.3 V

AVSUP , DVSUP

AHVSUP, DVSUP , AVSUP

−0.5 0.5 V

1200 1300 1200 1000 960

+0.3 V

SUP2

mW mW mW mW mW

Input Current, all Digital Pins −−20 +20 mA Input Voltage, all Analog Inputs SCn_IN_s,

−0.3 V

SUP1

+0.3 V

MONO_IN

Input Current, all Analog Inputs SCn_IN_s,

−5 +5mA

MONO_IN

Oana

Output Current, all SCART Outputs SCn_OUT_s Output Current, all Analog Outputs

DACp_s

2) 3), 4) 3), 4)

2) 3) 3)

except SCART Outputs

Cana

positive value means current flowing into the circuit

“n” means “1”, “2”, “3”, or “4”, “s” means “L” or “R”, “p” means “M” or “A”

The analog outputs are short-circuit proof with respect to First Supply Voltage and ground.

Total chip power dissipation must not exceed absolute maximum rating.

Output Current, other pins connected to capacitors

CAPL_p, AGNDC

3) 3)

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating onl y. Functional operation of the device at these or any oth er condi tions beyond those indic ated i n the “Rec ommended Operating Conditions/Character istics” of this specificati on is not i mplied. Ex posure to abs olute maximum ratings conditions for extended periods may affect device reliability.

58 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

4.6.2. Recommended Operating Conditions (TA = 0 to 70 °C)

4.6.2.1. General Recommended Operating Conditions

Symbol Parameter Pin Name Min. Typ. Max. Unit

SUP1

First Supply Voltage

AHVSUP 7.6 8.0 8.7 V

(AHVSUP = 8 V) First Supply Voltage

4.75 5.0 5.25 V

(AHVSUP = 5 V)

SUP2

SUP3

STBYQ1

Second Supply Voltage DVSUP 4.75 5.0 5.25 V Third Supply Voltage AVSUP 4.75 5 .0 5.25 V STANDBYQ Setup Time before

Turn-off of Second Supply Voltage

STANDBYQ, DVSUP

1 µs

4.6.2.2. Analog Input and Output Recommendations

Symbol Parameter Pin Name Min. Typ. Max. Unit

AGNDC

AGNDC-Filter-Capacitor AGNDC −20% 3.3 µF Ceramic Capacitor in Parallel −20% 100 nF

inSC

DC-Decoupling Capacitor in front of

SCn_IN_s

−20% 330 nF

SCART Inputs

inSC

inMONO

LSC

VMA

SCART Input Level 2.0 V Input Level, Mono Input MONO_IN 2.0 V SCART Load Resistance SCn_OUT_s SCART Load Capacitance 6.0 nF Main/AUX Volume Capaci tor CAPL_M,

CAPL_A

FMA

“n” means “1”, “2”, or “3”, “s” means “L” or “R”, “p” means “M” or “A”

Main/AUX Filter Capacitor DACM_s,

DACA_s

RMS

10 kΩ

10 µF

−10% 1 +10% nF

Micronas 59

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MSP 34x0G PRELIMINARY DATA SHEET

4.6.2.3. Recommendations for Analog Sound IF Input Signal

Symbol Parameter Pin Name Min. Typ. Max. Unit

VREFTOP

IF_FMTV

IF_FMRADIO

IF_FM

IF_AM

FMNI

AMNI

FM1/FM2

VREFTOP-Filter-Capacitor VREFTOP −20% 10 µF Ceramic Capacitor in Parallel −20% 100 nF Analog Input Frequency Range

for TV Applications

ANA_IN1+, ANA_IN2+,

09MHz

ANA_IN−

Analog Input Frequency for

10.7 MHz

FM-Radio Applications Analog Input Range FM/NICAM 0.1 0.8 3 V Analog Input Range AM/NICAM 0.1 0.45 0.8 V Ratio: NICAM Carrier/FM Carrier

(unmodulated carriers) BG: I:

Ratio: NICAM Carrier/AM Carrier

−20

−23

−7

−10

0 0

dB dB

−25 −11 0 dB

(unmodulated carriers) Ratio: FM-Main/FM-Sub Satellite 7 dB Ratio: FM1/FM2

7dB

German FM-System

PR SUP

MAX

Ratio: Main FM Carrier/

15 −−dB

Color Carrier Ratio: Main FM Carrier/

15 −−dB

Luma Components Passband Ripple −−±2dB Suppression of Spectrum

15 − dB

above 9.0 MHz (not for FM Radio) Maximum FM-Deviation (approx.)

normal mode HDEV2: high deviation mode HDEV3: very high deviation mode

±180 ±360 ±540

kHz kHz kHz

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PRELIMINARY DATA SHEET MSP 34x0G

4.6.2.4. Crystal Recommendations

Symbol Parameter Pin Name Min. Typ. Max. Unit General Crystal Recommendations

Crystal Parallel Resonance Frequency at 12 pF Load Capacitance

Crystal Series Resistance 8 25 Ω Crystal Shunt (Parallel) Capacitance 6.2 7.0 pF External Load Capacitance

XTAL_IN,

XTAL_OUT Crystal Recommendations for Master-Slave Applications f

TOL

TEM

Accuracy of Adjustment −20 +20 ppm Frequency Variation

versus Temperature

Crystal Recommendations for FM / NICAM Applications

TOL

TEM

Motional (Dynamic) Capacitanc e 19 24 fF Required Open Loop Clock

Frequency (T

= 25 °C)

amb

AUD_CL_OUT

(No MSP-clock synchronization to I2S clock possible)

Accuracy of Adjustment −30 +30 ppm Frequency Variation

versus Temperature

18.432 MHz

PSDIP approx. 1.5 P(L)QFP approx. 3.3

(MSP-clock must perform synchronization to I2S clock)

pF pF

−20 +20 ppm

18.431 18.433 MHz

−30 +30 ppm

Crystal Recommendations for all analog FM/AM Applications

TOL

TEM

Motional (Dynamic) Capacitanc e 15 fF Required Open Loop Clock

Frequency (T

= 25 °C)

amb

AUD_CL_OUT

(No MSP-clock synchronization to I2S clock possible)

18.4305 18.4335

MHz

Accuracy of Adjustment −100 +100 ppm Frequency Variation

−50 +50 ppm

versus Temperature

Amplitude Recommendation for Operation with External Clock Input (C V

XCA

External capacitors at each crystal pin to groun d are required. They are ne cessary to tune the open-loo p fre-

Required Open Loop Clock Frequency (T

= 25 °C)

amb

AUD_CL_OUT 18.429 18.435 MHz

after reset typ. 22 pF)

load

External Clock Amplitude XTAL_IN 0.7 V

quency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layou ts, the acc urate capacitor size should be determined with th e customer PCB

. The sug-

gested values (1.5...3.3 pF) are figures based on experience and should serve as “start value”. To define the capacitor s ize, reset the MSP without trans mitting any further I2C telegrams. Measure th e fre-

quency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz as closely as possible. The higher the capacity, the lower the resulting clock frequency.

Micronas 61

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MSP 34x0G PRELIMINARY DATA SHEET

4.6.3. Characteristics

= 0 to 70 °C, f

at T

= 60 °C, f

at T

= Junction Temperature

CLOCK

= 18.432 MHz, V

CLOCK

= 18.432 MHz, V

SUP1

= 7.6 to 8.7 V, V

SUP1

= 8 V, V

SUP2

= 4.75 to 5.25 V for min./max. values

SUP2

= 5 V for typical values,

MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel

4.6.3.1. General Characteristics

Symbol Parameter Pi n Na m e Min. Typ. Max. Unit Test Condit ions

Supply

SUP1A

SUP2A

SUP3A

SUP1S

Clock

First Supply Current (active) (AHVSUP = 8 V)

First Supply Current (active) (AHVSUP = 5 V)

Second Supply Current (active) DVSUP 55 70 mA Third Supply Current (active) AVSUP 30 38 mA First Supply Current

(AHVSUP = 8 V) First Supply Current

(AHVSUP = 5 V)

AHVSUP 17

11 11

AHVSUP 5.6 7.7 mA STANDBYQ = low

3.7 5.1 mA

25 16

17 11

mA mA

Vol. Main and Aux = 0 dB Vol. Main and Aux = -30dB

Vol. Main and Aux = 0 dB Vol. Main and Aux = -30 dB

CLOCK

JITTER

xtalDC

Startup

ACLKAC

ACLKDC

outHF_ACL

Clock Input Frequency XTAL_IN 18.432 MHz Clock High to Low Ratio 45 55 % Clock Ji t ter (Verification not

provided in Production Test) DC-Voltage Oscillator 2.5 V Oscillator Startup Time at

VDD Slew-rate of 1 V/1 µs Audio Clock Output AC Voltage AUD_CL_OUT 1.2 1.8 V Audio Clock Output DC Voltage 0.4 0.6 V HF Output Resistance 140 Ω

XTAL_IN, XTAL_OUT

0.4 2 ms

50 ps

SUP3

load = 40 pF I

= 0.2 mA

max

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PRELIMINARY DATA SHEET MSP 34x0G

4.6.3.2. Digital Inputs, Digital Outputs

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

Digital Input Levels

DIGIL

DIGIH

DIGI

DLEAK

DIGIL

DIGIH

ADRSEL

Digital Input Low Voltage STANDBYQ Digital Input High Voltage 0.5 V Input Impedance 5 pF Digital Input Leakage Current −11µA0V < U

Digital Input Low Voltage ADR_SEL 0.2 V Digital Input High Voltage 0.8 V Input Current Address Select Pin −500 −220 µAU

Digital Output Levels

DCTROL

DCTROH

Digital Output Low Voltage D_CTR_I/O_0 Digital Output High Voltage V

D_CTR_I/O_0/1

D_CTR_I/O_1

SUP2

−0.3

0.2 V

220 500 µAU

SUP2

INPUT

D_CTR_I/O_0/1: tri-state

ADR_SEL

0.4 V IDDCTR = 1 mA V IDDCTR = −1 mA

< DVSUP

= DVSS = DVSUP

Micronas 63

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MSP 34x0G PRELIMINARY DATA SHEET

4.6.3.3. Reset Input and Power-Up

Symbol Parameter Pi n Na m e Min. Typ. Max. Unit Test Condit ions

RESETQ Input Levels

V V Z I

RES

RHL

RLH

RES

DVSUP AVSUP

4.5 V

Reset High-Low Transition Voltage RESETQ 0.3 0.4 V Reset Low-High Transition Voltage 0.45 0.55 V Input Capacitance 5 pF Input High Current 20 µAU

SUP2

RESETQ

t/ms

= DVSUP

RESETQ

0.45×DVSUP

0.3...0.4×DVSUP

Internal Reset

Low-to-High Threshold

Reset Delay >2 ms

High

Low

High-to-Low Threshold

Note: The reset should not reach hi gh level before the oscillator has started. This requires a reset delay of >2 ms

0.45 x DVSUP means

2.25 Volt with D VSUP = 5.0 V

t/ms

Fig. 4–26: Power-up sequence

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PRELIMINARY DATA SHEET MSP 34x0G

4.6.3.4. I2C-Bus Characteristics

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

I2CIL

I2CIH

I2C1

I2C2

I2C5

I2C6

I2C3

I2C4

I2C

I2COL

I2COH

I2COL1

I2COL2

I2C-Bus Input Low Voltage I2C_CL, I2C-Bus Input High Voltage 0.6 V I2C Start Condition Setup Time 120 ns I2C Stop Condition Setup Time 120 ns I2C-Data Setup Time

before Rising Edge of Clock I2C-Data Hold Time

after Falling Edge of Clock I2C-Clock Low Pulse Time I2C_CL 500 ns I2C-Clock High Pulse Time 500 ns I2C-BUS Frequency 1.0 MHz I2C-Data Output Low Voltage I2C_CL, I2C-Data Output

High Leakage Current I2C-Data Output Hold Time

after Falling Edge of Clock I2C-Data Output Setup Time

before Rising Edge of Clock

I2C_DA

55 ns

I2C_DA

15 ns

100 ns f

0.3 V

0.4 V I

1.0 µAV

SUP2

I2COL

I2COH

= 1 MHz

I2C

= 3 mA

= 5 V

I2C_CL

I2C_DA as input

I2C_DA as output

Fig. 4–27: I

C bus timing diagram

I2C1

I2C5

I2COL2

I2C4

1/F

I2C

I2C3

I2C6

I2COL1

I2C2

Micronas 65

Page 66

MSP 34x0G PRELIMINARY DATA SHEET

4.6.3.5. I2S-Bus Characteristics

Symbol Parameter Pi n Na m e Min. Typ. Max. Unit Test Condit ions

I2SIL

I2SIH

I2SI

LEAKI2S

I2SOL

I2SOH

I2SOWS

I2SOCL

I2S10/I2S20

s_I2S

h_I2S

d_I2S

I2SWS

I2SCL

Input Low Voltage I2S_DA_IN1/2

I2S_CL

Input High Voltage 0.5 V

I2S_WS

0.2 V

SUP2

Input Impedance 5 pF Input Leakage Current −11µA0V < U I2S Output Low Voltage I2S_CL

I2S_WS

I2S Output High Voltage V

I2S_DA_OUT

SUP2

− 0.3

0.4 V I VI

I2SOL

I2SOH

INPUT

= 1 mA

= −1 mA

< DVSUP

I2S-Word Strobe Output Frequency I2S_WS 32.0 kHz I2S-Clock Output Frequency I2S_CL 1.024

2.048

MHz MHz

I2S_CONFIG[0] = 0

I2S_CONFIG[0] = 1 I2S-Clock Output High/Low-Ratio 0.9 1.0 1. 1 I2S Input Setup Time

before Rising Edge of Clock I2S Input Hold Time

I2S_CL I2S_DA_IN1/2

12 ns for details see Fig. 4–28

“I2S bus timing diagram”

40 ns

after Rising Edge of Clock I2S Output Delay Time

after Falling Edge of Clock

I2S_CL I2S_WS

28 ns C

=30pF

I2S_DA_OUT I2S-Word Strobe Input Frequency I2S_WS 32.0 kHz I2S-Clock Input Frequency I2S_CL 1.024 MHz

I2SCL

I2S-Clock Input High/Low Ratio 0.9 1.1

66 Micronas

Page 67

PRELIMINARY DATA SHEET MSP 34x0G

1/F

I2S_WS

I2S_CL

I2S_DA_IN

MODUS[6] = 0

MODUS[6] = 1

R LSB L MSB

Detail A

16/32 bit left channel

I2SWS

Detail C

L LSB

R MSB

16/32 bit right channel

R LSB L LSB

I2S_DA_OUT

I2S_WS

I2S_CL

I2S_DA_IN

I2S_DA_OUT

R LSB

L MSB

Data: MSB first, I2S master

Detail B

MODUS[6] = 0

MODUS[6] = 1

Detail A

R LSB L MSB

16,18...32 bit left channel

16, 18...32 bit left channel

R LSB

Detail B

L MSB

Data: MSB first, I2S slave

1/F

L LSB

I2SWS

Detail C

L LSB

R MSB

16/32 bit right channel16/32 bit left channel

R LSB L LSB

16, 18...32 bit right channel

R LSB L LSB

16, 18...32 bit right channel

Detail C

I2S_CL

s_I2S

1/F

I2SCL

Detail A,B

I2S_CL

s_I2S

h_I2S

I2S_DA_IN1/2

I2S_WS as INPUT

d_I2S

I2S_WS as OUTPUT

d_I2S

I2S_DA_OUT

Fig. 4–28: I2S bus timing diagram

Micronas 67

Page 68

MSP 34x0G PRELIMINARY DATA SHEET

4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC

Symbol Parameter Pi n Na m e Min. Typ. Max. Unit Test Condit ions

Analog Ground

AGNDC0

AGNDC Open Circuit Voltage (AHVSUP =8 V)

AGNDC Open Circuit Voltage (AHVSUP = 5 V)

outAGN

AGNDC Output Resistance (AHVSUP = 8 V)

AGNDC Output Resistance (AHVSUP = 5 V)

Analog Input Resistance

inSC

inMONO

SCART Input Resistance from T

= 0 to 70 °C

MONO Input Resistance from T

= 0 to 70 °C

Audio Analog-to-Digital-Converter

AICL

Analog Input Clipping Level for Analog-to-DigitalConversion (AHVSUP = 8 V)

Analog Input Clipping Level for Analog-to-DigitalConversion (AHVSUP = 5 V)

AGNDC 3.77 V R

2.51 V

70 125 180 kΩ 3 V ≤ V

47 83 120 kΩ

SCn_IN_s

25 40 58 kΩ f

MONO_IN 152435kΩ f

SCn_IN_s,

MONO_IN

2.00 2.25 V

1.13 1.51 V

RMS

≥10 MΩ

load

AGNDC

= 1 kHz, I = 0.05 mA

signal

= 1 kHz, I = 0.1 mA

signal

= 1 kHz

signal

≤ 4 V

SCART Outputs

outSC

OUTSC

SCtoSC

rSCtoSC

outSC

SCART Output Resistance SCn_OUT_s

Deviation of DC-Level at SCART Output from AGNDC Voltage

Gain from Analog Input to SCART Output

SCn_IN_s,

MONO_IN

→ Frequency Response from Analog

SCn_OUT_s Input to SCART Output

Signal Level at SCART Output

SCn_OUT_s (AHVSUP = 8 V)

Signal Level at SCART Output (AHVSUP = 5V)

“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”

= 1 kHz, I = 0.1 mA

signal

200 200

330 460

500

Ω Ω

= 27 °C

= 0 to 70 °C

−70 +70 mV

−1.0 +0.5 dB f

signal

= 1 kHz

−0.5 +0.5 dB with resp. to 1 kHz Bandwidth: 0 to 20000 Hz

1.8 1.9 2.0 V

RMS

= 1 kHz

signal

Volume 0 dB Full Scale input from I

1.17 1.27 1.37 V

RMS

68 Micronas

Page 69

PRELIMINARY DATA SHEET MSP 34x0G

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

Main and AUX Outputs

outMA

outDCMA

Main/AUX Output Resistance DACp_s

DC-Level at Main/AUX-Output (AHVSUP = 8 V)

2.1

3.3 4.6

5.0

kΩ kΩ

1.80 2.04612.28 V mV

= 1 kHz, I = 0.1 mA

signal

= 27 °C

= 0 to 70 °C

Volume 0 dB Volume −30 dB

outMA

DC-Level at Main/AUX-Output (AHVSUP = 5 V)

Signal Level at Main/AUX-Output (AHVSUP = 8 V)

1.12 1.36401.60 V

1.23 1.37 1.51 V

RMS

Volume 0 dB Volume −30 dB

= 1 kHz

signal

Volume 0 dB

Full scale input from I Signal Level at Main/AUX-Output (AHVSUP = 5 V)

“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”

0.76 0.90 1.04 V

RMS

4.6.3.7. Sound IF Inputs

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

IFIN

VREFTOP

ANA_IN

XTALK BW

Input Impedance ANA_IN1+,

ANA_IN2+,

1.5

6.8

ANA_IN− DC Voltage at VREFTOP VREFTOP 2.45 2.65 2.75 V DC Voltage on IF Inputs ANA_IN1+,

1.3 1.5 1.7 V ANA_IN2+, ANA_IN−

Crosstalk Attenuation ANA_IN1+,

ANA_IN2+,

3 dB Bandwidth 10 MHz

ANA_IN−

40 dB f

9.1

2.5

11.4kΩkΩ

Gain AGC = 20 dB Gain AGC = 3 dB

= 1 MHz

signal

Input Level = −2 dBr

AGC AGC Step Width 0.85 dB

4.6.3.8. Power Supply Rejection

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

PSRR: Rejection of Noise on AHVSUP at 1 kHz

PSRR AGNDC AGNDC 80 dB

From Analog Input to I

From Analog Input to SCART Output

From I

S Input to SCART Output SCn_OUT_s

S Input to MAIN or AUX

From I Output

“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”

S Output MONO_IN,

SCn_IN_s MONO_IN,

SCn_IN_s SCn_OUT_s

DACp_s

70 dB

60 dB 80 dB

Micronas 69

Page 70

MSP 34x0G PRELIMINARY DATA SHEET

4.6.3.9. Analog Performance

Symbol Parameter Pi n Na m e Min. Typ. Max. Unit Test Condit ions

Specifications for AHVSUP = 8 V

SNR Signal-to-Noise Ratio

from Analog Input to I

S Output MONO_IN,

SCn_IN_s

85 88 dB Input Level = −20 dB with

resp. to V unweighted

AICL

, f

sig

= 1 kHz,

20 Hz ...16 kHz

from Analog Input to SCART Output

from I

S Input to SCART Output SCn_OUT_s

from I

S Input to Main/AUX-Output

MONO_IN, SCn_IN_s

→ SCn_OUT_s

DACp_s

for Analog Volume at 0 dB for Analog Volume at −30 dB

THD Total Harmonic Distortion

from Analog Input to I

from Analog Input to SCART Output

from I

S Input to SCART Output SCn_OUT_s

from I

S Input to Main or AUX Out-

put

“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”

S Output MONO_IN,

SCn_IN_s

MONO_IN, SCn_IN_s → SCn_OUT_s

DACA_s, DACM_s

93 96 dB Input Level = −20 dB,

= 1 kHz,

sig

unweighted 20 Hz ...20 kHz

85 88 dB Input Level = −20 dB,

= 1 kHz,

sig

unweighted 20 Hz ...16 kHz

Input Level = −20 dB, 85 78

88 83

dB dB

= 1 kHz,

sig

unweighted

20 Hz ...16 kHz

0.01 0.03 % Input Level = −3 dBr with resp. to V unweighted

AICL

, f

sig

= 1 kHz,

20 Hz ...16 kHz

0.01 0.03 % Input Level = −3 dBr, f

= 1 kHz,

sig

unweighted 20 Hz ...20 kHz

0.01 0.03 % Input Level = −3 dBr, f

= 1 kHz,

sig

unweighted 20 Hz ...16 kHz

0.01 0.03 % Input Level = −3 dBr, f

= 1 kHz,

sig

unweighted 20 Hz ...16 kHz

70 Micronas

Page 71

PRELIMINARY DATA SHEET MSP 34x0G

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

Specifications for AHVSUP = 5 V

SNR Signal-to-Noise Ratio

from Analog Input to I

S Output MONO_IN,

SCn_IN_s

82 85 dB Input Level = −20 dB with

resp. to V unweighted

AICL

, f

sig

= 1 kHz,

20 Hz ...16 kHz

from Analog Input to SCART Output

from I

S Input to SCART Output SCn_OUT_s

from I

S Input to Main/AUX-Output

MONO_IN, SCn_IN_s

→ SCn_OUT_s

DACp_s

for Analog Volume at 0 dB for Analog Volume at −30 dB

THD Total Harmonic Distortion

from Analog Input to I

from Analog Input to SCART Output

from I

S Input to SCART Output SCn_OUT_s

from I

S Input to Main or AUX Out-

put

“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”

S Output MONO_IN,

SCn_IN_s

MONO_IN, SCn_IN_s → SCn_OUT_s

DACA_s, DACM_s

90 93 dB Input Level = −20 dB,

= 1 kHz,

sig

unweighted 20 Hz ...20 kHz

82 85 dB Input Level = −20 dB,

= 1 kHz,

sig

unweighted 20 Hz ...16 kHz

Input Level = −20 dB, 82 75

85 80

dB dB

= 1 kHz,

sig

unweighted

20 Hz ...16 kHz

0.03 0.1 % Input Level = −3 dBr with resp. to V unweighted

AICL

, f

sig

= 1 kHz,

20 Hz ...16 kHz

0.1 % Input Level = −3 dBr, f

= 1 kHz,

sig

unweighted 20 Hz ...20 kHz

0.1 % Input Level = −3 dBr, f

= 1 kHz,

sig

unweighted 20 Hz ...16 kHz

0.1 % Input Level = −3 dBr, f

= 1 kHz,

sig

unweighted 20 Hz ...16 kHz

Micronas 71

Page 72

MSP 34x0G PRELIMINARY DATA SHEET

Symbol Parameter Pi n Na m e Min. Typ. Max. Unit Test Condit ions

CROSSTALK Specifications for AHVSUP = 8 V and 5 V

XTAL K Crosstalk Attenuation

− PLCC68

− PSDIP64

between left and right channel within SCART Input/Output pair (L→R, R→L)

SCn_IN → SCn_OUT

SC1_IN or SC2_IN → I

SC3_IN → I

S Input → SCn_OUT

S Output PLCC68

between left and right channel within Main or AUX Output pair

S Input → DACp

between SCART Input/Output pairs D = disturbing program

O = observed program D: MONO/SCn_IN → SCn_OUT PLCC68

O: MONO/SCn_IN → SCn_OUT D: MONO/SCn_IN → SCn_OUT or unsel. PLCC68

O: MONO/SCn_IN → I D: MONO/SCn_IN → SCn_OUT PLCC68

O: I

S Input → SCn_OUT

D: MONO/SCn_IN → unselected PLCC68

O: I

S Input → SC1_OUT

PLCC68

PSDIP64

S Output PLCC68

PSDIP64

PLCC68

PSDIP64

PLCC68

PSDIP648075

S Output PSDIP64

PSDIP64

80 80

100 100

100 95

100 100

dB dB

Input Level = −3 dB, f

= 1 kHz, unused ana-

sig

log inputs connected to ground by Z < 1 kΩ

unweighted 20 Hz ...20 kHz

unweighted 20 Hz ...16 kHz

(unweighted 20 Hz ...20 kHz same signal source on left and right disturbing channel, effect on each observed output channel

Crosstalk between Main and AUX Output pairs

S Input → DACp

PLCC68

PSDIP649590

XTALK Crosstalk from Main or AUX Output to SCART Output

and vice versa

D = disturbing program O = observed program

D: MONO/SCn_IN/DSP → SCn_OUT PLCC68

O: I

S Input → DACp

D: MONO/SCn_IN/DSP → SCn_OUT PLCC68

O: I

S Input → DACp

D: I

S Input → DACp PLCC68

O: MONO/SCn_IN → SCn_OUT

S Input → DACM PLCC68

D: I

O: I

S Input → SCn_OUT

“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “M” or “A”

PSDIP64

85 80

90 85

100 95

dB dB

(unweighted 20 Hz ...16 kHz) same signal source on left and right disturbing channel, effect on each observed output channel

(unweighted 20 Hz ...20 kHz) same signal source on left and right disturbing channel, effect on each observed output channel

SCART output load resistance 10 kΩ

SCART output load resistance 30 kΩ

72 Micronas

Page 73

PRELIMINARY DATA SHEET MSP 34x0G

4.6.3.10. Sound Standard Dependent Characteristics

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

NICAM Characteristics (MSP Standard Code = 8)

NICAMOUT

S/N

NICAM

THD

BER fR

NICAM

XTALK SEP

NICAM

Tolerance of Output Voltage of NICAM Baseband Signal

S/N of NICAM Baseband Signal 72 dB NICAM: −6 dB, 1 kHz, RMS

Total Harmonic Distortion + Noise of NICAM Baseband Signal

NICAM: Bit Error Rate 1 10 NICAM Frequency Response ,

20...15000 Hz NICAM Crosstalk Attenuation (Dual ) 80 dB NICAM Channel Separation (St ereo) 80 dB

FM Characteristics (MSP Standard Code = 3)

S/N THD

FMOUT

Tolerance of Output Voltage of FM Demodulated Signal

S/N of FM Demodulated Signal 73 dB 1 FM-carrier 5.5 MHz, 50 µs, Total Harmonic Distortion + Noise

of FM Demodulated Signal

DACp_s SCn_OUT_s

DACp_s, SCn_OUT_s

−1.5 +1.5 dB 2.12 kHz, Modulator input

level = 0 dBref

unweighted 0 to 15 kHz, Vol = 9 dB NIC_Presc = 7F Output level 1 V DACp_s

0.1 % 2.12 kHz, Modulator input

level = 0 dBref

−7

FM+NICAM, norm conditions

−1.0 +1.0 dB Modulator input level = −12 dB dBref; RMS

−1.5 +1.5 dB 1 FM-carrier, 50 µs, 1 kHz,

40 kHz deviation; RMS

1 kHz, 40 kHz deviation;

0.1 %

RMS, unweighted 0 to 15 kHz (for S/N); full input range, FM-Prescale = 46 → Output Level 1 V

hex

DACp_s

hex

RMS

, V o l= 0 dB

RMS

XTALK

SEP

FM Frequency Responses,

20...15000 Hz

FM Crosstalk Attenuation (Dual) 80 dB 2 FM-carriers 5.5/5.74 MHz,

FM Channel Separation (Stereo) 50 dB 2 FM-carriers 5.5/5.74 MHz,

AM Characteristics (MSP Standard Code = 9)

S/N

AM(1)

S/N

AM(2)

THD

“n” means “1” or “2”; “s” means “L” or “R”; “p” means “M” or “A”

S/N of AM Demodulated Signal measurement condition: RMS/Flat

S/N of AM Demodulated Signal measurement condition: QP/CCIR

Total Harmonic Distortion + Noise of AM Demodulated Signal

AM Frequency Response

50...12000 Hz

DACp_s, SCn_OUT_s

−1.0 +1.0 dB 1 FM-carrier 5.5 MHz, 50 µs, Modulator input level = −14.6 dBref; RMS

50 µs, 1 kHz, 40 kHz deviation; Bandpass 1 kHz

50 µs, 1 kHz, 40 kHz deviation; RMS

55 dB S IF level: 0.1−0.8 V

AM-carrier 54% at 6.5 MHz Vol = 0 dB, FM/AM

45 dB

prescaler set for output = 0.5 V Loudspeaker out;

0.6 %

Standard Code = 09 no video/chroma components

−2.5 +1.0 dB

RMS

hex

Micronas 73

Page 74

MSP 34x0G PRELIMINARY DATA SHEET

Symbol Parameter Pi n Na m e Min. Typ. Max. Unit Test Conditions

BTSC Characteristics (MSP Standard Code = 20

S/N

BTSC

S/N of BTSC Stereo Signal S/N of BTSC-SAP Signal

THD

BTSC

THD+N of BTSC Stereo Signal THD+N of BTSC SAP Signal

DBX

Frequency Response of BTSC Stereo, 50 Hz...12 kHz

Frequency Response of BTSCSAP, 50 Hz...9 kHz

MNR

Frequency Response of BTSC Stereo, 50 Hz...12 kHz

Frequency Response of BTSCSAP, 50 Hz...9 kHz

XTALK

BTSC

Stereo → SAP SAP → Stereo

SEP

DBX

Stereo Separation DBX NR 50 Hz...10 kHz 50 Hz...12 kHz

, 21

hex

DACp_s, SCn_OUT_s

)

dB dB

1 kHz L or R or SAP, 100% modulation, 75

µs deempha-

sis, RMS unweighted 0 to 15 kHz

0.1

0.5

% %

1 kHz L or R or SAP, 100% 75 µs EIM

, DBX NR or MNR, RMS unweighted 0 to 15 k Hz

−1.0

1.0

L or R or SAP, 1%...66% EIM

, DBX NR

−2.0 2.0 dB L or R 5%...66% EIM2), MNR

−2.0 2.0 dB SAP, white noise, 10% Modu-

lation, MNR

76 80

35 30

dB dB

1 kHz L or R or SAP, 100% modulation, 75 µs deemphasis, Bandpass 1 kHz

L or R 1%...66% EIM

, DBX

SEP

MNR

pil

Pilot

“n” means “1” or “2”; “s” means “L” or “R”; “p” means “M” or “A”

EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation,

Stereo Separation MNR 30 dB L = 300 Hz, R = 3.1 kHz

14% Modulation, MNR

Pilot deviation threshold Stereo off → on Stereo on → off

ANA_IN1+, ANA_IN2+

3.2

1.2

3.5

1.5

kHz kHz

4.5 MHz carrier modulated with f

= 15.734 kHz

SIF level = 100 mV indication: STATUS Bit[6]

Pilot Frequency Range 15.563 15.843 kHz standard BTSC stereo signal,

sound carrier only

when the DBX encoding process is replaced by a 75-µs preemphasis network.

74 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

BTSC Characteristics (MSP Standard Code = 20 with a minimum IF input signal level of 70 mVpp (measured without any video/chroma signal components)

S/N

BTSC

S/N of BTSC Stereo Signal S/N of BTSC-SAP Signal

THD

BTSC

THD+N of BTSC Stereo Signal THD+N of BTSC SAP Signal

DBX

Frequency Response of BTSC Stereo, 50 Hz...12 kHz

Frequency Response of BTSC-

, 21

hex

DACp_s, SCn_OUT_s

)

0.15

0.8

−1.0

1.0

dB dB

% %

SAP, 50 Hz...9 kHz

MNR

Frequency Response of BTSC Stereo, 50 Hz...12 kHz

Frequency Response of BTSC-

−2.0 2.0 dB L or R 5%...66% EIM2), MNR

−2.0 2.0 dB SAP, white noise, 10% Modu-

SAP, 50 Hz...9 kHz

XTALK

SEP

DBX

BTSC

Stereo → SAP SAP → Stereo

Stereo Separation DBX NR 50 Hz...10 kHz 50 Hz...12 kHz

75 75

35 30

dB dB

1 kHz L or R or SAP, 100% modulation, 75

µs deempha-

sis, RMS unweighted 0 to 15 kHz

1 kHz L or R or SAP, 100% 75 µs EIM

, DBX NR or MNR, RMS unweighted 0 to 15 kHz

L or R or SAP, 1%...66% EIM

, DBX NR

lation, MNR 1 kHz L or R or SAP, 100%

modulation, 75 µs deemphasis, Bandpass 1 kHz

L or R 1%...66% EIM

, DBX

SEP

MNR

“n” means “1” or “2”; “s” means “L” or “R”; “p” means “M” or “A”

EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation,

Stereo Separation MNR 30 dB L = 300 Hz, R = 3.1 kHz

14% Modulation, MNR

when the DBX encoding process is replaced by a 75-µs preemphasis network.

Micronas 75

Page 76

MSP 34x0G PRELIMINARY DATA SHEET

Symbol Parameter Pi n Na m e Min. Typ. Max. Unit Test Conditions

EIA-J Characteristics (MSP Standard Code = 30

S/N

EIAJ

S/N of EIA-J Stereo Signal

hex

S/N of EIA-J Sub-Channel

THD

EIAJ

THD+N of EIA-J Stereo Signal THD+N of EIA-J Sub-Channel

EIAJ

Frequency Response of EIA-J Stereo, 50 Hz...12 kHz

Frequency Response of EIA-J Sub-Channel, 50 Hz...12 kHz

XTALK

EIAJ

Main → SUB Sub → MAIN

SEP

EIAJ

Stereo Separation 50 Hz...5 kHz 50 Hz...10 kHz

FM-Radio Characteristics (MSP Standard Code = 40

S/N THD

UKW

S/N of FM-Radio Stereo Signal DACp_s, THD+N of FM-Radio Stereo Signal 0.1 %

Frequency Response of FM-Radio Stereo 50 Hz...15 kHz −1.0 +0.5 dB

)

DACp_s, SCn_OUT_s

)

hex

SCn_OUT_s

0.2

0.3

−0.5

1.0

dB dB

% %

1 kHz L or R, 100% modulation, 75 µs deemphasis, RMS unweighted 0 to 15 kHz

100% modulation, 75 µs deemphasis

−1.0

66 80

1.0

dB dB

1 kHz L or R, 100% modulation, 75 µs deemphasis, Bandpass 1 kHz

EIA-J Stereo Signal, L or R 35 28

68 dB 1 kHz L or R, 100% modula-

dB dB

100% modulation

tion, 75 µs deemphasis, RMS

unweighted

0 to 15 kHz

L or R, 1%...100% modula-

tion, 75 µs deemphasis

SEP

UKW

Pilot

“n” means “1” or “2”; “s” means “L” or “R”; “p” means “M” or “A”

Stereo Separation 50 Hz...15 kHz 45 dB Pilot Frequency Range ANA_IN1+

ANA_IN2+

18.844 19.125 kHz standard FM radio

stereo signal

76 Micronas

Page 77

PRELIMINARY DATA SHEET MSP 34x0G

5. Appendix A: Overview of TV-Sound Standards

5.1. NICAM 728

Table 5–1: Summary of NICAM 728 sound modulation parameters

Specification I B/G L D/K

Carrier frequency of digital sound

Transmission rate 728 kbit/s Type of modulation Differentially encoded quadrature phase shift keying (DQPSK) Spectrum shaping

Roll-off factor

Carrier frequency of analog sound component

Power ratio between vision carrier and analog sound carrier

Power ratio between analog and modulated digital sound carrier

6.552 MHz 5.85 MHz 5.85 MHz 5.85 MHz

by means of Roll-off filters

1.0 0.4 0.4 0.4

6.0 MHz FM mono

10 dB 13 dB 10 dB 16 dB 13 dB

10 dB 7 dB 17 dB 11 dB China/

5.5 MHz FM mono

6.5 MHz AM mono 6.5 MHz FM mono

terrestrial cable

Hungary 12 dB 7 dB

Poland

Table 5–2: Summary of NICAM 728 sound coding characteristics

Characteristics Values

Audio sampling frequency 32 kHz Number of channels 2 Initial resolution 14 bit/sample Companding characteristics near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks Coding for compressed samples 2’s complement Preemphasis CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz) Audio overload level +12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz)

Micronas 77

Page 78

MSP 34x0G PRELIMINARY DATA SHEET

5.2. A2-Systems

Table 5–3: Key parameters for A2 Systems of Standards B/G, D/K, and M

Characteristics Sound Carrier FM1 Sound Carrier FM2

TV-Sound Standard Carrier frequency in MHz 5.5 6.5 4.5 5.7421875 6.2578125

Vision/sound power difference 13 dB 20 dB Sound bandwidth 40 Hz to 15 kHz Preemphasis 50 µs75 µs50 µs75 µs Frequency deviation (nom/max) ±27/±50 kHz ±17/±25 kHz ±27/±50 kHz ±15/±25 kHz

Transmission Modes

Mono transmission mono mono Stereo transmissio n (L+R)/2 (L+R)/2 R (L−R)/2 Dual sound transmission language A language B

Identification of Transmission Mode

Pilot carrier frequency 54.6875 kHz 55.0699 kHz Max. deviation portion Type of modulation / modulation depth AM / 50%

B/G D/K M B/G D/K M

4.724212

6.7421875

5.7421875

±2.5 kHz

Modulation frequency mono: unmodulated

stereo: 117.5 Hz dual: 274.1 Hz

149.9 Hz

276.0 Hz

78 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

5.3. BTSC-Sound System

Table 5–4: Key parameters for BTSC-Sound Systems

Aural

BTSC-MPX-Components

Carrier

(L+R) Pilot (L−R) SAP Prof. Ch.

Carrier frequency (f (f

= 15.734 kHz)

hNTSC

= 15.625 kHz)

hPAL

4.5 MHz Baseband f

2 f

5 f

6.5 f

Sound bandwidth in kHz 0.05 - 15 0.05 - 15 0.05 - 12 0.05 - 3.4 Preemphasis 75 µs DBX DBX 150 µs

Max. deviation to Aural Carrier 73 kHz

25 kHz

5kHz 50kHz1) 15 kHz 3 kHz

(total)

Max. Freq. Deviation of Subcarrier Modulation Type AM

Sum does not exceed 50 kHz due to interleaving effects

10 kHz FM

3kHz FM

5.4. Japanese FM Stereo System (EIA-J)

Table 5–5: Key parameters for Japanese FM-Stereo Sound System EIA-J

Aural

EIA-J-MPX-Components

Carrier

(L+R) (L−R) Identification

3.5 f

Carrier frequency (f

= 15.734 kHz) 4.5 MHz Baseband 2 f

Sound bandwidth 0.05 - 15 kHz 0.05 - 15 kHz − Preemphasis 75 µs75µs none Max. deviation portion to Aural Carrier 47 kHz 25 kHz 20 kHz 2 kHz Max. Freq. Deviation of Subcarrier

Modulation Type

10 kHz FM

60%

AM Transmitter-sided delay 20 µs0 µs0 µs Mono transmission L+R − unmodulated Stereo tran smission L+RL−R 982.5 Hz Bilingual transmission Language A Language B 922.5 Hz

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MSP 34x0G PRELIMINARY DATA SHEET

5.5. FM Satellite Sound

Table 5–6: Key parameters for FM Satellite Sound

Carrier Frequency Maximum

FM Deviation

6.5 MHz 85 kHz Mono 15 kHz 50 µs

7.02/7.20 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive

7.38/7.56 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive

7.74/7.92 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive

Sound Mode Bandwidth Deemphasis

5.6. FM-Stereo Radio

Table 5–7: Key parameters for FM-Stereo Radio Systems

Aural Carrier

Carrier frequency (f Sound bandwidth inkHz 0.05 - 15 0.05 - 15

= 19 kHz) 10.7 MHz Baseband f

(L+R) Pilot (L−R) RDS/ARI

FM-Radio-MPX-Components

2 f

3 f

Preemphasis:

− USA

− Europe

Max. deviation to Aural Carr ier 75 kHz

(100%)

75 µs 50 µs

90% 10% 90% 5%

75 µs 50 µs

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PRELIMINARY DATA SHEET MSP 34x0G

6. Appendix B: Manual/Compatibility Mode

To adapt the modes of the STANDARD SELECT register to individual re quirements and for reasons o f com- patibility to the MSP 34x0D, the MSP 34x0G offers an Manual/Compatibility Mode, which pr ovides so phi sticated programming of the MSP 34x0G.

Using the STANDARD SELECT regi ster gene rally provides a more economic way to program the MSP 34x0G and will resul t in op timal behavior. There-

fore, it is not recommend to use the Manual/Compatibility mode. In those cases, where the

MSP 34x0D is to be substituted by the MSP 34x0G, the tips given in Sect ion 6 .10. on page 97 have to be obeyed by the controller software.

6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode

Table 6–1: Demodulator Write Registers; Subaddress: 10

Demodulator Write Registers

AUT O_FM/AM 00 21 3410,

A2_Threshold 00 22 all A2 Stereo Identification Threshold 00 19 CM_Threshold 00 24 all Carrier-Mute Threshold 00 2A AD_CV 00 BB all SIF-input selection, configuration of AGC, and Carrier-Mute Function 00 00 86 MODE_REG 00 83 3410,

Address (hex)

MSPVersion

3450

Description Reset

1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of

Automatic Switching between NICAM and FM/AM in case of bad NICAM reception

2. MODUS[0]=0 (Manual Mod e): Activation and configuration of Automatic Switching between NICAM and FM/AM in case of bad NICAM reception

Controlling of MSP-Demodulator and Interface options. As soon as this register is applied, the MSP 34x0G wor ks in the MSP 34x0D co mpatibility

mode. Warning: In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only

MSP 34x0D features are available; the use of MODUS and STATUS regis ter is not allowed.

The MSP 34x0G is reset to the normal mode by first programming the MODUS register followed by transmitting a valid standard code to the STANDARD SELECTION register.

; these registers are not readable!

hex

Mode

00 00 83

hex

00 00 87

Page

85 85

FIR1 FIR2

DCO1_LO DCO1_HI

DCO2_LO DCO2_HI

PLL_CAPS 00 1F Not of interest for the customer

Note: All registers except AUTO_FM/AM, A2_Threshold, and CM_Threshold are initialized during STANDARD SELECTION and are automatically updated when Automatic Sound Select (MODUS[0]=1) is on.

00 01 00 05

00 93 00 9B

00 A3 00 AB

FIR1-filter coefficients channel 1 (6 ⋅ 8 bit) FIR2-filter coefficients channel 2 (6 ⋅ 8 bit), + 3 ⋅ 8 bit offset (total 72 bit)

Increment channel 1 Low Part Increment channel 1 High Part

Increment channel 2 Low Part Increment channel 2 High Part

Switchable PLL capacitors to tune open-loop frequency

00 00 89

00 56 92

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MSP 34x0G PRELIMINARY DATA SHEET

Table 6–2: Demodulator Read Registers; Subaddress: 11

Demodulator Read Registers

C_AD_BITS 00 23 3410, ADD_BITS 00 38 NICAM: bit [10:3] of additional data bits 91 CIB_BITS 00 3E NICAM: CIB1 and CIB2 control bits 91 ERROR_RATE 00 57 NICAM error rate, updated with 182ms 92 PLL_CAPS 02 1F Not for customer use 92 AGC_GAIN 02 1E Not for customer use 92

Address (hex)

MSPVersion

3450

Description Page

NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits 91

; these registers are not writable!

hex

6.2. DSP Write and Read Registers for Manual/Compatibility Mode

Table 6–3: DSP-Write Registers; Subaddress: 12

Write Register Address

(hex)

Bits Operational Modes and Adjustable Range Reset

, all registers are readable as well

hex

Mode

Page

Volume SCART1 channel: Ctrl. mode 00 07 [7:0] [Linear mode / logarithmic mode] 00 FM Fixed Deemphasis 00 0F [15:8] [50 µs, 75 µs, J17, OFF] 50 µs93 FM Adaptive Deemphasis [7:0] [OFF, WP1] OFF 93 Identification Mode 00 15 [7:0] [B/G, M] B/G 94 FM DC Notch 00 17 [7:0] [ON, OFF] ON 94 Volume SCART2 channel: Ctrl. mode 00 40 [7:0] [Linear mode / logarithmic mode] 00

Table 6–4: DSP Read Registers; Subaddress: 13

Additional Read Registers Address

Stereo detection register for A2 Stereo Systems

DC level readout FM1/Ch2-L 00 1B [15:0] [8000 DC level readout FM2/Ch1-R 00 1C [15:0] [8000

(hex)

00 18 [15:8] [80

Bits Output Range Page

, all registers are not wr itable

hex

... 7F

hex

] 8 bit two’s co mp lemen t 94

hex

... 7FFF

hex

... 7FFF

hex

] 16 bit two’s complement 94

hex

] 16 bit two’s complement 94

hex

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PRELIMINARY DATA SHEET MSP 34x0G

6.3. Manual/Compatibility Mode: Description of Demodulator Write Registers

6.3.1. Automatic Switching between NICAM and

Analog Sound

In case of bad NICAM reception or loss of the NICAM-carrier, the MSP 34x0G offers an Automatic Switching (fall back) to the analog sound (FM/AMmono), without the necessity for the controller of reading and evaluating any parameters. If a proper NICAM signal retur ns, switching back to th is source is performed automatically as well. The feature evaluates the NICAM ERROR_RATE and switches, if necessary, all output channels which are assigned to the NICAM-source, to the analog source, and vice versa.

An appropriate hysteresis algorithm avoids oscillating effects (see Fig. 6–1). STATUS[9] and C_AD_BI TS[11] (Address: 0023

) provide informa ti on abo ut the actual

hex

NICAM-FM/AM-status.

Selected Sound

NICAM

analog sound

thresholdthreshold/2

ERROR_RATE

6.3.1.1. Function in Automatic Sound Select Mode

The Automatic Sound Select feature (MODUS[0]=1) includes the procedure mentioned above. By default, the internal ERROR_RATE threshold is set to 700

dec

. i.e.:

– NICAM → analog Sound if ERROR_RATE > 700 – analog Sound → NICAM if ERROR_RATE < 700/2

The ERROR_RATE value of 700 corresponds to a BER of approximately 5.46*10

-3

/s.

Individual configuration of the threshold can be done using Table 6–5. However, the inter nal setting used by the standard selection is recommended.

The optimum NICAM sound can be assigned to the MSP output chan nels by selecting one of the “Stereo or A/B”, “Stereo or A”, or “Stereo or B” source channels

6.3.1.2. Function in Manual Mode

If the manual mode (MODUS[0]=0) is required, the activation and configuration of the Automatic Switching feature has to be done as described in Table 6–6. Note that the channel matrix of the corresponding output-channels must be set according to the NICAM-mode and need no t to be changed in the FM/ AM-fallback case.

Fig. 6–1: Hysteresis for Automatic Switching

Example:

Required threshold = 500: bits[10:1] = 00 1111 1010

Table 6–5: Coding of Automatic NICAM/Analog Sound Switching;

Automatic Sound Select is on (MODUS[0] = 1)

Mode Description AUTO_FM [11:0]

1 Default

2 Autom atic Switching with

3 Forced Analog Mono bit[11] = 1

The NICAM path may be assigned to “Stereo or A/B”, “Stereo or A”, or “Stereo or B” source channels (see Table 2–2 on page 11).

Automatic Switching with

internal threshold

external threshold

(Customizing of Automatic Sound Select)

Addr. = 00 21

bit[11:0] = 0 700 NICAM or FM/AM,

bit[11] = 0 bit[10:1] = 25...1000

bit[0] = 1

bit[10:1] = ignored bit[0] = 1

hex

= threshold/2

ERROR_RATEThreshold/dec

set by customer; recommended range: 50...2000

Source Select: Input at NICAM Path

depending on ERROR_RATE

always FM/AM

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MSP 34x0G PRELIMINARY DATA SHEET

Table 6–6: Coding of Automati c NICA M/Anal og Sou nd Swi tc hin g;

Automatic Sound Select is off (MODUS[0] = 0)

Mode Description AUTO_FM [11:0]

0 reset status

1 Automatic Switching with

2 Automatic Switching with

3 Forced Analog Mono

Forced NICAM (Automatic Switching disabled)

internal threshold (Default, if Automatic Sound Select is on)

external threshold (Customizing of Automatic Sound Select)

(Automatic Switching disabled)

Addr. = 00 21

bit[11] = 0 bit[10:1] = 0 bit[0] = 0

bit[11] = 0 bit[10:1] = 0 bit[0] = 1

bit[11] = 0 bit[10:1] = 25...1000

bit[0] = 1 bit[11] = 1

bit[10:1] = 0 bit[0] = 1

hex

= threshold/2

ERROR_RATEThreshold/dec

none always NICAM; Mute in

700 NICAM or FM/AM,

set by customer; recommended range: 50...2000

none always FM/AM

Source Select: Input at NICAM Path

case of no NICAM available

depending on ERROR_RATE

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PRELIMINARY DATA SHEET MSP 34x0G

6.3.2. A2 Threshold

The threshold between Stereo/Bilingual and Mono Identification for the A2 Standard ha s been made programmable according to the user’s preferences. An internal hysteresis ensures robustness and stability

Table 6–7: Write Register on I

Function Name

C Subaddress 10

: A2 Threshold

hex

Address THRESHOLDS

00 22

(write) A2 THRESHOLD Register

hex

Defines threshold of all A2 and EIA_J standards for Stereo and Bilingual detection

bit[15:0] 07F0

force Mono Identification

hex

... 0190

default setting after reset

hex

... 00A0

recommended range : 00A0

minimum Threshold for stable detection

hex

...03C0

A2_THRESH

hex

6.3.3. Carrier-Mute Threshold

The Carrier-Mut e threshold has been m ade programmable according to the user’s preferences. An inter nal hysteresis ensures stable behavior.

Table 6–8: Write Register on I2C Subaddress 10

Function Name

: Carrier-Mute Threshold

hex

Address THRESHOLDS

00 24

(write) Carrier-Mute THRESHOLD Register

hex

Defines threshold for the carrier mute feature bit[15:0] 0000

Carrier-Mute always ON (both channels muted)

hex

... 002A

default setting after reset

hex

... 07FF

Carrier-Mute always OFF

hex

(both channels forced on)

recommended range : 0014

hex

...0050

CM_THRESH

hex

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6.3.4. Regist er AD_CV

The use of this register is no longer recommended. Use it only in cases where compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with th e MODUS register provides a more economic way to program the MSP 34x0G.

Table 6–9: AD_CV Register; reset status: all bits are “0”

AD_CV

hex

)

(00 BB

Bit Function Settings 2-8, 0A-60

Automatic setting by STANDARD SELECT Register

hex

[0] not used must be set to 0 0 0 [1:6] Reference level in case of Automatic Gain

101000 100011 Control = on (see Table 6–10). Constant gain factor when Automatic Gain Control = off (see Table 6–11).

[7] Determination of Automatic Gain or

Constant Gain

[8] Selection of Sound IF source

(identical to MODUS[8])

[9] MSP-Carrier-Mute Feature 0 = off: no mute

0 = constant gain 1 = automatic gain

0 = ANA_IN1+ 1 = ANA_IN2+

1 = on: mute as de-

scribed in section 2.2.2. [10:15] not used must be set to 0 0 0 X : not affected while choosing the TV sound standard by means of the STANDARD SELECT Register

Note: This register is initialized during STANDARD SELECTION and is automatically updated when Automatic Sound Select (MODUS[0]=1) is on.

Table 6–10: Reference Values for Active AGC (AD_CV[7] = 1)

Application Input Signal Contains AD_CV [6:1]

Ref. Value

Terrestrial TV

− FM Standards

− NICAM/FM

− NICAM/AM

− NICAM only

1 or 2 FM Carriers 1 FM and 1 NICAM Carrier 1 AM and 1 NICAM Carrier

1 NICAM Carrier only

101000 101000 100011

010100

SAT 1 or more FM Carriers 100011 35 0.10 − 3 V ADR FM and ADR carriers see DRP 3510A data sheet

For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the robustness of the internal processing, the IC works up to and even more than 3 V FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear.

AD_CV [6:1] in integer

40 40 35

Range of Input Signal at pin ANA_IN1+ and ANA_IN2+

0.10 − 3 V

0.10 − 1.4 V

pp pp

(recommended: 0.10 − 0.8Vpp)

0.05 − 1.0 V

, if norm conditions of FM/NICAM or

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PRELIMINARY DATA SHEET MSP 34x0G

Table 6–11: AD_CV parameters for Constant Input Gain (AD_CV[7]=0)

Step AD_CV [6:1]

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result. Due to the robustness of the internal processing, the IC works up to and even more than 3 V FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear.

Constant Gain

000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100

Gain Input Level at pin ANA_IN1+ and ANA_IN2+

3.00 dB

3.85 dB

4.70 dB

5.55 dB

6.40 dB

7.25 dB

8.10 dB

8.95 dB

9.80 dB

10.65 dB

11.50 dB

12.35 dB

13.20 dB

14.05 dB

14.90 dB

15.75 dB

16.60 dB

17.45 dB

18.30 dB

19.15 dB

20.00 dB

maximum input level: 3 V

maximum input level: 0.14 V

, if norm conditions of FM/NICAM or

(FM) or 1 Vpp (NICAM)

6.3.5. Register MODE_REG Note: The use of this register is no longer recom-

mended. It should be used on ly in cases where software compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS register provides a more economic way to program the MSP 34x0G.

As soon as this register is applied, the MSP 34x0G works in the MSP 34x0D Manual/Compatibility

Mode. In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only MSP 34x0D features are available; the

use of MODUS and STATUS register is not allowed. The MSP 34x0G is rese t to the normal mode by first programming the MODUS register, followed by transmitting a valid standard code to the STANDARD SELECTION register.

The register ‘MODE_REG’ contains the control bits determining th e operation mode of the MSP 34x0G in the MSP 34x0D Manual/Compatibi lity Mode; Table 6– 12 explains all bit positions.

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MSP 34x0G PRELIMINARY DATA SHEET

Table 6–12: Control word ‘MODE_REG’; reset status: all bits are “0”

MODE_REG 00 83

hex

Automatic setting by STANDARD SELECT Register

Bit Function Comment Definition 2 - 5 8, A, B 9

[0] not used 0 : must be used 0 0 0 [1] DCTR_TRI Digital control out

0/1 tri-state

[2] I

S_TRI I2S outputs tri-state

(I2S_CL, I2S_WS,

0 : active 1 : tri-s tate

XXX

I2S_DA_OUT)

[3] I

[4] I

S Mode

S_WS Mode WS due to the Sony or

[5] Audio_CL_OUT Switch

Master/Slave mode

of the I

S bus

Philips-Format

Audio_Clock_Output

0 : Master 1 : Slave

0 : Sony 1 : Philips

0 : on 1 : tri-s tate

XXX

to tri-state

[6] NICAM

Mode of MSP-Ch1 0 : FM

011

1 : Nicam [7] not used 0 : must be used 0 0 0 [8] FM AM Mode of MSP-Ch2 0 : FM

001

1 : AM [9] HDEV High Dev iat ion Mode

(channel matrix m ust b e

0 : normal

1 : high deviation mode

000

sound A) [11:10] not used 0 : must be used 0 0 0 [12] MSP-Ch1 Gain see also Table 6–14 0 : Gain = 6 dB

000

1 : Gain = 0 dB

[13] FIR1-Filter

Coeff. Set

[14] ADR Mode of MSP Ch1/

[15] AM-Gain Gain for AM

NICAM and I2S-Master mode are not allowed simultaneously X: not affected by

6.4. Manual/Compatibility Mode: Description of Demodulator Read Registers

Note: The use of these register is no longer recom-

mended. It should be used on ly in cases where software compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the STATUS register provides a more economic way to program the MSP 34x0G and to retr ieve information from the IC.

All registers except C_AD_ BITs are 8 bits wide. They can be read out of the RAM of the MSP 34x0G if the MSP 34x0D Manual/Compatibility Mode is required.

All transmissions take place in 16-bit words. The valid 8-bit data are the 8 LSBs of the received data word.

If the Automatic Sound Selec t feature is not used, the NICAM or FM-identi fication parameters must be re ad and evaluated by the controller in order to enable appropriate switching of the channel select matrix of the baseband processing part. The FM-identification registers are desc ribed in s ection 6.6.1 . To handle the NICAM-sound and to observe the NICAM-quality, at least the registers C_AD_BITS and ERROR_RATE must be read and evaluated by the controller. Additional data bits and CIB bits, if supplie d by the NICAM transmitter, can be obtained by reading the registers ADD_BITS and CIB_BITS.

Table 6–16: NICAM operation modes as defined by the EBU NICAM 728 specification

C4 C3 C2 C1 Operation Mode

0 0 0 0 Stereo sound (NICAMA/B),

independent mono sound (FM1)

0 0 0 1 Two independent mono signals

(NICAMA, FM1)

0 0 1 0 Three independent mono channels

(NICAMA, NICA MB , FM1) 0 0 1 1 Data transmission only; no audio 1 0 0 0 Stereo sound (NICAMA/B), FM1

carries same channel 1 0 0 1 One mono signal (NICAMA). FM1

carries same channel as NICAMA 1 0 1 0 Tw o in dependent m ono chann els

(NICAMA, NICAMB). FM1 carries

same channel as NICAMA 1 0 1 1 Data transmission only; no audio x 1 x x Unimplemented sound coding

option (not yet defined by EBU

NICAM 728 specification) AUTO_FM: monitor bit for the AUTO_FM Status:

0: NICAM source is NICAM 1: NICAM source is FM

6.4.1. NICAM Mode Control/Additional Data Bits Register

NICAM operation mode cont rol bits and A[2:0] of the additional data bits.

Format:

MSB C_AD_BITS 00 23

11...76543210

Auto

... A[2] A[1] A[0] C4 C3 C2 C1 S

_FM

hex

LSB

Important: “S” = Bit[0] indicates correct NICAM-syn-

chronization (S = 1). If S = 0, the MSP 3410/3450G has not yet synchronized correctly to frame and sequence, or has lost synchroni zation. The remaining read registers a re therefore not valid. The MS P mutes the NICAM outpu t automatically and tr ies to synchronize again as long as MODE_REG[6] is set.

The operation mode is coded by C4-C1 as shown in Table 6–16.

Note: It is no longer necessary to read out and evaluate the C_AD_BITS. All evaluation is performed in the MSP and indicated in the STATUS register.

6.4.2. Additional Data Bits Register

Contains the remaining 8 of the 11 additional data bits. The additional data bits are not yet defined by the NICAM 728 system.

Format:

MSB ADD_BITS 00 38

76543210

A[10] A[9] A[8] A[7] A[ 6] A[5] A[4] A[3]

hex

LSB

6.4.3. CIB Bits Register

CIB bits 1 and 2 (see NICAM 728 specifications). Format:

MSB CIB_BITS 00 3E

76543210

hex

LSB

xxxxxxCIB1CIB2

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6.4.4. NICAM Error Rate Register

ERROR_RATE 00 57

Error free 0000 maximum error rate 07FF

hex

Average error rate of the NICAM reception in a time interval of 182 ms, which should be cl os e to 0. T he in itial and maximum value of ERROR_RATE is 2047. This value is also active if the NICAM bit of MODE_REG is not set . Since th e value is ac hieved by filtering, a certain transition time (approx. 0.5 sec) is unavoidable. Acceptable audio may have error rates up to a value of 700 int. Individual evaluation of this value by the controller and an appropriate threshold may define the fallback mode from NICAM to FM/ AM-Mono in case of poor NICAM reception.

The bit error rate per second (BE R) can be calcul ated by means of the following formula:

−6

BER = ERROR_RATE * 12.3*10

6.4.5. PLL_CAPS Readback Register

It is possible to read out the actual setting of the PLL_CAPS. In standard applications, this register is not of interest for the customer.

PLL_CAPS 02 1F

hex

6.4.7. Automatic Search Function for FM-Carrier Detection in Satellite Mode

The AM demodulation ability of the MSP 3410G and MSP 3450G offers the possibili ty to calc ulate the “field strength” of the momentarily selected FM carrier, which can be read ou t by the contro ller. In SAT rec eivers, this feature can be used to make automatic FM carrier sea r ch pos sible.

For this, the MSP has to be switched to AM-mode (MODE_REG[8]), FM-Prescale must be set to 7F

hex

= +127

, and the FM DC notch (see section

dec

6.5.7.) must be switched off. The sound-IF frequency

range must now be “scanned” in the MSP-channel 2 by means of the programmable quadrature mixer with an appropriate in cremental frequency (i.e. 10 kHz). After each incrementation, a fie ld strength value is available at the quasi-peak de tec tor output (quasi-peak de tec tor source must be set to F M), which must be examined for relative maxima by the controller. This results in either continuing sea rch or switching the MSP back to FM demodulation mode.

During the search p rocess, the FIR2 must be loaded with the coefficient set “AUTOSEARCH”, which enables small bandwidth, resulting in appr opriate field strength characteristics. The absolute field strength value (can be read out of “quasi-peak de tector output FM1”) also gives information on whether a main FM carrier or a subcarrier was detected; and as a practical consequence, the FM bandwidth (FIR1/2) and the deemphasis (50 µs or adaptive) can be switched accordingly.

minimum frequency 1111 1111 FF nominal frequency 0101 0110 56

RESET

maximum frequency 0000 0000 00

PLL_CAPS 02 1F

PLL open xxxx xxx0 PLL closed xxxx xxx1

hex

6.4.6. AGC_GAIN Readback Register

It is possible to read out the actual setting of AGC_GAIN in Automatic Gain Mode. In standard applications, this reg ister is not of in terest for the customer.

AGC_GAIN 02 1E

max. amplification (20 dB)

min. amplification (3 dB)

hex

0001 0100 14

0000 0000 00

hex

Due to the fact that a constant demodulation frequency offset of a few kHz leads to a DC level in the demodulated signal, further fine tun in g o f the found car r ie r ca n be achieved by evaluating the “DC Level Readout FM1”. Therefore, the FM DC Notch must be switched on, and the demodulator part must be switched back to FM-demodulation mode.

For a detailed description of the automatic search function, please refer to the correspon ding MSP Windows software.

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6.5. Manual/Compatibility Mode: Description of DSP Write Registers

6.5.1. Additional Channel Matrix Modes

Loudspeaker Matrix 00 08 Headphone Matrix 00 09 SCART1 Matrix 00 0A SCART2 Matrix 00 41 I2S Matrix 00 0B Quasi-Peak

Detector Matrix

00 0C

hex

SUM/DIFF 0100 0000 40 AB_XCHANGE 0101 0000 50 PHASE_CHANGE_B 0110 0000 60 PHASE_CHANGE_A 0111 0000 70 A_ONLY 1000 0000 80

L L L L L L

hex

6.5.2. Volume Mo des of SCART1/2 Outputs

Volume Mode SCART1 00 07 Volume Mode SCART2 00 40

linear 0000 0

logarithmic 0001 1

Linear Mode Volume SCART1 00 07 Volume SCART2 00 40

OFF 0000 0000 00

0dB gain (digital full scale (FS) to 2

output)

RMS

+6 dB gain (−6 dBFS to 2

output)

RMS

hex

RESET

hex

RESET 0100 0000 40

0111 1111 7F

[3:0] [3:0]

hex

H H

hex

B_ONLY 1001 0000 90

hex

This table shows additional modes for the channel matrix registers.

The sum/difference mode can be used together with the quasi-peak detector to deter mine the sound m aterial mode. If the difference signal on channe l B (right) is near to zero, and the sum signal on chann el A (left) is high, the incomi ng aud io si gna l i s mon o. If there is a significant level on the difference signa l, the incoming audio is stereo.

Note: SCART Volume linear mode will not be supporte d in the future (doc umented for compatibility r easons only).

6.5.3. FM Fixed Deemphasis

FM Deemphasis 00 0F

hex

50 µs 0000 0000 00

RESET 75 µs 0000 0001 01 J17 0000 0100 04 OFF 0011 1111 3F

hex

Note: This register is initialized during STANDARD SELECTION and is auto maticall y updated whe n Automatic Sound Select (MODUS[0]=1) is on.

6.5.4. FM Adaptive Deemphasis

FM Adaptive Deemphasis WP1

OFF 0000 0000 00

WP1 0011 1111 3F

00 0F

RESET

hex

Note: This register is initialized during STANDARD SELECTION and is auto maticall y updated whe n Automatic Sound Select (MODUS[0]=1) is on.

Micronas 93

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MSP 34x0G PRELIMINARY DATA SHEET

6.5.5. NICAM Deemphasis

A J17 Deemphasis is always applied to the NICAM signal. It is not switchable.

6.5.6. Identification Mode for A2 Stereo Systems

Identification Mode 00 15

Standard B/G (German Stereo)

Standard M (Korean Stereo)

Reset of Ident-Filter 0011 1111 3F

hex

0000 0000 00 RESET

0000 0001 01

hex

To shorten the response ti me of the i dent ifi ca tio n al gorithm after a program change between two FM-Stere o capable programs, the reset of the ident-filter can be applied.

Sequence:

1. Program change

6.6. Manual/Compatibility Mode: Description of DSP Read Registers

All readable registers are 16-bit wide. Transmissions

C bus have to take place in 16-bit words. Some of

via I the defined 16-bit words a re divided into low and hig h byte, thus holding two different control entities.

These registers are not writable.

6.6.1. Stereo Detection Register

for A2 Stereo Systems

Stereo Detection Register

Stereo Mode Reading

MONO near zero STEREO positive value (ideal

BILINGUAL negative value (ideal

00 18

hex

(two’s complement)

reception: 7F

reception: 80

hex

hex)

)

2. Reset ident-filter

3. Set identification mode back to standard B/G or M

4. Wait approx. 500 ms

5. Read stereo detection register Note: This register is initialized during STANDARD

SELECTION and is automati cally update d when Automatic Sound Select (MODUS[0]=1) is on.

6.5.7. FM DC Notch

The DC compensation filter (FM DC Notch) for FM input can be switched off. This is used to sp eed up th e automatic search functio n (see Section 6.4.7.). In normal FM-mode, the FM DC Notch should be switched on.

FM DC Notch 00 17

ON 0000 0000 00

OFF 0011 1111 3F

hex

Reset

hex

Note: It is no longer necess ar y to read out and evaluate the A2 identification level. All evaluation is performed in the MSP an d i ndi c ated in the S TATUS r egister.

6.6.2. DC Level Register

DC Level Readout FM1 (MSP-Ch2)

DC Level Readout FM2 (MSP-Ch1)

DC Level [8000

00 1B

hex

00 1C

hex

... 7FFF

hex

values are 16 bit two’s complement

H+L

hex

]

The DC level register measures the DC compon ent of the incoming FM sign als (FM1 and FM2). This can be used for seek functions in satel lite recei vers and for IF FM frequencies fine tuning. A too low demodulation frequency (DCO) results in a positive DC-level and vice versa. For further proc essing, the DC content of the demodulated FM signals is suppressed. Th e time constant τ, defi ning the transi tion time of the DC Level Register, is approximately 28 ms.

94 Micronas

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PRELIMINARY DATA SHEET MSP 34x0G

6.7. Demodulator Source Channels in Manual Mode

6.7.1. Terrestric Sound Standards

Ta b l e 6 –17 shows th e source channel assignment of the demodulated sign als in case of manual mode for all terrestric sound standards. See Table 2–2 for the assignment in the Automatic Sound Select mode. In manual mode for terrestri c sound standards, only two demodulator sources are defined.

6.7.2. SAT Sound Standards

Ta b l e 6 –18 shows th e source channel assignment of the demodulated signals for SAT sound standards.

Table 6–17: Manual Sound Select Mode for Terrestric Sound Standards

Broadcasted Sound Standard

B/G-FM D/K-FM M-Korea M-Japan

B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM

(with high deviation FM)

Selected MSP Standard Code

03 04, 05 02 30

08 09 0A 0B 0C 0D

Source Channels of Sound Select Block

Broadcasted Sound Mode

MONO Sound A Mono Mono Mono STEREO German Stereo

BILINGUAL, Languages A and B

NICAM not available or NICAM error rate too high

MONO Sound A Mono STEREO Sound A Mono BILINGUAL,

Languages A and B MONO Sound A Mono Mono Mono STEREO Korean Stereo Stereo Stereo MONO + SAP Sound A Mono Mono Mono

FM Matrix FM/AM

(use 0 for channel select)

Korean Stereo No Matrix Left = A

Sound A Mono

Sound A Mono1)analog Mono Left = NICAM A

Stereo Stereo

Right = B

analog Mono no sound

analog Mono NICAM Mon o

analog Mono NICAM Stereo

Stereo or A/B

(use 1 for channel select)

Left = A Right = B

with AUTO_FM: analog Mono

Right = NICAM B

BTSC

FM-Radio 40

Automatic refresh to Sound A Mono, do not write any other value to the register FM Matrix!

STEREO + SAP Korean Stereo Stereo Stereo MONO STEREO MONO + SAP STEREO + SAP MONO Sound A Mono Mono Mono STEREO Korean Stereo Stereo Stereo

Sound A Mono Mono Mono

No Matrix

Left = Mono Right = SAP

Micronas 95

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MSP 34x0G PRELIMINARY DATA SHEET

Table 6–18: Manual Sound Select Modes for SAT-Standards

Broadcasted Sound Standard

FM SAT

Selected MSP Standard Code

6, 50

hex

Source Channels of Sound Select Block

Broadcasted Sound Mode

MONO Sound A Mono Mono Mono Mono STEREO No Matrix Stereo Stereo Stereo BILINGUAL No Matrix Left = A (FM1)

FM Matrix FM/AM

(source select: 0)

Right = B (FM2)

for SAT-Modes

Stereo or A/B

(source select: 1)

Left = A (FM1) Right = B (FM2)

Stereo or A

(source select: 3)

A (FM1)

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PRELIMINARY DATA SHEET MSP 34x0G

6.8. Exclusions of Audio Baseband Features

In general, all fu nctions can be switched indepen dently. Two exceptions exist:

1. NICAM cannot be processed simultaneously with the FM2 channel.

2. FM adaptive deemphasis cannot be processed simultaneously with FM-identification.

6.9. Phase Relationship of Analog Outputs

The analog output signals: Lo udspeaker, head phone, and SCART2 all have the same phases. The user does not need to correct output phases when using these analog outputs di re ctly. The SCART1 output has opposite phase.

Using the I

S-outputs for other DSP s or D/A converters, care must be taken to adjust for the correct phase. If the attached copr ocessor is one of the MSP family, the following schematics h elp to determine the phase relationship.

6.10. Compatibility Restrictions to MSP 34x0D

The MSP 34x0G is fully hardware compatible to the MSP 34x0D. However, to substitute a M SP 34x0D by the correspondin g MS P 34x0G, t he c on tro ll er so ftware has to be adapted slightly:

1. The register FM-Matrix (00 0E changed from “no matrix (00

)” during mono transmission of all TV-sound

(03

hex

low part) must be

hex

)” to “sound A mono

hex

standards (see also Table 6–17).

2. With the MSP 34x0G, the STAND ARD SELECTION initializes the FM-deemphasis, which is not the case for the MSP 34x0D. So, if STANDARD SELECTION is applied, this I

C instruction can be omitted.

SCART1 SCART2 SCART3 SCART4

MONO

SCART

DSP

Input

Select

I2S_OUT1/2I2S_IN1/2

Audio

Baseband

Processing

MONO, SCART1...4

SCART1-Ch.

SCART2-Ch.

Loudspeaker

Headphone

SCART1

SCART2

SCART

Output Select

Fig. 6–2: Phase diagram of the MSP 34x0G

Micronas 97

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MSP 34x0G PRELIMINARY DATA SHEET

7. Appendix D: MSP 34x0G Version History

MSP 3430G-A1

First release for BTSC-Stereo/SAP and FM-Radio.

MSP 3440G-A2

Extended Automatic Sound Sele ct feature (incompatible to Version A1).

Known restrictions: – SAP detection unstable

MSP 34x0G-B5

– additional package PLQFP64 – digital input specification changed as of version B5

and later (see Section 4.6. on page 58)

– max. analog high supply voltage AHVSUP 8.7 V. – supply currents changed as of version B5 and later

(see Section 4.6.3. on page 62)

– programmable A2 and carrier mute thresholds – new D/K standard 0D – additional preference in Automatic Standard Detec-

tion

MSP 34x0G-B6

– improved AM-performance – new D/K standard for Poland – improved I – faster system-D/K for stereo detection – extended features in the CONTROL register

MSP 34x0G-B8

C hardware proble m handling

: HDEV3 and NICAM

hex

– fine-tuning of A2-identification and carrier mute – EIA-J identification: faster transition time stereo/

bilingual to mono

– J17 FM-deemphasis implemented – input specification for RESETQ and TESTEN

changed

– MDB implemented

98 Micronas

Page 99

PRELIMINARY DATA SHEET MSP 34x0G

8. Appendix E: Application Circuit

DVSS

AHVSS

DVSS

Tuner 2

Tuner 1

330 nF

330 nF 330 nF

SIF 2 IN

Signal GND

SIF 1 IN

56 pF 56 pF 56 pF

ANA_IN1+

MONO_IN

SC1_IN_L SC1_IN_R

ASG SC2_IN_L

SC2_IN_R ASG

SC3_IN_L SC3_IN_R

ASG SC4_IN_L SC4_IN_R

STANDBYQ

ADR_SEL

I2C_DA I2C_CL

ADR_WS ADR_CL ADR_DA I2S_WS I2S_CL I2S_DA_IN1 I2S_DA_IN2 I2S_DA_OUT

100

µF

3.3 µF100

ANA_IN-

VREFTOP

ANA_IN2+

MSP 34x0G

if ANA_IN2+ not used

C s. section 4.6.2.

18.432 MHz

10 µF10 µF

AGNDC

XTAL_IN

XTAL_OUT

8V(5V)

CAPL_A

CAPL_M

DACM_L

DACM_R

DACM_SUB

DACA_L

DACA_R

SC1_OUT_L

SC1_OUT_R

SC2_OUT_L

SC2_OUT_R

D_CTR_I/O_0 D_CTR_I/O_1

AUD_CL_OUT

TESTEN

1 nF

100 Ω

100 pF 56 pF

1 µF

22 µF

AHVSS

ANA_IN1/2+

Alternative circuit for

1 kΩ

SIF-inputs for more attenuation of video components:

LOUD SPEAKER

HEAD PHONE

AHVSUP 470

1.5 nF 10 µF

AHVSS

VREF1

VREF2

RESETQ (from Controller, see section 4.6.3.3.)

RESETQ

DVSUP

220 pF 470 pF

1.5 nF

10 µF

DVSS

AVSUP 470

1.5 nF

10 µF

AVSS

5 V 5 V 8 V

AVSS

(5 V)

AHVSS

Micronas 99

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MSP 34x0G PRELIMINARY DATA SHEET

9. Data Sheet History

1. Preliminary data sheet: “MSP 34x0G Multistandard Sound Processor Family, Edition Sept. 30, 1998, 6251-476-1PD. First release of the preliminary data sheet.

2. Preliminary data sheet: “MSP 34x0G Multistandard Sound Processor Family, Edition Oct. 9, 1998, 6251-476-2PD. Second release of the preliminary data sheet. Major changes:

– Table 3–9 on page 24: MODUS Register bit [0] func-

tion changed

– Table 3–11 on page 30: Treble Headphone Channel

– Table 3–11 on page 33: Volume SCART1/2 Output

Channel register address changed

– Table 6–17 on page 95: M-BTSC and RM-Radio

description ch ange d

– pin ASG3 changed to “not connected”

3. Preliminary data sheet: “MSP 34x0G Multistandard Sound Processor Family, Edition Oct. 6, 1999, 6251-476-3PD. Third release of the preliminary data sheet. Major changes:

4. Preliminary data sheet: “MSP 34x0G Multistandard Sound Processor Family, Edition Jan. 19, 2001, 6251-476-4PD. Fourth release of the preliminary data sheet. Major changes:

– specification for version B8 added

(see Appendix D: Version History)

– MSP 3460 added, MSP 3430 removed – description for MDB added – specification for MNR added

– I

C-bus description changed

– ACB register: documentation for bit allocation

D_CTR_I/O changed

– specification for version B5 and B6 added

(see Appendix D: Version History)

– section 4.: specification for PLQFP64 package

added

– reset description modified

Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com

Printed in Germany Order No. 6251-476-4PD

All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infr ingements or other right s of third parties whic h may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its conte nt, at any t ime, withou t obligatio n to noti fy any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH .

100 Micronas

Datasheet MSP3460G Datasheet (Micronas Intermetall)

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

2. Functional Description

2.2. Sound IF Processing

2.2.1. Analog Sound IF Input

2.2.2. Demodulator: Standards and Features

2.2.3. Preprocessing of Demodulator Signals

2.2.4. Automatic Sound Select

2.2.5. Manual Mo de

2.4. Source Selection and Output Channel Matrix

2.5. Audio Baseband Processing

2.5.1. Automatic Volume Correction (AVC)

2.5.2. Loudspeaker and Headphone Outputs

2.5.3. Subwoofer Output

2.5.4. Quasi-Peak Detector

2.5.5. Micronas Dynamic Bass (MDB)

2.5.5.1. Dynamic Amplification

2.5.5.3. MDB Parameters

2.6. SCART Signal Routing

2.6.1. SCART DSP In and SCART Out Select

2.5.5.2. Adding Harmonics

2.6.2. Stand-by Mode

2.7. I2S Bus Interface

2.8. ADR Bus Interface

2.9. Digital Control I/O Pins and Status Change Indication

2.10. Clock PLL Oscillator and Crystal Specifications

3. Control Interface

3.1.1. Inte rn al Hardware Error Handling

3.1.2. Descr ipti on of CONTROL Register

3.1.3. Protocol Description

3.1.4.1. Symbols

3.1.4.2. Write Telegrams

3.1.4.3. Read Telegrams

3.1.4.4. Examples

3.3.1. User Registers Overview

3.3.2. Description of User Registers

3.3.2.1. STANDARD SELECT Register

3.3.2.2. Refresh of STANDARD SELECT Register

3.3.2.3. STANDARD RESULT Register

3.4. Programming Tips

3.5. Examples of Minimum Initialization Codes

3.5.1. B/G-FM (A2 or NICAM)

3.5.2. BTSC-Stereo

3.5.3. BTSC-SAP with SAP at Loudspeaker Channel

3.5.4. FM-Stereo Radio

3.5.5. Automatic Standard Detection

4. Specifications

4.1. Outline Dimensions

4.2. Pin Connections and Short Descriptions

4.3. Pin Descriptions

4.4. Pin Configurations

4.5. Pin Circuits

4.6. Electrical Characteristics

4.6.1. Absolute Maximum Ratings

4.6.2. Recommended Operating Conditions (TA = 0 to 70 °C)

4.6.2.1. General Recommended Operating Conditions

4.6.2.2. Analog Input and Output Recommendations

4.6.2.3. Recommendations for Analog Sound IF Input Signal

4.6.2.4. Crystal Recommendations

4.6.3. Characteristics

4.6.3.1. General Characteristics

4.6.3.2. Digital Inputs, Digital Outputs

4.6.3.3. Reset Input and Power-Up

4.6.3.4. I2C-Bus Characteristics

4.6.3.5. I2S-Bus Characteristics

4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC

4.6.3.7. Sound IF Inputs

4.6.3.8. Power Supply Rejection

4.6.3.9. Analog Performance

4.6.3.10. Sound Standard Dependent Characteristics

5. Appendix A: Overview of TV-Sound Standards

5.1. NICAM 728

5.2. A2-Systems

5.3. BTSC-Sound System

5.4. Japanese FM Stereo System (EIA-J)

5.5. FM Satellite Sound

5.6. FM-Stereo Radio