Datasheet MSM7731-01GA Datasheet (OKI)

E2U0060-18-84

Preliminary

¡ Semiconductor MSM7731-01

This version: Aug. 1998

¡ Semiconductor

MSM7731-01

Multifunction PCM CODEC (Voice Signal Processor)

GENERAL DESCRIPTION

The MSM7731 is an LSI device developed for portable, handsfree communication with built-in
line echo canceler, acoustic echo canceler, and transmission signal noise canceler. Built-in to the
voice signal interface is a linear CODEC for the analog interface on the acoustic-side, and a linear
CODEC for the analog interface on the line-side. On the line-side, in addition to the analog
interface, there is also a m-law PCM/16-bit linear digital interface.
Equipped with gain and mute controls for data transmission and reception, a m-law PCM/16­bit linear digital interface for memo recording and message output, and transfer clock and sync
clock generators for digital communication, this device is ideally suited for a handsfree system.

FEATURES

• Single 3 V power supply operation (2.7 V to 3.6 V)

• Built-in 2-channel (line and acoustic) echo canceler
Echo attenuation : 35 dB (typ.)
Cancelable echo delay time :

Line echo canceler + acoustic echo canceler : Tlined = 27 ms (max.),

Tacoud = 59 ms – Tlined (max.)

Acoustic echo canceler only : Tacoud = 59 ms (max.)

• Built-in transmission signal noise canceler
Noise attenuation: 13 dB (typ.) for white noise

40 dB (typ.) for single tone

• Built-in 2-channel CODEC

Synchronous transmission and reception enables full duplex operation

• Built-in analog input gain amp stage (max. gain = 30 dB)

• Analog output configuration: Push-pull drive (can drive a 1.2 kW load)

• Built-in transmit slope filter

• Digital interface coding formats: m-law PCM, 16-bit linear (2's complement)

• Digital interface sync formats: Normal-sync, short-frame-sync

• Built-in digital transmission clock generators

Sync clock (SYNC): 8 kHz output
Transmission clock (BCLK): 64 kHz output (m-law PCM)/128 kHz

output (16-bit linear)

• Digital transmission rate

External input: 64 kbps to 2048 kbps
Internal generation: 64 kbps (m-law PCM)/128 kbps (16-bit linear)

• Fixed digital interface sync clock (SYNC) enables automatic power-down

• Master clock frequency: 19.2 MHz

Compatible with crystal oscillator and crystal

• Low power consumption

Operating mode: typ. 105mW (when VDD = 3.0 V)
Power-down mode: typ. 0.3mW (when VDD = 3.0 V)

• Control by both the serial microcomputer interface and parallel port is possible

• Transmit/receive mute function, transmit/receive programmable gain setting

• Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSM7731-01GA)

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¡ Semiconductor MSM7731-01

BLOCK DIAGRAM

TEST9

AGND

AVDDDGND1, 2

DV

DD1, 2

TEST1-4, 8

PCMO

PCMI

P/S
& S/P

LINEEN

LIN

LGSX

LVFRO

RC LPF

RC LPF

ADC

BPF

LPF

DAC

LOUT

LPWI

+

–

1.2kW

Linear CODEC

(Line side)

Power Calc.

Howling Detector

Double Talk Det

+

–

ATTsL

SinL

SoutL

+

+

Center
Clip

Line Adaptive
FIR Filter
(LAFF)

GainLATTrL

RinL

RoutL

Line Echo Canceler

TPAD

Slope
Filter

Noise
Canceler

SoutA

STTsA

+
–

+

Acoustic Adaptive
FIR Filter
(AAFF)

LPADA

SinA

Power Calc.

Howling Detector

Double Talk Det

ATTrA

RoutA

GainA

RinA

RPAD

+

Acoustic Echo Canceler

+

–

+

–

+

–

DAC

RC LPF

1.2kW

RC LPF

ADC

BPF

Linear CODEC

(Acoustic side)

APWI

AVFRO

AGSX

AOUT

AIN

V

REF

SG

LEC Controller

LTHR

LGC

LATT

LHLD

LHD

MCU Interface

DEN

EXCK

DIN

DOUT

MCUSEL

EC/NC/SF/PAD

Controller

RPAD1-4

TPAD1-4

ECSEL

GLPADTHR

NCTHR

SLPTHR

RST

PCMEO

P/S
& S/P

PCMEI

AEC Controller

ATHR

AGC

AATT

AHLD

AHD

Timing Gen

SYNC

SYNCSEL

BCLK

CLKSEL

PCMSEL

Clock Gen

PDN/RST

MCK/X1

X2

LPF

Center
Clip

GPADA

GPADL

LPADL

¡ Semiconductor MSM7731-01

PIN CONFIGURATION (TOP VIEW)

EXCK

DIN

NCTHR

SLPTHR

TEST1

TEST2

TEST3

TEST4

TEST8

PDN/RST

RST

64

63

62

61

60

59

58

57

56

55

54

53 SYNC

52 BCLK

51 CLKSEL

50 PCMI

49 PCMEI

ECSEL

MCUSEL

AHD

AHLD

AATT

AGC

DGND1

ATHR

LHD

LHLD

LATT

DD1

10
11
12LGC
13LTHR
14RPAD4
15DV
16RPAD3

1
2
3
4
5
6
7
8
9

48

PCMEO

47

PCMO

46

PCMSEL

45

SYNCSEL

44

DOUT

43

DEN

42

DV

GLPADTHR

41

TEST9

40

LINEEN

39

AGND

38

DD2

37 LOUT
36 LPWI
35 LVFRO
34 LGSX
33 LIN

17

18

19

20

21

22

23

24

25

26

27

28AIN

29AVFRO

30APWI

31AOUT

32SG

DD

X2

AV

RPAD2

RPAD1

TPAD4

DGND2

TPAD3

TPAD2

TPAD1

MCK/X1

AGSX

64-Pin Plastic QFP

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¡ Semiconductor MSM7731-01

PIN DESCRIPTIONS

Pin PinType TypeSymbol Symbol

133
234
335

AHD

436
537
638

AATT

AGC

739
840
941

LHD GLPADTHR

10 42
11 43
12 44

LATT DEN

LGC

13 45
14 46
15 47

DD1

16 48
17 49
18 50
19 51
20 52
21 53
22 54
23 55
24 56
25 57
26 58

DD

27 59
28 60
29 61
30 62
31 63
32 64

IIECSEL LIN
IOMCUSEL LGSX
IO

LVFRO
IIAHLD LPWI
IO
II
IIDGND1

LOUT

AGND

LINEEN

IOATHR TEST9
II
IILHLD DV

DD2

II
IO

DOUT
IILTHR SYNCSEL
IIRPAD4 PCMSEL
IODV

PCMO
IORPAD3 PCMEO
IIRPAD2 PCMEI
IIRPAD1 PCMI
IIDGND2 CLKSEL
I I/OTPAD4 BCLK
I I/OTPAD3 SYNC
IITPAD2
IITPAD1

RST

PDN/RST

IIMCK/X1 TEST8

OIX2 TEST4

IIAV

TEST3

OIAGSX TEST2

IIAIN TEST1

OIAVFRO SLPTHR

IIAPWI NCTHR

OIAOUT DIN
OISG EXCK

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¡ Semiconductor MSM7731-01

g

PIN FUNCTIONAL DESCRIPTION

AIN, AGSX

These are the acoustic analog input and level adjusting pins. The AIN pin is connected to the
inverting input of the internal amp and the AGSX pin is connected to the amp output. For level
adjustment, refer to the diagram below (Figure 1). At power-down reset, the AGSX pin goes to
a high impedance state.

AVFRO, AOUT, APWI

These are the acoustic analog output and level adjusting pins. The AVFRO pin is an audio
output and can directly drive 20 kW. The AOUT pin is an analog output and can directly drive
a load of 1.2 kW. For level adjustment, refer to the diagram below (Figure 1). At power-down
reset, these output pins go to a high impedance state.

LIN, LGSX

These are the line analog input and level adjusting pins. The LIN pin is connected to the
inverting input of the internal amp and the LGSX pin is connected to the amp output. For level
adjustment, refer to the diagram below (Figure 1). At power-down reset, the LGSX pin goes to
a high impedance state. If LIN is not used, short the LIN and LGSX pins together.

LVFRO, LOUT, LPWI

These are the line analog output and level adjusting pins. The LVFRO pin is an audio output
and can directly drive 20 kW. The LOUT pin is an analog output and can directly drive a load
of 1.2 kW. For level adjustment, refer to the diagram below (Figure 1). At power-down reset,
these output pins go to a high impedance state. If LOUT is not used, short the LPWI and LOUT
pins together.

LINEEN

This is the power-down control pin for the line CODEC. A logic "0" continues normal operation
and a logic "1" powers down only the line CODEC. If the line CODEC is not used, power down
the line CODEC and short the LIN pin to the LGSX pin and the LPWI pin to the LOUT pin. This
procedure results in the low consumption of electrical power. At power-down, the output pins
go to a high impedance state. Since this pin is ORed with CR0-B5 of the control register, set the
pin to a logic "0" when controlling power-down by the control register. If the pin setting is
changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7).

=R2/R1

V

AGSX/VI

£30

Speaker

R2≥20kW

V

I

Speaker amp

V

O/VAVFRO

R3≥20kW

+
–

10mF0.1mF

=R3/R4

R1C1

C2

Microphone

Acoustic side (microphone, speaker)

R2

R3

R4

V

O

AGSX

AIN

SG

AVFRO

APWI

AOUT

Acoustic CODEC

to ENCODER

–
+

from DECODER

–
+

Reception signal

Transmission si

VREF

Line CODEC

nal

LGSX

LIN

Same as the acoustic
analog interface

LVFRO

LPWI

LOUT

LINEEN

Line side (portable phone)

Figure 1 Analog Interface

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¡ Semiconductor MSM7731-01

AGND

This is the analog ground pin.

DGND1, DGND2

These are the digital ground pins.

AV

DD

This is the analog +3 V power supply pin.

DV

DD1

, DV

DD2

These are the digital +3 V power supply pins.

SG

This is the output pin for the analog signal ground potential. The output voltage is approximately

1.4 V. Insert 10 mF and 0.1 mF ceramic bypass capacitors between the AGND and SG pins. At
power-down reset, this output becomes 0 V.

PDN/RST

This is the power-down reset control input pin. If a logic "0" is input to this pin, the device enters
the power-down state. At this time, all control register bits and internal variables will be reset.
After the power-down reset state is released, the device enters the initial mode (refer to the CR0
control register description). During normal operation, set this pin to a logic "1". Since the
PDN/RST pin is ORed (negative logic) with CR0-B7 of the control register, set the pin to a logic
"1" when controlling power-down reset by the control register.

MCK/X1

This is the master clock input pin. The clock frequency is 19.2 MHz. The input clock may be
asynchronous with respect to the SYNC signal or the BCLK signal. Refer to Figure 2 (a) for an
example application of an external clock and Figure 2 (b) for an example oscillator circuit.

X2

This is the crystal oscillator output pin. If an existing external clock is to be used, leave this pin
open and input the clock to the MCK pin. Refer to Figure 2 (b) for an example oscillator circuit.

MCK/X1 X2 MCK/X1 X2

R

Figure 2 (a) External Clock Application

Crystal

CC

R
C
Crystal

Figure 2 (b) Oscillator Circuit Example

: T.B.D
: T.B.D
: 19.2 MHz

Example

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¡ Semiconductor MSM7731-01

SYNC

This is the 8 kHz sync signal I/O pin for digital data communication. This pin is switched to
function as an input or output by the CLKSEL pin. If the internal clock mode is selected by the
CLKSEL pin, an 8 kHz clock synchronized to the BCLK signal is output and digital data
communication is performed. If the external clock mode is selected by the CLKSEL pin, this pin
becomes an input that requires an 8 kHz clock input synchronized to the BCLK pin, and digital
data communication is performed based on this input clock. Fixing this signal to a logic "1" or
logic "0" causes this device to internally write a logic "1" to the PDN/RST (CR0-B7) bit of the
control register, and to enter the power-down reset state. This automatic power-down control
is valid when external clock mode is selected by the CLKSEL pin and automatic power-down
control has been turned ON by the SYPDN (CR11-B0) bit of the control register.

BCLK

This is the shift clock I/O pin for digital data communication. This pin is switched to function
as an input or output by the CLKSEL pin. If the internal clock mode is selected by the CLKSEL
pin, a 64 kHz or 128 kHz clock synchronized to the SYNC signal is output and digital data
communication is performed. Switching between 64 kHz and 128 kHz is performed by the
PCMSEL pin. If m-law PCM is selected by the PCMSEL pin, a 64 kHz clock is output. Or, if 16­bit linear mode is selected, a 128 kHz clock is output. If the external clock mode is selected by
the CLKSEL pin, this pin becomes an input that requires a clock input synchronized to the
SYNC. In this case, the clock frequency range is from 64 kHz to 2048 kHz.

CLKSEL

This pin selects internal or external clock modes for the SYNC and BCLK signals. A logic "0"
selects the internal clock mode. At this time, SYNC and BCLK pins are configured as output pins
and each internally generated clock is output to perform digital data communication. A logic
"1" selects the external clock mode and configures the SYNC and BCLK pins as input pins. At
this time, digital data communication is performed with the externally input SYNC and BCLK
clocks. If digital data communication is not used, set this pin to a logic "0" to select internal
clocks. If the pin setting is changed, reset must be activated by either the PDN/RST pin or the
PDN/RST bit (CR0-B7).

PCMI

This is the digital receive signal input pin on the line-side. This input signal is shifted at the
rising edge of the BCLK signal and input. The beginning of digital data is identified on the rising
edge of the SYNC signal. The coding format can be selected as m-law PCM or 16-bit linear (2's
complement) by the PCMSEL pin. If the PCMI pin is not used, set it to a logic "1" if m-law PCM
has been selected, or a logic "0" if 16-bit linear mode has been selected. The sync format can be
selected as normal-sync or short-frame-sync by the SYNCSEL pin. Refer to Figure 3 for the
timing. This digital input signal is added internally to the CODEC digital output signal. Be
careful of overflow when using the CODEC.

PCMO

This is the digital transmit signal output pin on the line-side. This output signal is synchronized
to the rising edge of the BCLK and SYNC signals and then output. When not used for output,
this pin is in the high impedance state. It is also at high impedance during the power-down reset
and the initial modes. The coding format can be selected as m-law PCM or 16-bit linear (2's
complement) by the PCMSEL pin. The sync format can be selected as normal-sync or short­frame-sync by the SYNCSEL pin. Refer to Figure 3 for the timing.

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¡ Semiconductor MSM7731-01

PCMEI

This is the message signal input pin. Use this pin when a message is output to the speaker on
the acoustic-side. This input signal is shifted at the rising edge of the BCLK signal and then
input. The beginning of digital data is identified on the rising edge of the SYNC signal. The
coding format can be selected as m-law PCM or 16-bit linear (2's complement) by the PCMSEL
pin. If the PCMEI pin is not used, set it to a logic "1" if m-law PCM has been selected, or a logic
"0" if 16-bit linear mode has been selected. The sync format can be selected as normal-sync or
short-frame sync by the SYNCSEL pin. Timing is the same as for the PCMI pin (refer to Figure

3). This digital input signal is added internally to the echo canceler output signal. Be careful
of overflow during telephone conversations.

PCMEO

This output pin is for memo recording. Use it with the memo function. This output signal is
synchronized to the rising edge of the BCLK and SYNC signals and then output. When not used
for output, this pin is in the high impedance state. It is also at high impedance during the power­down reset and the initial modes. The coding format can be selected as m-law PCM or 16-bit
linear (2's complement) by the PCMSEL pin. The sync format can be selected as normal-sync
or short-frame-sync by the SYNCSEL pin. Timing is the same as for the PCMO pin (refer to
Figure 3).

SYNCSEL

This is the sync timing selection pin for digital data communication. A logic "0" selects
normal-sync timing and a logic "1" selects short-frame-sync timing. Refer to Figure 3 for the
timing. If the pin setting is changed, reset must be activated by either the PDN/RST pin or the
PDN/RST bit (CR0-B7).

PCMSEL

This is the coding format selection pin for digital data communication. A logic "1" selects m-law
PCM and a logic "0" selects 16-bit linear (2's complement) coding format. When an internal clock
is selected, the BCLK signal determines the output clock frequency. If the digital interface is not
used, set this pin to logic "0" to select 16-bit linear coding format.
Since this pin is logically ORed with the PCMSEL bit (CR11-B1), set the pin to a logic "0" when
controlling by the control register.
If the pin setting is changed, reset must be performed by either the PDN/RST pin or the PDN/
RST bit (CR0-B7).

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¡ Semiconductor MSM7731-01

SYNC

BCLK
PCMI

PCMEI
PCMO

PCMEO

SYNC

BCLK
PCMI

PCMEI
PCMO

PCMEO

SYNC

D15 D14 D13 D12 D2 D1 D0 D15 D14

D15 D14 D13 D12 D2 D1 D0 D15 D14

Hi-Z

(a) 16-bit linear coding format timing (normal sync)

D7 D6 D5 D4 D2 D1 D0 D7 D6

D7 D6 D5 D4D3D3 D2 D1 D0 D7 D6

mm

(b)

m-law PCM coding format timing (normal sync)

mm

Hi-Z

BCLK
PCMI

PCMEI
PCMO

PCMEO

SYNC

BCLK
PCMI

PCMEI
PCMO

PCMEO

D15 D14 D13 D2 D1 D0 D15

D15 D14 D13

D3

D3 D2 D1 D0 D15

Hi-ZHi-Z

(c) 16-bit linear coding format timing (short-frame sync)

D7 D6 D5 D4 D2 D1 D0 D7

D7 D6 D5 D4D3D3 D2 D1 D0 D7

mm

(c)

m-law PCM coding format timing (short-frame sync)

mm

Hi-ZHi-Z

Figure 3 Digital Interface Timing

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¡ Semiconductor MSM7731-01

ECSEL

This is the echo canceler mode selection pin. A logic "1" selects the single echo canceler mode
and a logic "0" selects the dual echo canceler mode. Since this pin is ORed with the CR0-B0 bit
of the control register, set the pin to a logic "0" when controlling by the control register. If the
pin setting is changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit
(CR0-B7). If the single echo canceler mode is selected, echo canceler control on the line-side is
unnecessary.

LTHR/ATHR

This is the "through mode" control pin for the echo canceler. In the "through mode", SinL/A and
RinL/A data is directly output to SoutL/A and RoutL/A respectively while each respective
echo coefficient is maintained. A logic "0" selects the normal mode (echo canceler operation) and
a logic "1" selects the "through mode." Since this pin is ORed with the CR4-B7 and CR5-B7 bits
of the control register, set the pin to a logic "0" when controlling the "through mode" by the
control register. Because data is shifted into this pin in synchronization with the rising edge of
the SYNC signal, hold the data at the pin for 250 ms or longer. For further details, refer to the
electrical characteristics.

LHD/AHD

This pin turns ON or OFF the function to detect and cancel the howling that occurs in an acoustic
system such as a handsfree communication system. A logic "0" turns the function ON and a logic
"1" turns the function OFF. Since this pin is ORed with the CR4-B4 and CR5-B4 bits of the control
register, set the pin to a logic "0" when controlling by the control register. Because data is shifted
into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin
for 250 ms or longer. For further details, refer to the electrical characteristics.

LHLD/AHLD

This pin controls the updating of adaptive FIR filter coefficients for the echo canceler. A logic
"0" selects the normal mode (coefficient updating) and a logic "1" selects the fixed coefficient
mode. Since this pin is ORed with the CR4-B2 and CR5-B2 bits of the control register, set the pin
to a logic "0" when controlling by the control registers. Because data is shifted into this pin in
synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 ms or
longer. For further details, refer to the electrical characteristics.

LATT/AATT

This pin turns ON or OFF the ATT function to prevent howling by means of attenuators
(ATTsL/A, ATTrL/A) provided in the RinL/A inputs and SoutL/A outputs of the echo
canceler. If input is only to RinL/A, the ATTsL/A for SoutL/A is activated. If input is only to
SinL/A, or if there is input to both SinL/A and RinL/A, the ATTrL/A for RinL/A input is
activated. The ATT value of each attenuator is approximately 6 dB. A logic "0" turns ON and
a logic "1" turns OFF the ATT function. Since this pin setting is logically ORed with the CR4­B1 and CR5-B1 bits of the control register, set the pin to a logic "0" when controlling by the control
register. Because data is shifted into this pin in synchronization with the rising edge of the SYNC
signal, hold the data at the pin for 250 ms or longer. For further details, refer to the electrical
characteristics.

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¡ Semiconductor MSM7731-01

LGC/AGC

This pin turns ON or OFF the gain control function to control the input level and prevent
howling by means of gain controls (GainL/A) provided in the RinL/A inputs of the echo
canceler. The gain controller adjusts the RIN input level when it is –10 dBm0 or above, and it
has the control range of 0 to –8.5 dB. A logic "0" turns the function ON and a logic "1" turns the
function OFF. Since this pin is ORed with the CR4-B0 and CR5-B0 bits of the control register,
set the pin to a logic "0" when controlling by the control register. Because data is shifted into this
pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250
ms or longer. For further details, refer to the electrical characteristics.

Notes:
Lxx/Axx: In the above, Lxx refers to line echo canceler control pins and Axx to acoustic echo

canceler control pins.

xxL/xxA: In the above pin descriptions, xxL refers to line echo canceler functions and xxA to

acoustic echo canceler functions.

GLPADTHR

This is the mode control pin for the attenuators (LPADL/A) provided in the SinL/A inputs and
the amplifiers (GPADL/A) provided in the SoutL/A outputs of the echo canceler. A logic "0"
selects the "through mode" and a logic "1" selects the normal mode (PAD operation). The levels
are set by the CR10 register. Settings of ±18, ±12, ±6 and 0 dB are possible. The default setting
is ±12 dB. If the echo return loss (value of returned echo) is amplified, set the LPAD level such
that echo return loss will be attenuated. It is recommended to set the GPAD level to the positive
level equal to the LPAD level. Since this pin is ORed with the CR1-B2 bit of the control register,
set the pin to a logic "0" when controlling by the control register. Because data is shifted into this
pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250
ms or longer. For further details, refer to the electrical characteristics.

NCTHR

This is the noise canceler "through mode" control pin. In the "through mode" the noise canceler
is halted and data is directly output. A logic "0" selects the normal mode (noise canceler
operation) and a logic "1" selects the "through mode". Since this pin is ORed with the CR1-B0
bit of the control register, set the pin to a logic "0" when controlling by the control register.
Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal,
hold the data at the pin for 250 ms or longer. For further details, refer to the electrical
characteristics. When this pin is changed from normal mode to "through mode", approximately
20 ms of data dropout will occur.

SLPTHR

This is the "through mode" control pin for the transmit slope filter. In the "through mode", the
filter is halted and data is directly output. A logic "0" selects the normal mode (slope filter
operation) and a logic "1" selects the "through mode". Since this pin is ORed with the CR1-B1
bit of the control register, set the pin to a logic "0" when controlling by the control register.
Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal,
hold the data at the pin for 250 ms or longer. For further details, refer to the electrical
characteristics.

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¡ Semiconductor MSM7731-01

RST

This input pin resets coefficients of the echo canceler and noise canceler. A logic "0" causes the
reset state to be entered. At this time, the filter coefficients for the echo canceler and noise
canceler are reset. Control register contents are preserved. While reset is being processed, there
is no sound. During normal operation, set this pin to a logic "1". Since this pin is ORed (negative
logic) with the CR0-B6 bit of the control register, set the pin to a logic "1" when controlling by
the control register. Use this pin in cases where the echo path changes (due to line switching
during a telephone conversation, etc.), or when resuming telephone communication. Because
data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the
data at the pin for 250 ms or longer.
For further details, refer to the electrical characteristics.

DEN, EXCK, DIN, DOUT

This is the serial port for the microcomputer interface. 13 bytes of control registers are provided
in this LSI device. These pins are used to write and read data from an external microcomputer.
The DEN pin is an enable signal input pin, the EXCK pin is a clock signal input pin for data
shifting, the DIN pin is an address and data input pin, and the DOUT pin is a data output pin.
If the microcomputer interface is not used, set the DEN pin to a logic "1" and the EXCK and DIN
pins to a logic "0". In addition, use the MCUSEL pin to specify the "unused" setting of the
microcomputer interface. Figure 4 shows the input timing.

MCUSEL

This pin selects whether the microcomputer interface is used or unused. A logic "0" specifies
that the microcomputer interface is used and a logic "1" specifies that it is not used. If the
microcomputer interface is not used, this pin must be set to a logic "1". This pin is ORed with
the CR0-B1 bit of the control register.

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¡ Semiconductor MSM7731-01

DEN

1

EXCK

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

DIN

DOUT

DEN

EXCK

DIN

DOUT

DEN

EXCK

A6W A5A4A3A2A1A0 B7B6B5B4B3B2B1B0

Hi-Z

(a) Data Write Timing 1 (8-Bit MCU)

1

2 3 4 5 6 7 8 10 11 12 13 14 15 16

A6W A5A4A3A2A1A0B7B6B5B4B3B2B1B0

9

Hi-Z

(b) Data Write Timing 2 (16-Bit MCU)

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

DIN

DOUT

DEN

EXCK

DIN

DOUT

A6R A5A4A3A2A1A0

Hi-Z Hi-Z

B6B7 B5 B4 B3 B2 B1 B0

(c) Data Read Timing 1 (8-Bit MCU)

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A6R A5A4A3A2A1A0

Hi-Z Hi-Z

B6B7 B5 B4 B3 B2 B1 B0

(d) Data Read Timing 2 (16-Bit MCU)

Figure 4 Microcomputer Interface I/O Timing

13/43

¡ Semiconductor MSM7731-01

RPAD4, RPAD3, RPAD2, RPAD1

These are the receive signal gain adjusting and mute setting pins. Refer to Table 1 for the
settings. Set these pins to a logic "0" when controlling by the control register. Because data is
shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data
at the pin for 250 ms or longer. For further details, refer to the electrical characteristics.

TPAD4, TPAD3, TPAD2, TPAD1

These are the transmit signal gain adjusting and mute setting pins. Refer to Table 1 for the
settings. Set these pins to a logic "0" when controlling by the control register. Because data is
shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data
at the pin for 250 ms or longer. For further details, refer to the electrical characteristics.

Table 1 RPAD/TPAD Settings

RPAD4

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

RPAD3

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

RPAD2

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

RPAD1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

TPAD4

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

TPAD3

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

TPAD2

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

TPAD1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

Level

21 dB
18 dB
15 dB
12 dB

9 dB
6 dB
3 dB

0 dB
–3 dB
–6 dB
–9 dB

–12 dB
–15 dB
–18 dB
–21 dB

MUTE

TEST1-4, 8

Test inputs. Set these pins to a logic "0".

TEST9

Test output.

14/43

¡ Semiconductor MSM7731-01

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage
Digital Input Voltage
Digital Output Voltage
Storage Temperature

Symbol

V

DD

V

DIN

V

OUT

T

STG

Condition

—
—
—
—

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply voltage
Operating Temperature

Input High Voltage V

Input Low Voltage

Digital Input Rise Time
Digital Input Fall Time
Master Clock Frequency
Master Clock Duty Ratio
Bit Clock Frequency
Bit Clock Duty Ratio
Synchronous Signal Frequency
Synchronous Signal Width
Transmit/Receive Sync Signal
Setting Time
Digital Output Load

Bypass Capacitor for SG

Symbol

V

DD

Ta

IH

V

IL

t

IR

t

If

F

MCK

D

MCK

F

BCK

D

CK

F

SYNC

t

WS

t

BS

t

SB

R

DL

C

DL1

C

DL2

C

SG

Condition

—

—
SYNC, BCLK input pins
MCK/X1 input pin 0.65¥V
Other digital input pins 0.45¥V
MCK/X1 input pin
Other digital input pins 0.16¥V
All digital inputs — ns—20
All digital inputs — ns—20
MCK/X1 –100 ppm MHz+19.2 +100 ppm
MCK/X1 40 %50 60
BCLK (during input) 64 kHz— 2048
BCLK (during input) 40 %50 60
SYNC (during input) –100 ppm kHz8 +100 ppm
SYNC (during input) 1 BCLK ms— 100
BCLK to SYNC (during input) 100 ns——
SYNC to BCLK (during input) 100 ns——
DOUT, PCMO, PCMEO 1 kW——
DOUT, PCMO, PCMEO — pF—50
SYNC, BCLK (during output) — pF—20
SG to AG 10+0.1 mF——

Min.

2.7

–40

0.5¥V

0

Rating

–0.3 to +5.0
–0.3 to V
–0.3 to V

–55 to +150

Typ.

+25

DD

DD

DD

—

—

DD

DD

+0.3
+0.3

0.35¥V

Max.

3.6

+85

DD

DD

DD

Unit

V
V
V

°C

Unit

V

°C

V—V

V

15/43

¡ Semiconductor MSM7731-01

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

(V

= 2.7 V to 3.6 V Ta = –25°C to +70°C)

DD

Parameter

Power Supply Current 1
Power Supply Current 2
Input Leakage Current

High Level Digital Output Voltage
Low Level Digital Output Voltage
Digital Output Leakage Current
Input Capacitance

Analog Interface

Parameter

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Voltage Level (*1)

Offset Voltage

SG Output Voltage
SG Output Impedance

Symbol

I

DD1

I

DD2

I

IH

I

IL

V

OH

V

OL

I

O

C

IN

Symbol

R

INA

R

INL

R

LA1

R

LA2

R

LL1

R

LL2

C

LA1

C

LL1

V

OA1

V

OA2

V

OL1

V

OL2

V

OFA1

V

OFA2

V

OFL1

V

OFL2

V

SG

R

SG

Condition

Operating, no signal (V

Power down mode (VDD = 3.0 V, MCK = 0 V)

V

= V

I

DD

= 3.0 V)

DD

VI = 0 V
I

= 0.4 mA 0.5¥V

OH

Min.

—
—
—
—

DD

Typ.

35

0.1
—
—

Max.

45

1
2
2

DD

Unit

mA
mA

mA
mA

V—V
IOL = 3.2 mA 0 V0.2 0.4
DOUT, PCMO, PCMEO — mA—10

—pF5—

= 2.7 V to 3.6 V Ta = –25°C to +70°C)

Min.

10

Typ.

—

Max.

—

Unit

MW

AIN, APWI

—

Condition

(V

DD

LIN, LPWI 10 MW——

AGSX, AVFRO

20

—

—

kW
AOUT 1.2 kW——
LGSX, LVFRO 20 kW——
LOUT 1.2 kW——
AGSX, AVFRO, AOUT
LGSX, LVFRO, LOUT
AGSX, AVFRO — Vpp— 1.3
AOUT — Vpp— 2.6
LGSX, LVFRO — Vpp— 1.3
LOUT — Vpp— 2.6

R

= 20 kW

L

= 1.2 kW

R

L

= 20 kW

R

L

R

= 1.2 kW

L

—
—

—
—

100
100

pF
pF

AVFRO –100 mV— +100
AOUT –20 mV— +20
AVFRO –100 mV— +100
LOUT –20 mV— +20
SG — V1.4 —
SG

—kW40 80

*1 0.320 Vrms = 0 dBm0, +3.14 dBm0 = 1.30 Vpp

16/43

¡ Semiconductor MSM7731-01

Digital Interface

= 2.7 V to 3.6 V Ta = –25°C to +70°C)

(V

DD

—
—

—
—

—
—
—
—
—
—
30
—
—
30

Unit

ms——

ms

ms

kHz
kHz

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Parameter

Power-down Reset Signal
Pulse Width
Power-down Reset Start Time
Power-down Reset End Time

Power-down Reset Internal Setting Time

Control Pulse Width
Control Start Time
Control End Time
Bit Clock Frequency

Bit Clock Duty Ratio
Synchronous Signal Frequency
Sync Signal Duty Ratio
Transmit/Receive Sync
Signal Setting Time
Input Setup Time
Input Hold Time 100 ns——
Digital Output Delay Time RDL = 1 kW, CDL = 50 pF

MCU Interface Digital
Input/Output Setting Timing

Symbol

t

RSTW

t

PDND

t

PDNH

t

PDNS

t

PARW

t

PARD

t

PARH

F

BCK

D

CK

F

SYNC

D

SYNC

t

BS

t

SB

t

DS

t

DH

t

SDX

t

XD1

t

XD2

t

XD3

t

M1

t

M2

t

M3

t

M4

t

M5

t

M6

t

M7

t

M8

t

M9

t

M10

t

M11

f

ECK

Condition

PDN/RST pin
PDN/RST control bit

PDN/RST pin and PDN/RST control bit
PDN/RST pin and PDN/RST control bit

SYNC pin (input mode) 140 ms— 180
(*3)

C

= 20 pF (output mode, PCM)

DL

= 20 pF (output mode, linear)

C

DL

CDL = 20 pF (output mode) 40 %50 60
CDL = 20 pF (output mode) — kHz8—
CDL = 20 pF (output mode)
BCLK to SYNC (output mode)
SYNC to BCLK (output mode)

—
—

R

= 1 kW, CDL = 50 pF

DL

RDL = 1 kW, CDL = 50 pF

= 1 kW, CDL = 50 pF

R

DL

RDL = 1 kW, CDL = 20 pF —

RDL = 1 kW, CDL = 20 pF

Min.

Typ.

1

1.6
—ns—50
—ms—

250 ms——

—
—
—
—

—
—
64

128

40 %50 60

100
100

—
—

100 ns——

—
—
—
—
20
20
50

100

50
50

—
—
—
—
—
—
—
—
—
—
—

0
50
—

—
—
—

100 — —

—MHz—10EXCK Clock Frequency — —

Max.

200+a (*2)

250
250

100
100
100
100

*2 a : Crystal activation time
*3 Applies to the following pins/control bits:

LINEEN, SLPTHR, NCTHR, GLPADTHR, TPAD6-1, RPAD6-1, RST, ATHR, AATT, AHLD,
AHD, AGC, LTHR, LATT, LHLD, LHD, and LGC

17/43

¡ Semiconductor MSM7731-01

AC Characteristics (Line CODEC/Acoustic CODEC)

2.7 V to 3.6 V, Ta = –25°C to +70°C)

(V

DD =

Condition

Parameter

Transmit Frequency
Response

Receive Frequency
Response

Transmit Signal
to Distortion Ratio

Receive Signal
to Distortion Ratio

Transmit Gain
Tracking

Receive Gain
Tracking

Idle Channel Noise

Symbol

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

Freq.

0 to 60

T1
T2

300 to 3000 –0.15 — +0.20 dB
T3
T4
T5
T6
R1
R2
R3
R4
R5

1020 Reference dB
3300 –0.15 — +0.80 dB
3400 0 — 0.80 dB

3968.75 13 — — dB

0 to 3000 –0.15 — +0.20 dB

1020 Reference dB
3300 –0.15 — +0.80 dB0
3400 0 — 0.80 dB

3968.75 13 — — dB
SD T1 35 —3
SD T2 35 —0
SD T3 35 —–30

1020
SD T4
SD T5 23 —–45

SD R1 —3
SD R2 —0
SD R3 —–30

1020

SD R4
SD R5 —–45

GT T1 –0.2 +0.2
GT T2 Reference
GT T3 1020 –0.2 +0.2–40
GT T4 –0.5 +0.5
GT T5 –1.2 +1.2

GT R1 –0.2 +0.2
GT R2 Reference
GT R3 1020 –0.2 +0.2
GT R4 –0.5 +0.5
GT R5 –1.2 +1.2

N

N

IDLT

IDLR

———

——

Level

(dBm0)(Hz)

–10

–50
–55

–10
–40
–50
–55

—

—

Others

Min.

Typ.—Max.—Unit

25

0

—

—

—
—

(*4)

28 —–40

—
—

—
35
35

(*4)

35
28
23

3

—

—

—

—

—

—

—

—

—

—

3

—

—

—

—

—

(*4)

(*4)

—

(–75.7)

(–79.7)

—–40

–68

–72

dB

dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB

dBm0p
(dBmp)

A

A

P
P

VT

VR

SRRT

SRRR

1020

Noise Freq.:

0 to 50 kHz

Absolute Signal
Amplitude

Power Supply Noise
Rejection Ratio

*4 P-message weighted filter used

0.320 Vrms = 0 dBm0 = –7.7 dBm

0

Noise Level:

50 mV

PP

A/LGSX

A/LVFRO

—

0.285

0.285

0.320

0.320

0.359

0.359

Vrms

Vrms

30——dB
30——dB

18/43

¡ Semiconductor MSM7731-01

p

p

Echo Canceler Characteristics

= 2.7 V to 3.6 V, Ta = –25°C to +70°C)

(V

DD

Parameter

Echo Attenuation

Symbol

Eres

Tacoud Single mode — — 59 ms

Cancelable Echo
Delay Time

Measurement System Block Diagram

Tacoud Dual mode (acoustic side) — —

lined Dual mode (line side) — — 27 ms

T

Acoustic side
Line side (when CODEC or 16-bit linear data
interface is used)
Line side (m-law PCM used) 30

Condition

Min. Typ. Max. Unit

—

35

—

59–Tlined

dB

ms

White noise generator

L.P.F.

5kHz

Level meter

Noise Canceler Characteristics

Parameter

Noise Attenuation

Symbol

res White noise, voice band — 13 — dB

N

MSM7731

Analog

Analog Analog

RIN

Line or Acoustic

SOUT

Power supply voltage 3V
CODEC input gain = 1
CODEC out

ut gain = 1

EC

ROUT

(V

DD

SIN

= 2.7 V to 3.6 V, Ta = –25°C to +70°C)

Condition

Analog

Min. Typ. Max. Unit

T

D

Delay

Echo delay time

ATT

E.R.L

(echo return loss)

Measurement System Block Diagram

White noise generator

L.P.F.

5kHz

Analog

AIN LOUT

Power supply voltage 3V
CODEC input gain = 1
CODEC out

MSM7731

Analog

Level meter

NC

ut gain = 1

19/43

¡ Semiconductor MSM7731-01

TIMING DIAGRAM

Power-down Reset Timing

PDN/RST pin

PDN/RST control bit

Internal operation

PCMO, PCMEO
DOUT

Power-down Reset Setting Timing

SYNC (External clock)

BCLK (External clock)

t

PDND

t

RSTW

t

PDNH

Power-down Initial mode

Hi-Z

PDN/RST control bit

Control Timing

Pin/control bit

t

PARD

Internal operation

Note: Applies to the following pins/control bits:

LINEEN, SLPTHR, NCTHR, GLPADTHR, TPAD6-1, RPAD6-1, RST, ATHR, AATT,
AHLD, AHD, AGC, LTHR, LATT, LHLD, LHD, and LGC

t

PDNS

t

PARW

Internal processing

t

PARH

(Internal write)

20/43

¡ Semiconductor MSM7731-01

Digital Input Timing (Normal-sync)

BCLK

012345678910

t

BS

t

SB

t

WS

SYNC

PCMI
PCMEI

t

DS

MSB LSB

t

DH

Digital Input Timing (Short-frame-sync)

BCLK

SYNC

PCMI
PCMEI

012345678910

t

BS

t

SB

t

DS

t

WS

t

DH

MSB LSB

Digital Output Timing (Normal-sync)

BCLK

SYNC

PCMO
PCMEO

012345678910

t

BS

t

t

SB

WS

t

SDX

t

XD1

t

XD2

MSB LSB

Hi-Z

Digital Output Timing (Short-frame-sync)

BCLK

SYNC

PCMO
PCMEO

012345678910

t

BS

t

t

SB

WS

t

XD1

t

XD2

MSB LSB

Hi-Z

t

XD3

Hi-Z

t

XD3

Hi-Z

21/43

¡ Semiconductor MSM7731-01

Microcomputer Interface I/O Timing

M11

t

M9

t

M10

t

M8

t

B7 B5B6 B3B4 B1B2 B0

B7 B6

M6

M4

t

t

M5

t

M7

t

A5A6 A3A4 A1A2 A0 B5 B3B4 B1B2 B0

21 43 65 87 109 1211 1413 1615

M3

t

M1

t

M2

t

W/R

DEN

EXCK

DIN

DOUT

22/43

¡ Semiconductor MSM7731-01

[

]

[dB]

Rin input level vs. echo attenuation

(Measuring conditions) Rin signal : 5 kHz band white noise

E.R.L : –6dB
Delay time : 4ms
ATT, GC : OFF
Noise floor : –60dBm (P-message filter unused)

RIN input level vs. echo attenuation

45

40

35

30

25

20

15

Echo attenuation [dB]

10

5

0

–50 –45 –40 –35 –30 –25 –20 –15 –10

Rin input level

dBm

E.R.L. level vs. echo attenuation (with GLPAD)

(Measuring conditions) Rin signal : 5 kHz band white noise

Rin input level : –20dBm (with GLPAD=±0dB)

: –26dBm (with GLPAD=±6dB)
: –32dBm (with GLPAD=±12dB)
: –38dBm (with GLPAD=±18dB)

Delay time : 4ms
ATT, GC : OFF
Noise floor : –60dBm (P-message filter unused)

E.R.L vs. echo attenuation (with GLPAD)

45

40

35

30

25

GLPAD=±0dB
GLPAD=±6dB
GLPAD=±12dB
GLPAD=±18dB

20

15

Echo attenuation [dB]

10

5

0

–40 25

–35 –30 –25 –20 –15 –10 –5 0 5 10 15 20

E.R.L.

23/43

¡ Semiconductor MSM7731-01

]

]

Echo delay time vs. echo attenuation (Dual echo canceler mode/acoustic side)

(Measuring conditions) Rin signal : 5 kHz band white noise

Rin input level : –16dBm
E.R.L : –6dB
ATT, GC : OFF
Noise floor : –60dBm (P-message filter unused)

Echo delay time vs. echo attenuation

Dual echo canceler mode (acoustic side)

45
40
35
30
25
20
15
10

Echo attenuation [dB]

5
0

5

10 15 20 25 30 35 40 45 50 55 60

Echo delay time [ms

Echo delay time vs. echo attenuation (Dual echo canceler mode/line side)

(Measuring conditions) Rin signal : 5 kHz band white noise

Rin input level : –16dBm
E.R.L : –6dB
ATT, GC : OFF
Noise floor : –60dBm (P-message filter unused)

Echo delay time vs. echo attenuation

Dual echo canceler mode (line side)

45
40
35
30
25
20
15
10

Echo attenuation [dB]

5
0

5

10 15 20 25 30 35 40 45 50 55 60

Echo delay time [ms

24/43

¡ Semiconductor MSM7731-01

]

q

]

Echo delay time vs. echo attenuation (Single echo canceler mode)

(Measuring conditions) Rin signal : 5 kHz band white noise

Rin input level : –16dBm
E.R.L : –6dB
ATT, GC : OFF
Noise floor : –60dBm (P-message filter unused)

Echo delay time vs. echo attenuation

Single echo canceler mode

45
40
35
30
25
20
15
10

Echo attenuation [dB]

5
0

5

10 15 20 25 30 35 40 45 50 55 60

Echo delay time [ms

Slope filter frequency characteristic (with CODEC frequency characteristic)

(Measuring conditions) Rin input level : –16dBm

Noise floor : –60dBm (P-message filter unused)

Slope filter frequency characteristic

10

0

–10

–20

–30

Gain [dB]

–40

–50

–60

1 501 1001 1501 2001 2501 3001 3501

Fre

uency [Hz

25/43

¡ Semiconductor MSM7731-01

Echo Canceler Characteristics Data 1 (Line Echo, White Noise)

(Measuring conditions) Rin signal : 5 kHz band white noise

Rin input level : –20dBm
E.R.L : 0dB
ATT, GC : OFF
Noise floor : –60dBm (P-message filter unused)

Echo attenuation=40dB

Echo Canceler Characteristics Data 2 (Line Echo, Voice)

(Measuring conditions) Rin signal : Voice

Rin input level : about –20dBm
E.R.L : 0dB
ATT, GC : OFF
Noise floor : –60dBm (P-message filter unused)

Echo attenuation=34dB

Echo Canceler Characteristics Data 3 (Acoustic Echo, Voice)

(Measuring conditions) Rin signal : Voice

Rin input level : about –20dBm
Speaker output level : 80dBa (at 1m)
Distance from microphone and speaker: 5cm
GC : OFF
ATT, Noise Canceller : ON
Noise floor : –60dBm (P-message filter unused)

Echo attenuation=34dB

Measurement System Block Diagram (Acoustic Echo)

3V

R7

M7731

EC

SOUT SIN

AIN

AGSX

R9

22k

100

C9

RV1

10µ

734

C10

+

R8

2.2k

J1

MIC

1µ

MIC

RIN ROUT

AVFRO

APWI

AOUT

R13

R14

22k

22k

R15

1.2k

RV4

10k

C13

0.1µ

R16

C14

10k

0.1µ

U13

LM4861

1
2
3
4

AG AG

R17

470k

C15

8
7
6
5

10p

5V

J3
SP

SP

26/43

¡ Semiconductor MSM7731-01

FUNCTIONAL DESCRIPTION

Control Registers

Table 2 Control Register Map

Reg

Name

CR00000000

Address

A6 A5 A4 A3 A2 A1 A0

Contents

B7 B6 B5 B4 B3 B2 B1 B0

*PDN/RST

*RST *LINEEN CLKEN PCMEN PCMEEN OPE

*MCUSEL

*GLPADTHR

*SLPTHR *NCTHR

OPE

*ECSEL

R/W

R/W

R/WCR10000001 DMWR — — — —

R/WCR20000010 — — RPAD6 RPAD5 RPAD4 RPAD3 RPAD2 RPAD1

R/WCR30000011 — — TPAD6 TPAD5 TPAD4 TPAD3 TPAD2 TPAD1

R/WCR40000100 *LTHR — — *LHD LCLP *LHLD *LATT *LGC

R/WCR50000101 *ATHR — — *AHD ACLP *AHLD *AATT *AGC

R/WCR60000110 A15 A14 A13 A12 A11 A10 A9 A8

R/WCR70000111 A7 A6 A5 A4 A3 A2 A1 A0

*: Shared control bit with port (pin)
—: Reserved bit. Do not change the initial value ("0").

R/WCR80001000 D15 D14 D13 D12 D11 D10 D9 D8

R/WCR90001001 D7 D6 D5 D4 D3 D2 D1 D0

R/WCR10 0001010GPADA2 GPADA1 LPADA2 LPADA1 GPADL2 GPADL1 LPADL2 LPADL1

R/WCR11 0001011 READY — — — — — PCMSEL SYPDN

R/WCR12 0001100 — — — — — — — —

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¡ Semiconductor MSM7731-01

(1) CR0 (basic operating mode settings)

CR0

Initial value (*4)

B7

PDN/RST

0

B6

RST

0

B5

LINEEN

0

B4

CLKEN

0

B3

PCMEN

0

B2

PCMEEN

0

B1

OPE

MCUSEL

0

B0

OPE

ECSEL

0

Note: *4. Initial values are the values set when reset is activated by the PDN/

RST pin. (Initial values are also set in the same manner, except for

CR0-B7, when reset by the PDN/RST bit of B7).

B7.......... Power-down reset 0: power-on, 1: power-down reset

During power-down reset, this device enters the power-down state. At this
time, all control register bits and internal variables are reset. After power-down
reset is released, this device enters the initial mode. This bit is internally ORed
with the inverted PDN/RST signal.

B6.......... Reset control 0: normal operation, 1: reset

At reset, the coefficients for the echo canceler and noise canceler are reset.
Control register contents are preserved. While reset is being processed, there
is no sound. Use this bit in cases where the echo path changes (due to line
switching during a telephone conversation, etc.), or when resuming telephone
communicaion. This bit is internally ORed with the inverted RST signal.

B5.......... Line CODEC I/O control 0: ON, 1: OFF

When OFF, the line CODEC is in the power-down state, the line CODEC output
pin is at high impedance and line CODEC input pin is internally processed as
an idle pattern input. This bit is internally ORed with the LINEEN pin. When
the line CODEC is not used, this control results in low consumption of electrical
power.
This bit can only be set to "0" or "1" during power-down reset and the initial
mode.

B4.......... SYNC, BCLK output control 0: ON, 1: OFF

When OFF, the SYNC and BCLK output pins are in the high impedance state.
This control is valid when the CLKSEL pin is at a logic "0" and has selected the
internal clock mode. When the SYNC and BCLK clocks are not used externally,
this control results in low consumption of electrical power.
This bit can only be set to "0" or "1" during power-down reset and the initial
mode.

B3.......... PCM I/O control 0: ON, 1: OFF

When OFF, the PCMO output pin is in the high impedance state and the PCMI
input pin is internally processed as an idle pattern input. When the line digital
interface is not used, this control results in low consumption of electrical power.
This bit can only be set to "0" or "1" during power-down reset and the initial
mode.

B2.......... PCME I/O control 0: ON, 1: OFF

When OFF, the PCMEO output pin is in the high impedance state and the
PCMEI input pin is internally processed as an idle pattern input. When not
used for message output and memo recording, this control results in low
consumption of electrical power.
This bit can only be set to "0" or "1" during power-down reset and the initial
mode.

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¡ Semiconductor MSM7731-01

B1, B0 ... Operating mode selection

(0, 0): Initial mode

Approximately 200 ms after power-down reset is released, the initial mode is
entered.
Only in this mode can the contents of the internal default value store memory
be modified and CR0-B5 to CR0-B0, CR1-B7, CR11-B1 and CR11-B0 be set. In
this mode, digital signal output pins are at high impedance, digital communication
input pins are internally processed as idle pattern inputs, and neither the echo
canceler nor the noise canceler operates. This mode is skipped when the
MCUSEL pin is "1". This mode is released by setting the modes shown below.
Refer to the flowchart of Figure 5.

(1, 0): Dual echo canceler mode

The acoustic echo canceler, line echo canceler and other functions can be operated
by control from the control registers. Refer to Figure 6.
The initial setting for cancelable echo delay time is as follows:

Acoustic delay time (Tacoud) = 44 ms
Line delay time (Tlined) = 15 ms

(1, 1): Single echo canceler mode

The acoustic echo canceler and other functions can be operated by control from
the control registers. Control of the line echo canceler is unnecessary in this
mode. Refer to Figure 7.

(Other): Reserved bit (cannot be used)

Initial mode

Note: The MCUSEL pin is internally ORed with B1, and the ECSEL pin is

internally ORed with B0. To return to the initial mode after it has been
released, activate power-down reset.

Power-down reset

Power-down state

Power-down reset release

Wait for 200 ms

• Control registers are reset

• Internal variables are reset

Set control register

Modify default store memory

CR0–B1=1

YES

Start normal operation

NO

Note: During the initial mode, the READY bit

(CR11-B7) is "1", at all other times it is "0".

Acoustic
CODEC

Acoustic
Echo
Canceler

Noise
Canceler

Slope
Filter

Line
Echo
Canceler

Line
CODEC

Figure 6 Dual Echo Canceler Mode

Acoustic
CODEC

Acoustic
Echo
Canceler

Noise
Canceler

Slope
Filter

Line
CODEC

Figure 5 Initial Mode Flowchart

Figure 7 Single Echo Canceler Mode

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¡ Semiconductor MSM7731-01

(2) CR1

CR1

Initial value

B7

DMWR

0

B6

—

0

B5

—

0

B4

—

0

B3

—

0

B2

GLPADTHR

0

B1

SLPTHR

0

B0

NCTHR

0

B7.......... Internal data memory write control 0: write inhibited, 1: write

In internal data memory, the data set in CR8 (D15 to D8) and CR9 (D7 to D0) is
written to the memory address set in CR6 (A15 to A8) and CR7 (A7 to A0).
Writing is possible only during the initial mode.

For further details, refer to the internal data memory access method.
B6, B5, B4, B3 .. Reserved bits Modification of initial values is inhibited

B2.......... Echo canceler I/O PAD control 0: "through mode", 1: normal mode

This bit controls the attenuators (LPADL/A) provided in the SinL/A inputs

and the amplifiers (GPADL/A) provided in the SoutL/A outptus of the echo

canceler. Levels are set by the CR10 register. Use this bit when the echo return

loss (value of returned echo) is amplified. This bit is internally ORed with the

GLPADTHR pin.

B1.......... Slope filter control 0: normal mode (slope filter operation), 1: "through mode"

This bit controls operation of the transmit slope filter. In the "through mode",

the filter is halted and data is output directly. This bit is internally ORed with

the SLPTHR pin.

B0.......... Noise canceler control 0: normal mode (noise canceler operation), 1: "through mode"

This bit controls operation of the noise canceler. In the "through mode", the

noise canceler is halted and data is output directly. This bit is internally ORed

with the NCTHR pin. If this bit is changed to the normal mode, approximately

20 ms of data dropout will occur.

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¡ Semiconductor MSM7731-01

(3) CR2 (Receive side level control)

CR2

Initial value

B7

—

0

B6

—

0

B5

RPAD6

0

B4

RPAD5

0

B3

RPAD4

0

B2

RPAD3

0

B1

RPAD2

0

RPAD1

B7, B6 ... Reserved bits Modification of initial values is inhibited

B5, B4, B3, B2, B1, B0 ...... Receive side level setting (RPAD)

These bits adjust the receive signal gain and set the mute level. Notice that only

the mute level setting differs from pin control.

When using this register, set the RPAD4, 3, 2, 1 pins to a logic "0".

(0, 0, 1, 0, 1, 0): 30 dB
(0, 0, 1, 0, 0, 1): 27 dB
(0, 0, 1, 0, 0, 0): 24 dB
(0, 0, 0, 1, 1, 1): 21 dB
(0, 0, 0, 1, 1, 0): 18 dB
(0, 0, 0, 1, 0, 1): 15 dB
(0, 0, 0, 1, 0, 0): 12 dB
(0, 0, 0, 0, 1, 1): 9 dB
(0, 0, 0, 0, 1, 0): 6 dB
(0, 0, 0, 0, 0, 1): 3 dB
(0, 0, 0, 0, 0, 0): 0 dB
(1, 1, 1, 1, 1, 1): –3 dB
(1, 1, 1, 1, 1, 0): –6 dB
(1, 1, 1, 1, 0, 1): –9 dB
(1, 1, 1, 1, 0, 0): –12 dB
(1, 1, 1, 0, 1, 1): –15 dB
(1, 1, 1, 0, 1, 0): –18 dB
(1, 1, 1, 0, 0, 1): –21 dB
(1, 1, 1, 0, 0, 0): –24 dB
(1, 1, 0, 1, 1, 1): –27 dB
(1, 1, 0, 1, 1, 0): –30 dB
(1, 1, 0, 1, 0, 1): –33 dB
(1, 1, 0, 1, 0, 0): –36 dB
(1, 1, 0, 0, 1, 1): –39 dB
(1, 1, 0, 0, 1, 0): –42 dB
(1, 1, 0, 0, 0, 1): –45 dB
(1, 1, 0, 0, 0, 0): –48 dB
(1, 0, 1, 1, 1, 1): –51 dB
(1, 0, 1, 1, 1, 0): –54 dB
(1, 0, 1, 1, 0, 1): –57 dB
(1, 0, 1, 1, 0, 0): –60 dB
(1, 0, 1, 0, 1, 1): MUTE

B0

0

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¡ Semiconductor MSM7731-01

(4) CR3 (Transmit side level control)

CR3

Initial value

B7

—

0

B6

—

0

B5

TPAD6

0

B4

TPAD5

0

B3

TPAD4

0

B2

TPAD3

0

B1

TPAD2

0

TPAD1

B7, B6 ... Reserved bits Modification of initial values is inhibited

B5, B4, B3, B2, B1, B0 ...... Transmit side level setting (TPAD)

These bits adjust the transmit signal gain and set the mute level. Notice that

only the mute level setting differs from pin control.

When using this register, set the RPAD4, 3, 2, 1 pins to a logic "0".

(0, 0, 1, 0, 1, 0): 30 dB
(0, 0, 1, 0, 0, 1): 27 dB
(0, 0, 1, 0, 0, 0): 24 dB
(0, 0, 0, 1, 1, 1): 21 dB
(0, 0, 0, 1, 1, 0): 18 dB
(0, 0, 0, 1, 0, 1): 15 dB
(0, 0, 0, 1, 0, 0): 12 dB
(0, 0, 0, 0, 1, 1): 9 dB
(0, 0, 0, 0, 1, 0): 6 dB
(0, 0, 0, 0, 0, 1): 3 dB
(0, 0, 0, 0, 0, 0): 0 dB
(1, 1, 1, 1, 1, 1): –3 dB
(1, 1, 1, 1, 1, 0): –6 dB
(1, 1, 1, 1, 0, 1): –9 dB
(1, 1, 1, 1, 0, 0): –12 dB
(1, 1, 1, 0, 1, 1): –15 dB
(1, 1, 1, 0, 1, 0): –18 dB
(1, 1, 1, 0, 0, 1): –21 dB
(1, 1, 1, 0, 0, 0): –24 dB
(1, 1, 0, 1, 1, 1): –27 dB
(1, 1, 0, 1, 1, 0): –30 dB
(1, 1, 0, 1, 0, 1): –33 dB
(1, 1, 0, 1, 0, 0): –36 dB
(1, 1, 0, 0, 1, 1): –39 dB
(1, 1, 0, 0, 1, 0): –42 dB
(1, 1, 0, 0, 0, 1): –45 dB
(1, 1, 0, 0, 0, 0): –48 dB
(1, 0, 1, 1, 1, 1): –51 dB
(1, 0, 1, 1, 1, 0): –54 dB
(1, 0, 1, 1, 0, 1): –57 dB
(1, 0, 1, 1, 0, 0): –60 dB
(1, 0, 1, 0, 1, 1): MUTE

B0

0

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¡ Semiconductor MSM7731-01

(5) CR4 (Line echo canceler settings)

CR4

Initial value

B7

LTHR

0

B6

—

0

B5

—

B4

LHD

0

0

B3

LCLP

0

B2

LHLD

0

B1

LATT

0

B0

LGC

0

B7.......... "Through mode" control 1: "through mode", 0: normal mode (echo cnaceler operation)

This is the "through mode" control bit for the line echo canceler. In the "through

mode", RinL and SinL data is output directly to RoutL and SoutL respectively.

Coefficients are not reset.

This bit is internally ORed with the LTHR pin.
B6, B5 ... Reserved bits Modification of initial values is inhibited

B4.......... Howling detector control 1: OFF, 0: ON

This bit controls the function to detect and cancel the howling that occurs in an

acoustic system such as a handsfree communication system.

This bit is internally ORed with the LHD pin.

B3.......... Center clip control 1: ON, 0: OFF

When the SoutL output of the line echo canceler is –57 dBm0 or less, the center

clip function forcibly sets it to the minimum positive value.

B2.......... Coefficient update control 1: fixed coefficients, 0: updated coefficients

This bit selects whether the adaptive FIR filter (AFR) coefficients for the line

echo canceler will be updated.

This bit is internally ORed with the LHLD pin.

B1.......... Attenuator control 1: ATT OFF, 0: ATT ON

This bit turns ON or OFF the ATT function to prevent howling by means of

attenuators (ATTsL, ATTrL) provided in the RinL input and SoutL output of

the line echo canceler.

If input is only to RinL, the ATT for SoutL (ATTsL) is activated. If input is only

to SinL, or if there is input to both SinL and RinL, the ATT for RinL input

(ATTrL) is activated. The ATT value of each attenuator is approximately 6 dB.

This bit is internally ORed with the LATT pin.

B0.......... Gain controller 1: GC OFF, 0: GC ON

This bit turns ON or OFF the gain control function to control the RinL input

level and prevent howling by means of a gain controller (GainL) provided in the

RinL input of the line echo canceler.

The gain controller adjusts the RIN input level when it is –10 dBm0 or above,

and it has the control range of 0 to –8.5 dB.

This bit is internally ORed with the LGC pin.

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¡ Semiconductor MSM7731-01

(6) CR5 (Acoustic echo canceler settings)

CR5

Initial value

B7

ATHR

0

B6

—

0

B5

—

B4

AHD

0

0

B3

ACLP

0

B2

AHLD

0

B1

AATT

0

B0

AGC

0

B7.......... "Through mode" control 1: "through mode", 0: normal mode (echo cnaceler operation)

This is the "through mode" control bit for the acoustic echo canceler. In the

"through mode", RinA and SinA data is output directly to RoutA and SoutA

respectively. Coefficients are not reset.

This bit is internally ORed with the ATHR pin.
B6, B5 ... Reserved bits Modification of initial values is inhibited

B4.......... Howling detector control 1: OFF, 0: ON

This bit controls the function to detect and cancel the howling that occurs in an

acoustic system such as a handsfree communication system.

This bit is internally ORed with the AHD pin.

B3.......... Center clip control 1: ON, 0: OFF

When the SoutA output of the acoustic echo canceler is –57 dBm0 or less, the

center clip function forcibly sets it to the minimum positive value.

B2.......... Coefficient update control 1: fixed coefficients, 0: updated coefficients

This bit selects whether the adaptive FIR filter (AFR) coefficients for the

acoustic echo canceler will be updated.

This bit is internally ORed with the AHLD pin.

B1.......... Attenuator control 1: ATT OFF, 0: ATT ON

This bit turns ON or OFF the ATT function to prevent howling by means of

attenuators (ATTsA, ATTrA) provided in the RinA input and SoutA output of

the acoustic echo canceler.

If input is only to RinA, the ATT for SoutA (ATTsA) is activated. If input is only

to SinA, or if there is input to both SinA and RinA, the ATT for RinA input

(ATTrA) is activated. The ATT value of each attenuator is approximately 6 dB.

This bit is internally ORed with the AATT pin.

B0.......... Gain controller 1: GC OFF, 0: GC ON

This bit turns ON or OFF the gain control function to control the RinA input

level and prevent howling by means of a gain controller (GainA) provided in

the RinA input of the acoustic echo canceler.

The gain controller adjusts the RIN input level when it is –10 dBm0 or above,

and it has the control range of 0 to –8.5 dB.

This bit is internally ORed with the AGC pin.

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¡ Semiconductor MSM7731-01

(7) CR6 (Internal data memory write register)

CR6

Initial value

B7

A15

0

B6

A14 A13 A12 A11 A10 A9 A8

0

B5

0

B7 to B0.......Memory upper address control

This register sets the upper address of memory. For the writing method, refer

to the Method of Internal Data Memory Access section.

(8) CR7 (Internal data memory write register)

CR7

Initial value

B7

A7

0

B6

A6 A5 A4 A3 A2 A1 A0

0

B5

0

B7 to B0.......Memory lower address control

This register sets the lower address of memory. For the writing method, refer

to the Method of Internal Data Memory Access section.

(9) CR8 (Internal data memory write register)

B4

B4

B3

0

0

0

B3

0

B2

0

B2

0

B1

0

B1

0

B0

0

B0

0

CR8

Initial value

B7

D15

0

B6

D14 D13 D12 D11 D10 D9 D8

0

B5

0

B7 to B0.......Memory upper data control

This register sets the memory's upper data. For the writing method, refer to the

Method of Internal Data Memory Access section.

(10) CR9 (Internal data memory write register)

CR9

Initial value

B7

D7

0

B6

D6 D5 D4 D3 D2 D1 D0

0

B5

0

B7 to B0.......Memory lower data control

This register sets the memory's lower data. For the writing method, refer to the

Method of Internal Data Memory Access section.

B4

B4

B3

0

0

0

B3

0

B2

0

B2

0

B1

0

B1

0

B0

0

B0

0

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¡ Semiconductor MSM7731-01

(11) CR10 (Echo canceler I/O level settings)

CR10

Initial value

B7

GPADA2

0

B6

GPADA1 LPADA2 LPADA1 GPADL2 GPADL1 LPADL2 LPADL1

0

B7, B6 ... Acoustic output level control

These bits control the PAD level of the gain of the acoustic echo canceler's SoutA

output. PAD is turned ON or OFF by either the GLPADTHR pin or the

GLPADTHR control register bit (CR1-B2). It is recommended to set the level to

the positive level equal to LPADA2 and LPADA1.

(0, 1) : +18 dB

(0, 0) : +12 dB

(1, 1) : +6 dB

(1, 0) : 0 dB
B5, B4 ... Acoustic input level control

These bits control the PAD level of the loss of the acoustic echo canceler's SinA

input. PAD is turned ON or OFF by either the GLPADTHR pin or the

GLPADTHR control register bit (CR1-B2). Set the level such that echo return

loss (value of returned echo) will be attenuated.

(0, 1) : –18 dB

(0, 0) : –12 dB

(1, 1) : –6 dB

(1, 0) : 0 dB
B3, B2 ... Line output level control

These bits control the PAD level of the gain of the line echo canceler's SoutL

output. PAD is turned ON or OFF by either the GLPADTHR pin or the

GLPADTHR control register bit (CR1-B2). It is recommended to set the level to

the positive level equal to LPADL2 and LPADL1.

(0, 1) : +18 dB

(0, 0) : +12 dB

(1, 1) : +6 dB

(1, 0) : 0 dB
B1, B0 ... Line input level control

These bits control the PAD level of the loss of the line echo canceler's SinL

output. PAD is turned ON or OFF by either the GLPADTHR pin or the

GLPADTHR control register bit (CR1-B2). Set the level such that echo return

loss (value of returned echo) will be attenuated.

(0, 1) : –18 dB

(0, 0) : –12 dB

(1, 1) : –6 dB

(1, 0) : 0 dB

B5

B4

0

0

B3

B2

0

0

B1

0

B0

0

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¡ Semiconductor MSM7731-01

(12) CR11 (SYNC power-down control register)

CR11

Initial value

B7

READY

0

B6

—

0

B5

—

0

B4

—

B3

—

0

0

B2

—

B1

PCMSEL

0

0

B0

SYPDN

0

B7.......... Data write flag 1: write enabled, 0: write disabled

After power-down reset is released, this device enters the initial mode.

This bit becomes "1" only during the initial mode, enabling access to the internal

data memory. Checking this bit will detect whether writing by an external

microcomputer is possible.

B6 to B2.......Reserved bits Modification of initial values is inhibited

B1.......... PCM coding format control 1: m-law PCM, 0: 16-bit linear

This is the coding format selection bit for digital data communication. A logic

"1" selects m-law PCM and a logic "0" selects 16-bit linear (2's complement)

coding format. When an internal clock is selected, the BCLK signal determines

the output clock frequency to be used when internal clock is selected.

If the digital interface is not used, set this bit to logic "0" to select 16-bit linear

coding format. Since this bit is ORed with the PCMSEL pin, set this bit to logic

"0" when controlling by the pin. If this bit setting is changed, reset must be

activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7).

B0.......... SYNC power-down 1: SYNC power-down ON, 0: SYNC power-down OFF

This bit turns ON or OFF the function that automatically enters the power-

down reset state when the SYNC signal is fixed to a logic "1" or "0". This function

is valid when the external clock mode has been selected by the CLKSEL pin. If

the SYNC signal is fixed at 8kHz or longer, this device automatically writes a

logic "1" to the control register PDN/RST bit (CR0-B7) and enters the power-

down reset state. For timing details, refer to the electrical characteristics.

(13) CR12 (Reserved register)

CR12

Initial value

B7

—

0

B6

—

0

B5

—

B4

—

0

0

B3

—

B2

—

0

0

B1

—

0

B7 to B0.......Reserved bits Modification of initial value is inhibited.

B0

—

0

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¡ Semiconductor MSM7731-01

RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS

In this device, the same function is controlled by either a pin or a control retister.
For example, when a function is controlled by a pin, setting of the corresponding control register
is important. Table 3 shows the relationship between settings of pins when functions are
controlled by control registers and settings of control registers when functions are controlled by
pins. The setting value of a control register when a function is controlled by a pin is equal to its
initial value when the device is reset by the PDN/RST pin or the PDN/RST bit (CR0-B7).

Table 3 Relationship between pins and control registers

Function

LINEEN 0Logic "0"

PDN/RST 0Logic "1"

PCMSEL 0Logic "0"

ECSEL 0Logic "0"

LTHR/ATHR 0Logic "0"

LHD/AHD 0Logic "0"

LHLD/AHLD 0Logic "0"

LATT/AATT 0Logic "0"

LGC/AGC 0Logic "0"

GLPADTHR 0Logic "0"

NCTHR 0Logic "0"

SLPTHR 0Logic "0"

RST 0Logic "1"

MCUSEL 0Logic "0"

RPAD4-1 0Logic "0"

TPAD4-1 0Logic "0"

Setting of pin when function is

controlled by control register

Setting of control register when

function is controlled by pin

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¡ Semiconductor MSM7731-01

Method of Internal Data Memory Access

So that the default values such as the cancelable echo delay time can be changed, contents of the
memory that stores default values can be modified during the initial mode (CR0-B1, CR0-B0 =
"00").
Refer to the procedure below.

1. Set the address of the default value store memory. (CR6, CR7)

2. Set the modified values (data). (CR8, CR9)

3. Set the write command. (CR1-B7 = "1")

After the write operation is complete, the write command (CR1-B7) is cleared to "0". Consecutive
writes are possible.

Echo Canceler Delay Time

Cancelable echo delay time is as follows.

(1) Single echo canceler mode

Acoustic echo canceler

Default: 59 ms

Variable range: 0.5 to 59 ms (in 0.5 ms steps)

Line echo canceler operation is halted.

(2) Dual echo canceler mode (operation of acoustic and line echo cancelers)

Condition: acoustic delay time + line delay time ≤ 59 ms

Acoustic echo canceler

Default: 44 ms

Variable range: 0.5 to 58.5 ms (in 0.5 ms steps)

Line echo canceler

Default: 15 ms

Variable range: 0.5 to 27 ms (in 0.5 ms steps)

Memory addresses are shown below.

(1) Single echo canceler mode

Memory address of acoustic echo canceler delay time: 009DH

(2) Dual echo canceler mode

Memory address of acoustic echo canceler delay time: 009BH
Memory address of line echo canceler delay time: 009CH

The method for calculating delay time is shown below.

delay time [s] ¥ 8000 = delay time data (HEX)

Example of 30 ms:

0.03 ¥ 8000 = 240 (DEC)
= 00F0 (HEX)

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¡ Semiconductor MSM7731-01

Noise Attenuation

There is a trade-off between noise attenuation and sound quality. In other words, increasing
the noise attenuation deteriorates sound quality, and decreasing the noise attenuation improves
sound quality. The following three types of noise attenuation levels can be selected with this
device.

Noise attenuation Sound quality
Type 1 approx. 13 dB (typ.) Typ.
Type 2 approx. 10 dB (typ.) Better than Type 1
Type 3 approx. 9 dB (typ.) Better than Type 2

Note: Only type 1 is compatible with pin control.

Memory address: 01C8H
Data to be stored:

Data
Type 1 2000H
Type 2 3333H
Type 3 4666H

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¡ Semiconductor MSM7731-01

NOTES ON USE

1. Use a stabilized power supply with a low level of noises (especially spike noises and pulse
noises of high frequencies) in order to prevent this device from malfunction or degradation
in characteristics.

2. Place a good characteristics of bypass-capacitor for the power supply near the pins of this
device in order to assure its electrical characteristics.

3. Place a good characteristics of bypass-capacitor for the analog signal ground (SG pin) near
the pins of this device in order to assure its electrical characteristics.

4. Connect the AGND, DGND1 and DGND2 to the system ground at a shortest distance and
in a low impedance state.

5. Use a separate power supply for an external speaker amplifier so as not to be disturbed by
externally generated noises.

6. When an external speaker amplifier is used, do gain adjusting without overflow (saturation)
of speaker amplifier output.
The overflow of speaker amplifier output decreases the echo attenuation.

7. Set the analog signal input level to less than 1.3VPP to prevent overflow.
Otherwise, voice will be distorted.

8. Set the echo return loss (ERL) to be attenuated. If the echo return loss is to be amplified, the
GLPAD function should be used.
The ERL refers to echo attenuation (loss) between the echo canceler output (RoutA/RoutL)
and the echo canceler input (SinA/SinL).
Refer to Characteristics Diagram for the ERL vs. echo attenuation.

9. The input level should be –10 to –20dBm0.
Refer to Characteristics Diagram for the RIN input level vs. echo attenuation.

10.Adjust the volume at the position of the echo canceler input (RinA/RinL).

When in Dual Echo Canceler mode : Adjust the volume with TPAD and RPAD.
When in Signal Echo Canceler mode : Adjust the volume with TPAD and RPAD, or

with the analog input (LIN) that is set at less
than 1.3VPP.

11. When the echo path is changed (when resuming telephone communication), reset the device
with the PDN/RST pin or the PDN/RST bit.

12. After turning on the power, be sure to reset the device with PDN/RST pin or the PDN/RST
bit.

13.In order to get the highest performance of this device, the following functions should be
used.

AATT/LATT : ON
AGC/LGC : ON

SLPTHR : Normal mode (slope filter operation)
NCTHR : Normal mode (noise canceler operation)
RPAD6-1 : Adjusting the volume of receive signal.
TPAD6-1 : Adjusting the volume of transmit signal.

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¡ Semiconductor MSM7731-01

APPLICATION CIRCUIT

Analog or Digital

CODEC

LINEAR

LINE

ECHO

CANCELER

A-outL

Rout

AFF

Rin

+

A-inL

Sin

Sout

PCMO

P/S&S/P

PCMI

PCMEO

PCMEI

Voice

MSM6679B

Processor

Recognition

cnt n

cnt 1

Memory

Vocabulary

TPAD

SLOPE

FILTER

NOISE

CANCELER

MSM7731-01

ACOUSTIC

ECHO

LINEAR

Sout

+

CANCELER

Sin

CODEC

A-inA

AFF

–

Rin

Rout

RPAD

A-outA

Speaker

amplifier

DEN

EXCK
DIN
DOUT

SYNC
SYNCSEL
BCLK
CLKSEL
PCMSEL

PDN/RST
MCK/X1

Clock Gen Timing Gen MCU I/F EC/NC/PAD control

X2

Microphone

Speaker (8W)

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¡ Semiconductor MSM7731-01

PACKAGE DIMENSIONS

(Unit : mm)

QFP64-P-1414-0.80-BK

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.87 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

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