Datasheet MSM7717-03MS-K, MSM7717-02MS-K, MSM7717-01GS-K, MSM7717-01MS-K, MSM7717-03GS-K Datasheet (OKI)

E2U0041-28-81

¡ Semiconductor MSM7717-01/02/03

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7717-01/02/03

Single Rail CODEC

GENERAL DESCRIPTION

The MSM7717 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400
Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is
optimized for ISDN terminals and telephone terminals in digital wireless systems.
The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output, which can drive a 1.2 kW load, can directly drive a handset receiver
differentially.

FEATURES

• Single power supply: 2.7 V to 3.8 V

• Low power consumption
Operating mode: 20 mW Typ. VDD = 3 V
Power-down mode: 0.03 mW Typ. VDD = 3 V

• Conforms to ITU-T Companding law

MSM7717-01: m/A-law pin selectable
MSM7717-02: m-law
MSM7717-03: A-law

• Built-in PLL eliminates a master clock

• Serial data rate: 64/128/256/512/1024 kHz

96/192/384/768/1536/1544/2048/200 kHz

• Adjustable transmit gain

• Adjustable receive gain

• Built-in reference voltage supply

• Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM7717-01GS-K)

(Product name: MSM7717-02GS-K)
(Product name: MSM7717-03GS-K)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: MSM7717-01MS-K)

(Product name: MSM7717-02MS-K)
(Product name: MSM7717-03MS-K)

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¡ Semiconductor MSM7717-01/02/03

BLOCK DIAGRAM

AIN–
AIN+

GSX

SGC

SG

VFRO

PWI

AOUT–

AOUT+

–
+

SG

GEN

RC

LPF

–
+

SG

–
+

SG

–
+

SG

8th

BPF

VR

GEN

5th

LPF

CONV.

DA

CONV.

PWD

AD

AUTO
ZERO

TCONT

PLL

RTIM

RCONT

PWD

Logic

PCMOUT

XSYNC

BCLK

RSYNC

(ALAW)

PCMIN

PDN
V

DD

AG
DG

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¡ Semiconductor MSM7717-01/02/03

PIN CONFIGURATION (TOP VIEW)

SG

AOUT+

AOUT–

NC

PWI

VFRO

NC

V

DD

DG

PDN

RSYNC

PCMIN

1

2

3

4

5

6

7

8

9

10

11

12 13

NC : No connect pin

24-Pin Plastic SOP

24

23

22

21

20

19

18

17

16

15

14

SGC

AIN+

AIN–

GSX

NC

NC

(ALAW)*

NC

AG

BCLK

XSYNC

PCMOUT

1

SG

AOUT+

AOUT–

VFRO

RSYNC

PCMIN

2

3

4

PWI

5

V

6

DD

7

DG

8

PDN

9

10 11

NC : No connect pin

20-Pin Plastic SSOP

20

19

18

17

16

15

14

13

12

SGC

AIN+

AIN–

GSX

NC

(ALAW)*

AG

BCLK

XSYNC

PCMOUT

* The ALAW pin is only supported by the MSM7717-01GS-K/MSM7717-01MS-K.

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¡ Semiconductor MSM7717-01/02/03

PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN–, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp.
The level adjustment should be performed in any method shown below. When not using AIN–
and AIN+, connect AIN– to GSX and AIN+ to SG. During power-saving and power-down
modes, the GSX output is at AG voltage.

1) Inverting input type

Analog input

2) Noninverting input type

Analog input

AG

Analog signal ground.

C1

C2

R5

R1

R3

R2

R4

GSX
AIN–
AIN+
SG

AIN+
AIN–
GSX

SG

R1 : variable

–
+

+
–

R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) (F)

Gain = R2/R1 < 10

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5) (F)

Gain = 1 + R4 / R3 £ 10

VFRO

Receive filter output.
The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage (SG)
when the digital signal of +3 dBm0 is input to PCMIN and can drive a load of 20 kW or more.
For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO
and PWI.
During power-saving mode this output is in a high impedance state, and during power-down
mode, the VFRO output is at an SG level.
When adjusting the receive signal on the basis of frequency characteristics, refer to the Frequency
Characteristics Adjustment Circuit.

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¡ Semiconductor MSM7717-01/02/03

PWI, AOUT+, AOUT–

PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT–. When the PWI pin is not used, the PWI pin to
the AOUT– pin, and leave the pins AOUT– and AOUT+ open. The output of AOUT+ is inverted
with respect to the output of AOUT–. Since these outputs provide differential drive of an
impedance of 1.2 kW, these outputs can directly be connected to a receiver of handset using a
piezoelectric earphone. Refer to the application example. Since the driver amplifiers are being
activated during the power-saving mode, the amplifiers can output other external signals from
AOUT+ and AOUT– pins. AOUT+ and AOUT– outputs are in a high impedance state during
the power-down mode.

External Signal Input

Receive filter

–
+

SG

–
+

SG

V

DD

VFRO

PWI

AOUT–

AOUT+

VI

R6

R7

Analog output

VO

Analog inverted output

ZL

ZL > 1.2 k

R6 > 20 kW

Gain = VO/VI = R7/R6 £ 1

W

Power supply for 2.7 V to 3.8 V. (Typically 3.0 V)

PCMIN

PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
The power-saving state means that the reference voltage generator (VRGEN), PLL, and receive
driver amplifiers are in the operating mode and the other circuits are in the non-operating mode.

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¡ Semiconductor MSM7717-01/02/03

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be

synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the

AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this signal. This
synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device

operates in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.

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¡ Semiconductor MSM7717-01/02/03

DG

Ground for the digital signal circuits.
This ground is separate from the analog signal ground AG. The DG pin must be connected to the
AG pin on the printed circuit board to make a common analog ground AG.

PDN

Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.
Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output from
MSD in a sequential order.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down mode.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7717-03 (A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

+0

–0

–Full scale

PCMIN/PCMOUT

MSM7717-02 (m-law)

MSD

1000 0000

1111 1111

0111 1111

0000 0000

MSM7717-03 (A-law)

MSD

1010 1010

1101 0101

0101 0101

0010 1010

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¡ Semiconductor MSM7717-01/02/03

SG

Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.

The output drive current capability is ±200 mA.

This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power-saving or power-down mode.

SGC

Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.

ALAW

Control signal input of the companding law selection.
Only the MSM7717-01GS-K/7717-01MS-K has this pin. The CODEC will operate in the m-law
when this pin is at a logic "0" level and the CODEC will has this pin operate in the A-law when
this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the
pin is internally pulled down.

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¡ Semiconductor MSM7717-01/02/03

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Storage Temperature

Symbol

V

DD

V

AIN

V

DIN

T

STG

Condition

—

—

—

—

Rating

–0.3 to +7

–0.3 to VDD + 0.3

–0.3 to VDD + 0.3

–55 to +150

Unit

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Analog Input Voltage

High Level Input Voltage

Low Level Input Voltage

Symbol

DD

AIN

V

IH

IL

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

DD

1.4——Connect AIN– and GSXV

—0.45¥V

DD

—0V

64, 128, 256, 512, 1024,

Clock Frequency kHz

BCLKF

C

2048, 96, 192, 384, 768,

1536, 1544, 200

Sync Pulse Frequency

Clock Duty Ratio

Digital Input Rise Time

Digital Input Fall Time

Transmit Sync Pulse Setting Time

Receive Sync Pulse Setting Time

High Level Sync Pulse Width

Low Level Sync Pulse Width

PCMIN Setup Time

PCMIN Hold Time

Digital Output Load

Analog Input Allowable DC Offset

S

C

t

lr

PCMIN, PDN, ALAW

lf

XS

SX

RS

SR

WSH

WSL

DS

DH

DL

DL

V

off

UnitMax.Typ.Min.Condition

DD

V

V

V

°C

V3.83.02.7Voltage must be fixedV

°C+85+25–30—TaOperating Temperature

V

PP

VV

V0.16¥V

kHz108.06.0XSYNC, RSYNCF

%605040BCLKD

ns50——XSYNC, RSYNC, BCLK,

ns50——t

ns——100BCLKÆXSYNC, See Fig. 1t

ns——100XSYNCÆBCLK, See Fig. 1t

ns——100BCLKÆRSYNC, See Fig. 1t

ns——100RSYNCÆBCLK, See Fig. 1t

ms——1 BCLKXSYNC, RSYNC, See Fig. 1t

ms——1 BCLKXSYNC, RSYNC, See Fig. 1t

ns——100See Timing Diagramt

ns——100See Timing Diagramt

kW——0.5Pull-up resistorR

pF100———C

mV+100—–100Transmit gain stage, Gain = 1

mV+10—–10Transmit gain stage, Gain = 10

ns1000——XSYNC, RSYNC, BCLK—Allowable Jitter Width

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¡ Semiconductor MSM7717-01/02/03

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

Parameter

Power Supply Current

High Level Input Voltage

Low Level Input Voltage

High Level Input Leakage Current

Low Level Input Leakage Current

Digital Output Low Voltage

Digital Output Leakage Current

Input Capacitance

Symbol

I

DD1

I

DD2

I

DD3

V

IH

V

IL

I

IH

I

IL

V

OL

I

O

C

IN

Operating mode

No signal

Power-saving mode, PDN = 1,

BCLK or XSYNC Æ OFF

Power-down mode, PDN = 0,

BCLK OFF

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

Pull-up resistor > 500 W

= 2.7 V to 3.8 V, Ta = –30°C to +85°C)

(V

DD

Condition

VDD = 3.8 V

Min.

—

Typ.

10

Max.

14

Unit

mA

VDD = 3.0 V

—

—

—

— 6.5 10.0

—

—

0.45¥V

0.0

—

—

0.0

—

DD

2.0

0.005

—

—

—

—

0.2

—

8.0

0.05

V

DD

0.16¥V

2.0

0.5

0.4

10

mA

mA

DD

mA

mA

mA

— —5—pF

V

V

V

10/19

¡ Semiconductor MSM7717-01/02/03

Transmit Analog Interface Characteristics

(V

= 2.7 V to 3.8 V, Ta = –30°C to +85°C)

DD

Parameter

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

Symbol

R

INX

R

LGX

C

LGX

V

OGX

V

OSGX

Condition Min. Typ. Max. Unit

AIN+, AIN–

GSX with respect to SG

Gain = 1

10

20

—

–0.7

–20

—

—

—

—

—

—

—

30

+0.7

+20

MW

kW

pF

V

mV

Receive Analog Interface Characteristics

= 2.7 V to 3.8 V, Ta = –30°C to +85°C)

(V

DD

Parameter

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

Symbol

R

INPW

R

LVF

R

LAO

C

LVF

C

LAO

V

OVF

V

OAO

V

OSVF

V

OSAO

PWI 10

VFRO with respect to SG

AOUT+, AOUT– (each) with

respect to SG

VFRO

AOUT+, AOUT–

VFRO, R

respect to SG

AOUT+, AOUT–, R

with respect to SG

VFRO with respect to SG

AOUT+, AOUT–, Gain = 1 with

respect to SG

Condition Min. Typ. Max. Unit

= 20 kW with

L

= 0.6 kW

L

20

0.6

—

—

–1.0

–1.0

–100

–100

—

—

—

—

—

—

—

—

—

—

—

—

30

50

+1.0

+1.0

+100

+100

MW

kW

kW

pF

pF

V

V

mV

mV

11/19

¡ Semiconductor MSM7717-01/02/03

AC Characteristics

Parameter

Transmit Frequency Response

Receive Frequency Response

Transmit Signal to Distortion Ratio 1020 dB

Symbol

Loss T1

Loss T2

Loss T3

Loss T4

Loss T5

Loss T6

Loss R1

Loss R2

Loss R3

Loss R4

Loss R5

SD T1 35 43 —3

SD T2 35 41 —0

SD T3 35 38 —–30

SD T4 28 30 —–40

Freq.

(Hz)

60 20 26 —

300 –0.15 +0.07 +0.2

1020 Reference

2020 –0.15 –0.01 +0.2

3000 –0.15 +0.15 +0.2

3400 0 0.4 0.8

300 –0.15 –0.03 +0.2

1020 Reference

2020 –0.15 –0.02 +0.2 dB0

3000 –0.15 +0.15 +0.25

3400 0 0.56 0.8

(FS = 8 kHz, V

Level

(dBm0)

DD

Condition

*1

= 2.7 V to 3.8 V, Ta = –30°C to +85°C)

Min. Typ. Max. Unit

dB0

SD T5 23 25 —–45

SD R1 36 43 —3

SD R2 36 41 —0

SD R3 36 40 —–30

Receive Signal to Distortion Ratio 1020 dB

Transmit Gain Tracking

Receive Gain Tracking

SD R4

SD R5

GT T1 –0.3 +0.01 +0.3

GT T2 Reference

GT T3 1020 –0.3 0 +0.3 dB–40

GT T4 –0.6 –0.03 +0.6

GT T5 –1.2 +0.15 +1.2

GT R1 –0.3 –0.06 +0.3

GT R2 Reference

GT R3 1020 –0.3 –0.02 +0.3 dB

GT R4 –0.6 –0.02 +0.6

GT R5 –1.2 –0.27 +1.2

3

–10

–50

–55

3

–10

–40

–50

–55

*1

30

*2

29

25

*2

24

33.5
—–40

32

30

—–45

27

*1 Psophometric filter is used.
*2 Upper columns are specified for the m-law, lower for the A-law.

12/19

¡ Semiconductor MSM7717-01/02/03

AC Characteristics (Continued)

Parameter

Idle Channel Noise

Absolute Level (Initial Difference)

Absolute Level

(Deviation of Temperature and Power)

Absolute Delay

Transmit Group Delay

Receive Group Delay

Crosstalk Attenuation

Symbol

Nidle T

Nidle R

AV T 0.338 0.35 0.362

AV R 0.483 0.5 0.518

AV Tt –0.2 — +0.2

AV Rt –0.2 — +0.2

Td 1020 — — 0.6 ms0

tGD T1

tGD T2

tGD T3

tGD T4

tGD T5

tGD R1

t

GD

t

GD

t

GD

t

GD

CR T 7580—

CR R 76

R2

R3

R4

R5

(FS = 8 kHz, V

Freq.

(Hz)

Level

(dBm0)

Condition

AIN = SG

——

— –76.5

—

—

V

DD

= 2.7 V to 3.8 V, Ta = –30°C to +85°C)

DD

Min. Typ. Max. Unit

–72.5

*2

*1

*1 *3

— –74

–70.5

= 3.0 V

–68

Ta = 25°C

*4

1020

V

0

= 2.7 V

DD

to 3.8 V

Ta = –30

*4

to 85°C

A to A

BCLK

= 64 kHz

500

600

1000

2600

2800

500

600

1000

2600

2800

*5

*5

TRANS Æ RECV

— 0.19 0.75

— 0.11 0.35

— 0.02 0.1250

— 0.05 0.125

— 0.75

0.07

— 0.00 0.75

— 0.35

0.00

— 0.00 0.125 ms0

— 0.09 0.125

— 0.12 0.75

1020 dB0

RECV Æ TRANS

70 —

dBm0p

Vrms

dB

dB

ms

*1 Psophometric filter is used.
*2 Upper column is specified for the m-law, lower for the A-law.
*3 Input "0" code to PCMIN.
*4 AVR is defined at VFRO output.
*5 With respect to minimum value of the group delay distortion

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¡ Semiconductor MSM7717-01/02/03

AC Characteristics (Continued)

Parameter

Symbol

Freq.

(Hz)

4.6 kHz to

Discrimination 0

DIS

72 kHz

300 to

S

3400

fa = 470

IMD

fd = 320

Digital Output Delay Time

PSR T

PSR R

t

SD

t

XD1

t

XD2

t

XD3

0 to

50 kHz

CL = 100 pF + 1 LSTTL

Level

(dBm0)

*6 Measured under idle channel noise.

(FS = 8 kHz, V

Condition

0 to

4000 Hz

4.6 kHz to

100 kHz

*6

PP

= 2.7 V to 3.8 V, Ta = –30°C to +85°C)

DD

Min. Typ. Max. Unit

30 32 — dB

— –37.5 –35 dBm0Out-of-band Spurious 0

— –52 –35 dBm0Intermodulation Distortion –4 2fa – fd

—30—dBPower Supply Noise Rejection Ratio 50 mV

20 — 200

20 — 200

20 — 200

20 — 200

ns

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¡ Semiconductor MSM7717-01/02/03

TIMING DIAGRAM

PCM Data Input/Output Timing

Transmit Timing

BCLK 12345678910

XSYNC

t

XS

t

XD1

t

t

SD

t

SX

WSH

PCMOUT D2 D3 D4 D5 D6 D7 D8MSD

When t
When t

£ 1/2 • Fc, the Delay of the MSD bit is defined as t

XS

£ 1/2 • Fc, the Delay of the MSD bit is defined as tSD.

SX

Receive Timing

BCLK

RSYNC

t

RS

12345678910

t

SR

t

WSH

PCMIN MSD

t

WSL

t

XD2

t

WSL

t

DS

t

DH

t

D2 D3 D4 D5 D6 D7 D8

XD3

XD1

.

Figure 1 Basic Timing

15/19

¡ Semiconductor MSM7717-01/02/03

APPLICATION CIRCUIT

+3 V

MSM7717-01

51 kW

Analog input

Analog inverted output*

Analog output*

0 V

+3 V

0 to 10 W

10 mF

0.1 mF

51 kW

+

0.1 mF

1 mF

AIN–

GSX

AIN+

SG

AOUT+

AOUT–

PWI

VFRO

SGC

AG

V

DD

PCMOUT

XSYNC

RSYNC

BCLK

PCMIN

ALAW

PDN

DG

PCM signal output

8 kHz SYNC signal input

PCM shift clock input
PCM data

Control of companding law
1: A-law
0: m-law

Power down control input
1: Normal operation
0: Power down

* These output signals have amplitudes above and below the offset level of VDD/2.

FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT

MSM7717-XX

AIN–

GSX

AIN+

SG

AOUT+

AOUT–

PWI

Transmit frequency
characteristic
Adjustment determined by
C1, C2, R1 and R2

Receive frequency
characteristic
Adjustment determined by
C3, C4, R3 and R4

M

Microphone amp

C1

R5

C2

C4

R1

R2

R4

R3 C3

VFRO

16/19

¡ Semiconductor MSM7717-01/02/03

NOTES ON USE

• To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the device pins.

• Connect the AG pin and the DG pin as close as possible. Connect to the system ground with
low impedance.

• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the
use of IC socket is unavoidable, use the short lead type socket.

• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
sources such as power supply transformers surround the device.

• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch­up that may otherwise occur when power is turned on.

• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.

17/19

¡ Semiconductor MSM7717-01/02/03

PACKAGE DIMENSIONS

(Unit : mm)

SOP24-P-430-1.27-K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.58 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

18/19

¡ Semiconductor MSM7717-01/02/03

(Unit : mm)

SSOP20-P-250-0.95-K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.18 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

19/19