Datasheet MSM7716GS-K, MSM7716TS-K Datasheet (OKI)

E2U0043-28-82

¡ Semiconductor MSM7716

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7716

Single Rail Linear CODEC

GENERAL DESCRIPTION

The MSM7716 is a single-channel CODEC CMOS IC for voice signals that contains filters for linear A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, the device is optimized for applications for the analog interfaces of audio signal processing DSPs and digital wireless systems. The analog output signal can directly drive a ceramic type handset receiver. In addition, levels for analog outputs can be set by external control.

FEATURES

• Single power supply : +2.7 V to +3.6 V

• Low power consumption Operating mode : 24 mW Typ. Power down mode : 0.05 mW Typ.

• Digital signal input/output interface : 14-bit serial code in 2's complement format

• Sampling frequency(fs) : 4 to 16 kHz

• Transmission clock frequency : fs ¥ 14 min., 2048 kHz max.

• Filter characteristics : when fs = 8 kHz, complies with ITU-T Recommen-

dation G. 714

• Built-in PLL eliminates a master clock

• Two input circuits in transmit section

• Two output circuits in receive section

• Transmit gain adjustable using an external resistor

• Receive gain adjustable by external control 8 steps, 4 dB/step

• Transmit mic-amp is eliminated by the gain setting of a maximum of 36 dB.

• Analog outputs can drive a load of a minimum of 1 kW ; an amplitude of a maximum of 4.0 V with push-pull driving.

• Built-in reference voltage supply

• Package options: 32-pin plastic TSOP (TSOPI32-P-814-0.50-1K) (Product name : MSM7716TS-K) 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name : MSM7716GS-K)

PP

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¡ Semiconductor MSM7716

BLOCK DIAGRAM

MAO

MAIN

PBO

PBIN

– +

SW 1

SW 2

RC

LPF

8th

BPF

14 BIT

ADCONV

AUTO ZERO

TCONT

PLL

PCMOUT

SYNC

SW 4

– +

SG

GEN

SW 4

SGC SG

VFO

AUXO

PWI

AOUT–

AOUT+

SW 3

VOL

– +

SW 3

VR

GEN

RC

LPF

5th

LPF

14 BIT

DACONV

PWD

SW CONT

VOL CONT

RTIM

RCONT

PWD logic

CONT Logic

BCLK

PCMIN

PDN

DEN CDIN DCLK

V

DD

AG DG

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¡ Semiconductor MSM7716

PIN CONFIGURATION (TOP VIEW)

1

MAIN

2

MAO

3

NC

4

NC

5

PBO

6

PBIN

7

NC

8

SGC

9

AG

10

AUXO AOUT+ AOUT–

AOUT+ AOUT–

11 12 13

NC

14

NC

15

PWI

16 17

VFO V

NC : No connect pin

32-Pin Plastic TSOP

1

AG

2

AUXO

3 4 5

PWI

6

VFO

7

NC

8

NC

9

NC

10

V

DD

11

DCLK

12

NC

13

CDIN

14

DEN

15 16

DG PCMIN

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18

30 29 28 27 26 25 24 23 22 21 20 19 18 17

PDN SYNC NC NC NC BCLK PCMOUT PCMIN DG DEN CDIN NC NC NC DCLK

DD

SGC PBIN PBO NC NC MAO MAIN NC NC PDN SYNC NC BCLK PCMOUT

NC : No connect pin

30-Pin Plastic SSOP

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¡ Semiconductor MSM7716

PIN AND FUNCTIONAL DESCRIPTIONS

MAIN, MAO

Transmit microphone input and the level adjustment. MAIN is connected to the noninverting input of the op-amp, and MAO is connected to the output of the op-amp. The level adjustment should be configured as shown below. During power saving and power down modes, the MAO output is in high impedance state.

R1 : variable R2 > 20 kW C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) (F)

Gain = R2/R1 < 63

Microphone input

C1

R1

R2

MAO MAIN

– +

SG

PBIN, PBO

Transmit handset input and the level adjustment. PBIN is connected to the noninverting input of the op-amp, and PBO is connected to the output of the op-amp. The level adjustment should be configured as shown below. During power saving and power down, the PBO output is in high impedance state.

Handset microphone input

V

DD

C2

R3

R4

PBO PBIN

– +

SG

R3 : variable R4 > 20 kW C2 > 1/(2 ¥ 3.14 ¥ 30 ¥ R3) (F)

Gain = R4/R3 < 63

Power supply pin for +2.7 to 3.6 V (Typically 3.0 V).

AG

Analog signal ground.

DG

Ground pin for the digital signal circuits. This ground is separated from the analog signal ground in this device. The DG pin must be connected to the AG pin on the printed circuit board.

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¡ Semiconductor MSM7716

VFO

Receive filter output. The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage when the digital signal of +3 dBm0 is input to PCMIN. VFO can drive a load of 20 kW or more. This output can be externally controlled in the level range of 0 to –28 dB in 4 dB increments. During power saving or power down, VFO output is at the voltage level (VDD/2) of SG with a high impedance state.

PWI, AOUT+, AOUT–

PWI is connected to the inverting input of the receive driver. The receive driver output is connected to the AOUT– pin. Thus, a receive level can be adjusted with the pins PWI, AOUT–, and VFO described above. The output of AOUT+ is inverted with respect to the output of AOUT– with a gain of 1. The output signal amplitudes are a maximum of 2.0 VPP. These outputs, above and below the signal ground voltage (VDD/2), can drive a load of a minimum of 1 kW with push-pull driving (a load connected between AOUT+ and AOUT–). The output amplitudes are 4 VPP maximum during push-pull driving. These outputs can be mute controlled externally. These outputs are operational during power saving and output the SG voltage (VDD/2) in the high impedance state.

AUXO

Auxiliary receive filter output. The output signal is inverted with respect to the VFO output with a gain of 1. The output signal swings above and below the SG voltage (VDD/2), and can drive a minimum load of 0.5 kW with respect to the SG voltage. The output can be mute controlled externally. During power saving and power down, AUXO outputs the SG voltage (VDD/2) in the high impedance state.

BCLK

Shift clock signal input for PCMIN and PCMOUT. The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power-saving state.

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¡ Semiconductor MSM7716

SYNC

Synchronizing signal input. In the transmit section, the PCM output signal from the PCMOUT pin is output synchronously with this synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. In the receive section, 14 bits required are selected from serial input of PCM signals on the PCMIN pin by the synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK. When this signal frequency is 8 kHz, the transmit and receive section have the frequency characteristics specified by ITU-T G. 714. The frequency characteristics for 8 kHz are specified in this data sheet. For different frequencies of the SYNC signal, the frequency values in this data sheet should be translated according to the following equation:

Frequency values described in the data sheet

8 kHz

Setting this signal to logic "1" or "0" drives the device to power-saving state.

PCMIN

PCM signal input. A serial PCM signal input to this pin is converted to an analog signal synchronously with the SYNC signal and BCLK signal. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at a falling edge of the BCLK signal. The PCM signal is latched into the internal register when shifted by 14 bits. The top of the data (MSD) is identified at the rising edge of SYNC. The input signal should be input in the 14-bit 2's complement format. The MSD bit represents the polarity of the signal with respect to the signal ground.

¥ the SYNC frequency values to be actually used

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¡ Semiconductor MSM7716

PCMOUT

PCM signal output. The PCM output signal is output from MSD in sequential order, synchronously with the rising edge of the BCLK signal. MSD may be output at the rising edge of the SYNC signal, depending on the timing between BCLK and SYNC. This pin is in high impedance state except during 14-bit PCM output. It is also high impedance during power saving or power down mode. A pull-up resistor must be connected to this pin, because its output is configured as an open drain. The output coding format is in 14-bit 2's complement. The MSD represents a polarity of the signal with respect to the signal ground.

Table 1

Input/Output Level

+Full scale

+1

0

–1 1111 1111 1111 11

–Full scale

MSD 0111 1111 1111 11 0000 0000 0000 01 0000 0000 0000 00

1000 0000 0000 00

PCMIN/PCMOUT

PDN

Power down control signal input. A digital "L" level drives both transmit and receive circuits to a power down state. The control registers are set to the initial state.

SGC

Connection of a bypass capacitor for generating the signal ground voltage level. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin.

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¡ Semiconductor MSM7716

DEN, DCLK, CDIN

Serial control ports for the microcontroller interface. Writing data to the 8-bit control register enables control of the receive output level and the signal path. DEN is the "Enable" signal pin, DCLK is the data shift clock input pin, and CDIN is the control data input pin. When powered down (PDN = 0), the initial values are set as shown in Tables 2, 3, and 4. The initial values are held unless the control data is written after power-down release. The control data is shifted at the rising edge of the DCLK signal and latched into the internal control register at the rising edge of the DEN signal. When the microcontroller interface is not used, these pins should be connected to DG. The bit map of the 8-bit control register is shown below.

B7

SW1

B6

SW2

B5

SW3

B4

SW4

B3 —

B2

VOL1

B1

VOL2

B0

VOL3

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ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature

Symbol

V

DD

V

AIN

V

DIN

T

STG

Condition

AG = DG = 0 V AG = DG = 0 V AG = DG = 0 V

—

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage Operating Temperature Analog Input Voltage

High Level Input Voltage

Low

Level

Input Voltage

Clock Frequency

Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time

Sync Pulse Setting Time

High Level Sync Pulse Width *1 Low Level Sync Pulse Width *1 PCMIN Setup Time PCMIN Hold Time

Digital Output Load

DCLK Pulse Width

DEN Setting Time 1

DEN Setting Time 2

CDIN Setup Time CDIN Hold Time

Analog Input Allowable DC Offset

Allowable Jitter Width

Symbol

V

DD

Ta

V

AIN

V

IH

V

IL

F

C

F

S

D

C

t

Ir

t

If

tXS, t

RS

t

, t

SX

SR

t

WSH

t

WSL

t

DS

t

DH

R

DL

C

DL

t

WCL

t

WCH

t

CDL

t

DCL

t

CDH

t

DCH

t

CDS

t

CDH

V

off

—

Condition

— —

Gain = 1

SYNC, BCLK, PCMIN, PDN, DEN, DCLK, CDIN

BCLK

SYNC BCLK SYNC, BCLK, PCMIN, PDN, DEN, DCLK, CDIN BCLKÆSYNC, See Fig.1 SYNCÆBCLK, See Fig.1 SYNC, See Fig.1 SYNC, See Fig.1 1 BCLK — — — Refer to Fig.1 Refer to Fig.1 Pull-up resistor

— DCLK Low width, See Fig.2 DCLK High width, See Fig.2 DCLKÆDEN, See Fig.2 DENÆDCLK, See Fig.2 DCLKÆDEN, See Fig.2 DENÆDCLK, See Fig.2 See Fig.2 See Fig.2 Transmit gain stage, Gain = 0 dB Transmit gain stage, Gain = 20 dB SYNC, BCLK

Min.

2.7

–30

—

0.45 ¥ V

DD

0

14 ¥ Fs

4.0 40 — —

100 100

1 BCLK

100 100

0.5 — 50 50 50 50 50 50 50 50

–100

–10

—

Rating

–0.3 to +7.0 –0.3 to V –0.3 to V

–55 to +150

Typ.

3.0

+25

—

8.0 50 — — — — —

— — — — — — — — — — — — — — —

DD

+ 0.3 + 0.3

128 ¥ Fs

Max.

3.6

+85

1.4

V

DD

0.16 ¥ V

DD

16 60 50 50 — — —

— — —

100

— — — — — — — —

+100

+10

1000

Unit

V V V

°C

Unit

V

°C

V

PP

V

kHz

% ns ns ns ns —

ns ns

kW

pF

ns

mV mV

ns

*1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is

2048 kHz.

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¡ Semiconductor MSM7716

RECOMMENDED OPERATING CONDITIONS (Continued)

Parameter

Digital Output Delay Time

Symbol

t

SD

t

XD1

t

XD2

t

XD3

= 50 pF + 1 LSTTL

C

L

Pull-up resistor = 500 W

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

Parameter

Power Supply Current

High Level Input Voltage

Low Level Input Voltage

High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Input Capacitance

Symbol

I

DD1

I

DD2

I

DD3

V

IH

V

IL

I

IH

I

IL

V

OL

I

O

C

IN

Operating mode, No signal

Power-saving mode, PDN = 1, SYNC, BCLK Æ OFF

Power-down mode, PDN = 0

SYNC, BCLK, PCMIN, DEN, CDIN, DCLK, PDN

PCMOUT pull-up resistor = 500 W

Condition

(Fs = 8 kHz, V

Condition

V

DD

V

DD

— —

—

= 3.6 V = 3.0 V

Min.

20 20 20 20

= 2.7 V to 3.6 V, Ta = –30°C to +85°C)

DD

Min.

— —

—

0.45 ¥ V

DD

0.0

— —

0.0 —

Typ.

— — — —

Typ.

10.0

8.0

6.0

0.01

—

— —

0.2 —

Max.

100 100 100 100

Max.

17.0

13.0

11.0

0.05

V

DD

0.16 ¥ V

DD

2.0

0.5

0.4 10

Unit

mA mA

mA

mA mA

mA

— —5—pF

ns

V

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¡ Semiconductor MSM7716

Transmit Analog Interface Characteristics

Parameter

Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage

Symbol

R

MAIN, PBIN

INX

R

MAO, PBO with respect to SG

LGX

C

LGX

V

OGX

V

OSGX

Receive Analog Interface Characteristics

Parameter

Output Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

Symbol

R

OAO

R

OVO

R

LAO

R

LVO

C

LAO

V

OAO

V

OSA

AUXO, AOUT+, AOUT- — VFO — — 100 W AUXO, AOUT+, AOUT– (each) with respect to SG VFO with respect to SG Output open AUXO, AOUT+, AOUT–, VFO with respect to SG AUXO, AOUT+, AOUT–, VFO with respect to SG

(Fs = 8 kHz, V

= 2.7 V to 3.6 V, Ta = –30°C to +85°C)

DD

Condition Min. Typ. Max. Unit

Gain = 1

(Fs = 8 kHz, V

10 20 —

–0.7

–20

= 2.7 V to 3.6 V, Ta = –30°C to +85°C)

DD

— — — — —

— — 30

+0.7

+20

MW

kW

pF

V

mV

Condition Min. Typ. Max. Unit

0.5

20 —

–1.0

–100

—

— —

—

10

—

— 50

W

kW

pF

+1.0

+100VmV

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¡ Semiconductor MSM7716

AC Characteristics

Parameter

Overall Frequency Response

Transmit Frequency Response (Expected Value)

Receive Frequency Response (Expected Value)

Overall Signal to Distortion Ratio 1020 dB

Transmit Signal to Distortion Ratio (Expected Value)

Receive Signal to Distortion Ratio (Expected Value)

Symbol

Loss 1 Loss 2 Loss 3 Loss 4 Loss 5

Loss 6 Loss T1 Loss T2 Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Loss R2 Loss R3 Loss R4 Loss R5

SD 1 55.9 — —3 SD 2 55.9 — —0 SD 3 55.9 — —–10 SD 4 45.9 — —–20 SD 5 35.9 — —–30 SD 6 25.9 — —–40

SD 7 15.9 — —–50 SD T1 58 — —3 SD T2 58 — —0 SD T3 58 — —–10 SD T4 48 — —–20 SD T5 38 — —–30 SD T6 28 — —–40 SD T7 18 — —–50 SD R1 58 — — SD R2 58 — — SD R3 58 — — SD R4 48 — — SD R5 38 — — SD R6 28 — — SD R7 18 — —

Freq.

(Hz)

60 20 — —

300 –0.2 — +0.4 1020 Reference 2020 –0.2 — +0.4 3000 –0.2 — +0.4 3400 0 — 1.6

60 20 — —

300 –0.15 — +0.2 1020 Reference 2020 –0.15 — +0.2 3000 –0.15 — +0.2 3400 0 — 0.8

300 –0.15 — +0.2 1020 Reference 2020 –0.15 — +0.2 dB0 3000 –0.15 — +0.2 3400 0.0 — 0.8

1020 dB

(Fs = 8 kHz, V

Level

(dBm0)

3

0 –10 –20 –30 –40 –50

DD

Condition

Analog

to

Analog

to

Analog

*1

= 2.7 V to 3.6 V, Ta = –30°C to +85°C)

Min. Typ. Max. Unit

dB0

*1 Psophometric filter is used.

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¡ Semiconductor MSM7716

AC Characteristics (Continued)

Parameter

Overall Gain Tracking

Transmit Gain Tracking (Expected Value)

Receive Gain Tracking (Expected Value)

Symbol

GT 1 –0.4 +0.01 +0.4 GT 2 Reference GT 3 1020 –0.3 0.00 +0.8 dB GT 4 –1.3 –0.03 +1.3

GT 5 –1.6 –0.15 +1.6 GT T1 –0.3 +0.01 +0.3 GT T2 Reference GT T3 1020 –0.3 0.00 +0.3 dB GT T4 –0.6 –0.03 +0.6 GT T5 –1.2 +0.15 +1.2

GT R1 –0.3 –0.06 +0.3 GT R2 Reference GT R3 1020 –0.3 –0.02 +0.3 dB GT R4 –0.6 –0.02 +0.6 GT R5 –1.2 –0.27 +1.2

Freq.

(Hz)

(Fs = 8 kHz, V

Level

(dBm0)

3 –10 –40 –50 –55

DD

Condition

Analog

to

Analog

= 2.7 V to 3.6 V, Ta = –30°C to +85°C)

Min. Typ. Max. Unit

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¡ Semiconductor MSM7716

AC Characteristics (Continued)

Parameter

Overall Idle Channel Noise —

Transmit Idle Channel Noise (Expected Value) Receive Idle Channel Noise (Expected Value)

Symbol

Nidle A

Nidle T

Nidle R

AV T 0.338 0.350 0.362

Absolute Level (Initial Level)

AV R 0.483 0.500 0.518

Absolute Level (Deviation of Temperature and Power)

AV Tt –0.2 — +0.2

AV Rt –0.2 — +0.2

Absolute Delay

t

GD

Transmit Group Delay

Receive Group Delay

Crosstalk Attenuation

tGD T2 — — 0.1750ms*3

GD

tGD R1 t

GD

CR T 7585—

CR R 80

Freq.

(Hz)

(dBm0)

— — –70 –66

— — –76 –74

— –76

t

1020 — — 0.6 ms0

D

500

T1 — — 0.325

600 to 2600

T3 — 0.325

2800

500 to 2600

R2 2800

1020 dB0

(Fs = 8 kHz, V

Level

—

0

= 2.7 V to 3.6 V, Ta = –30°C to +85°C)

DD

Condition

AIN: no signal

*1

AIN: no signal

*1

V

= 3.0 V

DD

Ta = 25°C

*2

V

= +2.7

DD

to 3.6 V Ta = –30 to 85°C A to A BCLK = 64 kHz

*3

TRANS Æ RECV

RECV Æ TRANS

Min. Typ. Max. Unit

dBmOp

— –74

Vrms1020

dB

—t — 0.00 0.125 — 0.12 0.325

ms0

70 —

*1 Psophometric filter is used. *2 AVT is defined at MAO and PBO-PCMOUT.

AVR is defined at PCMIN-VFO. VOL = 0 dB

*3 Minimum value of the group delay distortion

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¡ Semiconductor MSM7716

AC Characteristics (Continued)

DIS

S

IMD

AUX

G

V2

G

V3

G

V4

G

V5

G

V6

G

V7

G

V8

Freq.

(Hz)

4.6 kHz to 72 kHz

300 to

3400 fa = 470 fb = 320

0 to

50 kHz

1020 0

(dBm0)

Parameter

Symbol

Discrimination 0

PSR T PSR R

G

VOL Gain Setting Value

*1 Measured inband.

(Fs = 8 kHz, V

Level

PP

Referenced

to 0 dB

setting

DD

Condition

0 to 4000 Hz

4.6 kHz to 100 kHz

*1

VFO to AUXO

Set at – 4 dB

–8 dB –12 dB –16 dB –20 dB –24 dB –28 dB

= 2.7 V to 3.6 V, Ta = –30°C to +85°C)

Min. Typ. Max. Unit

30 32 — dB

— –37.5 –35 dBm0Out-of-band Spurious 0

— –52 –40 dBm0Intermodulation Distortion –4 2fa – fb

—30—dBPower Supply Noise Rejection Ratio 50 mV

–1.0 0 +1.0Auxiliary Output Gain 1020 0

dB –5 –4 –3 –9 –8 –7

–13 –12 –11 –17 –16 –15

dB

–21 –20 –19 –25 –24 –23 –29 –28 –27

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¡ Semiconductor MSM7716

TIMING DIAGRAM

PCM Data Output Timing

Transmit Timing

BCLK 12345678910

SYNC

PCMOUT

t

XS

t

XD1

t

SD

When t When t

t

SX

t

WSH

t

XD2

D2 D3 D4 D5 D6 D7 D8

£ 1/2 • Fc, the Delay of the MSD bit is defined as t

XS

< 1/2 • Fc, the Delay of the MSD bit is defined as tSD.

SX

Receive Timing

BCLK

t

SYNC

PCMIN

12345678910

RS

t

SR

t

WSH

t

DS

DH

D2 D3 D4 D5 D6 D7 D8

Figure 1 Basic Timing Diagram

MCU Interface Timing

11

12 13 14 15 16 17

t

WSL

t

XD3

D9 D10 D11 D12 D13 D14MSD

.

XD1

11 12 13 14 15 16 17

t

WSL

D9 D10 D11 D12 D13 D14MSD

DCLK

DEN

t

CDL

1

2345678910111213

t

DCL

t

WCL

t

WCH

t

CDS

t

CDH

t

DCH

B3B4B5B6B7 B2 B1 B0CDIN

Figure 2 MCU Interface Timing Diagram

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FUNCTIONAL DESCRIPTION

Control Data Description

SW1, SW2 - - Control bits for the transmit speech path switch.

The AD converter input is selected according to the bit data shown in Table 2.

Table 2

State SW2 SW1 AD Converter Input Remarks

T1 0 0 No signal (muting state) — T2 0 1 Input signal to MAIN At initial setting T3 1 0 Input signal to PBIN — T4 1 1 Addition signal of both MAIN and PBIN The gain of each input drops about 6 dB

SW3, SW4 - - Control bits for the receive speech path switch.

The control should be performed according to Table 3.

Table 3

State SW3 AOUT+, AOUT– Output AUXO Output

DA: DA converter output. SG: signal ground voltage.

SW4

R1 0 SG SG R2 1 PWI SG R3 0 SG DA R4 1 PWI DA

0 0 1 1

VOL1, VOL2, VOL3 - - - Control bits for the receive signal output level.

By controlling these bits, the output levels of VFO and AUXO can be controlled according to Table 4.

Table 4

VOL1 VOL2 VOL3 Receive Signal Gain Remarks

0 0 0 0 dB At initial setting 0 0 1 –4 dB — 0 1 0 –8 dB — 0 1 1 –12 dB — 1 0 0 –16 dB — 1 0 1 –20 dB — 1 1 0 –24 dB — 1 1 1 –28 dB —

Remarks

—

At initial setting

— —

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¡ Semiconductor MSM7716

APPLICATION CIRCUIT

Microphone analog input

Handset analog input

Addition signal input

Analog output* Analog inverted

output* Auxiliary output*

0 V

+3 V

1 mF

10 mF

0 to 10 W

20 kW

+

20 kW

0.1 mF

1 mF

MSM7716

MAIN

MAO

PBIN

PBO

VFO

PWI

AOUT–

AOUT+

AUXO

SGC

AG

DG

V

DD

PCMOUT

PCMIN

BCLK

SYNC

PDN

DCLK

DEN

CDIN

1 kW

+3 V

PCM output

PCM input

PCM shift clock input

8 kHz SYNC pulse input

Power down control input "1" = Operation "0" = Power down

Controller

* The swing of the analog output signal is a maximum of ±1.0 V above and below the V

/2 offset level.

DD

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¡ Semiconductor MSM7716

APPLICATION INFORMATION

Digital pattern for 0 dBm0

The digital pattern for 0 dBm0 is shown below. (SYNC frequency = 8 kHz, signal frequency = 1 kHz)

S2 S3

SG

Sample No.

S1 S2 S3 S4 S5 S6 S7 S8

S1

MSD D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

S4

S5

S6 S7

0

1

0 1 0 1 0 0 1

0

1

0

1

0

1

0

1

S8

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1 0 0 1 0 1 1 0

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¡ Semiconductor MSM7716

NOTES ON USE

• To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins.

• Connect the AG pin and the DG pin as close as possible. Connect to the system ground with low impedance.

• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the use of IC socket is unavoidable, use the short lead type socket.

• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave sources such as power supply transformers surround the device.

• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup that may otherwise occur when power is turned on.

• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.

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¡ Semiconductor MSM7716

PACKAGE DIMENSIONS

(Unit : mm)

TSOPI32-P-814-0.50-1K

Mirror finish

Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)

Epoxy resin 42 alloy Solder plating 5 mm or more

0.27 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

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¡ Semiconductor MSM7716

(Unit : mm)

SSOP30-P-56-0.65-K

Mirror finish

Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)

Epoxy resin 42 alloy Solder plating 5 mm or more

0.19 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

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