The MSM7716 is a single-channel CODEC CMOS IC for voice signals that contains filters for
linear A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is
optimized for applications for the analog interfaces of audio signal processing DSPs and digital
wireless systems.
The analog output signal can directly drive a ceramic type handset receiver. In addition, levels
for analog outputs can be set by external control.
FEATURES
• Single power supply: +2.7 V to +3.6 V
• Low power consumption
Operating mode: 24 mW Typ.
Power down mode: 0.05 mW Typ.
• Digital signal input/output interface: 14-bit serial code in 2's complement format
SGC
PBIN
PBO
NC
NC
MAO
MAIN
NC
NC
PDN
SYNC
NC
BCLK
PCMOUT
NC : No connect pin
30-Pin Plastic SSOP
3/22
Page 4
¡ SemiconductorMSM7716
PIN AND FUNCTIONAL DESCRIPTIONS
MAIN, MAO
Transmit microphone input and the level adjustment.
MAIN is connected to the noninverting input of the op-amp, and MAO is connected to the output
of the op-amp. The level adjustment should be configured as shown below.
During power saving and power down modes, the MAO output is in high impedance state.
Transmit handset input and the level adjustment.
PBIN is connected to the noninverting input of the op-amp, and PBO is connected to the output
of the op-amp. The level adjustment should be configured as shown below.
During power saving and power down, the PBO output is in high impedance state.
Power supply pin for +2.7 to 3.6 V (Typically 3.0 V).
AG
Analog signal ground.
DG
Ground pin for the digital signal circuits.
This ground is separated from the analog signal ground in this device. The DG pin must be
connected to the AG pin on the printed circuit board.
4/22
Page 5
¡ SemiconductorMSM7716
VFO
Receive filter output.
The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage when
the digital signal of +3 dBm0 is input to PCMIN. VFO can drive a load of 20 kW or more.
This output can be externally controlled in the level range of 0 to –28 dB in 4 dB increments.
During power saving or power down, VFO output is at the voltage level (VDD/2) of SG with a
high impedance state.
PWI, AOUT+, AOUT–
PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Thus, a receive level can be adjusted
with the pins PWI, AOUT–, and VFO described above.
The output of AOUT+ is inverted with respect to the output of AOUT– with a gain of 1.
The output signal amplitudes are a maximum of 2.0 VPP.
These outputs, above and below the signal ground voltage (VDD/2), can drive a load of a
minimum of 1 kW with push-pull driving (a load connected between AOUT+ and AOUT–).
The output amplitudes are 4 VPP maximum during push-pull driving. These outputs can be
mute controlled externally. These outputs are operational during power saving and output the
SG voltage (VDD/2) in the high impedance state.
AUXO
Auxiliary receive filter output.
The output signal is inverted with respect to the VFO output with a gain of 1. The output signal
swings above and below the SG voltage (VDD/2), and can drive a minimum load of 0.5 kW with
respect to the SG voltage.
The output can be mute controlled externally.
During power saving and power down, AUXO outputs the SG voltage (VDD/2) in the high
impedance state.
BCLK
Shift clock signal input for PCMIN and PCMOUT.
The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit
and receive circuits to the power-saving state.
5/22
Page 6
¡ SemiconductorMSM7716
SYNC
Synchronizing signal input.
In the transmit section, the PCM output signal from the PCMOUT pin is output synchronously
with this synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all
timing signals of the transmit section.
In the receive section, 14 bits required are selected from serial input of PCM signals on the PCMIN
pin by the synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK.
When this signal frequency is 8 kHz, the transmit and receive section have the frequency
characteristics specified by ITU-T G. 714. The frequency characteristics for 8 kHz are specified in
this data sheet.
For different frequencies of the SYNC signal, the frequency values in this data sheet should be
translated according to the following equation:
Frequency values described in the data sheet
8 kHz
Setting this signal to logic "1" or "0" drives the device to power-saving state.
PCMIN
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal synchronously with the
SYNC signal and BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal. The PCM signal is latched into the
internal register when shifted by 14 bits.
The top of the data (MSD) is identified at the rising edge of SYNC.
The input signal should be input in the 14-bit 2's complement format.
The MSD bit represents the polarity of the signal with respect to the signal ground.
¥ the SYNC frequency values to be actually used
6/22
Page 7
¡ SemiconductorMSM7716
PCMOUT
PCM signal output.
The PCM output signal is output from MSD in sequential order, synchronously with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the SYNC signal, depending on the timing between
BCLK and SYNC.
This pin is in high impedance state except during 14-bit PCM output. It is also high impedance
during power saving or power down mode.
A pull-up resistor must be connected to this pin, because its output is configured as an open
drain.
The output coding format is in 14-bit 2's complement.
The MSD represents a polarity of the signal with respect to the signal ground.
Power down control signal input.
A digital "L" level drives both transmit and receive circuits to a power down state.
The control registers are set to the initial state.
SGC
Connection of a bypass capacitor for generating the signal ground voltage level.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.
7/22
Page 8
¡ SemiconductorMSM7716
DEN, DCLK, CDIN
Serial control ports for the microcontroller interface.
Writing data to the 8-bit control register enables control of the receive output level and the signal
path.
DEN is the "Enable" signal pin, DCLK is the data shift clock input pin, and CDIN is the control
data input pin.
When powered down (PDN = 0), the initial values are set as shown in Tables 2, 3, and 4. The initial
values are held unless the control data is written after power-down release.
The control data is shifted at the rising edge of the DCLK signal and latched into the internal
control register at the rising edge of the DEN signal.
When the microcontroller interface is not used, these pins should be connected to DG.
The bit map of the 8-bit control register is shown below.
B7
SW1
B6
SW2
B5
SW3
B4
SW4
B3
—
B2
VOL1
B1
VOL2
B0
VOL3
8/22
Page 9
¡ SemiconductorMSM7716
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
V
DD
V
AIN
V
DIN
T
STG
Condition
AG = DG = 0 V
AG = DG = 0 V
AG = DG = 0 V
—
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Analog Input Voltage
High Level Input Voltage
Low
Level
Input Voltage
Clock Frequency
Sync Pulse Frequency
Clock Duty Ratio
Digital Input Rise Time
Digital Input Fall Time
Sync Pulse Setting Time
High Level Sync Pulse Width *1
Low Level Sync Pulse Width *1
PCMIN Setup Time
PCMIN Hold Time
Digital Output Load
DCLK Pulse Width
DEN Setting Time 1
DEN Setting Time 2
CDIN Setup Time
CDIN Hold Time
Analog Input Allowable DC Offset
Allowable Jitter Width
Symbol
V
DD
Ta
V
AIN
V
IH
V
IL
F
C
F
S
D
C
t
Ir
t
If
tXS, t
RS
t
, t
SX
SR
t
WSH
t
WSL
t
DS
t
DH
R
DL
C
DL
t
WCL
t
WCH
t
CDL
t
DCL
t
CDH
t
DCH
t
CDS
t
CDH
V
off
—
Condition
—
—
Gain = 1
SYNC, BCLK, PCMIN, PDN,
DEN, DCLK, CDIN
BCLK
SYNC
BCLK
SYNC, BCLK, PCMIN, PDN,
DEN, DCLK, CDIN
BCLKÆSYNC, See Fig.1
SYNCÆBCLK, See Fig.1
SYNC, See Fig.1
SYNC, See Fig.11 BCLK———
Refer to Fig.1
Refer to Fig.1
Pull-up resistor
—
DCLK Low width, See Fig.2
DCLK High width, See Fig.2
DCLKÆDEN, See Fig.2
DENÆDCLK, See Fig.2
DCLKÆDEN, See Fig.2
DENÆDCLK, See Fig.2
See Fig.2
See Fig.2
Transmit gain stage, Gain = 0 dB
Transmit gain stage, Gain = 20 dB
SYNC, BCLK
Min.
2.7
–30
—
0.45 ¥
V
DD
0
14 ¥ Fs
4.0
40
—
—
100
100
1 BCLK
100
100
0.5
—
50
50
50
50
50
50
50
50
–100
–10
—
Rating
–0.3 to +7.0
–0.3 to V
–0.3 to V
–55 to +150
Typ.
3.0
+25
—
—
—
—
8.0
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DD
DD
+ 0.3
+ 0.3
128 ¥ Fs
Max.
3.6
+85
1.4
V
DD
0.16 ¥
V
DD
16
60
50
50
—
—
—
—
—
—
100
—
—
—
—
—
—
—
—
+100
+10
1000
Unit
V
V
V
°C
Unit
V
°C
V
PP
V
V
kHz
kHz
%
ns
ns
ns
ns
—
ns
ns
kW
pF
ns
ns
ns
ns
mV
mV
ns
*1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is
2048 kHz.
9/22
Page 10
¡ SemiconductorMSM7716
RECOMMENDED OPERATING CONDITIONS (Continued)
Parameter
Digital Output Delay Time
Symbol
t
SD
t
XD1
t
XD2
t
XD3
= 50 pF + 1 LSTTL
C
L
Pull-up resistor = 500 W
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
Parameter
Power Supply Current
High Level Input Voltage
Low Level Input Voltage
High Level Input Leakage Current
Low Level Input Leakage Current
Digital Output Low Voltage
Digital Output Leakage Current
Input Capacitance
AUXO, AOUT+, AOUT-—
VFO——100W
AUXO, AOUT+, AOUT– (each)
with respect to SG
VFO with respect to SG
Output open
AUXO, AOUT+, AOUT–, VFO
with respect to SG
AUXO, AOUT+, AOUT–, VFO
with respect to SG
(Fs = 8 kHz, V
= 2.7 V to 3.6 V, Ta = –30°C to +85°C)
DD
ConditionMin.Typ.Max.Unit
Gain = 1
(Fs = 8 kHz, V
10
20
—
–0.7
–20
= 2.7 V to 3.6 V, Ta = –30°C to +85°C)
DD
—
—
—
—
—
—
—
30
+0.7
+20
MW
kW
pF
V
mV
ConditionMin.Typ.Max.Unit
0.5
20
—
–1.0
–100
—
—
—
—
—
—
10
—
—
50
W
kW
kW
pF
+1.0
+100VmV
11/22
Page 12
¡ SemiconductorMSM7716
AC Characteristics
Parameter
Overall Frequency Response
Transmit Frequency Response
(Expected Value)
Receive Frequency Response
(Expected Value)
Overall Signal to Distortion Ratio1020dB
Transmit Signal to Distortion Ratio
(Expected Value)
Receive Signal to Distortion Ratio
(Expected Value)
Symbol
Loss 1
Loss 2
Loss 3
Loss 4
Loss 5
Loss 6
Loss T1
Loss T2
Loss T3
Loss T4
Loss T5
Loss T6
Loss R1
Loss R2
Loss R3
Loss R4
Loss R5
Absolute Level
(Deviation of Temperature and Power)
AV Tt–0.2—+0.2
AV Rt–0.2—+0.2
Absolute Delay
t
GD
Transmit Group Delay
Receive Group Delay
Crosstalk Attenuation
tGD T2——0.1750ms*3
GD
tGD R1
t
GD
CR T7585—
CR R80
Freq.
(Hz)
(dBm0)
——–70–66
——–76–74
—–76
t
1020——0.6ms0
D
500
T1——0.325
600 to 2600
T3—0.325
2800
500 to 2600
R22800
1020dB0
(Fs = 8 kHz, V
Level
—
—
0
= 2.7 V to 3.6 V, Ta = –30°C to +85°C)
DD
Condition
AIN: no signal
*1
AIN: no signal
*1
V
= 3.0 V
DD
Ta = 25°C
*2
V
= +2.7
DD
to 3.6 V
Ta = –30
to 85°C
A to A
BCLK
= 64 kHz
*3
TRANS Æ RECV
RECV Æ TRANS
Min.Typ.Max.Unit
dBmOp
dBmOp
—–74
Vrms1020
dB
dB
—t
—0.000.125
—0.120.325
ms0
70—
*1Psophometric filter is used.
*2AVT is defined at MAO and PBO-PCMOUT.
AVR is defined at PCMIN-VFO.
VOL = 0 dB
*3Minimum value of the group delay distortion
14/22
Page 15
¡ SemiconductorMSM7716
AC Characteristics (Continued)
DIS
S
IMD
AUX
G
V2
G
V3
G
V4
G
V5
G
V6
G
V7
G
V8
Freq.
(Hz)
4.6 kHz to
72 kHz
300 to
3400
fa = 470
fb = 320
0 to
50 kHz
10200
(dBm0)
Parameter
Symbol
Discrimination0
PSR T
PSR R
G
VOL Gain Setting Value
*1Measured inband.
(Fs = 8 kHz, V
Level
PP
Referenced
to 0 dB
setting
DD
Condition
0 to
4000 Hz
4.6 kHz to
100 kHz
*1
VFO to AUXO
Set at – 4 dB
–8 dB
–12 dB
–16 dB
–20 dB
–24 dB
–28 dB
= 2.7 V to 3.6 V, Ta = –30°C to +85°C)
Min.Typ.Max.Unit
3032—dB
—–37.5–35dBm0Out-of-band Spurious0
—–52–40dBm0Intermodulation Distortion–42fa – fb
—30—dBPower Supply Noise Rejection Ratio50 mV
–1.00+1.0Auxiliary Output Gain10200
dB
–5–4–3
–9–8–7
–13–12–11
–17–16–15
dB
–21–20–19
–25–24–23
–29–28–27
15/22
Page 16
¡ SemiconductorMSM7716
TIMING DIAGRAM
PCM Data Output Timing
Transmit Timing
BCLK12345678910
SYNC
PCMOUT
t
XS
t
XD1
t
SD
When t
When t
t
SX
t
WSH
t
XD2
D2D3D4D5D6D7D8
£ 1/2 • Fc, the Delay of the MSD bit is defined as t
XS
< 1/2 • Fc, the Delay of the MSD bit is defined as tSD.
SX
Receive Timing
BCLK
t
SYNC
PCMIN
12345678910
RS
t
SR
t
WSH
t
t
DS
DH
D2D3D4D5D6D7D8
Figure 1 Basic Timing Diagram
MCU Interface Timing
11
121314151617
t
WSL
t
XD3
D9 D10 D11 D12 D13 D14MSD
.
XD1
11121314151617
t
WSL
D9 D10 D11 D12 D13 D14MSD
DCLK
DEN
t
CDL
1
2345678910111213
t
DCL
t
WCL
t
WCH
t
CDS
t
t
CDH
CDH
t
DCH
B3B4B5B6B7B2B1B0CDIN
Figure 2 MCU Interface Timing Diagram
16/22
Page 17
¡ SemiconductorMSM7716
FUNCTIONAL DESCRIPTION
Control Data Description
SW1, SW2 - - Control bits for the transmit speech path switch.
The AD converter input is selected according to the bit data shown in Table 2.
Table 2
StateSW2SW1AD Converter InputRemarks
T100No signal (muting state)—
T201Input signal to MAINAt initial setting
T310Input signal to PBIN—
T411Addition signal of both MAIN and PBINThe gain of each input drops about 6 dB
SW3, SW4 - - Control bits for the receive speech path switch.
The control should be performed according to Table 3.
Table 3
StateSW3AOUT+, AOUT– OutputAUXO Output
DA: DA converter output. SG: signal ground voltage.
SW4
R10SGSG
R21PWISG
R30SGDA
R41PWIDA
0
0
1
1
VOL1, VOL2, VOL3 - - - Control bits for the receive signal output level.
By controlling these bits, the output levels of VFO and AUXO can be
controlled according to Table 4.
Power down control input
"1" = Operation
"0" = Power down
Controller
* The swing of the analog output signal is a maximum of ±1.0 V above and below the V
/2 offset level.
DD
18/22
Page 19
¡ SemiconductorMSM7716
APPLICATION INFORMATION
Digital pattern for 0 dBm0
The digital pattern for 0 dBm0 is shown below.
(SYNC frequency = 8 kHz, signal frequency = 1 kHz)
S2S3
SG
Sample No.
S1
S2
S3
S4
S5
S6
S7
S8
S1
MSD D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
0
0
1
0
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
0
1
1
1
0
S4
S5
S6S7
0
0
0
1
1
0
1
0
1
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
0
0
0
0
0
1
S8
1
0
1
0
1
0
1
1
0
1
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
1
1
1
1
1
0
1
1
0
0
0
0
0
1
0
1
0
0
1
0
1
1
0
19/22
Page 20
¡ SemiconductorMSM7716
NOTES ON USE
• To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin as close as possible. Connect to the system ground with
low impedance.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the
use of IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
sources such as power supply transformers surround the device.
• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup that may otherwise occur when power is turned on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.
20/22
Page 21
¡ SemiconductorMSM7716
PACKAGE DIMENSIONS
(Unit : mm)
TSOPI32-P-814-0.50-1K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
21/22
Page 22
¡ SemiconductorMSM7716
(Unit : mm)
SSOP30-P-56-0.65-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.19 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
22/22
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