The MSM7661B is an LSI device which converts digitally sampled NTSC or PAL video signals
to 8-bit format based on ITU-RBT601.
The input video signals available are composite video signals and S video signals.
The composite video signals are converted to YUV data via a 2-dimensional Y/C separation
circuit.
The A-to-D converted data is data sampled at pixel clock frequency or double pixel clock
frequency (the built-in decimation filter is used). Input signal synchronization can lock
synchronization and color burst at high speed through internal digital processing.
The MSM7661B is upward compatible with the MSM7661. It provides additional features which
are added to the MSM7661 indicated by the mark n and is superior to the MSM7661 in picture
quality and synchronization stability. The device, which includes an additional register added
to the MSM7661, has electrical characteristics which are nearly equal to those of the MSM7661.
The MSM7661B allows a pin-for-pin replacement with the MSM7661.
FEATURES (• indicates a new feature compared with MSM7660. n indicates a
new feature compared with MSM7661.)
• Input video signals include the following two types of digital data that are A-to-D converted
at pixel frequency or double pixel frequency :
NTSC/PAL composite video signal
NTSC/PAL S video signal
8-bit Y/8-bit C (CbCr) output (conforms to ITU-RBT601)
°
YCbCr4 : 2 : 2
YCbC4 : 1 : 1
n YCbCr 8-bit multiplex output (27 MHz) (not including SAV and EAV)
• 2-dimensional Y/C separation using adaptive comb filter (this filter is bypassed for S video
signal input)
NTSC: 3 lines/2 lines
PAL: 2 lines (3 virtual lines)
• Input signal synchronization can lock synchronization and color burst at high speed through
internal digital processing.
Sampling frequency
°
13.5 MHz (ITU-R601)
12.27 MHz (NTSC Square Pixel)
14.31818 MHz (NTSC 4Fsc)
14.75 MHz (PAL Square Pixel)
• Internal AGC/ACC circuit
Switchable between AGC and MGC (fixed gain)
n Switchable between ACC and MCC (fixed gain)
• Built-in decimation filter located in the input stage allows easy configuration of an external
filter circuit (located ahead of A/D converter).
• Automatic NTSC/PAL recognition (only for ITU-RBT.601)
• Sleep mode
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• Multiplex signal recognition (Teletext)
Data during vertical blanking is output in 8 bits in Through mode.
I2C-bus interface
°
• 3.3 V single power supply (each I/O pin is 5 V tolerable)
Chrominance signal input pin (valid only for S video input)
Description
Set each pin to "L" level at composite signal input.
9 to 16
CVBS[0 to 7]
Composite signal input pin
I
Luminance signal is input for S video input.
17
18
19
20
21 to 24
V
DD
GND
SCL
SDA
MODE[0 to 3]
2
I
C-bus clock pin
I
2
C-bus data pin
I
I/O
Mode input pins. These pins are internally pulled-down.
I
MODE[3]0: composite
MODE[2]0: NTSC
1: S video
MODE[1:0]00: ITU-R601
01: Square Pixel
10: 4Fsc (only for NTSC)
11: none
If ITU-R signals are input when registers are set to automatic NTSC/PAL
recognition mode, NTSC/PAL is automatically recognized irrespective of
MODE2 setting.
CLKX2 Dutyt
Input Data Setup Timet
Input Data Hold Timet
Output Data Delay Time 1 (*)t
Output Data Delay Time 2 (*)t
Output Data Delay Time 3 (*)t
Output Clock Delay Time (*) (External)
Output Clock Delay Time (*) (Internal)
SCL Clock Cycle Timet
Low Level Cyclet
CLKX2 Dutyt
Input Data Setup Timet
Input Data Hold Timet
Output Data Delay Time 1 (*)t
Output Data Delay Time 2 (*)t
Output Data Delay Time 3 (*)t
Output Clock Delay Time (*) (External)
Output Clock Delay Time (*) (Internal)
SCL Clock Cycle Timet
Low Level Cyclet
The basic input/output timing of the I2C-bus interface is as follows.
SDA
SCL
S
Start Condition
Data Line Stable: Data Valid Change of Data Allowed
MSB
12789
ACK
12
t
C_SCL
I2C-bus Basic Input/Output Timing
3-8
9
ACK
P
Stop Condition
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BLOCK DESCRIPTION
1.Prologue Block
The prologue block performs Y/C separation by inputting data.
Data can be input either at ordinary pixel frequency (ITU-R : 13.5 MHz) or at double pixel
frequency (ITU-R: 27 MHz).
When the double pixel frequency is used, data is processed after changing to the ordinary pixel
frequency via a decimeter circuit.
By changing the register setting, the decimeter circuit can be bypassed irrespective of whether
data is input at ordinary pixel frequency or at double pixel frequency.
The prologue block performs Y/C separation using a 2-dimensional adaptive comb filter when
composite signals (CVBS) are input.
The following operation modes can be changed via the I2C-bus. The * mark indicates a default.
The default is a state that is selected when reset.
1) Video input mode select
Composite video input *
S video input
2) Video input mode select
Auto NTSC/PAL select* (Only for ITU-R601)
Dependent on Operation mode selected
When ITU-R601 is selected, the video input mode is automatically determined by the number
of lines per field.
4) Decimeter circuit pass/bypass select
Decimeter circuit is passed. *
Decimeter circuit is bypassed.
5) Y/C separation mode select
Adaptive comb filter is used. *
Unadaptive comb filter is used.
Trap filter is used.
The adaptive comb filter detects the correlation up to 3 lines between continuous lines. The Y/
C is separated by the comb filter according to the way of correlation if theses lines are correlated.
The Y/C is separated by the trap filter if these lines are not correlated (only 2 lines in the case of
PAL).
In the unadaptive comb filter, the Y/C is always separated by removing the luminance
component based on the average of preceding and following lines (when there is the correlation
between 3 lines).
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If the comb filter is not used, the Y/C is separated by the trap filter.
The Y/C separation circuit is bypassed by S video signal input.
In adittion, the functions of this block work only when lines are valid as image information.
The processing of CVBS signals is not made during V-blanking.
2.Luminance Block
The luminance block removes synchronous signals from the signals containing luminance
components after Y/C separation. The signals are corrected and output as luminance signals.
The luminance signal output level gain control functions include three selectable modes such as
AGC (Auto Gain Control), MGC (manual Gain Control) + No Clamp, and MGC + Pedestal
Clamp.
In the AGC mode, the luminance level amplification is determined by comparing the depth of
SYNC with the reference value. The default is 40IRE which can be changed by the register. The
input is a sync chip clamp type.
In the MGC + No Clamp mode, the luminance signal output level is not affected by the input, and
the amplification and black level are controlled by setting the register.
In the MGC + Pedestal Clamp mode, the signal output level is clamped to the pedestal level of
the input. The signal amplification and black level are controllable from the clamped point by
setting the register.
This block can select the follwing operation modes.
1) Use of prefilter and sharp filter
Used*
Not used
These filters are used for enhancing the edges of luminance component signals.
2) Selection of aperture bandpass filter coefficient
Middle range*
High range
3) Coring range select
off*
±4LBS
±5LBS
±7LBS
4) Aperture weighting factor select
0*
0.25
0.75
1.5
The profile of these signals can be corrected by coring and aperture correction.
5) Use of pixel position correction circuit
Used*
Not used
6) AGC loop filter time constant select
SlowFactor value 1/1024n
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Medium1/64n*
Fast1/n
Fixed0
7) Parameter for AGC reference level fine adjustment
8) Parameter for sync separation level fine adjustment
The black level is controlled. When the default is specified, the depestal position is output as a
black level (=16).
9) Pedestral clamp selecton
Pedestral clamp is not used.*
Pedestral clamp is used. (AGC will not operate)
3.Chrominance Block
This is a chroma signal processing block.
The following modes can be selected.
1) Use of color bandpass filter
Used*
Not used
2) ACC loop filter time constant select
SlowFactor value 1/1024n
Medium1/64n*
Fast1/n
Fixed0
3) ACC reference level fine adjustment
4) Parameter for burst level fine adjustment
The threshold level for valid chroma amplitude is selected based on a color burst ratio.
0.5
0.25*
0.125
off
5) Color killer mode select
Auto color killer mode*
Forcible color killer
6) Parameter for color subcarrier phase fine adjustment
In this block, chroma signals pass through the chroma bandpass filter to cut an unnecessary
band. To maintain a constant chroma level, UV demodulation is performed on these signals
via the ACC correction circuit. (This filter can be bypassed.)
If the demodulation result does not reach a specified level, color killer signals are generated
to fix the ACC gain. This functions as an auto color killer control circuit.
The UV demodulation result is output as chrominance signals via a low pass filter.
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4.Synchronization Block
This is a synchronizing signal processing block.
Chip output synchronizing signals and synchronizing signals for internal use are generated by
this block. Various signals are output in this block and the following operation modes can be
selected.
1) SYNC threshold level adjustment
2-1) Fine adjustment of HSY signal (start side)
2-2) Fine adjustment of HSY signal (stop side)
3) HSY signal enable select
High Level
Active*
These signal are used to sync chip and clamp timing to the A/D converter
4) Fine adjustment of HSYNC_L signal
5-1) Fine adjustment of HVALID signal (start side)
5-2) Fine adjustment of HVALID signal (stop side)
6-1) Fine adjustment of VVALID signal (start side)
6-2) Fine adjustment of VVALID signal (stop side)
The data signals are transmitted or received at the rising edge of the HVALID signal.
7) TV, VTR mode select
TV mode
VTR mode*
The TV mode outputs a fixed pixel number per one line and absorbs a jitter that does not appear
on the TV receiver normally.
The VTR mode outputs the results of decoding in accordance with the HSYNC signal regardless
of whether a jitter exists or not.
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5.Epilogue Block
The Epilogue Block outputs UV signals from the chrominance block and Y signals from the
luminance block in the format based on the signal obtained by setting of the control register.
In this block, the following modes can be selected.
1) Display of blue back when synchronization fails.
OFF
ON*
2) Output modes
2.1) ITUR 601 mode
Output signal Y/CbCr format select
YCbCr4 : 2 : 2*
YCbCr4 : 1 : 1
The chrominance signal (U, V component) outputs Cb and Cr data to the C pin in an
output format described later.
2.2) YCbCr 8-bit multiplex output mode
This mode does not include SAV and EAV.
3) Selection of 8-bit chroma signal output format
Offset binary*
2's Complement
4) Output pin enable select
High impedance
Output enable*
5) Multiplex signal detect level adjustment
The levels to detect multiplexed signals sent during the vertical blanking period are configured
to be variable. The binary values after input signals are A-to-D converted are employed as the
levels to detect multiplexed signals, and the levels are set in eight steps with respect to the SYNC
tip level.
Detect level
OMR [5:3]
80 to 136
video in
6) Various modes detection
NTSC/PAL detect mode*
Multiplex signal detect mode
HSYNC synchronization detect mode
7) Output signal phase control
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6.I2C Control Block
This is the serial interface block based on the I2C standard of Phillips Corporation.
This block functions only as a Slave-Receiver.
The external control can set the internal registers (MRA, MRB, HSYT, etc.).
7.Test Control Block
This block is used to test this LSI. Normally it is not used.
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Register Description
Registers controlled by I2C bus are shown below.
A register setting value with an "*" indicates the default.
Enter "0" to the undefined register when setting registers.
OPCY[1:0]Output phase control for data Y*00:normal
01:forward l clock
10:Undefined
11:Undefined
Output phase control for data C (OPCC) <default: 0x00>
OPCC[7:2]Undefined
OPCC[1:0]Output phase control for data C*00:normal
01:forward l clock
10:Undefined
11:Undefined
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[
FUNCTIONAL DESCRIPTION
Input Signal Level
Input signal is 8 bits in a straight binary format.
The recommended input range is shown below.
255
reserved
246
200
NTSC:60
(PAL:63)
Iuminance
input black level
sync
4
0
input sync-tip level
7:0] input range
CVBS
13
chrominance
+DC
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Output format
The YCbCr 4:2:2 format and 4:1:1 format are shown below.
The output format can be changed by register settings.
PIXEL BYTE SEQUENCEOUTPUT
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cr7
Cr6
Cr5
Cr4
Cr3
Cr2
Cr1
Cr0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb7
Cb6
Cb5
Cb4
Cb3
Cb2
Cb1
Cb0
Y7(MSB)
Y6
Y5
Y4
Y3
Y2
Y1
Y0(LSB)
C7(MSB)
C6
C5
C4
C3
C2
C1
C0(LSB)
Y point023451
C point024
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb7
Cb6
Cb5
Cb4
Cb3
Cb2
Cb1
Cb0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cr7
Cr6
Cr5
Cr4
Cr3
Cr2
Cr1
Cr0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb7
Cb6
Cb5
Cb4
Cb3
Cb2
Cb1
Cb0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cr7
Cr6
Cr5
Cr4
Cr3
Cr2
Cr1
Cr0
PIXEL BYTE SEQUENCEOUTPUT
Y7
Y7(MSB)
Y6
Y5
Y4
Y3
Y2
Y1
Y0(LSB)
C7(MSB)
C6
C5
C4
C3
C2
C1
C0(LSB)
Y point023451
C point04
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb7
Cb6
Cr7
Cr6
0
0
0
0
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb5
Cb4
Cr5
Cr4
0
0
0
0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb3
Cb2
Cr3
Cr2
0
0
0
0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb1
Cb0
Cr1
Cr0
0
0
0
0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb7
Cb6
Cr7
Cr6
0
0
0
0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Cb5
Cb4
Cr5
Cr4
0
0
0
0
Y7
Y7
Y6
Y6
Y5
Y5
Y4
Y4
Y3
Y3
Y2
Y2
Y1
Y1
Y0
Y0
Cb1
Cb3
Cb0
Cb2
Cr1
Cr3
Cr0
Cr2
0
0
0
0
0
0
0
0
67
YCbCr 4:2:2 formatYCbCr 4:1:1 format
YCbCr 8-bit multiplex output mode format
1T
CLKX2
HVALID
Y (7:0)
INVALID
Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3
Y717 Cb718 Y718 Cr718 Y719
INVALID
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TIMING DESCRIPTION
A/D Converter Support Signal
The timing wave form of HSY/HCL signals, which measure the sync chip and clamp timing for
the A/D converter, is as follows.
CVBS
HSY
A/D Converter Support Signal
Line control signal
The line control signal timing is as follows.
CLK
COLOR
BURST
CLKO
HVALID
Y0Y1Y2Y3Y(n)Y(n+1)Y[7:0]
Cb0Cr0Cb2Cr2Cb(n)Cr(n)C[7:0]
Line Control Timing
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Total Number of Pixels
The total number of pixels vary depending on the mode and frequency used, as shown below
(default values when typical signals are input).
Video and Sampling Mode
Video Mode
NTSC
—
PAL
—
—
Total
Pixels
Active
Pixels
HBLK Pixels
Front-porchSampling Rate
Hsync.Back-porch
Total
1381221613.5 MHz858720
1401122812.27 MHz (SQ)780640
142134814.32 MHz (4FSC)910768
1441301413.5 MHz864720
1761423414.75 MHz (SQ)944768
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Vertical Synchronizing Signal
The vertical synchronizing signal timing is as follows.
524525123456789 2122
CVBS
HVALID
HSYNC_L
VSYNC_L
SYNC
(CSYNC_L)
VVALID
ODD
CVBS
HVALID
HSYNC_L
VSYNC_L
SYNC
(CSYNC_L)
VVALID
ODD
262263264265266267268269270271283284285
Vertical Synchronizing Signal (NTSC 60 Hz)
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621622623624625123456 2324
CVBS
HVALID
HSYNC_L
SYNC
(CSYNC_L)
VSYNC_L
VVALID
ODD
309310311312313314315316317318336337338
CVBS
HVALID
HSYNC_L
SYNC
(CSYNC_L)
VSYNC_L
VVALID
ODD
Vertical Synchronizing Signal (PAL 50 Hz)
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Horizontal Synchronizing Signal
The horizontal synchronizing signal timing is as follows.
Y[7:0]
HVALID
HSYNC_L
60 pixels
Horizontal Timing
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I2C BUS FORMAT
The I2C-bus interface input format is shown below.
Slave AddressSSubaddressAData 0AA
Symbol
S
Slave Address
A
Subaddress
Data n
Start condition
Slave address 1000001X, 8th bit is write signal.
Acknowledge. Generated by slave
Subaddress byte
Data to write to address designated by subaddress.
Description
......
Data nAP
PStop condition
As mentioned above, the write operation can be executed from subaddress to subaddress
continuously. When the write operation is executed at subaddresses discontinuously, the
Acknowledge and Stop condition formats are input repeatedly after Data 0.
If one of the following matters occurs, the decoder will not return "A" (Acknowledge).
• The slave address does not match.
• A non-existent subaddress is specified.
• The write attribute of a register does not match "X" (read/write control bit).
The input timing is shown below.
SDA
SCL
S
Start Condition
Data Line Stable: Data Valid Change of Data Allowed
MSB
12789
I2C-bus Basic Input/Output Timing
ACK
12
t
C_SCL
3-8
9
ACK
P
Stop Condition
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OPERATION MODE SETTING
The video mode includes ;
1. Internal terminal mode to be directly set by a dedicated terminal
2. Register setting mode to be specified by setting the internal registers
These modes can be changed by the mode register MRA [4].
The reset state (default) is the external terminal mode.
The following registers can be set in the external terminal mode.
13.5 MHz13.5 MHz"H""1" (Unused)CLKX2O or CLKXO (13.5 MHz)
When the double speed clock is used, data can be input at a double speed or at an ordinary speed
by setting the internal register (MRB2) and the clock for the A/D converter.
The internal processing after decimation filter is performed at an ordinary speed.