Datasheet MSM7652GS-2K Datasheet (OKI)

Preliminary

¡ Semiconductor MSM7652

This version: Jun. 1998

¡ Semiconductor

MSM7652

NTSC/PAL Digital Video Encoder

GENERAL DESCRIPTION

The MSM7652 is a digital NTSC/PAL encoder. By inputting digital image data conforming to
ITU Rec. 656 or ITURBT 601, it outputs selected analog composite video signals, analog S video
signals or Y, R-Y, B-Y signals. For the scanning system, interlaced or noninterlaced mode can be
selected.
Since the MSM7652 is provided with pins dedicated to overlay function, text and graphics can
be superimposed on a video signal.
In addition, this encoder has an internal 10-bit DAC. So, when compared with using a conventional
analog encoder, the number of components, the board space, and points of adjustment can
greatly be reduced, thereby realizing a low cost and high-accuracy system.
The MSM7652 provides the optional functions such as Closed Caption Signal Generation
Function.
The host interface provided conforms to Philips's I2C specifications, which reduces
interconnections between this encoder and mounting components.
The internal synchronization signal generator (SSG) allows the MSM7652 to operate in master
mode.

FEATURES

• Video signal system: NTSC/PAL

• Scanning system: interlaced/noninterlaced (NTSC : 262 lines/PAL : 312 lines)

• Input digital level: conforms to ITU-R601 (CCIR601)

• Input-output timing: conforms to ITU Rec. 656 or ITURBT 624-4

• Input signal sampling ratio : Y:Cb:Cr = 4:2:2

• Supported input formats

· ITU Rec. 656

· YCbCr 27 MHz format (8-bit input)

· ITU-R601 13.5 MHz (8-bit (Y) + 8-bit (CbCr) input)

• Output video signals

· NTSC/PAL composite video signals and S video signals

· Y, R-Y, B-Y analog signals (selectable)

• Sampling frequency : 27 MHz

• Internal SSG circuit (Can operate as a master in other operation modes than CCIR Rec. 656
mode)

• Internal 3ch 10-bit DAC

• 3-bit title graphics can be displayed

• Color bar function

•I2C-bus host interface function

• 3.3 V single power supply (each I/O pin is 5 V tolerable)

• Closed caption function

• Package
56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name: MSM7652GS-2K)

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MSM7652 ¡ Semiconductor

APPLICATIONS

• Video CD

• Video game equipment

• Electronic still cameras

• Video file systems

• Video cameras

• Videophones

• Multimedia equipment

• Video printers

• Videoconferencing systems

• Scanners

• Video graphics boards

2

¡ Semiconductor MSM7652

3

BLOCK DIAGRAM

Sync Generator & Timing Controller

Prologue

Block

I2C Control logic Test Control logic

IPF

Overlay
Control

YUV color
Generator

RESET_L

Black &

Blank Pedestal

Interpolator

+ LPF

Interpolator

+ LPF

Color Burst

Generator

Y Level

converter

U Level

converter

V Level

converter

Closed

Caption

Block

OLC

OLG
OLB

CD[7:0]

CLKX2

MODE

CLKX1O CLKSEL

SCL SDA

ADRS

Subcarrier

Generator

TENB TEST1

CVBSO (B-Y)

MSSEL[2:1]

BLANK_L

HSYNC_L

VSYNC_L

YD[7:0]

OLR

DAC

IPF

YA (Y)

DAC

IPF

IPF = Interpolation Filter

CA (R-Y)

DAC

VREF

FS

OUTSEL

COMP

MSM7652 ¡ Semiconductor

PIN CONFIGURATION (TOP VIEW)

DV

DD

MS

SDA

SCL

ADRS

RESET_L

MODE

OLC

OLR

OLG

10

DD

AGND

YA (Y)

AV

DGND
56

55

54

53

1

2

3

4

5

6

7

8

9

DD

AV

CVBSO (B-Y)
52

51

AGND

CA (R-Y)
50

49

COMP
48

FS
47

VREF
46

TENB
45

TEST1
44

DGND
43

42

41

40

39

38

37

36

35

34

33

DV

DD

SEL2

SEL1

CLKSEL

CD0

CD1

CD2

CD3

CD4

CD5

OLB

CLKX1O

OUTSEL

DV

DD

11

12

13

14

15

DGND

16

17

VSYNC_L

HSYNC_L

18

19

20

YD6

YD7

BLANK_L

NC : No-connection pin

56-Pin Plastic QFP

21

NC

22

YD5

23

YD4

24

YD3

25

YD2

26

YD1

27

YD0

32

31

30

29

28

DGND

CD6

CD7

CLKX2

DV

DD

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¡ Semiconductor MSM7652

PIN DESCRIPTIONS (1/2)

Pin I/O Symbol Description

1DV

DD

2IMS
3 I/O SDA I2C interface data bus
4 I SCL I

5 I ADRS

6 I RESET_L System reset signal. Negative porality
7 I MODE Broadcasting mode select pin. "0" : NTSC/"1" : PAL. Pulled down
8 I OLC

9 I OLR Overlay text color (Red component)
10 I OLG Overlay text color (Green component)
11 I OLB Overlay text color (Blue component)
12 O CLKX1O 13.5 MHz divided clock output signal

13 I OUTSEL

14 DV

DD

15 DGND Digital GND

16 I/O VSYNC_L

17 I/O HSYNC_L

18 I BLANK_L

19, 20 I YD7 to YD6

21 NC Not connected

22 to 27 I YD5 to YD0

28 DGND Digital GND
29 DV

DD

30 I CLKX2 Clock input pin (27 MHz)

31 to 38 I/O CD7 to CD0

39 I CLKSEL

3.3 V digital power supply
Selects between Master and Slave at 27 MHz or 13.5 MHz YCbCr operation. Pulled down

2

C interface clock bus

2

C-bus Slave address setting pin ("0" : 1000100 / "1" : 1000110).

I
Pulled down

Transparent control signal. "1" indicates overlay signal. Normally fixed to "0".

. Normally fixed to "0".

. Normally fixed to "0".

. Normally fixed to "0".

Video output signal format select pin. "0" : Y/C & Composite signal,
"1" : Y/B-Y/R-Y (component) signal. Pulled down

3.3 V digital power supply

Vertical sync signal input/output pin (ITU656: O, YCbCr: I/O)
Negative polarity
Horizontal signal input/output pin (ITU656 : O, YCbCr: I/O)
Negative polarity
Composite blank signal. Negative polarity. See the description on page 15
for the operating requirement.
MSB 2 bits of 8-bit digital image data input pins (for ITU656 and
YCbCr 27 MHz). Level conforms to ITU-601.
MSB 2 bits of 8-bit digital image luminance signal input pins (for YCbCr).
Level conforms to ITU-601.
YD7 is MSB.

LSB 6 bits of 8-bit digital image data input pins (for ITU656 and
YCbCr 27 MHz). Level conforms to ITU-601.
LSB 6 bits of 8-bit digital image luminance signal input pins (for YCbCr).
Level conforms to ITU-601.
YD0 is LSB.

3.3 V digital power supply

8bit digital image chrominance signal data input pins (13.5 MHz mode).
Level conforms to ITU-601. Fixed to "0" for ITU Rec. 656, 27 MHz-YCbCr mode.
Operation mode select pin. "0" : 27 MHz mode / "1" : 13.5 MHz mode.

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MSM7652 ¡ Semiconductor

PIN DESCRIPTIONS (2/2)

Pin I/O Symbol Description

40 I SEL1

Enable pin. Normally fixed to "0". Sleep mode "1" with TEST1 = "0"
(See Page 32 for details)

41 I SEL2

42 DV

DD

Pulled down

3.3 V digital power supply

43 DGND Digital GND

Interface select pin. ITU656 : "0", YCbCr 27 MHz : "1" (See Page 32 for details)

44 I TEST1

45 I TENB

Input pin1 for testing. Normally fixed to "0". (See Page 32 for details)
Pulled down

Input pin2 for testing.

Normally fixed to "0"

.

Pulled down

46 I/O VREF Reference voltage for DAC

47 I FS DAC full scale adjustment pin.

48 I COMP DAC phase complement pin.

49 AGND Analog GND

50 O CA

51 AV

DD

52 O CVBSO

Analog color chrominance signal output pin or component B-Y signal
output pin.

3.3 V analog power supply

Analog composite signal output pin or component R-Y signal output pin.
53 AGND Analog GND
54 O YA Analog luminance signal output pin or component Y signal output pin.
55 AV

DD

3.3 V analog power supply

56 DGND Digital GND

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¡ Semiconductor MSM7652

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Input Voltage
Analog Output Current
Power Consumption
Storage Temperature

Symbol

DV

DD

AV

DD

V

I

I

O

P

W

T

STG

Condition

—
—
= 3.3 V

DV

DD

—
—
—

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage (*1)

"H" Level Input Voltage
"L" Level Input Voltage
Operating Temperature 1 Ta1

Operating Temperature 2 Ta2

Symbol

DV

DD

AV

DD

V

IH

V

IL

Condition

—
—

—

—
DVDD = AVDD = 3.3 V
DVDD = AVDD = 3.3 V

DA output load = 37.5 W

Min.

3.0

3.0

2.2
—

0

Rating

Unit

–0.3 to +4.5

V

–0.3 to +4.5
–0.3 to +5.5

50

600

–55 to +150

Typ.

3.3

Max.

3.6

V

mA

mW

°C

Unit

V

3.3
—
—
25 ˚C

3.6
—

0.8
70

V
V

25 ˚C065

DVDD = AVDD = 3.3 V,

External Reference Voltage Vrefex

Ta = 25˚C

1.25 V——

DA Current Setting Resistance Riadj (*2) 385 W——
DA Output Load Resistance R

L

(*3) 75 W——

(*1) Supply an equal voltage to both DVDD and AVDD.
(*2) A volume control resistor of approx. 500 W is recommendable for adjusting the output

current. When a DA converter analog output is terminated with a 37.5 W load, Riadj
= approx. 192 W.

(*3) Indicates the value when Riadj = 385 W (typical value).

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MSM7652 ¡ Semiconductor

ELECTRICAL CHARACTERISTICS

DC Characteristics

(Ta = 0 to 70°C, DV

Parameter Symbol

"H" Level Output Voltage V

"L" Level Output Voltage V

Input Leak Current I
Output Leak Current I
Power Supply Current (operating) I

V

OH

OL

O

DDO

I

Condition

= –4 mA (*1)

I

OH

= 4 mA (*1)

I

OL

IOL = 6 mA (*2)

VI = GND to DV

DD

VI = GND to DVDD (*3)

— 120 mA— 140

= 3.3 V ±0.3 V, AVDD = 3.3 V ±0.3 V)

DD

Min.

0.7V

—

DD

Typ.

—

—V

Max.

—

0.4

— mA–10 +10
— mA–10 +10

Unit

RESET_L = "L"

Power Supply Current (standby) I

Power Supply Current (Sleep mode)

DDS

I

DDSM

I2 C-bus SDA Output Voltage SDAV
I2C-bus SDA Output Current SDAI

CLKX2 = 0 MHz

SEL2 = "H" 0.05 mA0.03 0.5

Low level, IOL = 3 mA

L

O

During Acknowledge

60 mA—65

—V0 0.4

—mA3—
Internal Reference Voltage Vrefin — 1.25 V——
DA Output Load Resistance R

L

—75W
Integral Linearity SINL — ±2 LSB
Differential Linearity SDNL — ±1 LSB

(*1) VSYNC_L, HSYNC_L, CD[7:0]
(*2) CLKX1O
(*3) SDA

AC Characteristics

Parameter Symbol Condition Min. Typ. Max. Unit

CLKX2 Cycle Time T
Input Data Setup Time
Input Data Hold Time
Output Delay Time
CLKX1O Delay Time

2

C-bus Clock Cycle Time t

I

2

C-bus High Level Cycle t

I

2

C-bus Low Level Cycle t

I

S

t

s1

t

h1

t

d1

t

d2

C_SCL

H_SCL

L_SCL

(Ta = 0 to 70°C, DV

—
—
—
—
—

Rpull_up = 4.7 kW

= 3.3 V ±0.3 V, AVDD = 3.3 V ±0.3 V)

DD

——

36.4 ns
7ns
5ns
525ns
525ns

200
100 —
100

—
—
—
—
——
—ns
——

—
—

nsRpull_up = 4.7 kW

nsRpull_up = 4.7 kW

8

¡ Semiconductor MSM7652

INPUT/OUTPUT TIMING

Input timing

TS

CLKX2

ts1

td1

Invalid data

th1

valid data

HSYNC_L,

VSYNC_L, BLANK_L,

YD, CD, MS, MODE,

OLR, OLG, OLB, OLC

Output timing

HSYNC_L, VSYNC_L

CLKX1O

td2

I2C-bus Interface Input/Output Timing

The following figure shows I2C-bus basic input/output timing.

SDA

SCL

S

Start Condition

Data Line Stable: Data Valid

MSB

12 789

Change of Data Allowed

ACK

t

C_SCL

I2C-bus Basic Input/Output Timing

12

t

L_SCL

t

H_SCL

3-8

9

ACK

P

Stop Condition

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MSM7652 ¡ Semiconductor

BLOCK FUNCTIONAL DESCRIPTION

1. Prologue Block

This block separates input data at the ITU Rec.656 format into a luminance signal (Y) and a
chrominance signal (Cb & Cr), and also generates information concerning sync signals
HSYNC_L, VSYNC_L, and BLANK_L.
This block separates input data at the 27 MHz YCbCr (8-bit input) format into a luminance
signal (Y) and a chrominance signal (Cb & Cr).
This block separates input data at the 13.5 MHz YCbCr (16-bit input) format into a chrominance
signal Cb and a chrominance signal Cr.
Of the processed input data, luminance and chrominance signals other than valid pixel data
are replaced by 8'h10 and 8'h80 respectively.

2. Y Limiter Block

This block limits the luminance input signal by clipping the lower limit of an input signal outside
the ITU601 Standard

• Signals are limited to YD = 16 when YD < 16.

• Signals are limited to TD = 254 when YD (input during a valid pixel period) = 255.
In other cases, signals are fed as is to next processing.

3. C Limiter Block

This block limits the chrominance signal by clipping the upper and lower limits of the input
signal outside the ITU601 Standard.
CD = 1 when CD = 0 is input during a valid pixel period.
CD = 254 when CD = 255 is input during a valid pixel period.

• Y Level Converter

Converts ITU-601 standard luminance signal level to DAC digital input level.

• U Level Converter

Converts ITU-601 standard chrominance signal level to DAC digital input level.

• V Level Converter

Converts ITU-601 standard chrominance signal level to DAC digital input level.

• YUV Color Generator

This block generates luminance and chrominance signals from over lay color signals OLR,
OLG and OLB. Control signals (CR [2:0] ) control the output content (overlay or color bar) and
output level (100%, 75%, 50%, 25%).

• Overlay Control

This block selects input image data or YUV Color Generator output signals.
It is determined by the level of the control signal (OLC, CR [2]), as shown below: (x : don't care)
CR [2] = 1, OLC = x: Selects color bar signal (YUV Color Generator output signal).
CR [2] = 0, OLC = 1: Selects overlay signal (YUV Color Generator output signal).
CR [2] = 0, OLC = 0: Selects input image data.

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¡ Semiconductor MSM7652

• Black & Blank Pedestal

This block adds sync signals at the luminance side to luminance signals.

• Interpolator + LPF

This block executes data interpolation and the elimination of high frequency components by
LPF for input chrominance signals.

•I2C Control Logic

This is the serial interface block based on I2C standard of Phillips Corporation.
Internal registers MR and CR can be set from the master side.
When writing to the internal registers other than MR [1] (black level control) and CR [1:0]
(overlay level), written contents are immediately set to them. It is during the vertical blanking
period that written contents are set to MR [1] and CR [1:0].

• Sync Generator & Timing Controller

This block generates sync signals and control signals.
This block operates in slave mode, which performs external synchronization, and in master
mode, which internally generates sync signals.

• Color Burst Generator

Outputs U and V components of amplitude of burst signals.

• Subcarrier Generator

Executes color subcarrier generation.

• Interpolation Filter (IPF)

This block performs upsampling at CLKX2 for luminance signals and chrominance signals
modulated with CLKX1 divided from CLKX2. Interpolation processing is executed in this
process.

• Closed Caption Block

This block generates the signal for closed caption.

11

MSM7652 ¡ Semiconductor

INPUT DATA FORMAT

The signal level specified by the ITU601 is input.
When other signal levels than specified by the ITU601 are input, the luminance signal level is
clipped to 16 to 254 and the chrominance signal level to 1 to 254.
For chrominance signal input, the offset binary and 2's complement formats are available by
setting of internal registers.

Digital Level

100% White level

235

Black Level

16

Y data

Digital Level

240(112)

128(0)

16(–112)

C data

Input luminance signal level Input chrominance signal level

Basic Pixel Sampling Ratio

4:2:2 is supported.

CLKX1

YD Y1 Y2 Y3 Y4 Y5 Y6

CD

Cb1 Cr1 Cb3 Cr3 Cb5 Cr5

4:2:2 sampling

at 8bit Y/8bit CbCr input

12

¡ Semiconductor MSM7652

INPUT TIMING (ITUR656 input)

The input data is fed in the encoder at the rising edge of a clock pulse.

CLKX2

DATA

SAV(1st) SAV(2nd) SAV(3rd) SAV(4th)

Cb0 Y00 Cr0 Y01 Cb1 Y10 Cr1

Y11

EAV(1st) EAV(2nd) EAV(3rd) EAV(4th)

CLKX1O

OLR, OLG,
OLB, OLC

don't care don't care

VALID DATA

Input Timing

RELATIONSHIP BETWEEN BLANK SIGNAL AND INPUT IMAGE DATA

The blank signal is generated by the ITU Rec.656 standard input data. The input image data is
valid when the blank signal is "H".

13

MSM7652 ¡ Semiconductor

VALID DATA RANGE

According to the ITU Rec.656 standard, the pixel data immediately from SAV (4th word) to a
fixed value before EVA is valid.
The following figure shows the relationship between the input data at the CCIR Rec.656 format
and the sync, luminance, chrominance signals which are processed inside the encoder.

Note) The values in parenthesis indicate values in PAL mode.

ITU Rec.656 standard input data

4Tclkx2

Sync signal VSYNC_L (0H)
generated by input signal

Sync signal VSYNC_L (1/2)
generated by input signal

Sync signal HSYNC_L generated
by input data

9Tclkx1 (16Tclkx1)

Sync signal BLANK_L generated
by input data

BLANK_L internally generated to
assure the horizontal and vertical
periods

Luminance signal separated from
input data

Chrominance signal separated
from input data

EAV

11Tclkx1 (4Tclkx1)

1716Tclkx2 (NTSC)/1728clkx2 (PAL)

4Tclkx2

63Tclkx1 (63Tclkx1) <Normal>
67Tclkx1 (67Tclkx1) <Colorstripe>

136Tclkx1 (146Tclkx1)

1440T (NTSC/PAL)

Cb0, Y00, Cr0, Y01, Cb1, Y10, Cr1, Y11....

SAV

4Tclkx1
(4Tclkx1)

711Tclkx1 (702Tclkx1) 20Tclkx1 (20Tclkx1)127Tclkx1 (142Tclkx1)

711Tclkx1 (702Tclkx1) 20Tclkx1 (20Tclkx1)127Tclkx1 (142Tclkx1)

Y008'h10

Y01 Y10 Y11 8'h10

Cb08'h80

Cr0 Cb1 Cr1 8'h80

1H

1/2H

EAV

Composite signal

Relationship between input data and sync signal, luminance signal, chrominance signals

14

¡ Semiconductor MSM7652

CLOCK TIMING2 (8bit Y/8bit CbCr input)

Input Data Timing

Input data and sync signals are fed into the encoder at the rising edge of CLKX2.

Input data is handled as valid pixel data when t

passes after the falling edge of HSYNC_L.

START

Chrominance signal of input data at this time is regarded as Cb.

ACTIVE VIDEO LINE

CLKX2

HSYNC_L

YD, CD,
OLR, OLB,
OLG,OLC

BLANK_L

t

START

t

s1

don't care don't care

t

ACT

t

h1

VALID DATA

Video data input timing

Input data is recognized as valid pixel data when input signal BLANK_L is "H" in the t

ACT

period.
When BLANK_L is "H" during the blanking period, however, input data is not output as valid
pixel data since processing to maintain blanking period is internally in-progress.

The values of t
t

are as follows.

START

differ slightly between in master mode and in slave mode. The values of

START

In YCbCr format input mode, the values of t
or in 8 bit (YCbCr) mode.

In master mode

Operation mode
ITU 601 NTSC
ITU 601 PAL

t

– tS1 = t

STA

START

t

STA

(Ts)

250
280

START

are the same, in 8 bit (Y) + 8 bit (CbCr) mode

In slave mode

Operation mode
ITU 601 NTSC
ITU 601 PAL

t

STA

(Ts)

260
290

15

MSM7652 ¡ Semiconductor

Timing of Input Data to HSYNC_L

CLKX2

CLKX1O

HSYNC_L

OLR,OLG, OLB, OLC

YD

Invalid Data

Invalid Data

t

START

Input Timing when BLANK_L is Input

CLKX2

BLANK_L

YD

Input timing at 27 MHz in YCbCr format

Timing of Input Data to HSYNC_L

CLKX2

Invalid Data Valid Data

Invalid Data Cb0 Y00 Cr0 Y01 Cb1 Y10

t

ACT

Cb0 Y00 Cr0 Y01 Cb1

CLKX1O

HSYNC_L

OLR,OLG, OLB, OLC

YD

CD

Invalid Data

Invalid Data Invalid Data Y0 Y1 Y2

Invalid Data

t

START

Input Timing when BLANK_L is Input

CLKX2

BLANK_L

YD

CD

Invalid Data Valid Data

Invalid Data Cb0 Cr0 Cb1

t

ACT

Y0 Y1 Y2

Cb0 Cr0 Cb1

16

Input timing at 13.5 MHz in YCbCr format

¡ Semiconductor MSM7652

Internal Synchronization Output Timing

Input and output timing of HSYNC_L and VSYNC_L in master mode is as follows.

CLKX2

HSYNC_L
VSYNC_L

VSYNC_L

t

d1

Output timing of internal synchronization, HSYNC_L and VSYNC_L

t

d1

YA

5235245251234567 17 18

Output timing of internal synchronization VSYNC_L

17

MSM7652 ¡ Semiconductor

OUTPUT FORMAT

The timing conforms to the ITU624 standard.
In the NTSC operation mode, the existence/non-existence of setup level is selected by setting of
internal regsiters.

Data level on the DAC input terminal:
When the contents of 100% luminance order color bar are input into the encoder, the input level
is as follows.

DAC data Lumi (IRE)

957

775
715

610
549

450
390

338
285
266

224

114

133

100

89

70
59

41
30

20
11

7.5
0

–20

–40

4

Composite Wave Form (NTSC)

Yellow

White

Cyan

NTSC Composite Signal (Setup 7.5)

Green

Magenta

Red

Black

Blue

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¡ Semiconductor MSM7652

DAC data Lumi (IRE)

775
715

610
549

450
390

285

224

DAC data Lumi (IRE)

858
836

100

89

70
59

41
30

11

0

–40

4

63
59

Y Wave Form (NTSC)

White

Yellow

NTSC Y Signal Output (Setup 0)

C Wave Form (NTSC)

Yellow

Cyan

Cyan

Green

Green

Magenta

Magenta

Red

Red

Blue

Black

Blue

754

622

512

402

270
188

166

–20

–44
–59

–63

44

20

0

Color Burst

NTSC C Signal Output

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MSM7652 ¡ Semiconductor

DAC data Lumi (IRE)

973

792
731

627
566

467
406

359
302

241

123

133

100

89

70
59

41
30

21.5
11

0

–21.5

–43

4

Composite Wave Form (PAL)

PAL Composite Signal

White

Yellow

Cyan

Green

Magenta

Red

Black

Blue

DAC data Lumi (IRE)

792
731

627
566

467
406

302

241

100

89

70
59

41
30

11

0

–43

4

Y Wave Form (PAL)

PAL Y Signal Output

White

Yellow

Cyan

Green

Magenta

Red

Blue

Black

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¡ Semiconductor MSM7652

DAC data Lumi (IRE)

21.5

–21.5

–44
–59

–63

63
59

44

0

858
836

754

630

512

394

270
188

166

C Wave Form (PAL)

Color Burst

PAL C Signal Output

Yellow

Cyan

Green

Magenta

Red

Blue

21

MSM7652 ¡ Semiconductor

NTSC (Interlaced)

Field 1

25926026126226312345678 171819

Field 2

25926026126226312345678 171819

Field 3

Reference sub-carrier phase

A B C

Reference sub-carrier phase

A B C

Reference sub-carrier phase

NEGATIVE HALF CYCLE
Burst relative –180° to B-Y axis

D

E

D

E

POSITIVE HALF CYCLE
Burst relative 180° to B-Y axis

25926026126226312345678 171819

A B C

D

E

Field 4

25926026126226312345678 171819

Reference sub-carrier phase

A B C

D

E

Output timing (Interlaced NTSC)

22

¡ Semiconductor MSM7652

Symbol

A
B
C
D
E

Name

First equalizing pulse period (3H)
Vertical synchronization period (3H)
Second equalizing pulse period (3H)
Burst pause period
Vertical blanking period (20H)

Output timing (Interlaced NTSC)

Period

Odd field (Even field)

259.5 to 262.5H
1 to 3H
4 to 6H

1 to 6,259.5 to 262.5H

1 to 17,259.5 to 262.5H

23

MSM7652 ¡ Semiconductor

NTSC (Non-interlaced)

Continuous Odd Field

Continuous Even Field

NEGATIVE HALF CYCLE
Burst relative –180° to B-Y axis

Reference sub-carrier phase

26026126212345678 171819

A B C

D

E

Reference sub-carrier phase

26026126212345678 171819

A B C

D

E

Reference sub-carrier phase

POSITIVE HALF CYCLE
Burst relative 180° to B-Y axis

Symbol

A
B
C
D

E

26026126212345678 171819

A B C

Reference sub-carrier phase

26026126212345678 171819

A B C

Output timing (Non-interlaced NTSC)

Name

First equalizing pulse period (2H)
Vertical synchronization period (3H)
Second equalizing pulse period (2H)
Burst pause period
Vertical blanking period (19H)

D

E

D

E

Period

Continuous odd • even field

261 to 262H

1 to 3H
4 to 6H

261 to 6H

261 to 17H

24

Output timing (Non-interlaced NTSC)

¡ Semiconductor MSM7652

PAL (Interlaced)

Field 1,5

Field 2,6

Field 3,7

Burst phase +135°
+V

30931031131231312 345678 232425

A B C

D

E

30931031131231312 345678 232425

A B C

D

E

Burst phase -135°

-V

Field 4,8

Symbol

A
B
C
D

E

30931031131231312 345678 232425

A B C

D

E

30931031131231312 345678 232425

A B C

D

E

Output timing (Interlaced PAL)

Name

First equalizing pulse period (2.5H)
Vertical synchronization period (2.5H)
Second equalizing pulse period (2.5H)
Burst pause period
Vertical blanking period (25H)

Field 1,5

311 to 312.5H

1 to 2.5H

2.5 to 5H

1 to 6,310 to 312.5H

1 to 22.5,311 to 312.5H

Field 2,6

311 to 312.5H

1 to 2.5H

2.5 to 5H

1 to 5.5,308.5 to 312.5H

1 to 22.5,311 to 312.5H

Period

Field 3,7

311 to 312.5H

1 to 2.5H

2.5 to 5H

1 to 5,311 to 312.5H

1 to 22.5,311 to 312.5H

Field 4,8

311 to 312.5H

1 to 2.5H

2.5 to 5H

1 to 6.5,309.5 to 312.5H

1 to 22.5,311 to 312.5H

Output timing (Interlaced PAL)

25

MSM7652 ¡ Semiconductor

PAL (Non-interlaced)

Continuous Odd Field

309

309

Continuous Even Field

Burst phase +135°
+V

31031131212345678 232425

A B C

D

E

31031131212345678 232425

A B C

D

E

Burst phase -135°

-V

Symbol

A
B
C
D

E

309

309

31031131212345678 232425

A B C

31031131212345678 232425

A B C

Output timing (Non-interlaced PAL)

Name

First equalizing pulse period (2H)
Vertical synchronization period (2.5H)
Second equalizing pulse period (2.5H)
Burst pause period
Vertical blanking period (24H)

D

E

D

E

Period

Continuous odd • even field

311 to 312H

1 to 2.5H

2.5 to 5H

311 to 6H

311 to 22H

26

Output timing (Non-interlaced PAL)

¡ Semiconductor MSM7652

<Equalizing pulse, vertical synchronization period>

q

Setting content of equalizing pulse vertical

w

synchronization period (Ts is sampling clock cycle in each mode)

q w e

1/2H1/2H

e
r

ITU 601 NTSC
ITU 601 PAL

q

31Ts
32Ts

w

365Ts
369Ts

e

64Ts
63Ts

1/2H
429Ts
432Ts

qEqualizing pulse width
wVertical sync pulse width
eSerration

qBlanking level
w

(synchronizing + blanking level) ¥ (2/3)

e

(synchronizing + blanking level) ¥ (1/3)

rSynchronzing level

<Horizontal blanking period>

r
e
w
q

t

q w

e

1H

r

t

qHorizontal sync pulse width
wBurst signal output period
eBurst signal start
rHorizontal blanking period (excluding front porch)
tFront porch start

qSynchronzing level

(synchronizing + blanking level) ¥ (1/3)

w
e(synchronizing + blanking level) ¥ (2/3)
rBlanking level
tPeak to peak value of burst

Horizontal blanking period

Setting content of horizontal blanking period (Ts is sampling clock cycle in each mode)

ITU601 NTSC
ITU601 PAL

q

63Ts
63Ts

w

31Ts
31Ts

e

71Ts
75Ts

r

127Ts
142Ts

t

838Ts
844Ts

Total dots/1H

858
864

Setting content of horizontal blanking period

27

MSM7652 ¡ Semiconductor

Setup Level Setting

When the NTSC operation mode is selected, one of the two kinds of setup level can be selected
by setting of registers.
When the setup level 0 is selected, the Black-to-White is 100IRE.
When the setup level 7.5IRE is selected, the Black-to-White is 92.5IRE.
However, this setup function is valid only for the NTSC mode and invalid for the PAL mode.

Color Bar Generation Function

The 75% luminance order color bar or 100% luminance order color bar is output by setting
internal registers. The output timings for each color bar color is as follows.

q

w

e

White

r

Yellow Cyan Green

t

y

Red Blue Black

Magenta

Operation mode

ITU601 NTSC
ITU601 PAL

(Ts : sampling block period)

28

u

Output timing of each color bar color

hblank

127Ts
142Ts

q

216Ts
230Ts

w

305Ts
318Ts

e

394Ts
406Ts

r

483Ts
494Ts

t

572Ts
582Ts

Contents of color bar output timing setting

y

661Ts
670Ts

u

750Ts
757Ts

1H

858Ts
864Ts

¡ Semiconductor MSM7652

I2C BUS FORMAT

Basic input format of I2C-bus interface is shown below.

Slave AddressS SubaddressA Data 0A A ..... Data n A P

Symbol

S
Slave Address

Start condition
Slave address 1000100X (ADRS pin : 0) or 1000110X (ADRS pin : 1),

Description

the 8th bit is R (1)/W (0) signal.
A
Subaddress
Data n

Acknowledge. Generated by slave

Subaddress byte

Data byte and acknowledge continues until data byte stop condition is met.
P Stop condition

As described above, it is possible to read and write data from subaddress to subaddress
continuously. Reading from and writing to discontinuous addresses is performed by repeating
the Acknowledge and Stop condition formats after Data 0.

If one of the following matters occurs, the encoder will not return "A" (Acknowledge).

• The slave address does not match.

• A non-existent subaddress is specified.

• The read/write attribute of a register does not match "X" (read : 1/write : 0 control bit).

The input timing is shown below.

SDA

SCL

MSB

S

Start Condition

Data Line Stable: Data Valid

12 789

Change of Data Allowed

ACK

t

C_SCL

t

I2C-bus Basic Input/Output Timing

12

L_SCL

t

H_SCL

3-8

9

ACK

P

Stop Condition

29

MSM7652 ¡ Semiconductor

CLOSED CAPTION FUNCTION

The closed caption function based on the NCI standard is available.
The caption information on each line is multiplexed as a 26-cycle signal which is synchronized
at 503 kHz. Each cycle is described below.

Cycles 1 to 7 Clock-Run-in period 7-cycle clock signal to synchronize caption data

with caption information.
Cycles 8 to 10 Start Code Fixed signal with logical level "001"
Cycles 11 to 26 Caption Information 2-byte multiplex information with combination of

the ASCII code bits 0 - 6 and the 7ODD parity bit.

The first byte is multiplexed in cycles 11 to 18 and
the second byte is multiplexed in cycles 19 to 26,
starting from LSB.

The output timing when data is multiplexed by the closed caption function is shown below.

50IRE

20IRE

0IRE

–40IRE

Cycle

10.0 ms

(reference)

1

234567891011121314151617181920212223242526

Transition time

Start

Clock Run in

13.9 ms

(reference)

Code

6.0 ms

(reference)

61.7 ms (reference)

16-bit Information

31.8 ms

(reference)

Caption signal

50IRE

30

100%

50%

Transition time : ns

Transition time

¡ Semiconductor MSM7652

INTERNAL REGISTERS

The register (ID number) for the Anticopy function and the register (CCSTAT) for the closed
caption can be read.
The registers other than ID number can be written.
Details of the internal registers are described below. (Values marked * are set by default.)

Sub-

Register name R/W

MR

(Mode register)

CR

(Command Register)

Write

Only

Write

Only

Default

address

value

00 00 MR[4] Override

MR[3] Chroma format Chrominance signal input format

MR[2] Black level control Black level setup

MR[1] Master/Slave Master or slave operation select

MR[0] Video mode select Operation mode switching

01 03 CR[4] Undefined —

CR[3] Interlace

CR[2] Color bar

CR[1:0] Overlay level Overlay signal/adjusting luminance order color

Item to be set Description

Switching between the external terminal and

internal register settings (for the operation mode)

*0 : External terminal setting enabled

1 : Internal register setting enabled

*0 : Offset binary

1 : 2's complement

Note : Valid in NTSC mode only

*0 : Black level 0IRE

1 : Black level 7.5IRE

*0 : Slave

1 : Master

*0 : ITU601 NTSC

1 : ITU601 PAL

Scanning method

*0 : Interlace

1 : Non-interlace

Adjusting luminance order color bar output control

*0 : Input image data or overlay data

1 : Luminance order color bar

bar output level control

00 : 25%

01 : 50%

10 : 75%

*11 : 100%

31

MSM7652 ¡ Semiconductor

Sub-

Register name R/W

CCEN Write

Only

CCLN Write

Only

CCODT0 Write

Only

CCODT1 Write

Only

CCEDT0 Write

Only

CCEDT1 Write

Only

CCSTAT Read/

Write

Default

address

value

02 00 CCEN[0] Closed Caption Enable Closed caption function on/off control

03 11 CCLN[4:0] Closed Caption Line Number Closed caption data insertion line

04 00 CCODT0[7:0] 1st byte of C.C. data, ODD field First byte closed caption data in odd-number

05 00 CCODT1[7:0] 2nd byte of C.C. data, ODD field Second byte closed caption data in odd-number

06 00 CCEDT0[7:0] 1st byte of C.C. data, EVEN field First byte closed caption data in even-number

07 00 CCEDT1[7:0] 2nd byte of C.C. data, EVEN field Second byte closed caption data in

08 00 CCSTAT[0] Odd field C.C. status odd-number field status

CCSTAT[1] Odd field C.C. status Even-number field status

Item to be set Description

*0 : C.C. encoding off

1 : Odd field encoding on

2 : Even field encoding on

3 : Both field encoding on

number setting

NTSC : CCLN + 4

PAL : CCLN + 1

field

field

field

even-number field

*0 : CCODT0, CCODT1 writing completed

1 : ODD Field C.C. bytes ENCODE completed

*0 : CCEDT0, CCEDT1 writing completed

1 : EVEN Field C.C. bytes ENCODE completed

OPERATION MODE SETTING BY PIN CONTROL

The contents of control using TEST1, SEL1, SEL2, CLKSEL, and MS are shown below.

TEST1 0 : Normal operation 1 : Test mode
SEL1 0 : Normal operation 1 : Sleep mode
SEL2 0 : ITU Rec. 656 1 : Y Cb Cr
CLKSEL 0 : 27 MHz 1 : 13.5 MHz
MS 0 : Slave 1 : Master

TEST1 SEL1 SEL2 CLKSEL MS Operation mode

0 0 0 0 0 ITUR656 Slave
0 0 0 1 0 13.5 MHz YCbCr Slave
0 0 0 1 1 13.5 MHz YCbCr Master
0 0 1 0 0 27 MHz YCbCr Slave
0 0 1 0 1 27 MHz YcbCr Master
0 1 x x x Sleep Mode

x : don't care

32

¡ Semiconductor MSM7652

FILTER CHARACTERISTICS

The characteristics of LPF used for color signal processing and interpolation filters used for
upsampling processing are shown below.

LPF for 422 color signals

The following shows the characteristics when the clock frequency is 13.5 MHz.

0

–20

–40

Level [dB]

–60

–80

–100

01234567

Frequency [MHz]

422 Interpolation + LPF Frequency Characteristic

Interpolation

The following shows the characteristics when the clock frequency is 27 MHz.

0

–20

–40

Level [dB]

–60

–80

–100

02468101214

Frequency [MHz]

Up Sampling Filter Frequency Characteristic

(Note) The characteristics of these filters are based on design data.

33

MSM7652 ¡ Semiconductor

APPLICATION CIRCUIT EXAMPLE

5 V or 3.3 V

Overlay

Controller

5 V or 3.3 V

DIP SW

I2C

Controller

MS
MODE
OUTSEL
CLKSEL
SEL1
SEL2

OLR
OLG
OLB
OLC

YD[7:0]YD[7:0]

CD[7:0]CD[7:0]

CLKX1O
VSYNC_L
HSYNC_L
BLANK_L

R

L

SCL

MSM7652

DGND AGND

R

L

3.3 V

SDA

DD

DV

3.3 V

DD

V

AV

COMP

CVBSO

CLKX2

REF

FS

YA

CA

Typ. 1.25 V

3.3 V
CC = 0.1 µF

C

R

C

C

LPF AMP

R1

LPF AMP

R1

LPF AMP

R1

RC = 500 Ω VR

Recommended Analog Output Circuit

+AVCC

YA
CA
CVBSO

150 W

164 pF

3.6 mH

164 pF

150 W

+
–

0.1 mF

75 W

560 W

1000 mF
+

OUTPUT

560 W

0.1 mF

LPF (Toko-make 621LJN-1471 is recommended.)

–AVCC

Note: The termination of a DA converter analog output with a 37.5 W load eliminates need for

an AMP.

34

¡ Semiconductor MSM7652

PACKAGE DIMENSIONS

(Unit : mm)

56-Pin Plastic QFP

35

MSM7652 ¡ Semiconductor

NOTICE

1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or

unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

5. Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, and medical equipment including
life-support systems.

7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

8. No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.

Copyright 1998 Oki Electric Industry Co., Ltd.

36