Datasheet MSM7578VRS, MSM7579GS-K, MSM7579MS-K, MSM7579RS, MSM7578VGS-K Datasheet (OKI)

E2U0017-28-81

¡ Semiconductor MSM7578H/7578V/7579

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7578H/7578V/7579

Single Rail CODEC

GENERAL DESCRIPTION

The MSM7578 and MSM7579 are single-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices are
particularly optimized for telephone terminals in digital wireless systems and ISDN systems.
The devices use the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal can directly drive a piezoelectric type handset receiver.

FEATURES

• Single power supply: +5.0 V ±5%

• Low power consumption
Operating mode: 25 mW Typ. 47 mW Max. VDD = 5 V
Power down mode: 0.05 mW Typ. 0.3 mW Max. VDD = 5 V

• ITU-T Companding law

MSM7578H: m-law
MSM7579: A-law
MSM7578V: m/A-law pin-selectable

• Built-in PLL eliminates a master clock

• Serial data rate: 64/128/256/512/1024/2048 kHz

96/192/384/768/1536/1544/200 kHz

• Adjustable transmit gain

• Built-in reference voltage supply

• Directly drive a line transformer of 600 W

• The 16-pin DIP and 24-pin SOP package products provide pin compatibility with the MSM7508B/
7509B

• The 20-pin SSOP package products have 1/3 the foot print of conventional products

• Package options:
16-pin plastic DIP (DIP16-P-300-2.54) (Product name : MSM7578HRS)

(Product name : MSM7579RS)
(Product name : MSM7578VRS)

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7578HGS-K)

(Product name : MSM7578VGS-K)
(Product name : MSM7579GS-K)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7578HMS-K)

(Product name : MSM7579MS-K)
(Product name : MSM7578VMS-K)

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¡ Semiconductor MSM7578H/7578V/7579

BLOCK DIAGRAM

AIN–
AIN+

GSX

SGC

SG

AOUT

–
+

RC

LPF

SG

GEN

–
+

SG

8th

BPF

GEN

5th

LPF

VR

CONV.

AUTO
ZERO

DA

CONV.

PWD

AD

TCONT

PLL

RTIM

RCONT

PWD

Logic

PCMOUT

XSYNC

BCLK

RSYNC
(ALAW)

PCMIN

PDN
V

DD

AG
DG

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¡ Semiconductor MSM7578H/7578V/7579

PIN CONFIGURATION (TOP VIEW)

1

SGC

2

SG

AOUT

3

V

4

DD

5

DG

6

PDN

RSYNC

7
8 9

PCMIN PCMOUT

16-Pin Plastic DIP

16

AIN+

15

AIN–

14

GSX

13

(ALAW)*

12

AG

11

BCLK
XSYNC

10

1

SGC

2

NC
SG

3
4

NC

AOUT

5

V

6

DD

DG AG

7
8

NC

9

NC

PDN

10
11

RSYNC

12 13

PCMIN

24

AIN+

23

AIN–

22

NC

21

GSX

20

NC

19

(ALAW)*

18

NC

17
16

BCLK
NC

15
14

XSYNC
PCMOUT

1

SGC

2

SG

AOUT

3

V

4

DD

NC

5
6

NC
DG AG

7
8

PDN

9

RSYNC

10 11

PCMIN PCMOUT

20

AIN+

19

AIN–

18

GSX

17

(ALAW)*

NC

16

NC

15
14

BCLK

13
12

XSYNC

NC : No connect pin

20-Pin Plastic SSOP

NC : No connect pin

24-Pin Plastic SOP

* The ALAW pin is only applied to the MSM7578VRS/MSM7578VGS-K/MSM7578VMS-K.

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¡ Semiconductor MSM7578H/7578V/7579

PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN–, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.

1) Inverting input type

Analog input

2) Non inverting input type

Analog input

AG

Analog signal ground.

AOUT

C1

C2

R5

R1

R3

R4

R2

GSX
AIN–
AIN+
SG

AIN+
AIN–
GSX

SG

R1 : variable

–
+

+
–

R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

Gain = R2/R1 £ 10

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)

Gain = 1 + R4 / R3 £ 10

Analog output.
The output signal has a maximum amplitude of 2.4 VPP above and below the signal ground
voltage (VDD/2).
The output load resistance is a minimum of 600 W.
During power saving, or power down mode, the output of AOUT is at the voltage level of the
signal ground.

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¡ Semiconductor MSM7578H/7578V/7579

V

DD

Power supply for +5 V.

PCMIN

PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic “1” or “0” drives both transmit and receive circuits to the
power saving state.

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the
AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly
the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.
Setting this signal to logic “1” or “0” drives both transmit and receive circuits to the power saving
state.

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¡ Semiconductor MSM7578H/7578V/7579

DG

Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.

PDN

Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down mode.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7579 (A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

+0
–0

–Full scale

PCMIN/PCMOUT

MSM7578H (m-law)

MSD
1000 0000
1111 1111
0111 1111
0000 0000

MSM7579 (A-law)

MSD
1010 1010
1101 0101
0101 0101
0010 1010

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¡ Semiconductor MSM7578H/7578V/7579

SG

Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.
The output drive current capability is ±300 mA.
This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power saving or power down mode.

SGC

Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.

ALAW

Control signal input of the companding law selection.
Provides only for the MSM7578VRS/7578VGS-K/7578VMS-K. The CODEC will operate in the
m-law when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin
is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the pin is
internally pulled down.

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¡ Semiconductor MSM7578H/7578V/7579

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature

Symbol

V

DD

V

AIN

V

DIN

T

STG

Condition

—
—
—
—

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage
Operating Temperature Ta
Analog Input Voltage

Input High Voltage

Input Low Voltage

Clock Frequency

Sync Pulse Frequency
Clock Duty Ratio
Digital Input Rise Time
Digital Input Fall Time

Transmit Sync Pulse Setting Time

Receive Sync Pulse Setting Time

Sync Pulse Width
PCMIN Set-up Time
PCMIN Hold Time

Digital Output Load

Analog Input Allowable DC Offset

Allowable Jitter Width

Symbol

V

DD

V

AIN

V

IH

V

IL

F

C

F

S

D

C

t

Ir

t

If

t

XS

t

SX

t

RS

t

SR

t

WS

t

DS

t

DH

R

DL

C

DL

V

off

—

Condition

Voltage must be fixed

—

Connect AIN– and GSX

XSYNC, RSYNC, BCLK,
PCMIN, PDN, ALAW

BCLK

XSYNC, RSYNC
BCLK
XSYNC, RSYNC, BCLK,
PCMIN, PDN, ALAW

BCLKÆXSYNC, See Timing Diagram
XSYNCÆBCLK, See Timing Diagram
BCLKÆRSYNC, See Timing Diagram
RSYNCÆBCLK, See Timing Diagram

XSYNC, RSYNC

—
—

Pull-up resistor

—
Transmit gain stage, Gain= 1
Transmit gain stage, Gain = 10

XSYNC, RSYNC, BCLK

Rating

0 to 7
–0.3 to V
–0.3 to V

DD

DD

+ 0.3
+ 0.3

–55 to +150

Min. Typ. Max. Unit

4.75
–30 +85

—

2.2

0

5

+25 °C

—

—

—

5.25

2.4

V

DD

0.8

64, 128, 256, 512, 1024,
2048, 96, 192, 384, 768,
1536, 1544, 200

6.0
40
—
—

100
100
100
100

1 BCLK

100
100

0.5
—

–100

–10

—

8.0
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—

9.0
60
50
50
—
—
—
—

100

—
—
—

100

+100

+10

1

Unit

V
V
V

°C

V

V

PP

V

V

kHz

kHz

%
ns
ns
ns
ns
ns
ns
ms
ns
ns

kW

pF
mV
mV

ms

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¡ Semiconductor MSM7578H/7578V/7579

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

= +5 V ±5%, Ta = –30°C to +85°C)

(V

DD

Parameter

Power Supply Current

Input High Voltage
Input Low Voltage
High Level Input Leakage Current
Low Level Input Leakage Current
Digital Output Low Voltage
Digital Output Leakage Current
Input Capacitance
Analog Input Resistance

Symbol

I

Operating mode, No signal

DD1

I

Power-down mode, PDN = 0

DD2

Power-save mode, PDN = 1,

I

DD3

XSYNC Æ OFF

V

IH

V

IL

I

IH

I

IL

Pull-up resistance > 500 W

V

OL

I

O

C

IN

Condition

—
—
—
—

—

Min.

—
—

—

2.2

0.0
—
—

0.0
—

Typ.

5

0.01

1.2

—
—
—
—

0.2
—

Max.

9

0.05

3.0

V

DD

0.8

2.0

0.5

0.4
10

— —5—pF

RINAIN+, AIN– — 10 — MW

Unit

mA
mA

mA

V
V

mA
mA

V

mA

Transmit Analog Interface Characteristics

Parameter

Input Resistance
Output Load Resistance
Output Load Capacitance
Output Amplitude
Offset Voltage

Symbol

R

AIN+, AIN–

INX

R

GSX with respect to SG

LGX

C

LGX

V

OGX

V

OSGX

Receive Analog Interface Characteristics

Parameter

Output Load Resistance
Output Load Capacitance
Output Amplitude
Offset Voltage

Symbol

R

AOUT with respect to SG

LAO

C

AOUT with respect to SG

LAO

V

AOUT with respect to SG

OAO

V

AOUT with respect to SG

OSAO

(V

= +5 V to ±5%, Ta = –30°C to +85°C)

DD

Condition Min. Typ. Max. Unit

Gain = 1

10
20
—

–1.2

–20

= +5 V to ±5%, Ta = –30°C to +85°C)

(V

DD

—
—
—
—
—

—
—
30

+1.2

+20

MW

kW

pF

V

mV

Condition Min. Typ. Max. Unit

0.6
—

–1.2

–100

—
—
—
—

—
50

kW

pF

+1.2

+100VmV

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¡ Semiconductor MSM7578H/7578V/7579

AC Characteristics

(V

= +5 V ±5%, Ta = –30°C to +85°C)

DD

Parameter

Transmit Frequency Response

Receive Frequency Response

Transmit Signal to Distortion Ratio 1020 dB

Receive Signal to Distortion Ratio 1020 dB

Transmit Gain Tracking

Receive Gain Tracking

Symbol

Loss T1
Loss T2
Loss T3
Loss T4
Loss T5
Loss T6
Loss R1
Loss R2
Loss R3
Loss R4
Loss R5
SD T1 35 43 —3
SD T2 35 41 —0
SD T3 35 38 —–30

SD T4 29

SD T5 24

SD R1 36 43 —3
SD R2 36 41 —0
SD R3 36 40 —–30

SD R4

SD R5

GT T1 –0.3 +0.01 +0.3
GT T2 Reference
GT T3 1020 –0.3 0 +0.3 dB–40
GT T4 –0.6 –0.13 +0.6

GT T5 –1.2 –0.15 +1.2
GT R1 –0.3 0 +0.3
GT R2 Reference
GT R3 1020 –0.3 +0.10 +0.3 dB
GT R4 –0.6 +0.20 +0.6
GT R5 –1.2 +0.25 +1.2

Freq.

(Hz)

300 –0.15 +0.07 +0.20 dB
1020 Reference dB
2020 –0.15 –0.04 +0.20 dB
3000 –0.15 +0.06 +0.20 dB
3400 0 0.4 0.80 dB

300 –0.15 –0.03 +0.20 dB
1020 Reference dB
2020 –0.15 –0.02 +0.20 dB0
3000 –0.15 +0.15 +0.20 dB
3400 0.0 0.4 0.80 dB

Level

(dBm0)

60 20 26 — dB

0

3

–10

–50
–55

3
–10
–40
–50
–55

Condition

*1

*2

*2

*1

*2

*2

Min. Typ. Max. Unit

31
30
27
26

30 33.5
29 32
25 30
24 27

—–40

—–45

—–40

—–45

*1 Psophometric filter is used
*2 Upper is specified for the MSM7578H, lower for the MSM7579

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¡ Semiconductor MSM7578H/7578V/7579

AC Characteristics (Continued)

(V

= +5 V ±5%, Ta = –30°C to +85°C)

DD

Parameter

Idle Channel Noise

Absolute Level (Initial Difference)

Absolute Level
(Deviation of Temperature and Power)

Absolute Delay

Transmit Group Delay

Receive Group Delay

Crosstalk Attenuation

Symbol

Freq.

(Hz)

Nidle T

Nidle R

——

— –78

AV T 0.5803 0.6007 0.6218

Level

(dBm0)

—

—

Condition

AIN = SG

*1 *2
*1 *3

V

= 5.0 V

DD

Min. Typ. Max. Unit

–72.5
–70.5

–70
–68

— –75

Ta = 25°C

AV R 0.5803 0.6007 0.6218

AV Tt –0.2 — +0.2

1020

AV Rt –0.2 — +0.2

0

V

DD

= +5 V
±5%
Ta = –30
to 85°C
A to A

Td 1020 — — 0.60 ms0

BCLK
= 64 kHz

tgd T1
tgd T2
tgd T3
tgd T4
tgd T5
tgd R1
tgd R2
tgd R3
tgd R4
tgd R5

CR T 7585—
CR R 80

500

600
1000
2600
2800

500

600
1000
2600
2800

1020 dB0

TRANS Æ RECV

RECV Æ TRANS

— 0.19 0.75

*4

— 0.11 0.35
— 0.02 0.1250
— 0.05 0.125
— 0.75

*4

— 0.00 0.75
— 0.35
— 0.00 0.125 ms0
— 0.09 0.125
— 0.12 0.75

70 —

0.07

0.00

dBmOp

Vrms

dB

dB

ms

*1 Psophometric filter is used
*2 Upper is specified for the MSM7578H, lower for the MSM7579
*3 MSM7578H: All "1", MSM7579: "11010101"
*4 Minimum value of the group delay distortion

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¡ Semiconductor MSM7578H/7578V/7579

AC Characteristics (Continued)

(V

= +5 V ±5%, Ta = –30°C to +85°C)

DD

DIS

S

IMD

t

SD

t

XD1

t

XD2

t

XD3

Freq.

(Hz)

4.6 kHz to
72 kHz
300 to

3400
fa = 470
fb = 320

0 to

50 kHz

CL = 100 pF

(dBm0)

Parameter

Symbol

Discrimination 0

PSR T

PSR R

Digital Output Delay Time

*5 The measurement under idle channel noise

Level

Condition

0 to
4000 Hz

4.6 kHz to
100 kHz

*5

PP

Min. Typ. Max. Unit

30 32 — dB

— –37.5 –35 dBmOOut-of-band Spurious 0

— –52 –35 dBmOIntermodulation Distortion –4 2fa – fb

—30—dBPower Supply Noise Rejection Ratio 50 mV

20 — 200
20 — 200
20 — 200

ns

20 — 200

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¡ Semiconductor MSM7578H/7578V/7579

TIMING DIAGRAM

PCM Data Input/Output Timing

Transmit Timing

BCLK 12345678910

XSYNC

t

XS

t

XD1

t

SX

t

WS

t

SD

t

XD2

t

XD3

PCMOUT D2 D3 D4 D5 D6 D7 D8MSD

When t
When t

£ 1/2 • Fc, the Delay of the MSD bit is defined as t

XS

£ 1/2 • Fc, the Delay of the MSD bit is defined as tSD.

SX

XD1

.

Receive Timing

BCLK 12345678910

t

RS

RSYNC

PCMIN D2 D3 D4 D5 D6 D7MSD

t

SR

t

WS

t

DS

t

DH

D8

11

11

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¡ Semiconductor MSM7578H/7578V/7579

APPLICATION CIRCUIT

Analog interface Digital interface

1 kW

5 V

PCM signal output

Analog input

MSM7578H/7579

PCMOUTAIN–

GSX

Analog output

AOUT

AIN+

PCMIN

BCLK

PCM data input

PCM Shift Clock input

SG

0.1 mF

XSYNC

8 kHz SYNC signal input

SGC

RSYNC

PDN

Power Down control input

"1" = Operation
"0" = Power down

0 V

+5 V

–

10 mF

+

1 mF

AG

DG

V

DD

0 to 10 W

The analog output signal has an amplitude of ±1.2 V above and below the offset voltage level of
VDD/2.

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¡ Semiconductor MSM7578H/7578V/7579

RECOMMENDATIONS FOR ACTUAL DESIGN

• To assure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the device pins.

• Connect the AG pin and the DG pin each other as close as possible. Connect to the system
ground with low impedance.

• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, use the short lead type socket.

• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
source such as power supply transformers surround the device.

• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch­up phenomenon when turning the power on.

• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.

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¡ Semiconductor MSM7578H/7578V/7579

PACKAGE DIMENSIONS

(Unit : mm)

DIP16-P-300-2.54

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.99 TYP.

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¡ Semiconductor MSM7578H/7578V/7579

(Unit : mm)

SOP24-P-430-1.27-K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.58 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

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¡ Semiconductor MSM7578H/7578V/7579

(Unit : mm)

SSOP20-P-250-0.95-K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.18 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

18/18