Datasheet MSM7560LGS-K, MSM7540LGS-K Datasheet (OKI)

E2U0027-28-83

¡ Semiconductor

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7540L/7560L

MSM7540L/7560L

Single Rail ADPCM CODEC

GENERAL DESCRIPTION

The MSM7540L/7560L are single channel ADPCM CODEC ICs which perform mutual transcoding
between an analog voice band signal 300 to 3400 Hz and 32 kbps ADPCM serial data.
Using advanced circuit technology, these devices operate from a single 3 V power supply and
provide low power consumption.
The MSM7540L/7560L are optimized for advanced digital cordless telephone system applications.

FEATURES

••

• Single 3 V Power Supply Operation

••

••

• ADPCM Algorithm : Complies completely with 1988's version ITU-T

••
G.721 (32 kbps)

••

• Transmit/Receive Full-Duplex Operation

••

••

• Transmit/Receive Synchronous Mode Only

••

••

• Serial ADPCM Transmission Data Rate : 32 kbps to 2048 kbps

••

••

• Serial PCM Transmission Data Rate : 64 kbps to 2048 kbps

••

••

• PCM Interface Coding Format

••

MSM7540L : A-law or Linear (14 bit, 2's compliment) Selectable
MSM7560L : m-law or Linear (14 bit, 2's compliment) Selectable

••

• Low Power Consumption

••

Operating Mode : 18 mW Typ. (VDD = 3.0 V)
Power-Down Mode : 0.3 mW Typ. (VDD = 3.0 V)

••

• Two Analog Input Amplifier Stages : Externally Adjustable Gain

••

••

• Analog Output Stage : Push-pull Drive (direct drive of 350 W␣ + 120 nF)

••

••

• Built-in Crystal Oscillator (10.368 MHz)

••

••

• Built-in Reference Voltage Supply

••

••

• Option Reset Specified by ITU-T G. 721/ADPCM

••

••

• Package:

••

28-pin plastic SOP (SOP28-P-430-1.27-K) (Product name: MSM7540LGS-K)

(Product name: MSM7560LGS-K)

32-pin plastic TSOP (TSOPI32-P-814-0.50-1K) (Product name: MSM7560LTS-K)

1/15

2/15

MSM7540L/7560L

¡ Semiconductor

AIN2

GSX2

XSYNC
IS

AIN1

GSX1

AOUT–

ADPCM
CODER

1

0

V

DD

BCLKA

0

1

PCMSO

PCMSI

PCMRI

PCMRO

IR
RSYNC

0

1

ADPCM
DECODER

1

0

BCLKB

AG DG X1 X2

PWI

V

REF

SG

CLOCK/
TIMING

MCK

LPS

RES

PDN

AOUT+

–
+

–1

VFRO

–
+

–
+

P

/

S

P

/

S

S

/

P

S

/

P

P

/

S

S

/

P

0

1

RC­LPF

A/D
Conv.

BPF

EX­PANDER

1

0

RC­LPF

D/A
Conv.

LPF

COM­PANDER

BLOCK DIAGRAM

¡ Semiconductor

PIN CONFIGURATION (TOP VIEW)

MSM7540L/7560L

1

RES

PCMRI

PCMRO

PCMSI

PCMSO

GSX1

2

3

4

IR

5

IS

6

7

8

LPS

9

DG

10

AG

11

SG

12

AIN1

13

14 15

AIN2 GSX2

28

27

26

25

24

23

22

21

20

19

18

17

16

BCLKB

BCLKA

XSYNC

RSYNC

MCK

X2

X1

PDN

V

DD

AOUT+

AOUT–

PWI

VFRO

X1
X2

NC

MCK
RSYNC
XSYNC

BCLKA
BCLKB

RES

PCMRI

PCMRO

IR
IS

NC

PCMSI

PCMSO

10
11
12
13
14
15
16

28-Pin Plastic SOP

1
2
3
4
5
6
7
8
9

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

PDN

V

DD

NC
AOUT+
AOUT–
PWI
VFRO
GSX2
AIN2

GSX1
AIN1
SG
AG
NC
DG
LPS

NC: No connection

32-Pin Plastic TSOP

3/15

¡ Semiconductor

(

)

MSM7540L/7560L

PIN AND FUNCTIONAL DESCRIPTIONS

AIN1, AIN2, GSX1, GSX2

Transmits analog input and the output for transmit gain adjustment.
AIN1 (AIN2) connects to the inverting input of the internal transmit amplifier. GSX1 (GSX2)
connects to the output of the internal transmit amplifier output. Refer to Fig. 1 for gain
adjustment.

VFRO, AOUT+, AOUT–, PWI

Receives analog output and the output for receive gain adjustment.
VFRO is receive filter output. AOUT+ and AOUT– are differential analog signal outputs which
can directly drive ZL = 350 W + 120 nF. Refer to Fig. 1 for gain adjustment.

Analog Input

Transmit Gain:
= (R2/R1) ¥ (R4/R3)

Receive Gain:
= (R6/R5)

C1

C2

R1

R3

RS*

R2

R4

R5

AIN1

GSX1

AIN2

GSX2

VFRO

PWI

–

+

–

+

to ENCODER

from DECODER

R6

V

+ 350 W

Analog OutputZL=120 nF

0

*: Side Tone Pass

Figure1 Analog Input/Output Interface

AOUT–

AOUT+

Gain = R6/RS

–

+

–1

4/15

¡ Semiconductor

MSM7540L/7560L

SG

Analog signal ground voltage output.
The output voltage of this pin is approximately 1.4 V. Put bypass capacitors between this pin
and the AG pin. During power-down this output voltage is 0 V. The external SG voltage, if
necessary, should be used via a buffer.

AG

Analog ground.

DG

Digital ground.
This ground is separated internally from the analog signal ground pin (AG). The DG pin must
be kept as close as possible to AG on the PCB.

V

DD

+3 V power supply.

LPS

PCM coding law selection.
MSM7540L only; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the
A-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value
character signal (2's complement).
MSM7560L only; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the
m-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value
character signal (2's complement).

PDN

Power down control input.
If this pin is "0", this device is in the power-down state.
Normally, this pin is set to "1".

RES

Optional reset input specified by ITU-T Recommendation G. 721.
If this pin is "0", the device is in the reset state. The reset width (during "L") should be 125 ms or
more.

MCK

Master clock input.
The frequency must be 10.368 MHz. The master clock signal may be asynchronous to BCLKA,
BCLKB, XSYNC, and RSYNC.

PCMSO

Transmit PCM data output.
PCM is output from MSB in synchronization with the rising edge of BCLKB and XSYNC.

5/15

¡ Semiconductor

PCMSI

Transmit PCM data input.
This signal is converted to transmit ADPCM data. PCM is shifted in synchronization with the
falling edge of BCLKB. Normally, this pin is connected to PCMSO.

PCMRO

Receive PCM data output.
PCM is the output signal after ADPCM decoder processing. This signal is output serially from
MSB in synchronization with the rising edge of BCLKB and RSYNC.

PCMRI

Receive PCM data input.
PCM is shifted on the falling edge of the BCLKB input from MSB. Normally, this pin is connected
to PCMRO.

IS

MSM7540L/7560L

Transmit ADPCM signal output.
After having encoded PCM with ADPCM, this signal is output from MSB in synchronization
with the rising edge of BCLKA and XSYNC. This pin is an open drain output and remains in a
high impedance state during power-down. IS requires a pull-up resistor.

IR

Receive ADPCM signal input.
The ADPCM signal is shifted in series and synchronization with the falling edge of BCLKA and
RSYNC and output from MSB.

BCLKB

Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI).
The frequency is set in the 64 kHz to 2048 kHz range.

XSYNC

8 kHz synchronous signal input for transmit PCM and ADPCM data.
Synchronize this signal with BCLKA and BCLKB signal. XSYNC is used to indicate the MSB of
the serial PCM and ADPCM data stream.
Be sure to input the XSYNC signal because it is also used as the imput of the timing generator.

RSYNC

8 kHz synchronous signal input for receive PCM and ADPCM data.
Synchronize this signal with BCLKA and BCLKB signal. RSYNC is used to indicate the MSB of
the serial PCM and ADPCM data stream.

BCLKA

Shift clock input for the ADPCM data (IS, IR).
The frequency is set in the of 32 kHz to 2048 kHz range.

6/15

¡ Semiconductor

MSM7540L/7560L

X1, X2

Crystal oscillator (10.368 MHz) connection.
Connect X2, the clock output pin, directly to the MCK pin.
When using a conventional external clock of 10.368 MHz, X1 should be connected to the ground,
X2 open, and provide the external clock through the MCK pin.

<Using a self-oscilation circuit>

MSM7540L/60L

X1

10.368 MHz

X2

MCK

<Using an external clock>

MSM7540L/60L

X1

10.368 MHz

X2

MCK

7/15

¡ Semiconductor

ABSOLUTE MAXIMUM RATINGS

MSM7540L/7560L

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Storage Temperature

Symbol

V

DD

V

AIN

V

DIN

T

STG

Condition

—

—

—

—

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Operating Temperature

Input High Voltage

Input Low Voltage

Master Clock Frequency

Bit Clock Freqency

Synchronous Signal Frequency

Clock Duty Ratio

Digital Input Rise Time

Digital Input Fall Time

Transmit Sync Signal Setting Time

Receive Sync Signal Setting Time

Synchronous Signal Width

PCM, ADPCM Set-up Time

PCM, ADPCM Hold Time

Digital Output Load

Bypass Capacitor for SG

Symbol

V

DD

Ta

V

IH

V

IL

f

MCK

f

BCKA

f

BCKB

f

SYMC

D

C

t

Ir

t

If

t

XS

t

XS

t

RS

t

SR

t

WS

t

DS

t

DH

R

DL

C

DL

C

SG

Condition Min. Typ. Max. Unit

Voltage must be fixed 2.7 — 3.6 V

MCK, XSYNC, RSYNC, PCMRI,

PCMSI, BCLKA, BCLKB, IR,

LPS, PDN, RES

MCK, XSYNC, RSYNC, PCMRI,

PCMSI, BCLKA, BCLKB, IR,

LPS, PDN, RES

MCK –

BCLKA 32 — 2048 kHz

BCLKB 64 — 2048 kHz

XSYNC, RSYNC — 8.0 — kHz

MCK, BCLKA, BCLKB 30 50 70

MCK, XSYNC, RSYNC, PCMRI,

PCMSI, BCLKA, BCLKB, IR,

LPS, PDN, RES

MCK, XSYNC, RSYNC, PCMRI,

PCMSI, BCLKA, BCLKB, IR,

LPS, PDN, RES

BCLKA, BCLKB to XSYNC 100 — — ns

XSYNC to BCLKA, BCLKB 100 — — ns

BCLKA, BCLKB to RSYNC 100 — — ns

RSYNC to BCLKA, BCLKB 100 — — ns

XSYNC, RSYNC 1 BCLK — 100 ms

— 100 — — ns

— 100 — — ns

IS (Pull-up Resistor) 500 — — W

IS, PCMSO, PCMRO

SG´GND

Rating

–0.3 to +5

–0.3 to V

–0.3 to V

–55 to +150

DD

DD

+ 0.3

+ 0.3

Unit

V

V

V

°C

–25 +25 +75 °C—

0.45

¥ V

DD

—VDDV

0.16

0—

0.01%

10.368 +

¥ V

DD

0.01%

V

MHz

%

——50ns

——50ns

— — 100 pF

— 10+0.1 — mF

8/15

¡ Semiconductor

ELECTRICAL CHARACTERISTICS

MSM7540L/7560L

DC and Digital Interface Characteristics

Parameter

Power Supply Current

Input High Voltage

Input Low Voltage

Input Leakage Current

Output Low Voltage

Output Leakage Current

Input Capacitance

Symbol

I

DD1

I

DD2

V

IH

V

IL

I

IH

I

IL

V

OL

I

O

C

IN

Operating Mode,

No Signal (

Power Down Mode (

VI = V

DD

VI = 0 V

1 LSTTL, Pull-up: 500 W

IS

Transmit Analog Interface Characteristics

Parameter

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Input Offset Voltage

SG Output Voltage V

SG Output Inpedance R

SG Rise Time T

Symbol

R

INX

R

LGX

C

LGX

V

OGX

V

OFGX

SG

SG

SG

AIN1, AIN2

GSX1, GSX2

GSX1, GSX2

GSX1, GSX2, R

Pre–OPAMPs

GND´SG 10 mF + 0.1 mF

(Rise Time to 90% of max.

level)

2.7 V to 3.6 V, Ta = –25°C to +70°C)

(V

DD =

Condition

Min.

—

Typ.

6

Max.

12

Unit

VDD = 3.0 V)

—

0.45 ¥ V

0.0

—

—

0.0

—

DD

0.1

—

—

—

—

0.2

—

0.2

V

DD

0.16 ¥ V

2.0

0.5

0.4

10

DD

—

—

V

DD

= 3.0 V)

— —5—pF

Condition

= 20 kW

L

—

—

Min.

10

20

—

—

–20

Typ.

—

—

—

—

—

Max.

—

—

100

*1.300

+20

— 1.4 — V

—4080kW

Unit

MW

kW

V

mV

— 700 — ms

mA

mA

V

V

mA

mA

V

mA

pF

PP

Receive Analog Interface Characteristics

Parameter

Input Resistance

Output Load Resistance

Output Capacitance

Output Voltage Level

Offset Voltage

Open Loop Gain

Symbol

R

INPW

R

LVF

R

LAO

C

LVF

C

LAO

V

OVF

V

OAO

V

OFVF

V

OFAO

G

DB

Condition

PWI

VFRO

AOUT+, AOUT–

VFRO

AOUT+, AOUT–

VFRO,

AOUT+,
AOUT–

RL = 50 kW

R

= 1.2 kW

L

Z

= 350 W

L

+ 120 nF(See Fig.1)

VFRO

AOUT+, AOUT– (GAIN = 0 dB),

Power amp only

Power amp (0.3 to 3.4 kHz,

Z

= 350 W + 120 nF)(See Fig.1)

L

Min.

10

50

1.2

—

—

—

—

—— V

–100

–20

40——dB

* –7.7 dBm (600 W) = 0 dBm0, + 3.14 dBm0 = 1.300 VPP (MSM7540L)

–7.7 dBm (600 W) = 0 dBm0, + 3.17 dBm0 = 1.300 VPP (MSM7560L)

Typ.

—

—

—

—

—

—

—

—

—

Max.

—

—

—

100

100

*1.300

*1.300

*1.300

+100

+20

Unit

MW

kW

kW

pF

pF

V

PP

V

PP

PP

mV

mV

9/15

¡ Semiconductor

MSM7540L/7560L

AC Chracteristics

Parameter

Transmit Frequency

Response

Receive Frequency

Response

Transmit Signal

to Distortion Ratio

Receive Signal

to Distortion Ratio

Transmit Gain

Tracking

Receive Gain

Tracking

(V

2.7 V to 3.6 V, Ta = –25°C to +70°C)

DD =

Condition

Symbol

Freq.

Level

Others

Min.

Typ.

Max.—Unit

(dBm0)(Hz)

L

T1

0 to 60

T2

300 to 3000 –0.15 — +0.20 dB

T3

T4

T5

T6

R1

R2

R3

R4

R5

1020 Reference dB

0

—

3300 –0.15 — +0.80 dB

3400 0 — 0.80 dB

3968.75 13 — — dB

0 to 3000 –0.15 — +0.20 dB

1020 Reference dB

3300 –0.15 — +0.80 dB0

—

3400 0 — 0.80 dB

3968.75 13 — — dB

L

L

L

L

L

L

L

L

L

L

OSS

OSS

OSS

OSS

OSS

OSS

OSS

OSS

OSS

OSS

OSS

SD T1 35 —3

SD T2 35 —0

SD T3 35 —–30

1020

(*1)

SD T4

SD T5 23 —–45

SD R1 —3

SD R2 —0

SD R3 —–30

1020

(*1)

SD R4

SD R5 —–45

GT T1 –0.2 +0.2

GT T2 Reference

GT T3 1020 –0.2 +0.2–40

GT T4 –0.5 +0.5

GT T5 –1.2 +1.2

GT R1 –0.2 +0.2

GT R2 Reference

GT R3 1020 –0.2 +0.2

GT R4 –0.5 +0.5

GT R5 –1.2 +1.2

3

–10

–50

–55

3

–10

–40

–50

–55

—

—

25

28 —–40

35

35

35

28

23

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

dB

dB

dB

dB

dB

dB

dB

dB

dB

—–40

dB

dB

dB

dB

dB

dB

dB

dB

dB

dB

dB

dB

*1 Use the P-message weighted filter

10/15

¡ Semiconductor

MSM7540L/7560L

AC Characteristics (Continued)

Parameter

Idle Channel Noise

Absolute Signal

Amplitude

Power Supply Noise

Rejection Ratio

Digital Output

Delay Time

Symbol

N

IDLT

N

IDLR

A

VT

A

VR

P

SRRT

P

SRRR

t

SDX

t

SDR

t

XD1

t

XD2

t

XD3

Noise Freq.

: 0 to 50 kHz

(V

2.7 V to 3.6 V, Ta = –25°C to +70°C)

DD =

Condition

Freq.

Level Min. Typ. Max. Unit

Others

(dBm0)(Hz)

–68

———

——

AIN = SG

—

(*1)

(*1)

(*2)

—

(–75.7)

–72

(–79.7)

dBm0p

(dBmp)

0.320

GSX2

0.285

0.359

Vrms

(*3)

1020

0

0.320

VFRO

0.285

0.359

Vrms

(*3)

Noise Level

30——dB

—

: 50 mV

PP

30——dB

50 — 200

50 — 200

ns

ns

1 LSTTL + 100 pF,

—

—

50 — 200

ns

Pull-up: 500 W

50 — 200

50 — 200

ns

ns

*1 Use the P-message weighted filter
*2 PCMRI input code "11010101"(MSM7540L)

"11111111"(MSM7560L)

*3 0.320 Vrms = 0 dBm0 = –7.7 dBm

Note: All ADPCM coder and decoder characteristics comply with ITU-T Recommendation

G.721.

11/15

¡ Semiconductor

(

)

TIMING DIAGRAM

Transmit Side PCM/ADPCM Data Interface

MSM7540L/7560L

BCLKB

XSYNC

PCMSO

PCMSO

012345678910

tsx

txs

tsdx

tws

txd1 txd2

MSB LSB

MSB

(during linear)

BCLKA

XSYNC

IS

012345678910

tsx

txs

txd1 txd2

MSB LSB

tsdx

txd3

Receive Side PCM/ADPCM Data Interface

BCLKA

RSYNC

IR

0 1 2 3 4 5 6 7 8 9 10 11 12 13

tsr

trs

MSB LSB

tds

tws

tdh

txd3

txd3

11 12 13

14

txd3

LSB

14

BCLKB

012345678910

tsr

trs

RSYNC

trd1

PCMRO

tsdx

PCMRO

MSB LSB

MSB

during linear

Note: Linear format

A code of an input/output level is determined by the 14-bit 2'compliment.
Refer to the table below for code format.

trd2

Input/Output level

+Full-scall

–Full-scall

txd3

trd3

LSB

MSB to LSB

01111111111111

0

00000000000000

10000000000000

12/15

¡ Semiconductor

APPLICATION CIRCUIT

V

DD

Receive
PCM Output

Receive ADPCM Input

Transmit ADPCM Output

Transmit
PCM Output

Transmit Analog Input

MSM7540L/7560L

1

RES

2

PCMRI

3

PCMRO

4

IR

5

IS

6

PCMSI

7

PCMSO

8

LPS

9

DG

10

AG

11

SG AOUT–

12

AIN1 PWI

13

GSX1 VFRO

14

AIN2 GSX2

BCLKB

BCLKA

XSYNC

RSYNC

MCK

X2

X1

PDN

V

DD

AOUT+

28

27

26

25

24

23

22

21

20

19

18

17

16

15

V

DD

10.368 MHz

MSM7540L/7560L

ADPCM Algorithm
Reset Input

Shift Clock Input for
PCM, ADPCM Data
(64 kHz to 2048 kHz)

8 kHz Sync Signal Input

Power Down Input

Receive Analog Output

(Push-Pull)

13/15

¡ Semiconductor

PACKAGE DIMENSIONS

SOP28-P-430-1.27-K

Mirror finish

MSM7540L/7560L

(Unit : mm)

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.75 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

14/15

¡ Semiconductor

TSOPI32-P-814-0.50-1K

Mirror finish

MSM7540L/7560L

(Unit : mm)

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.27 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

15/15