Datasheet MSM7534HGS-K, MSM7534RS, MSM7533HVGS-K, MSM7533HGS-K, MSM7533VRS Datasheet (OKI)

E2U0020-28-81

¡ Semiconductor MSM7533H/7533V/7534

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7533H/7533V/7534

2ch Single Rail CODEC

GENERAL DESCRIPTION

The MSM7533 and MSM7534 are two-channel CODEC CMOS ICs for voice signals ranging from
300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices
contain two-channel AD/DA converters in a single chip and achieve a reduced footprint and a
reduced number of external components.
The MSM7533 and MSM7534 are best suited for an analog interface to an echo canceller DSP used
in digital telephone terminals, digital PABXs, and hands free terminals.

FEATURES

• Single power supply: +5 V

• Power consumption
Operating mode: 35 mW Typ. 74 mW Max. VDD = 5 V
Power save mode: 7 mW Typ. 16 mW Max. VDD = 5 V
Power down mode: 0.05 mW Typ. 0.3 mW Max. VDD = 5 V

• ITU-T Companding law

MSM7533H: m-law
MSM7534: A-law
MSM7533V: m/A-law pin selectable

• Built-in PLL eliminates a master clock

• The PCM interface can be switched between 2 channel serial/parallel

• Transmission clock: 64/128/256/512/1024/2048 kHz

96/192/384/768/1536/1544/200 kHz
(During 2 channel serial mode, the 64 and 96 kHz clocks are disabled)

• Adjustable transmit gain

• Built-in reference voltage supply

• Analog output can directly drive a 600 W line transformer

• Package options:
20-pin plastic skinny DIP (DIP20-P-300-2.54-S1) (Product name : MSM7533HRS)

(Product name : MSM7533VRS)
(Product name : MSM7534RS)

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7533HGS-K)

(Product name : MSM7533VGS-K)
(Product name : MSM7534GS-K)

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¡ Semiconductor MSM7533H/7533V/7534

BLOCK DIAGRAM

AIN1

GSX1

AIN2

GSX2

AOUT1

AOUT2

SGC

–
+

–
+

–
+

–
+

SG

GEN

5th

LPF

5th

LPF

RC

LPF

RC

LPF

VR

GEN

8th

BPF

8th

BPF

S&H

S&H

AUTO
ZERO

DA

CONV.

AD

CONV.

TCONT

PLL

RTIM

RCONT

PWD

Logic

DOUT1
DOUT2

XSYNC

BCLK

RSYNC

(ALAW)

CHPS
DIN1
DIN2

PDN

V

DD

AG
DG

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¡ Semiconductor MSM7533H/7533V/7534

PIN CONFIGURATION (TOP VIEW)

SGC

AOUT2

AOUT1

PDN

CHPS

V

DD

DG

RSYNC

DIN2

DIN1

1

2

3

4

5

6

7

8

9

10 11

20

19

18

17

16

15

14

13

12

AIN2

GSX2

GSX1

AIN1

(ALAW) *

AG

BCLK

XSYNC

DOUT2

DOUT1

1

SGC

AOUT2

AOUT1

CHPS

RSYNC

2

3

NC

4

PDN

5

6

7

NC AG

V

8

DD

9

DG

10

11

DIN2

12 13

DIN1

NC : No connect pin

24-Pin Plastic SOP

24

AIN2

23

GSX2

22

GSX1

21

AIN1

20

NC

19

(ALAW) *

18

17

NC

16

BCLK

15

XSYNC

14

DOUT2

DOUT1

20-Pin Plastic Skinny DIP

* The ALAW pin is only applied to the MSM7533VRS/MSM7533VGS-K.

3/18

¡ Semiconductor MSM7533H/7533V/7534

PIN AND FUNCTIONAL DESCRIPTIONS

AIN1, AIN2, GSX1, GSX2

AIN1 and AIN2 are the transmit analog inputs for channels 1 and 2.
GSX1 and GSX2 are the transmit level adjustments for channels 1 and 2.
AIN1 and AIN2 are inverting inputs for the op-amp; GSX1 and GSX2 are connected to the output
of the op-amp and are used to adjust the level, as shown below.
When not using AIN1 and AIN2, connect AIN1 to GSX1 and AIN2 to GSX2. During power saving
and power down mode, the GSX1 and GSX2 outputs are at AG voltage.

CH1
Analog Input

CH2
Analog Input

R2

C1 R1

R4

C2 R3

GSX1

AIN1

GSX2

AIN2

CH1 Gain
–
+

–
+

Gain = R2/R1 £ 10

R1: Variable

R2 > 20 kW

C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

CH2 Gain

Gain = R4/R3 £ 10

R3: Variable

R4 > 20 kW

C2 > 1/(2 ¥ 3.14 ¥ 30 ¥ R3)

AOUT1, AOUT2

AOUT1 is the receive analog output for channel 1 and AOUT2 is used for channel 2.
The output signal has an amplitude of 3.4 VPP above and below the signal ground voltage (SG).
When the digital signal of +3 dBmO is input to DIN1 and DIN2, it can drive a load of 600 W or
more.
During power saving or power down mode, these outputs are at the voltage level of SG with a
high impedance.

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¡ Semiconductor MSM7533H/7533V/7534

V

DD

Power supply for +5 V.
A power supply for an analog circuit of the system which the device is applied should be used.
A bypass capacitor of 0.1 mF to 1 mF with excellent high frequency characteristics and a capacitor
of 10 mF to 20 mF should be connected between this pin and the AG pin if needed.

DIN1

DIN1 is the PCM signal input for channel 1, when the parallel mode is selected.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The analog signal is output from the AOUT1 pin.
The data rate of the PCM signal is equal to the frequency of BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is not used and should be connected to GND (0 V).

DIN2

DIN2 is the PCM signal input for channel 2, when the parallel mode is selected.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The analog signal is output from the AOUT2 pin.
The data rate of the PCM signal is equal to the frequency of BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is used for the 2ch multiplexed PCM signal input.

BCLK

Shift clock signal input for the DIN1, DIN2, DOUT1, and DOUT2 signals.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.

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¡ Semiconductor MSM7533H/7533V/7534

RSYNC

Receive synchronizing signal input.
The eight bits PCM data required are selected from serial PCM signals on the DIN1 and DIN2
pins by the receive synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK (generated from the same clock source as BCLK). The

frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly the

frequency characteristic of the receive section.
However, if the frequency characteristic of the system used is not strictly specified, this device
can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics in this specifications
are not guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the DOUT1 and DOUT2 pins is output in synchronization with this
transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all
timing signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristic of the transmit section.
However, if the frequency characteristic of the system used is not strictly specified, this device
can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics in this specification
are not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to power saving
state.

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¡ Semiconductor MSM7533H/7533V/7534

DOUT1

PCM signal output of channel 1 when the parallel mode is selected.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance sate during power saving or power down mode.
When the serial mode is selected, this pin is for the output of serial multiplexed 2ch PCM signal.
A pull-up resistor must be connected to this pin because it is an open drain output.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7534(A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

+0

–0

–Full scale

MSM7533H (m-law)

MSD

1000 0000

1111 1111

0111 1111

0000 0000

PCMIN/PCMOUT

MSM7534 (A-law)

MSD

1010 1010

1101 0101

0101 0101

0010 1010

DOUT2

PCM signal outputs for channel 2 when the parallel mode is selected.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down modes.
When the serial mode is selected, this pin is left open.
A pull-up resistor must be connected to this pin because it is an open drain output.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7534(A-law) outputs the character signal, inverting the even bits.

7/18

¡ Semiconductor MSM7533H/7533V/7534

CHPS

Control signal input for the mode selection of PCM input and output.
When this signal is at a logic "1" level, the PCM input and output are in the parallel mode. The
PCM data of CH1 and CH2 is input to DIN1 and DIN2, and output from DOUT1 and DOUT2
with the same timing.
When this signal is at a logic "0" level, the PCM input and output is in the serial mode. The PCM
data of CH1 and CH2 is input to DIN2 and output from DOUT1 as time division multiplexed
data.
The parallel mode is conveniently applied to the digital interface to the echo canceller (MSM7520),
and the serial mode is applied to the digital interface to PCM multiplexer's for PABXs.

PDN

Power down control signal.
When PDN is at a logic "0" level, both transmit and receive circuits are in a power down state.

AG

Analog signal ground.

DG

Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.

SGC

Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.

ALAW

Control signal input of the companding law selection.
Provides only for the MSM7533VRS/MSM7533VGS-K. The CODEC will operate in the m-law
when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin is at
a logic "1" level. The CODEC operates in the m-law if the pin is left open, since this pin is internally
pulled down.

8/18

¡ Semiconductor MSM7533H/7533V/7534

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Storage Temperature

Symbol

V

DD

V

AIN

V

DIN

T

STG

Condition

—

—

—

—

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Operating Temperature Ta

Analog Input Voltage

Digital Input High Voltage

Digital Input Low Voltage

Clock Frequency

Sync Pulse Frequency

Clock Duty Ratio

Digital Input Rise Time

Digital Input Fall Time

Transmit Sync Pulse Setting Time

Receive Sync Pulse Setting Time

Sync Pulse Width

DIN Set-up Time

DIN Hold Time

Digital Output Load

Analog Input Allowable DC Offset

Allowable Jitter Width

Symbol

V

DD

V

AIN

V

IH

V

IL

F

C

F

S

D

C

t

Ir

t

If

t

XS

t

SX

t

RS

t

SR

t

WS

t

DS

t

DH

R

DL

C

DL

V

off

—

Condition

Voltage must be fixed

—

Gain = 1

XSYNC, RSYNC, BCLK,

DIN1, DIN2, PDN, CHPS

BCLK = (eliminates 64, 96 kHz,

when 2ch serial mode)

XSYNC, RSYNC

BCLK

XSYNC, RSYNC, BCLK, DIN1,

DIN2, PDN, CHPS

BCLKÆXSYNC, See Timing Diagram

XSYNCÆBCLK, See Timing Diagram

BCLKÆRSYNC, See Timing Diagram

RSYNCÆBCLK, See Timing Diagram

XSYNC, RSYNC

DIN1, DIN2

DIN1, DIN2

Pull-up resistor, DOUT1, DOUT2

DOUT1, DOUT2

Transmit gain stage, Gain = 1

Transmit gain stage, Gain = 10

XSYNC, RSYNC

Rating

0 to 7

–0.3 to V

–0.3 to V

DD

DD

+ 0.3

+ 0.3

–55 to +150

Min. Typ. Max. Unit

4.75

–30 +85

—

2.2

0

5.0

+25 °C

—

—

—

5.25

3.4

V

DD

0.8

64, 128, 256, 512, 1024,

2048, 96, 192, 384, 768,

1536, 1544, 200

6.0

40

—

—

100

100

100

100

1 BCLK

100

100

0.5

—

VDD/2–100

VDD/2–10

—

8.0

50

—

—

—

—

—

—

—

—

—

—

—

—

—

—

9.0

60

50

50

—

—

—

—

100

—

—

—

100

VDD/2+100

VDD/2+10

500

Unit

V

V

V

°C

V

V

PP

V

V

kHz

kHz

%

ns

ns

ns

ns

ns

ns

ms

ns

ns

kW

pF

mV

mV

ns

9/18

¡ Semiconductor MSM7533H/7533V/7534

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

(V

= +5 V ±5%, Ta = –30°C to +85°C)

DD

Parameter

Power Supply Current

Symbol

I

DD1

I

DD2

Condition

Operating mode, No signal

Power-save mode, PDN = 1,

XSYNC or BCLK OFF

Min.

—

—

Typ.

7.0

1.3

Max.

14.0

3.0

Unit

mA

mA

Power-down mode, PDN = 0

I

DD3

Input High Voltage

Input Low Voltage

High Level Input Leakage Current

Low Level Input Leakage Current

Digital Output Low Voltage

Digital Output Leakage Current

Input Capacitance

V

IH

V

IL

I

IH

I

IL

Pull-up resistance > 500 W

V

OL

I

O

C

IN

Transmit Analog Interface Characteristics

Parameter

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

Symbol

R

INX

R

LGX

C

LGX

V

OGX

V

OSGX

AIN1, AIN2

GSX1, GSX2

with respect to SG

mA

V

V

mA

mA

V

mA

—

—

—

—

—

—

2.2

0.0

—

—

0.0

—

0.01

—

—

—

—

0.2

—

0.05

V

DD

0.8

2.0

0.5

0.4

10

— —5—pF

(V

= +5 V ±5%, Ta = –30°C to +85°C)

DD

Condition Min. Typ. Max. Unit

Gain = 1

10

20

—

–1.7

–20

—

—

—

—

—

—

—

30

+1.7

+20

MW

kW

pF

V

mV

Receive Analog Interface Characteristics

Parameter

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

Symbol

R

LAO

C

LAO

V

OAO

V

OSAO

AOUT1, AOUT2 (each) with

respect to SG

AOUT1, AOUT2

AOUT1, AOUT2, R

with respect to SG

AOUT1, AOUT2

with respect to SG

= +5 V ±5%, Ta = –30°C to +85°C)

(V

DD

Condition Min. Typ. Max. Unit

= 0.6 kW,

L

0.6

—

–1.7

–100

—

—

—

—

—

50

+1.7

+100

kW

pF

V

mV

10/18

¡ Semiconductor MSM7533H/7533V/7534

AC Characteristics

(V

= +5 V ±5%, Ta = –30°C to +85°C)

DD

Parameter

Transmit Frequency Response

Receive Frequency Response

Transmit Signal to Distortion Ratio 1020 dB

Receive Signal to Distortion Ratio 1020 dB

Transmit Gain Tracking

Receive Gain Tracking

Symbol

Loss T1

Loss T2

Loss T3

Loss T4

Loss T5

Loss T6

Loss R1

Loss R2

Loss R3

Loss R4

Loss R5

SD T1 35 43 —3

SD T2 35 41 —0

SD T3 35 38 —–30

SD T4 29 31.5 —–40

SD T5 24 27 —–45

SD R1 36 43 —3

SD R2 36 41 —0

SD R3 36 40 —–30

SD R4 30 33.5 —–40

SD R5 25 30 —–45

GT T1 –0.3 +0.01 +0.3

GT T2 Reference

GT T3 1020 –0.3 –0.09 +0.3 dB–40

GT T4 –0.5 –0.09 +0.5

GT T5 –1.2 –0.1 +1.2

GT R1 –0.3 0 +0.3

GT R2 Reference

GT R3 1020 –0.3 +0.09 +0.3 dB

GT R4 –0.5 +0.2 +0.5

GT R5 –1.2 +0.23 +1.2

Freq.

(Hz)

300 –0.15 +0.07 +0.20 dB

1020 Reference dB

2020 –0.15 –0.04 +0.20 dB

3000 –0.15 +0.06 +0.20 dB

3400 0 0.4 0.80 dB

300 –0.15 –0.03 +0.20 dB

1020 Reference dB

2020 –0.15 –0.02 +0.20 dB0

3000 –0.15 +0.15 +0.20 dB

3400 0.0 0.45 0.80 dB

Level

(dBm0)

60 20 26 — dB

–10

–50

–55

–10

–40

–50

–55

0

3

3

Condition

*1

*1

Min. Typ. Max. Unit

*1 Psophometric filter is used

11/18

¡ Semiconductor MSM7533H/7533V/7534

AC Characteristics (Continued)

(V

= +5 V ±5%, Ta = –30°C to +85°C)

DD

Parameter

Idle Channel Noise

Absolute Level (Initial Difference)

Absolute Level

(Deviation of Temperature and Power)

Absolute Delay

Transmit Group Delay

Receive Group Delay

Crosstalk Attenuation

Symbol

Freq.

(Hz)

Nidle T

Nidle R

——

— –78

AV T 0.821 0.850 0.880

Level

(dBm0)

—

—

Condition

AIN = SG

*1*2

*1 *3

V

= 5.0 V

DD

Min. Typ. Max. Unit

–73.5

–71.5

–70

–68

— –75

Ta = 25°C

AV R 0.821 0.850 0.880

1020

0

AV Tt –0.2 — +0.2

V

DD

*4

= 5 V ±

5%

Ta = –30

AV Rt –0.2 — +0.2

to 85°C

*4

A to A

Td 1020 — — 0.6 ms0

BCLK

= 64 kHz

T1 — 0.19 0.75

t

gd

tgd T2 — 0.11 0.35

tgd T3 — 0.02 0.1250

T4 — 0.05 0.125

t

gd

T5 — 0.75

gd

tgd R1

t

R2

gd

t

R3

gd

R4

t

gd

t

R5

gd

500

600

1000

2600

2800

500

600

1000

2600

2800

CR T 7580—

CR R 76

1020 dB0

*5

*5

TRANS Æ RECV

RECV Æ TRANS

0.07t

— 0.00 0.75

— 0.35

0.00

— 0.00 0.125 ms0

— 0.09 0.125

— 0.12 0.75

70 —

CR CH 78CH to CH 73 —

dBmOp

Vrms

dB

dB

ms

*1 Psophometric filter is used
*2 Upper is specified for the m-law, lower for the A-law
*3 Input "0" code to PCMIN
*4 AVT is defined between GSX and DOUT and AVR between DIN and AOUT
*5 Minimum value of the group delay distortion

12/18

¡ Semiconductor MSM7533H/7533V/7534

AC Characteristics (Continued)

(V

= +5 V ±5%, Ta = –30°C to +85°C)

DD

Parameter

Symbol

Freq.

(Hz)

(dBm0)

4.6 kHz to

Discrimination 0

DIS

72 kHz

300 to

S

3400

fa = 470

IMD

fd = 320

Digital Output Delay Time

PSR T

PSR R

t

SD

t

XD1

t

XD2

t

XD3

0 to

50 kHz

CL = 100 pF + 1 LSTTL

*6 The measurement under idle channel noise

Level

Condition

0 to

4000 Hz

4.6

100 kHz

*6

PP

kHz

Min. Typ. Max. Unit

30 32 — dB

to

— –37.5 –35 dBmOOut-of-band Spurious 0

— –52 –35 dBmOIntermodulation Distortion –4 2fa – fd

—30—dBPower Supply Noise Rejection Ratio 50 mV

20 — 200

20 — 200

ns

20 — 200

20 — 200

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¡ Semiconductor MSM7533H/7533V/7534

TIMING DIAGRAM

Transmit Timing

BCLK 12345678910

t

XS

XSYNC

DOUT1

t

XD1

DOUT2 D2

t

SX

t

WS

t

SD

t

XD2

t

XD3

D3 D4 D5 D6 D7 D8MSD

Transmit Side

Receive Timing

BCLK 12345678910

RSYNC

DIN1
DIN2

t

RS

t

SR

t

WS

D2

t

DS

t

DH

D3 D4 D5 D6 D7MSD

D8

Receive Side

11

11

BCLK

XSYNC

DOUT1

BCLK

RSYNC

DIN2

Figure. 1 Timing Diagram in the Parallel Mode (CHPS = 1)

MSD

D2 D3 D4 D5 D6 D7 D8 MSD D2 D3 D4 D5 D6 D7 D8

CH1 PCM Data CH2 PCM Data

Transmit Side

MSD

D2 D3 D4 D5 D6 D7 D8 MSD D2 D3 D4 D5 D6 D7 D8

CH1 PCM Data CH2 PCM Data

Receive Side

Figure. 2 Timing Diagram in the Serial Mode (CHPS = 0)

14/18

¡ Semiconductor MSM7533H/7533V/7534

APPLICATION CIRCUIT

Example of Basic Connection (PCM Serial Mode Operation)

+5 V

CH1
Analog Input

CH1
Analog Output

CH2
Analog Input

CH2
Analog Output

0 V

+5 V

0 to 20 W

0.1 mF

10 mF1 mF

+

AIN1
GSX1

AOUT1

AIN2
GSX2

AOUT2

SGC
AG
DG

MSM7533

DOUT1
DOUT2

DIN2
DIN1

BCLK

XSYNC
RSYNC

PDN

CHPS

V

DD

1 kW

(Open)

0 V

0 V

2CH Multiplex PCM
Signal Output

2CH Multiplex PCM
Signal Intput

Bit Clock Input
Sync Pulse Input

Power Down Control Input

1: Operation
0: Power Down

Example of Interface to the Echo Canceller MSM7520

MSM7533

SIN

ROUT

+5 V

RESET

POWER DOWN

+5 V

0 V

10 kW

+5 V

+5 V

0 V

AIN1
GSX1

AOUT1
PDN

CHPS
XSYNC

RSYNC
BCLK
DIN1
DOUT1

MSM7520-001

SIN
ROUT
SCK

SYNC

INT
IRLD

SYNCO
SCKO

RST
PWDWN

CKSEL
V

DD

AOUT2

GSX2

AIN2

V

DD

SGC

AG

DG

DOUT2

DIN2

SOUT

RIN

NLP

GC

HCL

ADP

ATT

V

SS

X1
X2

0.1 mF

1 mF

10 kW

10 W

+

10 mF

SOUT

RIN
+5 V

0 V

+5 V

+5 V

36 MHz CLK Input

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¡ Semiconductor MSM7533H/7533V/7534

RECOMMENDATIONS FOR ACTUAL DESIGN

• To assure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the device pins.

• Connect the AG pin and the DG pin each other as close as possible. Connect to the system
ground with low impedance.

• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, use the short lead type socket.

• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
source such as power supply transformers surround the device.

• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch­up phenomenon when turning the power on.

• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.

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¡ Semiconductor MSM7533H/7533V/7534

PACKAGE DIMENSIONS

(Unit : mm)

DIP20-P-300-2.54-S1

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

1.49 TYP.

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¡ Semiconductor MSM7533H/7533V/7534

(Unit : mm)

SOP24-P-430-1.27-K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.58 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

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