Datasheet MSM7507-01GS-K, MSM7507-01MS-K, MSM7507-02GS-K, MSM7507-02MS-K, MSM7507-03GS-K Datasheet (OKI)

E2U0019-28-81

¡ Semiconductor MSM7507-01/02/03

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7507-01/02/03

Single Rail CODEC

GENERAL DESCRIPTION

The MSM7507 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400
Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is
optimized for ISDN terminals, digital wireless systems, and digital PBX systems.
The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal, which is of a differential type and can drive a 600 W load, can directly
drive a handset receiver.

FEATURES

• Single power supply: +5 V ±5%

• Low power consumption
Operating mode: 20 mW Typ. 40 mW Max. VDD = 5 V
Power down mode: 0.03 mW Typ. 0.3 mW Max. VDD = 5 V

• ITU-T Companding law

MSM7507-01: m/A-law pin selectable
MSM7507-02: m-law
MSM7507-03: A-law

• Transmission characteristics conforms to ITU-T G.714

• Built-in PLL eliminates a master clock

• Serial data rate: 64/128/256/512/1024/2048 kHz

96/192/384/768/1536/1544/200 kHz

• Adjustable transmit gain

• Adjustable receive gain

• Built-in reference voltage supply

• Analog output can directly drive a 600 W line transformer

• The 24-Pin SOP package products provide pin compatibility with the MSM7543/7544

• The 20-Pin SSOP package products have 1/3 the foot print of conventional products

• Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7507-01GS-K)

(Product name : MSM7507-02GS-K)
(Product name : MSM7507-03GS-K)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7507-01MS-K)

(Product name : MSM7507-02MS-K)
(Product name : MSM7507-03MS-K)

1/18

¡ Semiconductor MSM7507-01/02/03

BLOCK DIAGRAM

AIN–
AIN+

GSX

SGC

SG

VFRO

PWI

AOUT–

AOUT+

–
+

RC

LPF

SG

GEN

–
+

SG

–
+

SG

–
+

SG

8th

BPF

GEN

5th

LPF

VR

CONV.

AUTO
ZERO

DA

CONV.

PWD

AD

TCONT

PLL

RTIM

RCONT

PWD

Logic

PCMOUT

XSYNC

BCLK

RSYNC
(ALAW)

PCMIN

PDN
V

DD

AG
DG

2/18

¡ Semiconductor MSM7507-01/02/03

PIN CONFIGURATION (TOP VIEW)

1

SG

AOUT+

AOUT–

RSYNC

PCMIN

2

3

4

NC

PWI

5

VFRO

6

7

NC

8

V

DD

DG

9

PDN

10

11

12 13

NC : No connect pin

24-Pin Plastic SOP

24

SGC

AIN+

23

AIN–

22

GSX

21

20

NC

19

NC

(ALAW)*

18

17

NC

16

AG

15

BCLK

14

XSYNC

PCMOUT

1

SG

AOUT+

AOUT–

RSYNC

PCMIN

2

3

PWI

4

VFRO

5

V

6

DD

7

DG

8

PDN

9

10 11

NC : No connect pin

20-Pin Plastic SSOP

20

19

18

17

16

15

14

13

12

* The ALAW pin is only applied to the MSM7507-01GS-K/MSM7507-01MS-K.

SGC

AIN+

AIN–

GSX

NC

(ALAW)*

AG

BCLK

XSYNC

PCMOUT

3/18

¡ Semiconductor MSM7507-01/02/03

PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN–, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.

1) Inverting input type

Analog input

2) Non inverting input type

Analog input

AG

Analog signal ground.

VFRO

C1

C2

R5

R1

R3

R4

R2

GSX
AIN–
AIN+
SG

AIN+
AIN–
GSX

SG

R1 : variable

–
+

+
–

R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

Gain = R2/R1 £ 10

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)

Gain = 1 + R4 / R3 £ 10

Receive filter output.
The output signal has an amplitude of 2.4 VPP above and below the signal ground voltage (SG)
when the digital signal of +3 dBmO is input to PCMIN and can drive a load of 20 kW or more.
For driving a load of 20 kW or less, connect a resistor of 20 kW or more between the pins VFRO
and PWI.
When adding the frequency characteristics to the receive signal, refer to the application example.
During power saving or power down mode, the output of VFRO is at the voltage level of SG.

4/18

¡ Semiconductor MSM7507-01/02/03

PWI, AOUT+, AOUT–

PWI is connected to the inverting input of the receive driver. The receive driver output is
connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO,
PWI, and AOUT–. When the PWI pin is not used, connect the PWI pin to the AOUT– pin, and
leave open the pins AOUT– and AOUT+. The output of AOUT+ is inverted with respect to the
output of AOUT–. Since the signal from which provides differential drive of an impedance of 1.2
kW, these outputs can directly be connected to a receiver of handset using a piezoelectric
earphone. Refer to the application example.

VI

Receive Filter

–
+

SG

–
+

SG

VFRO

PWI

AOUT–

AOUT+

R6

R7

ZLVO

R6 > 20 kW
ZL ≥ 1.2 kW

Gain = VO/VI = 2 ¥ R7/R6 £ 2

During power saving and power down modes, the outputs of AOUT+ and AOUT– are in a high
impedance state.

The electrical driving capability of the AOUT– pin and AOUT+ pin is ±1.3 V maximum. The

output load resistor has a minimum value of 0.6 kW.

If an output amplitude less than ±1.3 V is allowed, these outputs can drive a load resistance less

than that described above. For more details, refer to SINGLE POWER SUPPLY PCM CODEC
APPLICATION NOTE.

V

DD

Power supply for +5 V.

PCMIN

PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.

5/18

¡ Semiconductor MSM7507-01/02/03

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be

synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the

AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.

6/18

¡ Semiconductor MSM7507-01/02/03

DG

Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.

PDN

Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down modes.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7507-03 (A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

+0

–0

–Full scale

PCMIN/PCMOUT

MSM7507-02 (m-law)

MSD

1000 0000

1111 1111

0111 1111

0000 0000

MSM7507-03 (A-law)

MSD

1010 1010

1101 0101

0101 0101

0010 1010

7/18

¡ Semiconductor MSM7507-01/02/03

SG

Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.

The output drive current capability is ±300 mA.

This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power saving or power down modes.

SGC

Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.

ALAW

Control signal input of the companding law selection.
Provides only for the MSM7507-01GS-K/7507-01MS-K. The CODEC will operate in the m-law
when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin is at
a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the pin is internally
pulled down.

8/18

¡ Semiconductor MSM7507-01/02/03

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Storage Temperature

Symbol

V

DD

V

AIN

V

DIN

T

STG

Condition

—

—

—

—

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Operating Temperature Ta

Analog Input Voltage

Input High Voltage

Input Low Voltage V

Clock Frequency

Sync Pulse Frequency

Digital Input Rise Time

Digital Input Fall Time

Transmit Sync Pulse Setting Time

Receive Sync Pulse Setting Time

Sync Pulse Width

PCMIN Set-up Time

PCMIN Hold Time

Digital Output Load

Analog Input Allowable DC Offset

Allowable Jitter Width

Symbol

V

DD

V

AIN

V

IH

IL

F

C

F

S

C

t

Ir

t

If

t

XS

t

SX

t

RS

t

SR

t

WS

t

DS

t

DH

R

DL

C

DL

V

off

—

Condition

Voltage must be fixed

—

Connect AIN– and GSX

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

BCLK

XSYNC, RSYNC

BCLK

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

BCLKÆXSYNC, See Timing D

XSYNCÆBCLK, See Timing D

BCLKÆRSYNC, See Timing D

RSYNCÆBCLK, See Timing D

XSYNC, RSYNC

—

—

Pull-up resistor

—

Transmit gain stage, Gain = 1

Transmit gain stage, Gain = 10

XSYNC, RSYNC

–0.3 to V

–0.3 to V

–55 to +150

Min. Typ. Max. Unit

4.75

–30 +25 +85

—

2.2

0 — 0.8 V

64, 128, 256, 512, 1024,

2048, 96, 192, 384, 768,

1536, 1544, 200

6.0

40

—

—

iagram

iagram

iagram

iagram

100

100

100

100

1 BCLK

100

100

0.5

—

–100

–10

—

Rating

0 to 7

DD

DD

5.0

—

—

8.0

50

—

—

—

—

—

—

—

—

—

—

—

—

—

—

+ 0.3

+ 0.3

5.25

2.4

V

DD

9.0

60Clock Duty Ratio D

50

50

—

—

—

—

100

—

—

—

100

+100

+10

500

Unit

V

V

V

°C

V

°C

V

PP

V

kHz

kHz

%

ns

ns

ns

ns

ns

ns

ms

ns

ns

kW

pF

mV

mV

ns

9/18

¡ Semiconductor MSM7507-01/02/03

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

= +5 V ±5%, Ta = –30°C to +85°C)

(V

DD

Parameter

Power Supply Current

Input High Voltage

Input Low Voltage

High Level Input Leakage Current

Low Level Input Leakage Current

Digital Output Low Voltage

Digital Output Leakage Current

Input Capacitance

Transmit Analog Interface Characteristics

Parameter

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

Symbol

I

Operating mode

DD1

Power-save mode, PDN = 1,

I

DD2

XSYNC Æ OFF

I

Power-down mode, PDN = 0

DD3

V

IH

V

IL

I

IH

I

IL

V

Pull-up resistance > 500 W

OL

I

O

C

IN

Symbol

R

AIN+, AIN–

INX

R

GSX with respect to SG

LGX

C

LGX

V

OGX

V

OSGX

Condition

Condition Min. Typ. Max. Unit

—

—

—

—

—

Min.

—

—

—

2.2

0.0

—

—

0.0

—

Typ.

5.0

1.5

0.01

—

—

—

—

0.2

—

Max.

10

3.0

0.05

V

DD

0.8

2.0

0.5

0.4

10

Unit

mA

mA

mA

V

V

mA

mA

V

mA

— —5—pF

(V

= +5 V ±5%, Ta = –30°C to +85°C)

DD

Gain = 1

10

20

—

–1.2

–20

—

—

—

—

—

—

—

30

+1.2

+20

MW

kW

pF

V

mV

Receive Analog Interface Characteristics

Parameter

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

Symbol

R

PWI 10

INPW

VFRO with respect to SG

R

LVF

AOUT+, AOUT– (each) with

R

LAO

respect to SG

C

VFRO

LVF

AOUT+, AOUT–

C

LAO

VFRO, R

V

OVF

respect to SG

AOUT+, AOUT–, R

V

OAO

with respect to SG

VFRO with respect to SG

V

OSVF

AOUT+, AOUT–, Gain = 1 with

V

OSAO

respect to SG

= +5 V ±5%, Ta = –30°C to +85°C)

(V

DD

Condition Min. Typ. Max. Unit

= 20 kW with

L

= 0.6 kW

L

20

0.6

—

—

–1.2

–1.3

–100

–100

—

—

—

—

—

—

—

—

—

—

—

—

30

50

+1.2

+1.3

+100

+100

MW

kW

kW

pF

pF

mV

mV

10/18

V

V

¡ Semiconductor MSM7507-01/02/03

AC Characteristics

(V

= +5 V ±5%, Ta = –30°C to +85°C, SYNC = 8 kHz)

DD

Parameter

Transmit Frequency Response

Receive Frequency Response

Transmit Signal to Distortion Ratio 1020 dB

Receive Signal to Distortion Ratio 1020 dB

Transmit Gain Tracking

Receive Gain Tracking

Symbol

Loss T1

Loss T2

Loss T3

Loss T4

Loss T5

Loss T6

Loss R1

Loss R2

Loss R3

Loss R4

Loss R5

SD T1 35 43 —3

SD T2 35 41 —0

SD T3 35 38 —–30

SD T4 29

SD T5 24

SD R1 36 43 —3

SD R2 36 41 —0

SD R3 36 40 —–30

SD R4 30

SD R5 25

GT T1 –0.3 +0.01 +0.3

GT T2 Reference

GT T3 1020 –0.3 0 +0.3 dB–40

GT T4 –0.5 –0.03 +0.5

GT T5 –1.2 +0.15 +1.2

GT R1 –0.3 0 +0.3

GT R2 Reference

GT R3 1020 –0.3 +0.08 +0.3 dB

GT R4 –0.5 +0.12 +0.5

GT R5 –0.8 +0.15 +0.8

Freq.

(Hz)

300 –0.15 +0.07 +0.20 dB

1020 Reference dB

2020 –0.15 –0.04 +0.20 dB

3000 –0.15 +0.06 +0.20 dB

3400 0 0.4 0.80 dB

300 –0.15 –0.03 +0.20 dB

1020 Reference dB

2020 –0.15 0.0 +0.20 dB0

3000 –0.15 +0.05 +0.20 dB

3400 0.0 0.56 0.80 dB

Level

(dBm0)

60 20 26 — dB

0

3

–10

–50

–55

3

–10

–40

–50

–55

Condition

*1

*2

*2

*2

*1

*2

Min. Typ. Max. Unit

31.5

31

27

26

33.5

32

30

27

—–40

—–45

—–40

—–45

*1 Psophometric filter is used
*2 Upper is specified for the m-law, lower for the A-law

11/18

¡ Semiconductor MSM7507-01/02/03

AC Characteristics (Continued)

(V

= +5 V ±5%, Ta = –30°C to +85°C, SYNC = 8 kHz)

DD

Parameter

Idle Channel Noise

Absolute Level (Initial Difference)

Absolute Level

(Deviation of Temperature and Power)

Absolute Delay

Transmit Group Delay

Receive Group Delay

Crosstalk Attenuation

Symbol

Freq.

(Hz)

Nidle T

Nidle R

——

— –78

AV T 0.58 0.6007 0.622

Level

(dBm0)

—

—

Condition

AIN = SG

*1 *2

*1 *3

V

= 5.0 V

DD

Min. Typ. Max. Unit

–74.5

–72.5

–70

–69

— –75

Ta = 25°C

AV R 0.58 0.6007 0.622

AV Tt –0.2 — +0.2

1020

0

AV Rt –0.2 — +0.2

*4

V

= +5 V

DD

±5%

Ta = –30

*4

to 85°C

A to A

Td 1020 — — 0.60 ms0

BCLK

= 64 kHz

tgd T1

tgd T2

tgd T3

tgd T4

tgd T5

tgd R1

tgd R2

tgd R3

tgd R4

tgd R5

CR T 7580—

CR R 76

500

600

1000

2600

2800

500

600

1000

2600

2800

1020 dB0

TRANS Æ RECV

RECV Æ TRANS

— 0.19 0.75

*5

— 0.11 0.35

— 0.02 0.1250

— 0.05 0.125

— 0.75

*5

— 0.00 0.75

— 0.35

— 0.00 0.125 ms0

— 0.09 0.125

— 0.12 0.75

70 —

0.07

0.00

dBmOp

Vrms

dB

dB

ms

*1 Psophometric filter is used
*2 Upper is specified for the m-law, lower for the A-law
*3 Input "0" code to PCMIN
*4 AVR is defined at VFRO output
*5 Minimum value of the group delay distortion

12/18

¡ Semiconductor MSM7507-01/02/03

AC Characteristics (Continued)

(V

= +5 V ±5%, Ta = –30°C to +85°C, SYNC = 8 kHz)

DD

Parameter

Symbol

Discrimination 0

PSR T

PSR R

Digital Output Delay Time

Freq.

(Hz)

4.6 kHz to

DIS

72 kHz

300 to

S

3400

fa = 470

IMD

fb = 320

0 to

50 kHz

t

SD

t

XD1

CL = 100 pF + 1 LSTTL

t

XD2

t

XD3

(dBm0)

*6 The measurement under idle channel noise

Level

Condition

0 to

4000 Hz

4.6 kHz to

100 kHz

*6

PP

Min. Typ. Max. Unit

30 32 — dB

— –37.5 –35 dBmOOut-of-band Spurious 0

— –52 –35 dBmOIntermodulation Distortion –4 2fa – fb

—30—dBPower Supply Noise Rejection Ratio 50 mV

20 — 200

20 — 200

20 — 200

ns

20 — 200

13/18

¡ Semiconductor MSM7507-01/02/03

TIMING DIAGRAM

PCM Data Input/Output Timing

Transmit Timing

BCLK 12345678910

XSYNC

t

XS

t

XD1

t

SX

t

WS

t

SD

t

XD2

t

XD3

PCMOUT D2 D3 D4 D5 D6 D7 D8MSD

When t
When t

£ 1/2 • Fc, the Delay of the MSD bit is defined as t

XS

£ 1/2 • Fc, the Delay of the MSD bit is defined as tSD.

SX

XD1

.

Receive Timing

BCLK 12345678910

t

RS

RSYNC

PCMIN D2 D3 D4 D5 D6 D7MSD

t

SR

t

WS

t

DS

t

DH

D8

11

11

14/18

¡ Semiconductor MSM7507-01/02/03

APPLICATION CIRCUIT

Analog interface Digital interface

+5 V

MSM7507

AIN–

GSX

AIN+

SG

AOUT+

AOUT–

PWI

PCMOUT

XSYNC

RSYNC

BCLK

PCMIN

PDN

PCM signal output

8 kHz SYNC signal input

PCM shift clock input

PCM data input

Power Down control input

Analog input

600 W

Analog output

600 W

51 kW1:1

0.1 mF

300 W1:1

300 W

1 mF

VFRO

SGC

AG

V

DD

DG

0 V

+5 V

0–20W

10 mF

51 kW

0.1 mF

–

+

FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT

M

Microphone amp

C1

R5

C2

C4

R1

R2

R4

AIN–

GSX

AIN+

SG

AOUT+

AOUT–

PWI

Transmit frequency
characteristic
Adjustment determined with
C1, C2, R1, R2

Receive frequency
characteristic
Adjustment determined with
C3, C4, R3, R4

R3 C3

VFRO

15/18

¡ Semiconductor MSM7507-01/02/03

RECOMMENDATIONS FOR ACTUAL DESIGN

• To assure proper electrical characteristics, use bypass capacitors with excellent high frequency

characteristics for the power supply and keep them as close as possible to the device pins.

• Connect the AG pin and the DG pin each other as close as possible. Connect to the system

ground with low impedance.

• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an

IC socket is unavoidable, use the short lead type socket.

• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave

source such as power supply transformers surround the device.

• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch-

up phenomenon when turning the power on.

• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)

power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.

16/18

¡ Semiconductor MSM7507-01/02/03

PACKAGE DIMENSIONS

(Unit : mm)

SOP24-P-430-1.27-K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.58 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

17/18

¡ Semiconductor MSM7507-01/02/03

(Unit : mm)

SSOP20-P-250-0.95-K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.18 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

18/18