Datasheet MSM6996VAS, MSM6996VGS-K, MSM6996VRS, MSM6997HAS, MSM6996HRS Datasheet (OKI)

E2U0010-28-81

¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM6996H/6996V/6997H/6997V/6998/6999

Single Chip CODEC

GENERAL DESCRIPTION

The MSM6996H/MSM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999 are a single-channel
CODEC CMOS ICs containing filters for A/D and D/A converting of the voice signal ranging from
300 Hz to 3400 Hz.

FEATURES

• Compliance with ITU-T companding Law
MSM6996H/MSM6996V/MSM6998 : A-law
MSM6997H/MSM6997V/MSM6999 : m-law

• Capable of independent operation of transmission and reception

• Transmission clock in the range of 64 kHz to 2048 kHz

• Adjustable transmit gain

• 600 W drive for analog output
MSM6996H/MSM6996V/MSM6997H/MSM6997V single end drive
MSM6998/MSM6999 Push-pull drive

• Built-in analog loop back fanction
MSM6996V/MSM6997V

• Built-in reference voltage source

• Low Power Dissipation (60 mW to 70 mW Typ.)

• Package options :

16-pin plastic DIP (DIP16-P-300-2.54) (Product name : MSM6996HRS/MSM6997HRS)

(Product name : MSM6996VRS/MSM6997VRS)
(Product name : MSM6998RS/MSM6999RS)

16-pin cer DIP (DIP16-G-300-2.54-1) (Product name : MSM6996HAS/MSM6997HAS)

(Product name : MSM6996VAS/MSM6997VAS)
(Product name : MSM6998AS/MSM6999AS)

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM6996HGS-K/MSM6997HGS-K)

(Product name : MSM6996VGS-K/MSM6997VGS-K)
(Product name : MSM6998GS-K/MSM6999GS-K)

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¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

BLOCK DIAGRAM

MSM6996H/V
MSM6997H/V

AIN+
AIN–

GSX

V

DD

V

SS

AG
DG

+
–

Pre Filter

Voltage

REF.

5th

LPF

HPF

Auto
Zero

3rd

SAMPLE

C Ladder

COMP

SAR

T.PWD

Transmit

PLL

Transmit

Controller

XSYNC

XCLOCK
PCMOUT

*2

TMC

AOUT

AIN+
AIN–

GSX

V

DD

V

AG
DG

AOUT–

AOUT+

–
+

MSM6998, MSM6999

+
–

SS

+
–

R

–
+

Voltage

REF.

R

Pre Filter

5th
LPF

5th
LPF

5th
LPF

3rd

HPF

Auto
Zero

C Ladder

SAMPLE

C Ladder

C Ladder

R.PWD

Receive

Controller

Receive

PLL

*

1 BS : Only MSM6997H/V

*

2 Only MSM6996V, MSM6997V

COMP

SAR

Transmit

PLL

Transmit

Controller

T.PWD

R.PWD

Receive

Controller

Receive

PLL

PDN/BS

*1

PCMIN
RCLOCK

RSYNC

XSYNC

XCLOCK
PCMOUT

*3
PDN/BS
PCMIN
RCLOCK

RSYNC

*

3 BS : Only MSM6999

2/21

¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

PIN CONFIGURATION (TOP VIEW)

1

AIN+

2

AIN–

3

GSX

4

AG

AOUT

PCMIN

5
6

NC

7

V

DD

8 9

NC : No connect pin

16-Pin Plastic DIP

MSM6996HRS
MSM6997HRS

1

AIN+

16 1

V

SS

15

PCMOUT

14

PDN/BS

13

DG

12

XSYNC

11

RSYNC

10

XCLOCK
RCLOCK

AIN+
AIN–

GSX

AG

AOUT

TMC

V

DD

PCMIN

16-Pin Plastic DIP

16

V

SS

AIN+

1

2
3
4
5
6
7
8 9

MSM6996VRS
MSM6997VRS

16 1

V

SS

15

PCMOUT

14

PDN/BS

13

DG

12

XSYNC

11

RSYNC

10

XCLOCK
RCLOCK

AIN+
AIN–

GSX

AG
AOUT+
AOUT–

V

DD

PCMIN

16-Pin Plastic DIP

16

V

SS

AIN+

1

2
3
4
5
6
7
8 9

MSM6998RS
MSM6999RS

16

V

15

PCMOUT

14

PDN/BS

13

DG

12

XSYNC

11

RSYNC

10

XCLOCK
RCLOCK

16

SS

V

SS

2

AIN–

3

GSX

4

AG

AOUT

5

NC

6

V

7

DD

PCMIN

8 9

NC : No connect pin

16-Pin Cer DIP

MSM6996HAS
MSM6997HAS

15

PCMOUT

14

PDN/BS

13

DG

12

XSYNC

11

RSYNC
XCLOCK

10

RCLOCK

AIN–
GSX

AG

AOUT

TMC

V

DD

PCMIN

2
3
4
5
6
7
8 9

16-Pin Cer DIP

MSM6996VAS
MSM6997VAS

15

PCMOUT

14

PDN/BS

13

DG

12

XSYNC

11

RSYNC

10

XCLOCK
RCLOCK

AIN–
GSX

AG
AOUT+
AOUT–

V

DD

PCMIN

2
3
4
5
6
7
8 9

16-Pin Cer DIP

MSM6998AS
MSM6999AS

15

PCMOUT

14

PDN/BS

13

DG

12

XSYNC

11

RSYNC
XCLOCK

10

RCLOCK

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¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

AIN+
AIN–

GSX

AG
AG
NC
NC

AOUT

NC
NC

V

DD

PCMIN

1
2
3
4
5
6
7
8

9
10
11
12 13

24
23
22
21
20
19
18
17
16
15
14

V

SS

PCMOUT
PDN/BS
DG
NC
NC
NC
NC
XSYNC
RSYNC
XCLOCK
RCLOCK

AIN+
AIN–

GSX

AG
AG
NC
NC

AOUT

NC

TMC

V

DD

PCMIN

1
2
3
4
5
6
7
8

9
10
11
12 13

NC : No connect pin NC : No connect pin

24-Pin Plastic SOP

24-Pin Plastic SOP

24
23
22
21
20
19
18
17
16
15
14

V

SS

PCMOUT
PDN/BS
DG
NC
NC
NC
NC
XSYNC
RSYNC
XCLOCK
RCLOCK

MSM6996HGS-K
MSM6997HGS-K

AIN+
AIN–

GSX

AOUT+

AOUT–

PCMIN

1
2
3
4

AG
AG

5

NC

6

NC

7
8

NC

9

10

V

11

DD

12 13

MSM6996VGS-K
MSM6997VGS-K

24

V

SS

23

PCMOUT

22

PDN/BS
DG

21

NC

20

NC

19

NC

18

NC

17

XSYNC

16

RSYNC

15
14

XCLOCK
RCLOCK

NC : No connect pin

24-Pin Plastic SOP

MSM6998GS-K
MSM6999GS-K

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¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN–, GSX

These three pins are used for the transmit level adjustment.
AIN+ is a non-inverting analog input pin which is connected to the non-inverting input of a transmit
amplifier.
AIN– is an inverting analog input pin which is connected to the inverting input of the transmit
amplifier.
GSX is a transmit amplifier output pin.
Adjustment can be done by following method.

Analog
Input

C1

R1

R2

R3

AG

Notes: 1. R2 + R3 > 10 kW

2. When the DC off-set voltage of analog input is more than 20 mV, C1 and R1 should
provide for DC blocking.
In this case, cut-off frequency of HPF, composed by R1 and C1, should be less than 30 Hz.

3. R1 should be less than 20 kW

AG

AG is an analog ground.
AG is connected to the analog system ground.

AIN+

AIN–

GSX

Gain = 1 +

+

–

R2

< 10

R3

RC

Active

Filter

AOUT

AOUT is the analog signal output pin for the MSM6996H/V and MSM6997H/V.
The output voltage range is 5 VPP. This output can drive the 600 W resistor.

AOUT+, AOUT–

Analog output for the MSM6998 and MSM6999.
The output signal amplitudes are 5 VPP. The AOUT– output is inverted to the AOUT+ output. These
outputs can drive a 600 W impedance.

V

DD

VDD is the positive power supply.

The voltage supplied to this pin should be +5 V ±5%.

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¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

PCMIN

PCM signal input.
The serial input PCM signal is converted from digital to analog, synchronizing with the synchronous
signal RSYNC and clock signal RCLOCK.
The data rate of PCM signal ranges from 64 kbps to 2048 kbps.
The PCM signal is read at the falling edge of the clock signal and latched into the internal register
when finished to read eight bits data.
The top of the PCM data is specified by RSYNC pulse timing.

RCLOCK

Receive clock pulse input.
The frequency of this clock pulse should be identified with the data rate of PCM input signal at the
PCMIN pin.
This RCLOCK signal can be a continuous clock or a burst clock with nine bits or more.
In the case of a burst clock, input the following timing.

MSDD2D3D4D5D6D7D8PCMIN

RCLOCK

RSYNC

123456789

9 Clocks are required

XCLOCK

Transmit clock input.
The PCM output data rate from the PCMOUT pin is set by this clock frequency.
The applicable clock frequencies range from 64 kHz to 2048 kHz.
This XCLOCK signal can be a continuous clock or a burst clock with nine bits or more.
In the case of a burst clock, input the following timing.

MSD D2 D3 D4 D5 D6 D7 D8PCMOUT

XCLOCK

XSYNC

123456789

9 Clocks are required

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¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
The whole timing signal in the receive section are synchronize by this synchronizing signal.
This signal must be synchronize in phase with RCLOCK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics of receive section.
However, same as the RCLOCK frequency, this device can operate in the range of 8 kHz ±2 kHz, with

no guarantee of adherence to the electrical characteristics in this specification as a catalogue value.
Fixing this signal to logic "1" or "0", the receive circuit is driver in a power down state.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal.
All transmit timing signals are triggered to synchronize with this signal. This signal should be
synchronized in phase with XCLOCK pulse.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics of transmit section.

Fixing this signal to logic "1" or "0", the transmit circuit is driver in a power down state.

DG

Ground of digital signal.
This pin is electrically separated from the AG pin in this device.
The DG pin must be connected to the AG pin on the printed circuit board to make common to the
AG pin.

PDN/BS

Power down signal input.
When this input is held at low level more than 1 ms, the device is put into the power-down mode.

PCMOUT

PCM signal output.
The PCM output signal is output in synchronization with the rising edge of XCLOCK pulse orderly
from MSD first. (The first bit of the PCM signal may output at the rising edge of XSYNC pulse,
according to the timing of XSYNC and XCLOCK pulse.). During the PCMOUT signal output except
the 8-bit pulses, the pin is in an open state, therefore, multiple connections by wired-OR are easily
possible at this pin.
The code companding law and output code format depend on ITU-T Recommendation G.711, and
for the MSM6996H, MSM6996V, and MSM6998 (A-law) the output PCM signals are obtained by
inverting the even bits of signals.

Input/Output

Level

+Full scale

+0
–0

–Full scale

PCMIN/PCMOUT

MSM6996 (A-law) MSM6997 (m-law)

MSM6998 (A-law) MSM6999 (m-law)

10101010
11010101
01010101
00101010

10000000
11111111
01111111
00000000

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¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

TMC

Control signal input for mode selection.
This pin select the normal operating mode or analog loop-back mode.

TMC Input Mode

> 2.0 V Normal operation
< 0.8 V Analog loop-back

AIN

AOUT

V

SS

+
–

+
–

AG

Signal flow in normal operating mode
Signal flow in analog loop-back mode

TRANSMIT

Negative voltage power supply.

The range of power supply voltage is –5 V ±5%.

BPF

RECV

LPF

AD

DA

PCMOUT

PCMIN

8/21

¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Analog Input Voltage
Digital Input Voltage
Storage Temperature

Symbol

V

DD

V

SS

V

AIN

V

DIN

T

STG

Condition

—
—
—
—
—

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Symbol

V

DD

V

SS

Operating Temperature Ta °C—
Analog Input Voltage
Input High Voltage
Input Low Voltage
Clock Frequency
Sync Pulse Frequency
Clock Duty Ratio
Digital Input Rise Time
Digital Input Fall Time

Transmit Sync Timing

Receive Sync Timing

Transmit Sync Pulse Width
Receive Sync Pulse Width
PCMIN Set-up Time
PCMIN Hold Time

Analog Output Load

Digital Output Load

V

AIN

V

IH

V

RSYNC, RCLOCK, TMC, PDN/BS

IL

f

C

f

S

D

L

t

Ir

t

If

t

XS

t

SX

t

RS

t

SR

t

WX

t

WR

t

DS

t

DH

t

BS

t

BH

R

AL

C

AL

R

DL

C

DL

Transmit gain stage, Gain = 1

V

Offset Voltage

IO

Condition Min. Typ. Max. Unit

—
—

Connect AIN– and GSX

XSYNC, XCLOCK, PCMIN,

XCLOCK, RCLOCK kHz—

XSYNC, RSYNC — 8 — kHz

XCLOCK, RCLOCK 40 50 60 %

XSYNC, XCLOCK, PCMIN,

RSYNC, RCLOCK (Fig. 1)
XCLOCKÆXSYNC (Fig. 2)
XSYNCÆXCLOCK (Fig. 2)

RCLOCKÆRSYNC (Fig. 2)
RSYNCÆRCLOCK (Fig. 2)

AOUT, AOUT+, AOUT–

—

—

Rating

0 to 7

Unit

V

–7 to 0 V

–0.3 to VDD + 0.3

V

DD

–0.3 to V

DD

–55 to +150

+ 0.3

V
V

°C

(Ta = 0°C to 70°C)

4.75 5 5.25 V

–5.25 –5 –4.75 V

02570

——5V

2.0 —

V

DD

P-P

V

0 — 0.8 V

64 2048

— — 50 ns
— — 50 ns
50 — — ns

100 — — ns

50 — — ns
100 — — ns
1/fc — — ms—
1/fc — — ms—
100 — — ns—
100 — — ns—
200 — — ns—BS Set-up Time *
200 — — ns—BS Hold Time *
600 — — W

10 — — kWGSK

— — 100 pF

1——kW

— — 100 pF

–200 — +200Allowable Analog Input

mV

–20 — +20Transmit gain stage, Gain = 10

* : The value for the MSM6997 and MSM6999

9/21

¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

(VDD = +5 V ±5%, VSS = –5 V ±5%, Ta = 0°C to 70˚C)

Parameter

Power Supply Current
(Operating)

Power Supply Current
(Stand-by)
Input High Voltage
Input Low Voltage

Output Leakage Current
Analog Output Offset Voltage
Input Capacitance

Symbol

I

DD1

I

SS1

I

DD2

I

SS2

V

IH

V

IL

I

IH

I

IL

V

OL

I

OH

V

OFF

C

IN

R

IN

Condition Min. Typ. Max. Unit

12

XCLOCK, RCLOCK

*

2048 kHz

*

— 7.0

14
12

— 6.5

14

— — 3.0

—

— — 1.5

2.2 — — V

— — 0.8
— < 0.5 2.0

—

— < 0.2 0.5
— 0.1 0.4 VOutput Low Voltage
—< 510mA

–150 0 +150 mV

—5—pF—
—1—MWfIN < 3.4 kHzAnalog Input Resistance

mA

mA

V

mAInput Leakage Current

* : The upper is specified for the MSM6996/MSM6997 and the lower for the MSM6998/MSM6999

10/21

¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

AC Characteristics

(V

= +5 V ±5%, VSS = –5 V ±5%, Ta = 0°C to 70°C)

DD

Condition

60

Level

(dBm0)(Hz)

–40

–40

–10
–40
–50
–55

–10
–40
–50
–55

Min.

20

Typ.

—

Max.—Unit

dB0

dB

31——

dB

31——

3

–0.2 — +0.2

dB
–0.4 — +0.4
–0.8 — +0.8

3

–0.2 — +0.2

dB

Parameter

Transmit Frequency Response

Receive Frequency Response

Transmit Signal to Noise
Ratio *1

Receive Signal to Noise
Ratio *1

Transmit Gain Tracking

Receive Gain Tracking

Symbol

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

L

OSS

Freq.

T1
T2
T3
T4
T5
T6

R1
R2
R3
R4

R5

300 –0.15 — +0.25

820 Reference
2020 –0.15 — +0.25
3000 –0.15 — +0.25
3400 0 — 0.8

300 –0.1 — +0.2

820 Reference
2020 –0.1 — +0.2 dB0
3000 –0.1 — +0.2
3400 0 — 0.8

SD T1 36 — —3
SD T2 36 — —0
SD T3 36 — —–30
SD T4

1020

or

820

SD T5 26 — —–45
SD R1 36 — —3
SD R2 36 — —0
SD R3 36 — —–30
SD R4

1020

or

820

SD R5 26 — —–45
GT T1 –0.2 — +0.2
GT T2
GT T3
GT T4

1020 Reference

or

820
GT T5
GT R1 –0.2 — +0.2
GT R2 Reference
GT R3
GT R4 –0.4 — +0.4

1020

or

820
GT R5 –0.8 — +0.8

Note: *1 The measurement is taken with P-message filter

11/21

¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

AC Characteristics (Continued)

(V

= +5 V ±5%, VSS = –5 V ±5%, Ta = 0°C to 70°C)

DD

Condition

= 2 kW

Level

(dBm0)(Hz)

0

0

—

200

mVp-p

Min. Typ. Max. Unit

dBmOp

dB

— — 0.520—ms

— — 0.35
— — 0.125
— 0.125

—

ms

— — 0.75

dB

dBmO

—30—

dB

—30—
—30—
50 150 300
50 100 300

ns

50 100 300
50 180 300
—ns

20 100

Parameter

Idle Channel

*1

Noise

Absolute Gain

*2

Transmit
Receive
Transmit
Receive

Absolute Delay Time

Transmit Group Delay Time

Receive Group Delay Time

T to R

Crosstalk Attenuation

R to T

Out-of-Band Spurious

Intermodulation Distortion

Discrimination

VDD Noise Rejection
Ratio
VSS Noise Rejection
Ratio

Transmit
Receive
Transmit
Receive

Digital Output Delay Time

Digital Output Fall Time

*3

*3

Symbol

N

IDL

N

IDL

AV T –0.5 0 +0.50

AV R –0.5 0 +0.50

t
tGD T1 — — 0.75
tGD T2
tGD T3
tGD T4
t

GD

tGD R1 — — 0.75
tGD R2 — — 0.35
t

GD

tGD R4 — — 0.125
tGD R5 — — 0.75

C

R

C

R

S — — –300

IMD 1 — — –35–4 dBmO

Freq.

T — — –75—
R — — –75—

D

—
—

1020 or 820
1020 or 820

500

600
1000
2600

T5

2800

500

600

R3 — — 0.125 ms

1000
2600
2800

T ——66

1020 or 820

R ——66

1020 or 820
300 to 3400

f

= 470

a

= 320

f

b

4.6 kHz to

DIS 30 — —0dB

72 kHz

PPSR T — 30 —

PPSR R
NPSR T

0 to 300

kHz

NPSR R

t

SD

XD1

XD2

XD3

DO

R

DL

= 100 pF

C

DL

t
t
t

t

Notes: *1 The measurement is taken with P-message filter

*2 MSM6996/MSM6998 0 dB = 1.231 Vrms

MSM6997/MSM6999 0 dB = 1.227 Vrms

*3 Reference : 1800 Hz

12/21

¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

TIMING DIAGRAM

Wave Time Measurement Level

Basic Timing

XCLOCK

XSYNC

PCMOUT

0.4 V

2.4 V

1.4 V

t

WX

t

t

Ir

WR

2.4 V

t

If

t

DOf

1.4 V

0.4 V

Note: Timing between signal waves is judged at 1.4 V

Figure 1

12345678910

t

XS

t

SX

t

WX

t

XD1

t

SD

t

XD2

MSD D2 D3 D4 D5 D6 D7 D8

1/f

C

t

XD3

Transmitter
Section

Note 1):

RCLOCK

RSYNC

PCMIN

When tXS £ 1/2 ¥ fc, the Delay of the MSD bit is defined as t
When t

£ 1/2 ¥ fc, the Delay of the MSD bit is defined as tSD.

SX

XD1

.

12345678910

t

RStSR

t

WR

MSD

D2

tDSt

tDSt

D3

DH

DH

D4

D5

D6

D7

D8

Note 2): Transmit synchronizing and clock pulse, and Receive synchronizing and clock pulse may be

asynchronous mutually.

Note 3): The threshold level is 1.4 V.

Figure 2

Receiver
Section

Invalid Data

13/21

¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

Timing for 7 bits Decode (Specified for MSM6997/6999)

RSYNC

PCMIN

RCLOCK

Decoder

Operation

Timing for Bit-steal Function Setting

RSYNC

PCMIN

12345678 12345678 12345678

123456789

Allowable Range

BS

125

ms

~

~

~

~

Disable

8 Bits Decode 7 Bits Decode

123456789 123456789

t

BStBH

Figure 3

~

~

more than 10ms

~

~

8 Bits Decode

RCLK

~

PDN/BS

Notes: Follow these procedures when the Bit-steal function is used:

1. Set the RSYNC pin to OFF ("L") after the PDN/BS pin is set at "H" for 10ms or more.

2. Set the RSYNC to ON after a pulse is input at the PDN/BS pin.

3. The Bit-steal function starts to operate.

~

more than 10ms

~

~

14/21

¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

APPLICATION CIRCUIT

Basic Circuit

PCM ANALOG

INOUT

OUTIN

XTAL

2.048 MHz

10 M

4049 4049

+5 V

14

Q4 Q4

RE C R EC

15109 8721

+5 V

16 6

M4520RS

DG

2 kW

+5 V

Power Down
1 : NOR
0 : Power Down

INOUT

GSX
PDN/BS
CLOCK

SYNC

X R X R DG AG

Notes: 1. Insert diode for preventing from Latch-Up at turn on Power.

Recommended Diode Specification.

• High Speed Switching

• Allowerable Power dissipation 250 mW to 300 mW

• Forward Voltage Drop < 1.3 V (at 100 mA)

2. AG and DG must be connected in the printed circuit board mounted this device, for
preventing from Latch-Up.

AIN+ AOUT

AIN–

+–
–+

Note 1

0 V –5 V +5 V

VSSV

10 mF
10 mF

DD

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¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

Example of Multi-Channel Connections (8ch)

512 kHz

+5 V

+5 V

74161(1)

2

CK

1

CLR

7

E

10

E

9

L

74161(2)

2

CK

1

CLR

7

E

10

E

9

L

+5 V

14

Q

A

13

Q

B
P
T
O

P
T

O

11

Q

D

15

C

O

14

Q

A

13

Q

B

12

Q

C

+5 V

9

CK

CLR

9
1

A

2

BQ

74164

3

Q

A

4

Q

B

5

Q

C

6

Q
Q

Q

Q

No.4

D

10

No.5

E

11

No.6

F

12

No.7

G

13

H

XC
XS
RC
RS

PCM

OUT

No.1

PCM

IN

No.2

1 kW

Multiple
PCM

No.3

Example of Multi-Channel Timing

74161(1)
74161(2)

74164

Output

Multiple PCM

512K CLK

QC Output
Q

Output

B

Q

A

Q

B

Q

C

Q

H

87

No.

12345678

MSD LSD

No.8

No.

12 3 4 5 6 78

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¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

Transmit and Receive Level Adjustment (MSM6996H/V, MSM6997H/V)

a. Transformer of turns ratio 1 : 1

1 : 1

4WS
600 W

1 : 1

4WR
600 W

b. Transformer of turns ratio 1 : 2

2 : 1

4WS
600 W

2 : 1

4WR
600 W

600 W

300 W

AG

600 W Attenuator

AG

300 W Attenuator

20 kWR1
600 W

20 kWR1
300 W

1
2

3

5

1
2

3

5

AIN+
AIN–

GSX

AOUT

AIN+
AIN–

GSX

AOUT

When R1 is open and the attenuator is set at
0 dB,
4 WS maximum input level = +7.17 + L
(dBm)
4 WR maximum output level = +1.15 – L
(dBm)
LT : Transformer loss

When R1 is open and the attenuator is set at
0 dB,
4 WS maximum input level = +10.18 + L
(dBm)
4 WR maximum output level = +4.16 – L
(dBm)
LT : Transformer loss

T

T

T

T

Transmit and Receive Level Adjustment (MSM6998, MSM6999)

4WS
600 W

4WR
600 W

1 : 1

1 : 1

600 W

AG

20 kWR1
300 W

300 W

600 W Attenuator

1
2

3

5

6

AIN+
AIN–

GSX

AOUT+

AOUT–

When R1 is open and the attenuator is set at
0 dB,
4 WS maximum input level = +7.17 + L
(dBm)
4 WR maximum output level = +7.17 – L
(dBm)
LT : Transformer loss

T

T

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¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

RECOMMENDATIONS FOR ACTUAL DESIGN

• To assure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the device pins.

• Connect the AG pin and the DG pin each other as close as possible.
Connected to the system ground with low impedance.

• Mount the device directly on the board when mounted on printed circuit board.
Do not use IC sockets.
If an IC socket is unavoidable, use the short lead type socket.

• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source
such as power supply transformers surround the device.

• Keep the voltage on the VDD pin not lower than –0.3 V and the voltage on the VSS pin more than
+0.3 V even instantaneously to avoid latch-up phenomenon when turning the power on.

• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power
supply to avoid erroneous operation and the degradation of the characteristics of these devices.

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¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

PACKAGE DIMENSIONS

(Unit : mm)

DIP16-P-300-2.54

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.99 TYP.

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¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

(Unit : mm)

DIP16-G-300-2.54

16

1

0.80TYP

20.00MAX

1.50±0.101.00±0.10

2.54

9

8

0.50±0.10

7.50MAX

4.10±0.40

5.10MAX

2.54MIN

0.51MIN

SEATING PLANE

M

0.25

+0.15

0.25-0.05

7.62

0~15°

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¡ Semiconductor MSM6996H/6996V/6997H/6997V/6998/6999

(Unit : mm)

SOP24-P-430-1.27-K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.58 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

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